Thermal transistor

Abstract

This thermal transistor has a laminated structure in which a solid electrolyte layer and an active layer are sandwiched between a pair of electrodes. The thermal transistor uses oxidization or reduction of the active layer by causing a current to flow between the electrodes. The active layer is made from cerium oxide. The cerium oxide in the active layer is preferably CeO2-x (0≤x≤0.5). The cerium oxide in the active layer is CeO2 in the oxidized state, and at least a part of CeO2 is reduced to CeO2-δ (0<δ≤0.5, preferably 0<δ≤0.3) in the reduced state. At least a part of the crystal structure of the active layer changes by causing a current to flow between the electrodes.

Description

Thermal Transistor

[0001] The present invention relates to a transistor that electrically controls heat flow (hereinafter referred to as a "thermal transistor"), and more particularly to an all-solid-state thermal transistor that electrically switches the thermal conductivity of an oxide thin film.

[0002] The energy conversion efficiency of thermal power plants, factories, automobiles, and other facilities that use fossil fuels such as oil and coal as their primary energy source is said to be only one-third, with the remaining two-thirds of fossil fuel energy being released into the air as waste heat. If this waste heat could be converted into electricity and reused, it would be possible to reduce fossil fuel consumption and, at the same time, curb the generation of greenhouse gases. The recovery and reuse of low- to medium-temperature heat, around 100 to 300°C, is particularly desirable. However, unlike electricity, which can be controlled using conductors, or light, which can be controlled using optical fibers, there is no technology to control the transfer of heat, making it difficult to effectively reuse waste heat.

[0003] On the other hand, the thermal conductivity varies greatly depending on the Li concentration x. For example, ｘ CoO ２ and Li ｘ MoS ２ A thermal transistor has been proposed in which a substance such as the above is used as an active layer material, and the active layer material and electrolyte are sandwiched between two electrodes and a voltage is applied to perform electrochemical oxidation and reduction (see, for example, Non-Patent Documents 1 and 2). ｘ A thermal transistor has been proposed that utilizes the change in thermal conductivity that accompanies the change in crystal structure using a material whose crystal structure changes significantly upon oxidation / reduction (or protonation) such as the above (e.g., Non-Patent Document 3).

[0004] J. Cho et al., “Electrochemically tunable thermal conductivity of lithium cobalt”, Nature Communications 5, 4035 (2014)A. Sood et al., “An electrochemical thermal transistor”, Nature Communications 9, 4510 (2018)Q. Lu et al., “Bi-directional tuning of thermal transport in SrCoOx with electrochemically induced phase transitions”, Nature Materials 19, 655 (2020)

[0005] However, the proposed thermal transistors all use liquids such as electrolytes to perform oxidation and reduction, and therefore have the problem that they cannot be used unless they are placed in a sealed container. Furthermore, these electrolyte-type thermal transistors have the problem that it is difficult to integrate the electrodes, making it impossible to construct a transistor with this structure.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a thermal transistor that does not require sealing in a container or the like, that allows electrodes to be integrated, and that has a large change in thermal conductivity.

[0007] One aspect of the present invention is a thermal transistor having a laminated structure in which a solid electrolyte layer and an active layer are sandwiched between a pair of electrodes, and utilizing the phenomenon in which the active layer is oxidized or reduced by passing a current between the electrodes, wherein the active layer is made of cerium oxide.

[0008] The thermal transistor of the present invention has an all-solid-state structure equipped with electrodes, and does not need to be sealed in a container, etc. Furthermore, by changing the amount of current flowing between the electrodes, the thermal conductivity can be significantly changed.

[0009] FIG. 1 is a schematic diagram of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a manufacturing method of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 3 is a schematic diagram showing the operation of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a measurement state of transistor characteristics of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 5 is an X-ray diffraction pattern of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 6 is a TDTR decay curve of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 7 is a time-dependent change in thermal conductivity of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 8 is a TDTR decay curve of an all-solid-state thermal transistor in an ON state and an OFF state of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 9 is a thermal conductivity cycling characteristic of an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 10 is a comparison of changes in thermal conductivity; FIG. 11 is an X-ray diffraction pattern when a voltage is repeatedly applied to an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 12 is a TDTR decay curve when a voltage is repeatedly applied to an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 13 is a TDTR decay curve when a voltage is repeatedly applied to an all-solid-state thermal transistor according to an embodiment of the present invention; FIG. 14 is a TDTR decay curve when a voltage is repeatedly applied to an all-solid-state thermal transistor according to an embodiment of the present invention;

[0010] 1 is a schematic diagram of an all-solid-state thermal transistor according to an embodiment of the present invention, generally designated 100. The all-solid-state thermal transistor 100 includes a substrate 10 made of a solid electrolyte. The solid electrolyte of the substrate 10 is an oxide containing at least one metal selected from Y, Zr, Ce, and Gd, such as yttria-stabilized zirconia (YSZ), CeO ２ Ya, La ０．８ Sr ０．２ Ga ０．９ Mg ０．１ O ３ (LSGM) and the like are used.

[0011] An active layer 20 is provided on the substrate 10. The active layer 20 is made of cerium oxide.

[0012] A lower electrode 30 and an upper electrode 40 made of, for example, Pt are provided on the back surface of the substrate 10 and the surface of the active layer 20, respectively. In addition to Pt, Au, Pd, Ir, Ni, Rh, W, Ti, Al, Sn, Fe, Cu, alloys of these, transparent conductive oxides such as ITO, etc. may also be used for the lower electrode 30 and the upper electrode 40. The lower electrode 30 is a porous electrode.

[0013] In this way, the all-solid-state thermal transistor 100 has a laminated structure of the upper electrode 40 / active layer 20 / substrate 10 / lower electrode 30, and constitutes a thermal transistor that does not contain liquid such as an electrolyte or an ionic liquid, i.e., an all-solid-state thermal transistor.

[0014] The substrate 10 of the solid electrolyte layer is made of CeO ２ In this case, the substrate 10 can serve as both the solid electrolyte layer and the active layer. In this case, the all-solid-state thermal transistor 100 has an upper electrode 40 / CeO ２ It has a laminated structure of a substrate 10 / a lower electrode 30. Of course, CeO ２ Separately, CeO ２ An active layer 20 may be formed.

[0015] <Manufacturing Method> An example of a manufacturing method for the all-solid-state thermal transistor 100 will be described with reference to Figure 2. The manufacturing method includes the following steps 1 to 4.

[0016] Step 1: As shown in Fig. 2(a), a solid electrolyte substrate 10 is prepared. The substrate 10 is made of a material such as Y-stabilized zirconia (YSZ), CeO ２ A solid electrolyte for a solid oxide fuel cell, such as LSGM, can be used. Here, (100) YSZ is used. The size of the substrate is 1 cm in length and width, and 0.5 mm in thickness.

[0017] Subsequently, cerium oxide (CeO ２ The growth conditions are, for example, a substrate temperature of 900° C. and an oxygen pressure in the film-forming chamber of 5×10 ―３ Pa. The active layer 20 has a film thickness of, for example, 100 nm.

[0018] Step 2: As shown in FIG. 2(b), a lower electrode 30 is formed on the back surface of the YSZ substrate 10 using a sputtering method. By sputtering with an argon gas pressure of 4 Pascals, the lower electrode 30 becomes porous. Next, an upper electrode 40 is formed on the surface of the active layer 20 using a sputtering method. By sputtering with an argon gas pressure of 0.6 Pascals, the upper electrode 40 becomes a dense electrode. The substrate temperature may be room temperature. Both the lower electrode 30 and the upper electrode 40 are made of Pt, and for example, the lower electrode 30 is 20 nm thick and the upper electrode 50 is 100 nm thick.

[0019] Step 3: As shown in FIG. 2(c), the structure is divided into four equal parts in a direction perpendicular to the substrate 10 (shown by the dashed lines).

[0020] Step 4: As shown in FIG. 2(d), an all-solid-state thermal transistor 100 having a length and width of 5 mm and a thickness of about 0.5 mm is completed.

[0021] <Operation Principle> The operation principle of the all-solid-state thermal transistor 100 will be described with reference to Fig. 3. Fig. 3 is a schematic diagram showing the operation of the all-solid-state thermal transistor 100 according to the embodiment of the present invention. As shown in Fig. 3, the all-solid-state thermal transistor 100 is in an as-grown state, and is made of a Pt upper electrode 40 / CeO ２ It has a laminated structure of an active layer 20, a YSZ substrate 10, and a Pt lower electrode 30. The lower electrode 30 is grounded, and the upper electrode 40 is connected to a voltage terminal V.

[0022] First, when a negative voltage (-V) is applied to the voltage terminal V, electrons that enter the active layer 20 from the upper electrode 40 combine with oxygen in the active layer 20 to form O ２－ ions move toward the substrate 10. ２－ The ions pass through the porous lower electrode 30 and are separated into oxygen and electrons, and the oxygen is released into the air. As a result, the amount of oxygen in the active layer 20 decreases, and at least a portion of the cerium oxide in the active layer 20 is reduced to CeO ２ (fluorite structure) to CeO ２-δ (defective fluorite structure) (0<δ≦0.5, more preferably 0<δ≦0.3 due to the presence of a stable crystal structure) (reduced state).

[0023] Next, when a positive voltage (+V) is applied to the voltage terminal V, electrons move from the lower electrode 30 toward the upper electrode 40. At this time, the electrons combine with oxygen in the air in the porous lower electrode 30, forming O ２－ The ions move from the substrate 10 toward the active layer 20 .

[0024] Since the upper electrode 40 is a normal dense metal electrode (not porous), O ２－ Ions do not pass through the upper electrode 40, and only electrons pass through the upper electrode 40 to the outside, leaving oxygen in the active layer 20. As a result, the cerium oxide in the active layer 20 is oxidized by the remaining oxygen, and CeO ２-δ is CeO ２ (oxidized state).

[0025] 4 is a photograph showing the measurement state in which a voltage is applied to the all-solid-state thermal transistor 100 (5 mm x 5 mm) to confirm its operation, and a voltage is applied from external terminals (GND, V) between the upper electrode 40 and the lower electrode 30. The all-solid-state thermal transistor 100 is placed on a heater and energized while heated to 280°C.

[0026] As described above, in the all-solid-state thermal transistor 100 according to the embodiment of the present invention, by applying a positive or negative voltage between the lower electrode 30 and the upper electrode 40 and passing a constant current for a certain period of time, at least a part of the cerium oxide in the active layer 20 is converted to an oxidized state (CeO ２ ) and reduced state (CeO ２-δ , 0<δ≦0.5).

[0027] As described above, the substrate 10 of the solid electrolyte layer is made of CeO ２ In this case, the substrate 10 can serve as both the solid electrolyte layer and the active layer. ２ At least a part of the ２ ) and reduced state (CeO ２-δ , 0<δ≦0.5).

[0028] 5 shows the results of X-ray diffraction measurements when a voltage is applied to the all-solid-state thermal transistor 100, showing the change in the crystal structure of the active layer 20. In FIG. 5, the horizontal axis represents the scattering vector, the vertical axis represents the intensity, (a) represents the as-grown state, (b) represents the state during reduction from the oxidized state to the reduced state, (c) represents the reduced state, (d) represents the state during oxidation from the reduced state to the oxidized state, and (e) represents the oxidized state.

[0029] In the as-grown state, as shown in FIG. 5(a), the CeO ２ The peaks of the YSZ substrate and the YSZ substrate are observed.

[0030] When a negative voltage is applied to the upper electrode 40 of the as-grown all-solid-state thermal transistor (the lower electrode 30 is grounded), as shown in FIG. 5(b), CeO ２－δ The vertical axis on the left is the electron density Q, and as the electron density increases, that is, as the application time elapses, the CeO ２－δ The strength of is increasing.

[0031] FIG. 5(c) shows the change in the CeO ２－δ This is an X-ray diffraction pattern in a state where the intensity of CeO is almost constant (reduced state). ２ In addition to the peak of CeO ２－δ A peak of is observed.

[0032] FIG. 5(d) shows the case where a positive voltage is applied to the upper electrode 40 of the all-solid-state thermal transistor in the reduced state (the lower electrode 30 is grounded). As the electron density Q increases, that is, as the application time passes, the CeO ２－δ The intensity of the ions decreases and eventually disappears (oxidized state).

[0033] Figure 5(e) shows the X-ray diffraction pattern of the oxidized state. ２－δ The peak of CeO ２ There is only a peak of .

[0034] 5, it can be seen that the cerium oxide active layer 20 can be oxidized and reduced while maintaining a strong crystal orientation. The diffraction pattern of the YSZ substrate is almost constant.

[0035] 6 shows the TDTR decay curve of the all-solid-state thermal transistor according to the embodiment of the present invention, with the horizontal axis representing delay time and the vertical axis representing phase signal. In FIG. 6, the increase in the amplitude phase signal near the delay time of 0 ns is due to the upper electrode 40 being heated by the pulsed laser light. The subsequent decrease in the phase signal over time is due to heat penetration from the upper electrode 40 to the active layer 20. An enlarged view of the portion up to the delay time of 15 ns is also shown in FIG. 6.

[0036] In Figure 6, the upper decay curve shows the case where the active layer 20 is in a reduced state, and the lower decay curve shows the case where the active layer 20 is in an oxidized state. As is clear from Figure 6, as the active layer 20 approaches the oxidized state from the reduced state, the decay of the phase signal becomes faster and the thermal conductivity increases. In other words, the thermal conductivity of the all-solid-state thermal transistor 100 can be controlled by changing the state of the active layer 20 between the oxidized state and the reduced state.

[0037] 7 shows the change in thermal conductivity over time of the all-solid-state thermal transistor according to the embodiment of the present invention, which shows the change in thermal conductivity when a positive voltage is applied to the upper electrode 40 to change the active layer 20 from a reduced state to an oxidized state. In FIG. 7, the horizontal axis represents electron density and the vertical axis represents thermal conductivity. In the reduced state where the electron density is 0, the thermal conductivity is approximately 2.5 Wm －１ K －１ The thermal conductivity increases as the electron density increases, i.e., as the active layer 20 is oxidized by applying a voltage. －１ K －１ The thermal conductivity is saturated at

[0038] From the results of FIG. 7, by using the all-solid-state thermal transistor according to the embodiment of the present invention, the active layer 20 is changed between a reduced state and an oxidized state, and a current of about 2.5 Wm －１ K －１ Approximately 12Wm －１ K －１ Up to about 9.5Wm －１ K －１ It can be seen that the thermal conductivity can be changed.

[0039] Figure 8 shows the TDTR decay curves in the reduced state (OFF state) and the oxidized state (ON state) of Figure 6. The decay curves are clearly different between the reduced state (OFF state) and the oxidized state (ON state), indicating a change in thermal conductivity.

[0040] 9 shows the thermal conductivity cycle characteristics of the all-solid-state thermal transistor according to the embodiment of the present invention, where the horizontal axis represents the number of cycles and the vertical axis represents the thermal conductivity. As can be seen from FIG. 9, the thermal conductivity changes with good reproducibility within a range of five cycles. The average thermal conductivity in the ON state (oxidized state) is 12 Wm －１ K －１ The average thermal conductivity in the OFF state (reducing state) is 2.5 Wm －１ K －１ ON / OFF ratio: 4.8, variation: 9.5 Wm －１ K －１ It is as follows.

[0041] Figure 10 shows a comparison of the change in thermal conductivity between conventional electrolyte-type thermal transistors [1] to [4] and the all-solid-state thermal transistor according to the embodiment of the present invention. The sources of [1] to [4] are as follows:

[0042] [1] Cho, J. et al. Electrochemically Tunable Thermal Conductivity of Lithium Cobalt Oxide. Nat. Commun. 5, 4035 (2014). [2] Lu, Q. et al. Bi-directional Tuning of Thermal Transport in SrCoOx with Electrochemically Induced Phase Transitions. Nature Mater. 19, 655-662 (2020). [3] Ning, S. et al. Anomalous Defect Dependence of Thermal Conductivity in Epitaxial WO3 Thin Films. Adv. Mater. 31, e1903738 (2019). [4] Zhang, Y. et al. Wide-range continuous tuning of the thermal conductivity of La0.5Sr0.5CoO3-δ films via room-temperature ion-gel gating. Nat. Commun. 14, 2626 (2023)

[0043] As is clear from FIG. 10, the all-solid-state thermal transistor according to the embodiment of the present invention exhibits a large change in thermal conductivity (9.5 Wm) compared to the conventional electrolyte type thermal transistor. －１ K －１ ), and an ON / OFF ratio of 4.8. The thermal conductivity in the OFF state is equivalent to that of a conventional electrolyte-type thermal transistor.

[0044] Next, the switching stability (cycle life) of the all-solid-state thermal transistor according to the embodiment of the present invention will be described using Figures 11 to 14. Figure 11 shows the change in the crystalline structure of the active layer when voltage is repeatedly applied to the all-solid-state thermal transistor 100, as investigated using surface X-ray diffraction. In Figure 11, the horizontal axis represents the scattering vector, and the vertical axis represents its intensity.

[0045] The electrochemical reduction / oxidation treatment was carried out by applying a constant current of −10 μA / +10 μA. These treatments reduced the electron density Q to −1.5×10 in the case of reduction. ２２ cm －３ , and 0.9 × 10 for oxidation. ２２ cm －３ The switching process was carried out up to 100 cycles. Figure 11 shows the X-ray diffraction results when the switching process was carried out 0, 1, 10 to 100 times (in increments of 10). In Figure 11, the solid line indicates the ON (oxidation) state, and the dashed line indicates the OFF (reduction) state.

[0046] As can be seen from FIG. 11, in the on (oxidized) state, the a-phase (CeO ２ In the off (reduced) state, only the diffraction peak of the a phase was observed, whereas in the off (reduced) state, the diffraction peak of the a phase was weakened and the diffraction peaks of the reduced b, c, and d phases were observed. It is noteworthy here that no deterioration of the crystal structure was observed up to 100 cycles, indicating that the crystal structure of the active layer changed reproducibly over 100 switching cycles.

[0047] 12 and 13 show examples of TDTR decay curves (1, 50, and 100 cycles) measured at room temperature when a voltage is repeatedly applied to the all-solid-state thermal transistor 100. In FIGS. 12 and 13, the horizontal axis represents delay time, and the vertical axis represents phase signal. From FIG. 12, it can be seen that in the off (reduced) state, the thermal conductivity (κ) for 1 cycle, 50 cycles, and 100 cycles is 2.3 Wm －１ K －１ , 1.9Wm －１ K －１ , 2.2Wm －１ K －１ In addition, from FIG. 13, in the ON (oxidation) state, the thermal conductivity (κ) at 1 cycle, 50 cycles, and 100 cycles was 2.3 Wm －１ K －１ , 1.9Wm －１ K －１ , 2.2Wm －１ K －１ The actual measurements and simulations showed good agreement.

[0048] Figure 14 shows the thermal conductivity (upper graph) and the switching width and on / off ratio (lower graph) obtained from the TDRD measurement results. In Figure 14, the horizontal axis represents the number of cycles, and the vertical axis represents the thermal conductivity (upper graph), switching width, and on / off ratio (lower graph).

[0049] As shown in the upper graph of Figure 14, the average thermal conductivity in the ON (oxidized) state was 12.5 ± 0.85 Wm －１ K －１ The average thermal conductivity in the off (reduced) state was 2.2 ± 0.36 Wm －１ K －１ As shown in the lower diagram of FIG. 14, the on / off ratio was 5.8±0.85 and the κ switching width was 10.3±0.98 Wm －１ K －１ This is what happened.

[0050] Thus, in the all-solid-state thermal transistor 100 according to the embodiment of the present invention, the switching of the crystal structure and thermal conductivity remained stable for at least 100 cycles. The excellent cycle characteristics of this thermal transistor are due to the a-phase (CeO ２ ) and the b, c, and d phases (CeO ２－δ This is thought to be due to the similarity in the crystal structure of

[0051] As described above, in the all-solid-state thermal transistor 100 according to the embodiment of the present invention, by passing a current through the active layer 20, at least a part of the cerium oxide in the active layer 20 is converted into oxidized CeO ２ (fluorite structure) to reduced CeO ２-δ By reversibly changing the structure to a (defective fluorite structure) (0<δ≦0.5, more preferably 0<δ≦0.3 because a stable crystal structure exists), a large change in thermal conductivity (10.3±0.98 Wm －１ K －１ ), an ON / OFF ratio of (5.8±0.85) is obtained.

[0052] Furthermore, the change in thermal conductivity is reproducible, and good switching characteristics can be obtained as an all-solid-state thermal transistor.

[0053] Furthermore, because it is an all-solid-state structure that does not use an electrolyte, there is no need to seal it in a container or the like as with an electrolyte type, and it is also possible to integrate the electrodes.

[0054] The thermal conductivity of the all-solid-state thermal transistor of the present invention can be electrically controlled, which makes it possible to apply it to shutters that change the infrared transmittance, displays that utilize differences in infrared transmittance, thermal control devices for semiconductor integrated circuits, phonon logic circuits, etc.

[0055] 10 Substrate 20 Active layer 30 Lower electrode 40 Upper electrode 100 All-solid-state thermal transistor

Claims

1. A thermal transistor having a laminated structure in which a solid electrolyte layer and an active layer are sandwiched between a pair of electrodes, and utilizing the fact that the active layer is oxidized or reduced by passing a current between the electrodes, wherein the active layer is made of cerium oxide.

2. The thermal transistor according to claim 1, wherein the solid electrolyte layer and the active layer are both made of cerium oxide.

3. The cerium oxide is CeO ２－ｘ 3. The thermal transistor according to claim 1, wherein x is 0≦x≦0.

5.

4. The cerium oxide is CeO in its oxidized state. ２ and in the reduced state, CeO ２ At least a part of which is CeO ２－δ 3. The thermal transistor according to claim 1, wherein the temperature is reduced to (0<δ≦0.5).

5. The cerium oxide is CeO in its oxidized state. ２ and in the reduced state, CeO ２ At least a part of which is CeO ２－δ 3. The thermal transistor according to claim 1, wherein the temperature is reduced to (0<δ≦0.3).

6. A thermal transistor according to claim 1 or 2, characterized in that the crystal structure of at least a part of the active layer changes when a current is passed between the electrodes.

7. A thermal transistor according to claim 1 or 2, wherein the current is a constant current that flows for a fixed period of time.

8. The thermal transistor according to claim 1, wherein the solid electrolyte layer is made of an oxide containing at least one metal selected from the group consisting of Y, Zr, Ce, and Gd.

9. A thermal transistor according to claim 1 or 2, wherein one of the pair of electrodes in contact with the solid electrolyte layer is porous.

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