Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a well region which is provided so as to divide an outer peripheral region and an IGBT region; a plurality of field regions which are provided on the peripheral side of a chip with a space between the well region and the plurality of field regions and which are spaced apart from one another; and a cathode region which constitutes the well region and a diode. A plurality of corners of the well region each include a well-side curved portion. A plurality of corners of the plurality of field regions each include a field-side curved portion. The curvature of the outer edge of the well-side curved portion differs from the curvature of the inner edge of the innermost field-side curved portion. The cathode region is disposed so as to face, in the thickness direction of the chip, a region which is located more on the outer well connection electrode side than a gate line electrode with a space between the region and the gate line electrode.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device including a reverse conducting-insulating gate bipolar transistor (RC-IGBT).

[0003] JP 2018-120990 A

[0004] [Summary] There is a demand for improved electrical characteristics of semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a chip having a first main surface and a second main surface opposite to the first main surface, a peripheral region provided on a peripheral edge of the first main surface, an IGBT region provided inside the peripheral region in the first main surface, a well region of a first conductivity type provided in a surface layer of the first main surface in the peripheral region so as to partition the IGBT region, and a plurality of first conductivity type fillets disposed at intervals from the well region on the peripheral side of the chip in the surface layer of the first main surface in the peripheral region. a second conductivity type cathode region provided in a surface layer portion of the second main surface of the peripheral region and constituting a diode together with the well region; an insulating film covering at least the well region; an emitter electrode disposed on the insulating film so as to be electrically connected to the well region; a collector electrode provided on the second main surface so as to be electrically connected to the cathode region; and a second conductivity type cathode region provided on the insulating film at a distance from an outer edge of the well region toward the IGBT region so as to face the well region in the thickness direction of the chip. and an outer well connection electrode buried in the insulating film so as to be connected to a region in the well region that is closer to the outer edge of the well region than the gate line electrode, wherein, when viewed from the thickness direction of the chip, the well region is annular and surrounds the IGBT region, and has a plurality of corner portions; when viewed from the thickness direction of the chip, each of the plurality of field regions is annular and surrounds the well region, and has a plurality of corner portions, each of the plurality of corner portions of the well region includes a well-side curved portion; and each of the plurality of corner portions in each of the plurality of field regions includes a field-side curved portion, the curvature of the outer edge of the well-side curved portion differs from the curvature of the inner edge of an innermost field-side curved portion that is the innermost field-side curved portion of the plurality of field-side curved portions; and the cathode region is arranged so as to face, in the thickness direction of the chip, at least a region in the corner portion of the well region that is spaced closer to the outer well connection electrode than the gate line electrode is.

[0006] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view showing an example layout within a first main surface of a chip. FIG. 3 is a schematic plan view showing an example layout of well regions, field regions, channel stop regions, and gate wiring. FIG. 4 is a schematic plan view showing an enlarged view of the dashed-dotted frame A in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 4. FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. 4. FIG. 7 is a schematic cross-sectional view of the semiconductor device taken along line F7-F7 in FIG. 4. FIG. 8 is a schematic plan view showing an enlarged view of the dashed-dotted frame B in FIG. 3. FIG. 9 is a schematic cross-sectional view of the semiconductor device taken along line F9-F9 in FIG. 8. FIG. 10 is a schematic plan view showing an enlarged view of the well region and its periphery in FIG. 8. FIG. 11 is a schematic plan view of the semiconductor device in the same region as FIG. 10. FIG. 12 is a graph showing the relationship between forward voltage and forward current when the position of the cathode region is changed. FIG. 13 is a graph showing the relationship between the placement position of the cathode region and the forward current, and is a graph for explaining a first setting example of the prohibited range, first allowed range, and second allowed range. FIG. 14 is a graph showing the relationship between the placement position of the cathode region and the forward current, and is a graph for explaining a second setting example of the prohibited range, first allowed range, and second allowed range. FIG. 15 is a graph showing the relationship between the peak surge current and the forward voltage when the placement position of the cathode region is adjusted. FIG. 16 is a schematic cross-sectional view showing the cross-sectional structure of the periphery of the chip together with the cathode region according to the second layout example. FIG. 17 is a schematic plan view showing an enlarged view of a portion of the semiconductor device of the comparative example corresponding to the dashed-dotted frame B in FIG. 3. FIG. 18 is a graph showing the relationship between the position of the periphery of the chip and the electric field strength when a collector-emitter voltage is applied in the semiconductor device of the comparative example. FIG. 19 is a graph showing the relationship between the position of the periphery of the chip and the electric field strength when a collector-emitter voltage is applied in the semiconductor device of the first embodiment. Fig. 20 is a schematic plan view showing an enlarged view of a portion of an exemplary semiconductor device according to the second embodiment, which corresponds to the dashed-dotted frame B in Fig. 3. Fig. 21 is a schematic plan view of the semiconductor device in the same region as Fig. 20.22 is a schematic cross-sectional view of the semiconductor device taken along line F22-F22 in FIG. 21. FIG. 23 is a schematic plan view showing an enlargement of a well region and its periphery in a semiconductor device of a modified example. FIG. 24 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. FIG. 25 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. FIG. 26 is a schematic cross-sectional view of a peripheral portion of a chip in a semiconductor device of a modified example. FIG. 27 is a schematic plan view showing an enlargement of a well region and its periphery in a semiconductor device of a modified example. FIG. 28 is a schematic plan view showing an enlargement of a well region and its periphery in a semiconductor device of a modified example. FIG. 29 is a schematic plan view showing an enlargement of a well region and its periphery in a semiconductor device of a modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in the present disclosure, "the dimensions (depth, width, length) of A are equal to the dimensions (depth, width, length) of B" or "the dimensions (depth, width, length) of A and the dimensions (depth, width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (depth, width, length) of A and the dimensions (depth, width, length) of B is, for example, within 10% of the dimensions (depth, width, length) of A. Furthermore, "the radius of curvature of A is equal to the radius of curvature of B" or "the radii of curvature of A and B are equal to each other" also includes a relationship in which the difference between the radii of curvature of A and B is, for example, within 10% of the radius of curvature of A. Furthermore, "the curvature of A is equal to the curvature of B" or "the curvature of A and B are equal to each other" also includes a relationship in which the difference between the curvature of A and B is, for example, within 10% of the ... Furthermore, "the central angle of A is equal to the central angle of B" or "the central angle of A and the central angle of B are equal to each other" also includes a relationship in which the difference between the central angle of A and the central angle of B is, for example, within 10% of the central angle of A. Furthermore, as used in the present disclosure, "the concentration of A is equal to the concentration of B" or "the concentration of A and the concentration of B are equal to each other" also includes a relationship in which the difference between the concentration of A and the concentration of B is, for example, within 10% of the concentration of A.

[0011] First Embodiment [Overall Configuration of Semiconductor Device] The overall configuration of a semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 to 9. FIG. 1 schematically illustrates the planar structure of the semiconductor device 10 according to the first embodiment. FIG. 2 schematically illustrates an example of the layout of various wirings in the semiconductor device 10 of FIG. 1. FIG. 3 schematically illustrates an example of the layout of a well region 54, a plurality of field regions 56, gate line wiring 70, and a cathode region 110, which will be described later. Note that FIG. 2 omits a field electrode 102 and a channel stop electrode 106, which will be described later. For convenience, FIG. 3 collectively illustrates a plurality of field regions 56 as a single region.

[0012] FIG. 4 is an enlarged view of the dashed-dotted box A in FIG. 3 , showing the planar structure of a portion of the chip 12. FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 4 . FIG. 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in FIG. 4 . FIG. 7 is a schematic cross-sectional view of the semiconductor device 10 taken along line F7-F7 in FIG. 4 . FIG. 8 is an enlarged view of the dashed-dotted box B in FIG. 3 , showing the planar structure of a corner portion of the periphery of the chip 12 (described later). To facilitate understanding of the drawing, FIG. 8 omits the emitter pad electrode 94, emitter line electrode 96, field electrode 102, and well connection electrodes 84A and 84B (described later). FIG. 9 is a schematic cross-sectional view of the semiconductor device 10 taken along line F9-F9 in FIG. 8 .

[0013] 1 to 3, the semiconductor device 10 is an RC-IGBT (Reverse Conducting-IGBT) semiconductor device that includes an RC-IGBT (Insulated Gate Bipolar Transistor) that is integrated with an IGBT and a diode. The diode is a freewheeling diode for the IGBT. Such an RC-IGBT semiconductor device may also be referred to as a semiconductor switching device.

[0014] As shown in FIG. 1 , the semiconductor device 10 includes a hexahedral chip 12. The chip 12 can also be considered to be flat with its thickness in the Z direction. The chip 12 may also be referred to as a "semiconductor chip." In the first embodiment, the chip 12 has a single-layer structure formed of a silicon single crystal substrate (semiconductor substrate). The chip 12 has a first main surface 12A, a second main surface 12B (see FIG. 5 ) opposite the first main surface 12A, and first to fourth side surfaces 12C to 12F connecting the first main surface 12A and the second main surface 12B. Hereinafter, a view of the semiconductor device 10 from the Z direction will be referred to as a "planar view." Furthermore, directions perpendicular to the Z direction that are perpendicular to each other will be referred to as the "X direction" and the "Y direction."

[0015] Both the first main surface 12A and the second main surface 12B are rectangular in plan view. The first side surface 12C and the second side surface 12D constitute both end surfaces of the chip 12 in the Y direction. Both the first side surface 12C and the second side surface 12D extend in the X direction in plan view. The third side surface 12E and the fourth side surface 12F constitute both end surfaces of the chip 12 in the X direction. Both the third side surface 12E and the fourth side surface 12F extend in the Y direction in plan view.

[0016] As shown in FIG. 2, the semiconductor device 10 includes an IGBT region 14 provided in an inner portion of the first main surface 12A. The IGBT region 14 is a region having an IGBT structure and may be referred to as an "active region." In one example, the IGBT region 14 is polygonal in shape with four sides parallel to the first to fourth side surfaces 12C to 12F in a plan view. In the example shown in FIG. 2, the IGBT region 14 includes a recess recessed from the center in the Y direction of the side along the third side surface 12E toward the fourth side surface 12F in a plan view. The recess is polygonal in shape in a plan view. In the example shown in FIG. 2, the recess is rectangular in shape in a plan view.

[0017] The semiconductor device 10 includes a pad region 16 provided in a region defined by recesses in the IGBT region 14 on the first main surface 12A, and an outer periphery region 18 provided on the periphery of the chip 12. The pad region 16 is polygonal in plan view. In the example shown in FIG. 2, the pad region 16 is quadrangular in plan view. The outer periphery region 18 is provided in an annular shape extending along the first to fourth side surfaces 12C to 12F so as to surround the IGBT region 14 in plan view. In the example shown in FIG. 2, the outer periphery region 18 is quadrangular in plan view. The portion of the outer periphery region 18 extending along the third side surface 12E is connected to the pad region 16. It can be said that the IGBT region 14 is provided inside the outer periphery region 18 on the first main surface 12A.

[0018] 5 , the semiconductor device 10 includes an n-type (second conductivity type) drift region 20 provided inside the chip 12. The drift region 20 is provided throughout the entire interior of the chip 12. In the first embodiment, the chip 12 is configured of an n-type semiconductor substrate (an n-type semiconductor chip). The drift region 20 is provided by utilizing the chip 12.

[0019] The semiconductor device 10 includes an n-type buffer region 22 provided in a surface layer portion of the second main surface 12B. In the first embodiment, the buffer region 22 is a layer extending along the entire second main surface 12B. The buffer region 22 is exposed from the first to fourth side surfaces 12C to 12F (see FIG. 2). The buffer region 22 has a higher n-type impurity concentration than the drift region 20. The presence or absence of the buffer region 22 is optional, and a configuration without the buffer region 22 may also be employed.

[0020] The semiconductor device 10 includes a p-type (first conductivity type) collector region 24 provided in a surface layer portion of the second main surface 12B. The collector region 24 is provided in a surface layer portion on the second main surface 12B side of the buffer region 22. In the first embodiment, the collector region 24 is a layer extending along the second main surface 12B over substantially the entire area of ​​the second main surface 12B.

[0021] The semiconductor device 10 includes a trench isolation structure 26 provided in the first main surface 12A to define the IGBT region 14. A gate potential is applied to the trench isolation structure 26. The trench isolation structure 26 surrounds the IGBT region 14 and separates the IGBT region 14 from the outer periphery region 18 and the pad region 16 (see FIG. 2 ). In the first embodiment, the trench isolation structure 26 is a polygonal ring shape having four sides parallel to the first to fourth side surfaces 12C to 12F in a plan view.

[0022] The trench isolation structure 26 may have a width of 0.5 μm or more and 5 μm or less. Here, the width of the trench isolation structure 26 can be defined by the dimension in a direction perpendicular to the direction in which the trench isolation structure 26 extends in a plan view. The width of the trench isolation structure 26 is preferably 1 μm or more and 2.5 μm or less. The trench isolation structure 26 may have a depth of 1 μm or more and 20 μm or less. Here, the depth of the trench isolation structure 26 can be defined by the dimension in the Z direction of the trench isolation structure 26, in other words, the distance in the Z direction between the first main surface 12A and the bottom wall of an isolation trench 28 described below. The depth of the trench isolation structure 26 is preferably 4 μm or more and 10 μm or less.

[0023] The trench isolation structure 26 includes an isolation trench 28, an isolation insulating film 30, and an isolation buried electrode 32. The isolation trench 28 is dug downward from the first main surface 12A toward the second main surface 12B, thereby defining the wall surface of the trench isolation structure 26. The isolation insulating film 30 is a film that extends along the wall surface of the isolation trench 28. The isolation insulating film 30 defines a recess space within the isolation trench 28.

[0024] The isolation insulating film 30 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The isolation insulating film 30 preferably has a single-layer structure formed of a single insulating film. It is particularly preferable that the isolation insulating film 30 include a silicon oxide film formed of an oxide of the chip 12.

[0025] The isolated buried electrode 32 is buried in the isolation trench 28 with the isolation insulating film 30 sandwiched therebetween. In the first embodiment, the isolated buried electrode 32 is made of conductive polysilicon. A gate potential is applied to the isolated buried electrode 32.

[0026] The semiconductor device 10 includes an IGBT structure 34 provided in the IGBT region 14. The IGBT structure 34 may also be referred to as a "FET (Field Effect Transistor) structure." The IGBT structure 34 includes a p-type base region 36 provided in the IGBT region 14 in a surface layer portion of the first main surface 12A. The base region 36 may also be referred to as a "body region" or a "channel region." The base region 36 is provided so as to be shallower than the trench isolation structure 26. That is, the base region 36 has a bottom located closer to the first main surface 12A than the bottom wall of the trench isolation structure 26. The base region 36 extends in a layered manner along the first main surface 12A. The base region 36 contacts the inner circumferential wall of the trench isolation structure 26.

[0027] The IGBT structure 34 includes a plurality of trench gate structures 38 provided on the first main surface 12A in the IGBT region 14. A gate potential is applied to the plurality of trench gate structures 38. The plurality of trench gate structures 38 penetrate the base region 36 to reach the drift region 20. As shown in FIG. 2 , the plurality of trench gate structures 38 are arranged at intervals in the X direction in a plan view. Each trench gate structure 38 has a strip shape extending in the Y direction in a plan view. In other words, the plurality of trench gate structures 38 are arranged in stripes extending in the Y direction.

[0028] Each trench gate structure 38 includes a first end 38A on one side (the first side surface 12C side) and a second end 38B on the other side (the second side surface 12D side) in the longitudinal direction (Y direction). The first end 38A and the second end 38B are mechanically and electrically connected to the trench isolation structure 26.

[0029] That is, the plurality of trench gate structures 38, together with the trench isolation structure 26, constitute one ladder-shaped trench gate structure 38. The connection portion connecting the trench isolation structure 26 and the trench gate structure 38 may be considered as part of the trench isolation structure 26 or may be considered as part of the trench gate structure 38.

[0030] The multiple trench gate structures 38 may be arranged at intervals of 0.5 μm to 5 μm in the X direction. The intervals between the multiple trench gate structures 38 are preferably 1 μm to 3 μm. Each trench gate structure 38 may have a width of 0.5 μm to 5 μm. Here, the width of the trench gate structure 38 can be defined by the dimension in a direction perpendicular to the direction in which each trench gate structure 38 extends in a plan view.

[0031] The width of each trench gate structure 38 is preferably 1 μm or more and 2.5 μm or less. The width of each trench gate structure 38 is preferably equal to the width of the trench isolation structure 26. Each trench gate structure 38 may have a depth of 1 μm or more and 20 μm or less. The depth of each trench gate structure 38 is preferably 4 μm or more and 10 μm or less. The depth of each trench gate structure 38 is preferably equal to the depth of the trench isolation structure 26. Here, the depth of the trench gate structure 38 can be defined by the dimension of the trench gate structure 38 in the Z direction, in other words, the distance in the Z direction between the first main surface 12A and the bottom wall of a gate trench 40 described below.

[0032] One trench gate structure 38 will be described below. As shown in FIG. 5 , the trench gate structure 38 includes a gate trench 40, a gate insulating film 42, and a buried gate electrode 44. The gate trench 40 is dug downward from the first main surface 12A toward the second main surface 12B to define the wall surface of the trench gate structure 38. In the first embodiment, the gate trench 40 communicates with the isolation trench 28 at both longitudinal ends thereof, that is, a first end 38A and a second end 38B (both see FIG. 2 ). Specifically, as shown in FIG. 4 , the sidewall of the gate trench 40 communicates with the sidewall of the isolation trench 28, and the bottom wall of the gate trench 40 communicates with the bottom wall of the isolation trench 28.

[0033] As shown in FIGS. 4 and 5 , the gate insulating film 42 is in the form of a film that extends along the wall surface of the gate trench 40. The gate insulating film 42 defines a recess space within the gate trench 40. The gate insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The gate insulating film 42 preferably has a single-layer structure formed of a single insulating film. It is particularly preferable that the gate insulating film 42 include a silicon oxide film formed of an oxide of the chip 12. In the first embodiment, the gate insulating film 42 is formed of the same insulating film as the isolation insulating film 30. The gate insulating film 42 is connected to the isolation insulating film 30 at the communicating portion between the isolation trench 28 and the gate trench 40.

[0034] The buried gate electrode 44 is buried in the gate trench 40 with the gate insulating film 42 sandwiched therebetween. In the first embodiment, the buried gate electrode 44 is made of conductive polysilicon. A gate potential is applied to the buried gate electrode 44. The buried gate electrode 44 is connected to the isolation buried electrode 32 at the communicating portion between the isolation trench 28 and the gate trench 40.

[0035] 5 , the IGBT structure 34 includes a plurality of n-type emitter regions 46 provided in a surface portion of the base region 36 in a region along the plurality of trench gate structures 38. The plurality of emitter regions 46 are arranged on both sides of the plurality of trench gate structures 38. Each emitter region 46 has a strip shape extending along the plurality of trench gate structures 38 in a plan view. Each emitter region 46 has a higher n-type impurity concentration than the drift region 20. It is preferable that the emitter regions 46 are not provided in a region sandwiched between the trench isolation structure 26 and the trench gate structures 38 in the surface portion of the base region 36.

[0036] The IGBT structure 34 includes a plurality of contact holes 48 provided in the first main surface 12A so as to expose the emitter regions 46. The plurality of contact holes 48 are respectively provided in regions between pairs of adjacent trench gate structures 38 that are spaced apart from one another among the plurality of trench gate structures 38. In the first embodiment, each contact hole 48 is provided so that the opening width is constant from the opening toward the bottom wall. Note that each contact hole 48 may also be provided so that the opening width narrows from the opening toward the bottom wall.

[0037] In the first embodiment, the multiple contact holes 48 penetrate the emitter region 46 to reach the base region 36. Note that the multiple contact holes 48 may be spaced from the bottom of the emitter region 46 toward the first main surface 12A so as not to reach the base region 36. Each contact hole 48 has a strip shape extending along the multiple trench gate structures 38 in a plan view. As shown in FIG. 7 , the multiple contact holes 48 are arranged spaced apart from the trench isolation structure 26 in the longitudinal direction (Y direction). Therefore, the multiple contact holes 48 are shorter in the longitudinal direction (Y direction) than the multiple trench gate structures 38 (see FIG. 6 ).

[0038] 5 , the IGBT structure 34 includes a plurality of p-type contact regions 50 provided in regions different from the plurality of emitter regions 46 in the surface layer portion of the base region 36. Each of the plurality of contact regions 50 has a strip shape extending along the corresponding contact hole 48 in a plan view. The bottom of each of the plurality of contact regions 50 is provided in a region between the bottom wall of the corresponding contact hole 48 and the bottom of the base region 36. Each contact region 50 has a higher p-type impurity concentration than the base region 36.

[0039] As shown in FIG. 3 , the semiconductor device 10 includes a p-type pad well region 52 provided in the surface layer portion of the first main surface 12A in the pad region 16. The pad well region 52 defines the IGBT region 14. The pad well region 52 may also be referred to as a "pad anode region." In the first embodiment, the pad well region 52 has a higher p-type impurity concentration than the base region 36 (see FIG. 5 ). Note that the pad well region 52 may also have a lower p-type impurity concentration than the base region 36.

[0040] The pad well region 52 is provided in the pad region 16 at a distance from the periphery of the chip 12 toward the IGBT region 14. The pad well region 52 has a polygonal shape (a square shape in the first embodiment) that matches the pad region 16 in a plan view. The pad well region 52 contacts the trench isolation structure 26 (see FIG. 2). The pad well region 52 is provided so as to be deeper than the base region 36. Specifically, the pad well region 52 is provided so as to be deeper than the trench isolation structure 26 (the plurality of trench gate structures 38). The pad well region 52 has a portion that covers the bottom wall of the trench isolation structure 26.

[0041] The pad well region 52 has a peripheral portion that extends from the pad region 16 into the IGBT region 14. The peripheral portion of the pad well region 52 has a portion that crosses the trench isolation structure 26 and covers the bottom walls of the plurality of trench gate structures 38. The peripheral portion of the pad well region 52 covers the sidewalls of the trench isolation structure 26 and the sidewalls of the plurality of trench gate structures 38 in the IGBT region 14, and is connected to the base region 36 in the surface layer portion of the first main surface 12A. In other words, the pad well region 52 is electrically connected to the base region 36 and the plurality of emitter regions 46 in the IGBT region 14.

[0042] As shown in FIGS. 5 to 8 , the semiconductor device 10 includes a p-type well region 54 provided in a surface layer portion of the first main surface 12A in the peripheral region 18. The well region 54 is provided so as to separate the IGBT region 14 from the peripheral region 18. The well region 54 may also be referred to as an "anode region." In the first embodiment, the well region 54 has a higher p-type impurity concentration than the base region 36. However, the well region 54 may also have a lower p-type impurity concentration than the base region 36. It is preferable that the well region 54 has the same p-type impurity concentration as the pad well region 52.

[0043] The well region 54 is provided at a distance from the periphery of the chip 12 toward the IGBT region 14. The well region 54 is a layer extending along the first main surface 12A. The well region 54 is exposed from the first main surface 12A. The well region 54 is strip-shaped extending along the IGBT region 14 in a plan view. Specifically, as shown in FIG. 3 , the well region 54 is annular (a square annular shape in the first embodiment) surrounding the IGBT region 14 in a plan view. The well region 54 has four sides parallel to the periphery of the chip 12. The well region 54 has multiple (four in the first embodiment) corner portions 55P and multiple (four in the first embodiment) linear portions 55Q connecting the multiple corner portions 55P. The linear portions 55Q connect adjacent corner portions 55P in the X direction or the Y direction. The straight line portion 55Q extends along the X direction or the Y direction in a plan view. The well region 54 has an inner edge 54A on the IGBT region 14 side and an outer edge 54B on the peripheral edge side of the chip 12.

[0044] The well region 54 is provided integrally with the pad well region 52 in a portion extending along the third side surface 12E. In other words, the well region 54 integrally includes the pad well region 52 extending from the outer periphery region 18 side to the pad region 16. The width of the well region 54 may be 10 μm or more and 100 μm or less. The width of the well region 54 is preferably 40 μm or more and 80 μm or less. Here, the width of the well region 54 can be defined by the dimension in a direction perpendicular to the direction in which the well region 54 extends in a plan view.

[0045] 5 , the well region 54 is provided so as to be deeper than the base region 36. Specifically, the well region 54 is provided so as to be deeper than the trench isolation structure 26 (plurality of trench gate structures 38). The well region 54 is in contact with the trench isolation structure 26. The well region 54 has a portion that covers the bottom wall of the trench isolation structure 26. The well region 54 has a portion that is drawn from the outer periphery region 18 to the IGBT region 14 and connected to the base region 36. Therefore, an inner edge 54A of the well region 54 is located within the IGBT region 14.

[0046] 6 and 7 , the well region 54 has a portion that crosses the trench isolation structure 26 and covers the bottom walls of the plurality of trench gate structures 38. The well region 54 covers the sidewalls of the trench isolation structure 26 and the sidewalls of the plurality of trench gate structures 38 in the IGBT region 14, and is connected to the base region 36 in the surface layer portion of the first main surface 12A. In other words, as shown in FIGS. 5 and 7 , an inner edge 54A of the well region 54 is electrically connected to the base region 36 and the emitter region 46 in the IGBT region 14.

[0047] 8 , semiconductor device 10 includes at least one p-type field region 56 provided in a surface layer portion of first main surface 12A in peripheral region 18. In one example, a plurality of field regions 56 (four in the first embodiment) are provided. The number of field regions 56 is optional and may be 1 to 20 (typically 3 to 10).

[0048] The multiple field regions 56 are provided between the periphery of the chip 12 and the well region 54, spaced apart from both the periphery of the chip 12 and the well region 54. Each field region 56 has a strip shape extending along the well region 54 in a plan view. In one example, as shown in FIG. 3 , each of the multiple field regions 56 is annular (in the first embodiment, a rectangular annular shape) surrounding the well region 54 in a plan view. Each of the multiple field regions 56 has a predetermined width. Each field region 56 has multiple (four in the first embodiment) corner portions 57P and multiple (four in the first embodiment) straight portions 57Q connecting the multiple corner portions 57P. The straight portions 57Q connect adjacent corner portions 57P in the X direction or the Y direction. The straight portions 57Q extend along the X direction or the Y direction in a plan view. 8 in the direction in which each field region 56 extends. In other words, each of the lines L1 and L2 is an imaginary line indicating the boundary between the corner portion 57P and the line portion 57Q.

[0049] Each field region 56 may have a p-type impurity concentration higher than that of the base region 36. Each field region 56 may have a p-type impurity concentration equal to that of the well region 54. In the first embodiment, the p-type impurity concentration of each field region 56 is constant in the width direction of the field region 56. Each field region 56 is in an electrically floating state. Here, the width direction of a field region 56 can be defined as the direction perpendicular to the direction in which the field region 56 extends in a plan view.

[0050] 8, the multiple field regions 56 include an innermost field region 56A that is closest to the well region 54, and field regions 56B to 56D that are arranged closer to the periphery of the chip 12 than the innermost field region 56A. Note that hereinafter, when the innermost field region 56A and the field regions 56B to 56D are not to be distinguished from each other, they may be simply referred to as field regions 56.

[0051] 9, each field region 56 is preferably provided so as to be deeper than the base region 36. Each field region 56 is preferably provided so as to be shallower than the well region 54. Each field region 56 is preferably provided so as to be shallower than the well region 54 by a depth of 0.1 μm to 1 μm (preferably 0.5 μm or less) relative to the depth position of the bottom of the well region 54, for example.

[0052] Each field region 56 is preferably provided at a constant depth. In the width direction of the field regions 56, the distance between adjacent field regions 56 (hereinafter referred to as the "spacing of field regions 56") is preferably arranged so that it gradually increases toward the periphery of the chip 12. Note that the spacing between the multiple field regions 56 may be equal to one another.

[0053] Each field region 56 preferably has a width WF that is smaller than the width of the well region 54. In one example, the widths of the field regions 56B to 56D are equal to one another. The width of the innermost field region 56A is equal to the width of the field regions 56B to 56D. Hereinafter, when there is no need to distinguish between the width of the innermost field region 56A and the width of the field regions 56B to 56D, they will simply be referred to as the "width WF of the field region 56." Furthermore, the width WF of the field region 56 (the width of the innermost field region 56A and the width of the field regions 56B to 56D) can be defined by the dimension in a direction perpendicular to the direction in which the field region 56 extends in a plan view.

[0054] The width WF of each field region 56 may be 1 μm or more and 50 μm or less. The width WF of each field region 56 may be set to a value within any of the following ranges: 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less. The width WF of each field region 56 is preferably 10 μm or more and 30 μm or less.

[0055] The spacing between the field regions 56 may be 10 μm or more and 30 μm or less. The spacing between the field regions 56 may be 10 μm or more and 20 μm or less. The spacing between the field regions 56 may be 10 μm or more and 15 μm or less.

[0056] The semiconductor device 10 includes an n-type channel stop region 58 provided in a surface layer portion of the first main surface 12A at a distance from the plurality of field regions 56 toward the periphery of the chip 12 in the peripheral region 18. The channel stop region 58 has a higher n-type impurity concentration than the drift region 20. The channel stop region 58 may be exposed from the first to fourth side surfaces 12C to 12F (see FIG. 3).

[0057] 3, the channel stop region 58 has a band shape extending along the periphery of the chip 12 in a plan view. In one example, the channel stop region 58 has a ring shape (a square ring shape in the first embodiment) surrounding the plurality of field regions 56 in a plan view. The channel stop region 58 is in an electrically floating state.

[0058] As shown in FIGS. 5 to 7 and 9 , the semiconductor device 10 includes an insulating film 60 that selectively covers the first main surface 12A. In the first embodiment, the insulating film 60 has a layered structure including a main surface insulating film 62 and an interlayer insulating film 64. The main surface insulating film 62 selectively covers the first main surface 12A in the IGBT region 14, the peripheral region 18, and the pad region 16 (see FIG. 3 ). The main surface insulating film 62 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The main surface insulating film 62 preferably has a single-layer structure composed of a single insulating film.

[0059] It is particularly preferable that the main surface insulating film 62 includes a silicon oxide film made of an oxide of the chip 12. In one example, as shown in Figures 5 and 6, the main surface insulating film 62 is made of the same insulating film as the gate insulating film 42. The main surface insulating film 62 covers the first main surface 12A so as to expose the trench isolation structure 26 and the plurality of trench gate structures 38.

[0060] Specifically, the main surface insulating film 62 is connected to the isolation insulating film 30 and the gate insulating film 42. On the other hand, the main surface insulating film 62 exposes the isolation buried electrode 32 and the gate buried electrode 44. The main surface insulating film 62 covers the pad well region 52 (see FIG. 3 ), the well region 54, the plurality of field regions 56, and the channel stop region 58 in the pad region 16 and the peripheral region 18.

[0061] The interlayer insulating film 64 covers the main surface insulating film 62. The interlayer insulating film 64 is thicker than the main surface insulating film 62. The interlayer insulating film 64 may have a single-layer structure composed of a single insulating film, or a stacked structure including multiple insulating films. The interlayer insulating film 64 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The interlayer insulating film 64 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films.

[0062] The interlayer insulating film 64 covers the main surface insulating film 62 in the IGBT region 14, the peripheral region 18, and the pad region 16. The interlayer insulating film 64 covers the main surface insulating film 62, the trench isolation structure 26, and the plurality of trench gate structures 38 in the IGBT region 14. As shown in FIG. 9 , the interlayer insulating film 64 covers the pad well region 52, the well region 54, the plurality of field regions 56, and the channel stop region 58 with the main surface insulating film 62 sandwiched therebetween in the pad region 16 (see FIG. 3 ) and the peripheral region 18.

[0063] 3, the semiconductor device 10 includes a gate wiring 66 arranged in the form of a film inside the insulating film 60. In the first embodiment, the gate wiring 66 is made of a conductive polysilicon film. In one example, as shown in FIGS. 3 and 6, the gate wiring 66 includes a gate pad wiring 68, a gate line wiring 70, and a plurality of gate connection wirings 72. The gate line wiring 70 may also be referred to as a "gate finger wiring."

[0064] As shown in FIG. 3 , the gate pad wiring 68 is disposed within a portion of the insulating film 60 that covers the pad region 16. The gate pad wiring 68 faces the pad well region 52 in the thickness direction (Z direction) of the chip 12. Specifically, the gate pad wiring 68 is disposed in the form of a film on the main surface insulating film 62 and is covered by the interlayer insulating film 64 (see FIG. 6 ). The gate pad wiring 68 has a polygonal shape (a quadrangular shape in the first embodiment) that matches the pad region 16 in a plan view. The peripheral portion of the gate pad wiring 68 may be located within the pad region 16.

[0065] The peripheral portion of the gate pad wiring 68 may be drawn from the pad region 16 toward the IGBT region 14. In this case, the peripheral portion of the gate pad wiring 68 may be drawn from above the main surface insulating film 62 onto a portion of the trench isolation structure 26 (see FIG. 6) that defines the pad region 16, and may be connected to the isolated buried electrode 32 (see FIG. 6). The peripheral portion of the gate pad wiring 68 may also cover a portion (first end 38A and second end 38B (see FIG. 2)) of the plurality of trench gate structures 38, and may be connected to the plurality of buried gate electrodes 44 (see FIG. 6).

[0066] The gate line wiring 70 is disposed inside a portion of the insulating film 60 that covers the outer periphery region 18. As shown in FIGS. 5 to 7 , the gate line wiring 70 faces the well region 54 in the thickness direction (Z direction) of the chip 12. Specifically, the gate line wiring 70 is disposed in the form of a film on the main surface insulating film 62 and is covered by the interlayer insulating film 64. In the first embodiment, the gate line wiring 70 is disposed only in the portion that covers the well region 54. That is, the gate line wiring 70 faces the inner portion of the well region 54, spaced apart from the outer edge 54B and the inner edge 54A of the well region 54 in a plan view. Moreover, the entire area of ​​the gate line wiring 70 faces the well region 54 across the main surface insulating film 62.

[0067] As shown in FIG. 3 , the gate line wiring 70 extends in a strip shape along the well region 54 in a plan view. The gate line wiring 70 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the gate line wiring 70 is strip-shaped extending along the first to fourth side surfaces 12C to 12F in a plan view. The gate line wiring 70 defines the IGBT region 14 from four directions. The gate line wiring 70 may be strip-shaped or strip-shaped with edges so as to surround the IGBT region 14 in a plan view. In one example, the gate line wiring 70 is ring-shaped (a square ring-shaped in the first embodiment) so as to surround the IGBT region 14 in a plan view.

[0068] The gate line wiring 70 is provided integrally with the gate pad wiring 68 in a portion extending along the third side surface 12E. In other words, the gate line wiring 70 integrally includes the gate pad wiring 68 drawn from the peripheral region 18 to the pad region 16. The gate line wiring 70 has a width less than the width of the well region 54. The width of the gate line wiring 70 may be 10 μm or more and 100 μm or less. The width of the gate line wiring 70 is preferably 15 μm or more and 60 μm or less. Here, the width of the gate line wiring 70 can be defined by the dimension in a direction perpendicular to the direction in which the gate line wiring 70 extends in a plan view.

[0069] 4 and 6 , the plurality of gate connection wirings 72 are disposed inside the insulating film 60 so as to electrically connect the gate line wiring 70 to the plurality of trench gate structures 38. The plurality of gate connection wirings 72 are drawn from a portion of the gate line wiring 70 extending along the first side surface 12C (see FIG. 3 ) toward the first ends 38A of the plurality of trench gate structures 38. The plurality of gate connection wirings 72 are drawn from a portion of the gate line wiring 70 extending along the second side surface 12D (see FIG. 3 ) toward the second ends 38B of the plurality of trench gate structures 38 (see FIG. 2 ).

[0070] The plurality of gate connection wirings 72 are arranged at intervals along the gate line wiring 70 on the first side surface 12C side. Each gate connection wiring 72 on the first side surface 12C side is drawn out toward the trench isolation structure 26. The plurality of gate connection wirings 72 are preferably arranged at equal intervals in the X direction. The plurality of gate connection wirings 72 are drawn out from above the main surface insulating film 62 onto the trench isolation structure 26 on the first side surface 12C side and connected to the isolation buried electrode 32. In the first embodiment, the plurality of gate connection wirings 72 respectively cover the first ends 38A of the plurality of trench gate structures 38 and are connected to the plurality of gate buried electrodes 44.

[0071] The plurality of gate connection wirings 72 are arranged at intervals along the gate line wiring 70 on the second side surface 12D side. Each gate connection wiring 72 on the second side surface 12D side is drawn out toward the trench isolation structure 26. The plurality of gate connection wirings 72 are preferably arranged at equal intervals in the X direction. The plurality of gate connection wirings 72 are drawn out from above the main surface insulating film 62 onto the trench isolation structure 26 on the second side surface 12D side and connected to the isolated buried electrode 32.

[0072] In the first embodiment, the plurality of gate connection wirings 72 respectively cover the second ends 38B of the plurality of trench gate structures 38 and are connected to the plurality of gate buried electrodes 44. In the first embodiment, the gate wiring 66 is made of the same conductive material as the isolated buried electrode 32 and the plurality of gate buried electrodes 44. The gate wiring 66 includes lead-out portions that are led out from the isolated buried electrode 32 and the plurality of gate buried electrodes 44 onto the main surface insulating film 62 (see FIG. 6 ).

[0073] 5 , the semiconductor device 10 has a plurality of emitter openings 74 that expose the plurality of emitter regions 46 in a portion of the insulating film 60 that covers the IGBT region 14. The plurality of emitter openings 74 are provided in a one-to-one correspondence with the plurality of contact holes 48. The plurality of emitter openings 74 are each in communication with the corresponding contact holes 48. Each of the plurality of emitter openings 74 is strip-shaped and extends along the corresponding contact hole 48 in a plan view.

[0074] The semiconductor device 10 includes a plurality of emitter connection electrodes 76 embedded in the insulating film 60 so as to be electrically connected to the plurality of emitter regions 46. The plurality of emitter connection electrodes 76 are embedded in the plurality of emitter openings 74. The plurality of emitter connection electrodes 76 extend from the plurality of emitter openings 74 into the plurality of contact holes 48, thereby being electrically connected to the emitter regions 46 and the contact region 50.

[0075] Each emitter-connecting electrode 76 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each emitter-connecting electrode 76 has a stacked structure including a Ti-based metal film and a W-based metal film. The Ti-based metal may include at least one of a pure Ti film (a Ti film with a purity of 99% or more) and a Ti alloy film. The Ti alloy film may be a TiN film. The W-based metal may include at least one of a pure W film (a W film with a purity of 99% or more) and a W alloy film.

[0076] The Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or more) and an Al alloy film. The Al alloy film may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy. The Cu-based metal may include at least one of a pure Cu film (a Cu film with a purity of 99% or more) and a Cu alloy film. In the following description, the Ti-based metal film, the W-based metal film, the Al-based metal film, and the Cu-based metal film include the above.

[0077] The semiconductor device 10 includes at least one gate opening 78 (a plurality of gate openings in the first embodiment) that selectively exposes the gate line wiring 70 in a portion of the insulating film 60 that covers the gate line wiring 70. The number of gate openings 78 can be changed as desired. In one example, the insulating film 60 may be provided with a single gate opening 78.

[0078] 4 and 5 , the gate openings 78 are spaced apart from the inner and outer edges of the gate line wiring 70 to expose the inner portions of the gate line wiring 70. The gate openings 78 are spaced apart from one another from the IGBT region 14 toward the peripheral edge of the chip 12. Each gate opening 78 extends in a strip shape along the gate line wiring 70. Each gate opening 78 may be in an endless strip shape or a strip shape with edges that surrounds the IGBT region 14. In one example, each gate opening 78 is in a ring shape (a square ring shape in the first embodiment) that surrounds the IGBT region 14.

[0079] Although specific illustrations are omitted, the semiconductor device 10 may include at least one gate opening 78 (multiple in the first embodiment) that selectively exposes the gate pad wiring 68 in the portion of the insulating film 60 that covers the gate pad wiring 68.

[0080] The semiconductor device 10 includes at least one gate connection electrode 80 (multiple in the first embodiment) embedded in the insulating film 60 so as to be electrically connected to the gate line wiring 70. Each gate connection electrode 80 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each gate connection electrode 80 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0081] The plurality of gate connection electrodes 80 are embedded in the plurality of gate openings 78 in a one-to-one correspondence, respectively. The plurality of gate connection electrodes 80 are electrically connected to the gate line wiring 70 in the corresponding gate openings 78. When the insulating film 60 is provided with a gate opening 78 that exposes the gate pad wiring 68, the gate connection electrode 80 may be provided in the gate opening 78 so as to be electrically connected to the gate pad wiring 68.

[0082] The semiconductor device 10 includes a plurality of well openings 82 that selectively expose the well region 54 in a portion of the insulating film 60 that covers the peripheral region 18. The plurality of well openings 82 include at least one (multiple in the first embodiment) first well opening 82A that exposes the well region 54 on the IGBT region 14 side and at least one (multiple in the first embodiment) second well opening 82B that exposes the well region 54 on the peripheral edge side of the chip 12. The number of first well openings 82A and the number of second well openings 82B can be changed as desired. In one example, the insulating film 60 may be provided with a single first well opening 82A. In another example, the insulating film 60 may be provided with a single second well opening 82B.

[0083] The multiple first well openings 82A are provided at intervals from the middle of the well region 54 in the width direction (X direction in FIG. 5 ) toward the inner edge 54A of the well region 54. The multiple first well openings 82A selectively expose the region of the well region 54 on the inner edge 54A side. Specifically, the multiple first well openings 82A are provided at intervals from the gate line wiring 70 toward the inner edge 54A of the well region 54, thereby selectively exposing the inner edge portion of the well region 54.

[0084] 4 and 5 , the multiple first well openings 82A are provided at intervals from one another from the IGBT region 14 side toward the peripheral edge of the chip 12. Each first well opening 82A extends in a strip shape along the well region 54. Each first well opening 82A has a portion extending in the X direction along the well region 54 and a portion extending in the Y direction along the well region 54.

[0085] 4 , each first well opening 82A includes a plurality of segment openings 82AA provided at intervals so as to expose regions between the plurality of gate connection wirings 72 in a portion extending in the X direction. In other words, the plurality of segment openings 82AA are provided at intervals from the plurality of gate connection wirings 72 so as not to expose the plurality of gate connection wirings 72. The plurality of segment openings 82AA are arranged in a region surrounded by the trench isolation structure 26 (the plurality of trench gate structures 38), the gate line wirings 70, and the plurality of gate connection wirings 72. Each of the plurality of segment openings 82AA has a strip shape extending in the X direction.

[0086] 5, the plurality of second well openings 82B are provided at intervals from the middle of the well region 54 in the width direction toward the outer edge 54B of the well region 54. The plurality of second well openings 82B selectively expose the region of the well region 54 on the outer edge 54B side. Specifically, the plurality of second well openings 82B are provided at intervals from the gate line wiring 70 toward the outer edge 54B of the well region 54, thereby selectively exposing the outer edge portion of the well region 54.

[0087] 4 and 5 , the multiple second well openings 82B are provided at intervals from one another from the IGBT region 14 toward the peripheral edge of the chip 12. Each second well opening 82B extends in a strip shape along the well region 54. Each second well opening 82B may be in the shape of an endless strip or a strip with edges that surrounds the IGBT region 14. In one example, each second well opening 82B is in the shape of a ring (a square ring in the first embodiment) that surrounds the IGBT region 14.

[0088] 5, the semiconductor device 10 includes a plurality of well connection electrodes 84 embedded in the insulating film 60 so as to be electrically connected to the well regions 54. Each well connection electrode 84 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each well connection electrode 84 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0089] The multiple well-connecting electrodes 84 include at least one (multiple in the first embodiment) inner well-connecting electrode 84A and at least one (multiple in the first embodiment) outer well-connecting electrode 84B. Each inner well-connecting electrode 84A is connected to the well region 54 on the inner edge 54A side of the well region 54 (toward the IGBT region 14). Each outer well-connecting electrode 84B is connected to the well region 54 on the outer edge 54B side of the well region 54 (toward the peripheral edge of the chip 12). The number of inner well-connecting electrodes 84A and the number of outer well-connecting electrodes 84B can be changed as desired. In one example, there may be a single inner well-connecting electrode 84A. In another example, there may be a single outer well-connecting electrode 84B.

[0090] The multiple inner well connecting electrodes 84A are embedded in the multiple first well openings 82A in a one-to-one correspondence. That is, the multiple inner well connecting electrodes 84A are provided at intervals from the middle of the well region 54 in the width direction toward the inner edge 54A of the well region 54. The multiple inner well connecting electrodes 84A are electrically connected to a region of the well region 54 on the inner edge 54A side. Specifically, the multiple inner well connecting electrodes 84A are provided at intervals from the gate line wiring 70 in a region on the inner edge 54A side of the well region 54, and are thereby electrically connected to the inner edge of the well region 54.

[0091] The outer well connection electrodes 84B are embedded in the second well openings 82B in a one-to-one correspondence. That is, the outer well connection electrodes 84B are provided at intervals from the middle of the well region 54 in the width direction toward the outer edge 54B of the well region 54. Here, the width direction of the well region 54 can be defined as a direction perpendicular to the direction in which the well region 54 extends in a plan view. The outer well connection electrodes 84B are electrically connected to a region of the well region 54 on the outer edge 54B side. Specifically, the outer well connection electrodes 84B are provided at intervals in a region on the outer edge 54B side of the well region 54 from the gate line wiring 70, thereby electrically connecting to the outer edge of the well region 54.

[0092] As shown in FIG. 1 , the semiconductor device 10 includes a gate electrode 86 disposed on the insulating film 60. The gate electrode 86 is made of a conductive material different from that of the gate wiring 66 (see FIG. 3 ). In the first embodiment, the gate electrode 86 is made of a metal film. The gate electrode 86 has a lower resistance value than the gate wiring 66. The gate electrode 86 may be referred to as a "gate metal." The gate electrode 86 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the gate electrode 86 has a stacked structure including a Ti-based metal film and an Al-based metal film.

[0093] 1 and 2, the gate electrode 86 includes a gate pad electrode 88 and a gate line electrode 90. The gate line electrode 90 may also be referred to as a "gate finger electrode." The gate pad electrode 88 is disposed on a portion of the insulating film 60 that covers the gate pad wiring 68 (see FIG. 3). In one example, the gate pad electrode 88 has a polygonal shape (a quadrangular shape in the first embodiment) that matches the pad region 16 in a plan view.

[0094] The gate pad electrode 88 faces the gate pad wiring 68 across a part of the insulating film 60 (interlayer insulating film 64) in the thickness direction of the chip 12. The gate pad electrode 88 faces the pad well region 52 (see FIG. 3) across the insulating film 60 and the gate pad wiring 68 in the thickness direction of the chip 12. When the gate connection electrode 80 is connected to the gate pad wiring 68, the gate pad electrode 88 is electrically connected to the gate pad wiring 68 via the gate connection electrode 80 (see FIG. 5).

[0095] The gate pad electrode 88 may have a planar area equal to or larger than the planar area of ​​the pad region 16, or may have a planar area smaller than the planar area of ​​the pad region 16. The gate pad electrode 88 may have a planar area equal to or larger than the planar area of ​​the gate pad wiring 68, or may have a planar area smaller than the planar area of ​​the gate pad wiring 68.

[0096] 5 to 7, the gate line electrode 90 is disposed on the insulating film 60 on a portion thereof covering the gate line wiring 70. The gate line electrode 90 is provided integrally with the gate pad electrode 88 (see FIG. 2). The gate line electrode 90 is drawn out in a strip shape from the gate pad electrode 88 onto the insulating film 60. In the first embodiment, the gate line electrode 90 is drawn out from the gate pad electrode 88 onto the insulating film 60 to a region between the inner well connecting electrode 84A and the outer well connecting electrode 84B.

[0097] The gate line electrode 90 is arranged at a distance from the inner well connecting electrode 84A and the outer well connecting electrode 84B. The gate line electrode 90 covers the multiple gate connecting electrodes 80. That is, the gate line electrode 90 is arranged at a distance from the inner well connecting electrode 84A toward the outer edge 54B of the well region 54 (toward the peripheral edge of the chip 12). The gate line electrode 90 is arranged at a distance from the outer well connecting electrode 84B toward the inner edge 54A of the well region 54 (toward the IGBT region 14). The gate line electrode 90 is electrically connected to the gate line wiring 70 via the multiple gate connecting electrodes 80.

[0098] The gate line electrode 90 faces the gate line electrode 90 in the thickness direction of the chip 12, with a part of the insulating film 60 sandwiched therebetween. The gate line electrode 90 faces the well region 54 in the thickness direction of the chip 12, with the insulating film 60 and the gate line wiring 70 sandwiched therebetween. The gate line electrode 90 has a width less than the width of the well region 54. It is preferable that the gate line electrode 90 has a width less than the width of the gate line wiring 70. The width of the gate line electrode 90 can be changed as desired, and may be, for example, greater than or equal to the width of the gate line wiring 70.

[0099] As shown in FIGS. 1 and 2 , the gate line electrode 90 extends in a strip shape along the gate line wiring 70 in a plan view. The gate line electrode 90 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the gate line electrode 90 is strip-shaped extending along the first to fourth side surfaces 12C to 12F in a plan view. The gate line electrode 90 defines the IGBT region 14 from four directions. The gate line electrode 90 may be strip-shaped with no edges or strip-shaped with edges surrounding the IGBT region 14. In one example, the gate line electrode 90 is ring-shaped (a square ring-shaped in the first embodiment) surrounding the IGBT region 14, and has a pair of open ends 90A in the portion extending along the fourth side surface 12F.

[0100] The semiconductor device 10 includes an emitter electrode 92 disposed on the insulating film 60 and spaced apart from the gate electrode 86. The emitter electrode 92 is made of a different conductive material than the gate wiring 66. In the first embodiment, the emitter electrode 92 is made of a metal film. The emitter electrode 92 has a lower resistance than the gate wiring 66 (see FIG. 3). The emitter electrode 92 may also be referred to as an "emitter metal." The emitter electrode 92 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the emitter electrode 92 has a layered structure including a Ti-based metal film and an Al-based metal film. In other words, the emitter electrode 92 is made of the same material as the gate electrode 86.

[0101] The emitter electrode 92 includes an emitter pad electrode 94 and an emitter line electrode 96. The emitter line electrode 96 may also be referred to as an "emitter finger electrode." The emitter pad electrode 94 is disposed on a portion of the insulating film 60 that covers the IGBT region 14. In one example, the emitter pad electrode 94 is disposed spaced apart from the gate pad electrode 88 and the gate line electrode 90. The emitter pad electrode 94 has a polygonal shape having a recess that is recessed along the gate pad electrode 88 in a plan view.

[0102] 5 , the emitter pad electrode 94 collectively covers the plurality of trench gate structures 38 and the plurality of emitter connecting electrodes 76. The emitter pad electrode 94 faces the plurality of trench gate structures 38 with the insulating film 60 sandwiched therebetween. The emitter pad electrode 94 is electrically connected to the plurality of emitter regions 46 via the plurality of emitter connecting electrodes 76. The emitter pad electrode 94 includes an emitter leading portion 94A that is led from the IGBT region 14 to the outer periphery region 18 across the region immediately above the trench isolation structure 26 so as to face the well region 54 in the thickness direction of the chip 12.

[0103] The emitter lead-out portion 94A covers the region on the inner edge 54A side of the well region 54 relative to the middle portion in the width direction of the well region 54. Specifically, the emitter lead-out portion 94A covers the inner edge portion of the well region 54 at a distance from the gate line electrode 90 toward the IGBT region 14, and also collectively covers the multiple inner well connecting electrodes 84A. As a result, the emitter pad electrode 94 is electrically connected to the inner edge portion of the well region 54 via the multiple inner well connecting electrodes 84A.

[0104] 1 and 5, the emitter line electrode 96 is provided integrally with the emitter pad electrode 94. The emitter line electrode 96 is drawn out from the emitter pad electrode 94 onto the insulating film 60. Specifically, the emitter line electrode 96 passes through the region between the pair of open ends 90A of the gate line electrode 90 on the insulating film 60 and is drawn out in a strip shape from the emitter pad electrode 94 to the outer circumferential region 18.

[0105] 5 to 7, the emitter line electrode 96 is routed over the portion of the insulating film 60 that covers the well region 54. In other words, the emitter line electrode 96 faces the well region 54 across the insulating film 60 in the thickness direction of the chip 12. The emitter line electrode 96 is arranged at a distance from the gate line electrode 90 toward the outer edge 54B of the well region 54 (toward the peripheral edge of the chip 12) so as to cover the multiple outer well connection electrodes 84B. As a result, the emitter line electrode 96 is electrically connected to the outer edge of the well region 54 via the multiple outer well connection electrodes 84B.

[0106] As shown in FIGS. 1 and 2 , the emitter line electrode 96 extends in a strip shape along the outer edge 54B of the well region 54 in a plan view. The emitter line electrode 96 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the emitter line electrode 96 is strip-shaped extending along the first to fourth side surfaces 12C to 12F in a plan view. The emitter line electrode 96 defines the IGBT region 14 from four directions. The emitter line electrode 96 may be strip-shaped with or without edges that surround the IGBT region 14. In one example, the emitter line electrode 96 is ring-shaped (a square ring-shaped electrode in the first embodiment) that surrounds the IGBT region 14. 1 and 2, the emitter line electrode 96 has a plurality of (four in the first embodiment) corner portions 97P and a plurality of (four in the first embodiment) straight line portions 97Q connecting the plurality of corner portions 97P. The straight line portions 97Q connect the corner portions 97P adjacent to each other in the X direction or the Y direction. The straight line portions 97Q extend along the X direction or the Y direction in a plan view.

[0107] 9 , the insulating film 60 includes at least one field opening 98 (multiple in the first embodiment) that selectively exposes each field region 56 in the peripheral region 18. The multiple field openings 98 expose corresponding field regions 56 in a one-to-many correspondence. Note that a single field opening 98 may expose corresponding field regions 56 in a one-to-one correspondence. The multiple field openings 98 are strip-shaped extending along the corresponding field regions 56. In one example, the multiple field openings 98 are annular (square annular in the first embodiment) extending along the corresponding field regions 56.

[0108] The semiconductor device 10 includes at least one field connection electrode 100 (multiple in the first embodiment) embedded in an insulating film 60 so as to be electrically connected to a corresponding field region 56. Each field connection electrode 100 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each field connection electrode 100 has a layered structure including a Ti-based metal film and a W-based metal film.

[0109] The plurality of field connection electrodes 100 are embedded in the plurality of field openings 98 in a one-to-one correspondence, respectively. The plurality of field connection electrodes 100 are electrically connected to the corresponding field regions 56 in the corresponding field openings 98. In the first embodiment, the plurality of field connection electrodes 100 are in an electrically floating state.

[0110] The semiconductor device 10 includes a plurality of field electrodes 102 provided on the insulating film 60 in the peripheral region 18. The plurality of field electrodes 102 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In one example, each field electrode 102 may have a stacked structure including a Ti-based metal film and a W-based metal film. The plurality of field electrodes 102 are in an electrically floating state.

[0111] The plurality of field electrodes 102 are provided in one-to-one correspondence with the corresponding field regions 56. Each field electrode 102 collectively covers the corresponding plurality of field connection electrodes 100. Each field electrode 102 is electrically connected to the corresponding field region 56 via the corresponding plurality of field connection electrodes 100.

[0112] The field electrodes 102 are strip-shaped and extend along the corresponding field regions 56. In one example, the field electrodes 102 are ring-shaped (square ring-shaped in the first embodiment) and extend along the corresponding field regions 56.

[0113] The multiple field electrodes 102 include an innermost field electrode 102A corresponding to the innermost field region 56A and field electrodes 102B to 102D corresponding to the field regions 56B to 56D. The outermost field electrode 102D of the field electrodes 102B to 102D includes a field lead portion 102E extending toward the peripheral edge of the chip 12. Therefore, the width of the field electrode 102D is greater than the widths of the field electrodes 102B and 102C. The width of the field electrode 102D is greater than the width of the innermost field electrode 102A. In one example, the widths of the field electrodes 102B and 102C are equal to each other. In another example, the width of the innermost field electrode 102A is equal to the widths of the field electrodes 102B and 102C. The innermost field electrode 102A may also be referred to as the "field electrode 102A."

[0114] Each of the field electrodes 102A to 102D has a plurality of corner portions 103P (four in the first embodiment) and a plurality of straight portions 103Q (four in the first embodiment) connecting the corner portions 103P. The straight portions 103Q connect the corner portions 103P adjacent to each other in the X direction or the Y direction. The straight portions 103Q extend along the X direction or the Y direction in a plan view.

[0115] The insulating film 60 includes a channel stop opening 104 that exposes the channel stop region 58 in the peripheral region 18. The channel stop opening 104 has a strip shape that extends along the channel stop region 58. In one example, the channel stop opening 104 has a ring shape (a square ring shape in the first embodiment) that extends along the channel stop region 58. The channel stop opening 104 communicates with the periphery of the chip 12.

[0116] The semiconductor device 10 includes a channel stop electrode 106 provided on the insulating film 60 in the peripheral region 18. The channel stop electrode 106 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the channel stop electrode 106 may have a stacked structure including a Ti-based metal film and a W-based metal film. The channel stop electrode 106 is in an electrically floating state.

[0117] The channel stop electrode 106 has a strip shape extending along the channel stop region 58 in a plan view. In one example, the channel stop electrode 106 has a ring shape (a square ring shape in the first embodiment) extending along the channel stop region 58 in a plan view. The channel stop electrode 106 is electrically connected to the channel stop region 58 by extending into the channel stop opening 104 from above the insulating film 60. The channel stop electrode 106 may be provided at a distance from the periphery of the chip 12 toward the IGBT region 14 so as to expose the peripheral portion (channel stop region 58) of the first main surface 12A.

[0118] The semiconductor device 10 includes a collector electrode 108 provided on the second main surface 12B. In one example, the collector electrode 108 covers the second main surface 12B. The collector electrode 108 is electrically connected to the collector region 24 exposed from the second main surface 12B. The collector electrode 108 forms an ohmic contact with the collector region 24. The collector electrode 108 may cover the entire second main surface 12B so as to be continuous with the periphery of the chip 12 (the first to fourth side surfaces 12C to 12F).

[0119] The collector electrode 108 may have a single-film structure or a multilayer structure including at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film. The collector electrode 108 preferably includes at least a Ti film that directly covers the second main surface 12B. The collector electrode 108 may have a multilayer structure including, for example, a Ti film, a Ni film, a Pd film, and an Au film that are stacked in this order from the second main surface 12B side.

[0120] 8, the semiconductor device 10 includes an n-type cathode region 110 provided in the outer periphery region 18 in a surface layer portion of the second main surface 12B. The cathode region 110 has a higher n-type impurity concentration than the p-type impurity concentration of the collector region 24. The cathode region 110 is a region in which the conductivity type of a portion of the collector region 24 is replaced from p-type to n-type. The cathode region 110 preferably has a higher n-type impurity concentration than the drift region 20 (buffer region 22).

[0121] 9 , the cathode region 110 extends in a layered form along the second major surface 12B. The cathode region 110 is exposed from the second major surface 12B. The cathode region 110 penetrates the collector region 24 so as to be connected to the buffer region 22. The cathode region 110 is electrically connected to the collector electrode 108. The cathode region 110 forms an ohmic contact with the collector electrode 108. The cathode region 110 and the well region 54 form a diode 112. The diode 112 is configured as a freewheeling diode for the IGBT structure 34.

[0122] When a forward voltage VF of the diode 112 is applied between the emitter electrode 92 and the collector electrode 108, a forward current IF flows through the diode 112. The forward current IF flows from the outer well-connecting electrode 84B to the cathode region 110, for example.

[0123] The cathode region 110 may have an endless or edged strip shape surrounding the IGBT region 14 in a plan view. In one example, the cathode region 110 has a ring shape (a square ring shape with rounded corners in the first embodiment) surrounding the IGBT region 14 in a plan view. As shown in FIG. 10 , the cathode region 110 has a plurality of corner portions 111P (four in the first embodiment) and a plurality of straight line portions 111Q (four in the first embodiment) connecting the plurality of corner portions 111P. The straight line portions 111Q connect the corner portions 111P adjacent to each other in the X direction or the Y direction. The straight line portions 111Q extend along the X direction or the Y direction in a plan view.

[0124] 9 , the cathode region 110 is arranged so that the well region 54 has a portion facing the cathode region 110 and a portion facing the collector region 24 in the thickness direction of the chip 12. In other words, the cathode region 110 is narrower than the well region 54 so as not to face the entire well region 54 in the thickness direction of the chip 12. The width W1 of the cathode region 110 may be 5 μm or more and 90 μm or less. The width W1 of the cathode region 110 may be 10 μm or more and 40 μm or less. Here, the width W1 of the cathode region 110 can be defined by the dimension in a direction perpendicular to the direction in which the cathode region 110 extends in a plan view.

[0125] The cathode region 110 is provided at a distance from the base region 36 on the peripheral edge side of the chip 12 so as not to face the base region 36 at least in the thickness direction of the chip 12. The cathode region 110 is arranged at a distance from the plurality of trench gate structures 38 on the peripheral edge side of the chip 12 so as not to face the plurality of trench gate structures 38 in the thickness direction of the chip 12. The cathode region 110 is arranged at a distance from the trench isolation structures 26 on the peripheral edge side of the chip 12 so as not to face the trench isolation structures 26 in the thickness direction of the chip 12.

[0126] In this way, the cathode region 110 is disposed at a distance from the IGBT region 14 on the peripheral edge side of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. In other words, the cathode region 110 is provided only in the outer peripheral region 18, but is not provided in the IGBT region 14. In this case, the electrical influence from the IGBT region 14 to the diode 112 can be suppressed, and the electrical influence from the diode 112 to the IGBT region 14 can also be suppressed.

[0127] In one example, the ratio of the planar area of ​​the cathode region 110 to the planar area of ​​the second main surface 12B is 0.1% to 10%. In another example, the ratio of the planar area of ​​the cathode region 110 to the planar area of ​​the second main surface 12B may fall within any one of the ranges of 0.1% to 1%, 1% to 2%, 2% to 4%, 4% to 6%, 6% to 8%, and 8% to 10%.

[0128] (Configuration of Corner Portions of Peripheral Region) Next, the configuration of the corner portions of the peripheral region 18 will be described with reference to Figures 8 to 11. Figure 10 shows a schematic planar structure of the corner portion 57P and its surroundings in an enlarged view of Figure 8. Figure 11 shows a schematic planar structure of the semiconductor device 10 in the enlarged view of Figure 10. In Figure 10, the emitter line electrode 96, the field electrode 102, and the well-connecting electrodes 84A and 84B are omitted to make the drawing easier to understand.

[0129] As shown in FIG. 8 , each of the multiple corner portions 57P in each of the field regions 56A to 56D includes a field-side curved portion 57A to 57D. The field-side curved portions 57A to 57D are arc-shaped with a common second center of curvature CP2 as the center in a plan view. In the example shown in FIG. 8 , the second central angle θ2 of the arc-shaped field-side curved portions 57A to 57D is 90°. Because the field-side curved portions 57A to 57D are arcs with a common second center of curvature CP2, their radii of curvature are different from one another. More specifically, the radii of curvature increase in the order of the field-side curved portions 57A, 57B, 57C, and 57D. In other words, the curvature decreases in the order of the field-side curved portions 57A, 57B, 57C, and 57D. The lengths of the field-side curved portions 57A to 57D in the direction in which they extend are greatest in the order of field-side curved portions 57A, 57B, 57C, and 57D. Hereinafter, the innermost field-side curved portion 57A of the multiple field-side curved portions 57A to 57D may be referred to as the "innermost field-side curved portion 57A."

[0130] The straight portion 57Q of the field regions 56A-56D includes straight portions 57E-57H that are individually connected to the field-side curved portions 57A-57D as corner portions 57P. In a plan view, both ends of the field-side curved portion 57A in the direction in which the field-side curved portion 57A extends are each connected to the straight portion 57E. In a plan view, both ends of the field-side curved portion 57B in the direction in which the field-side curved portion 57B extends are each connected to the straight portion 57F. In a plan view, both ends of the field-side curved portion 57C in the direction in which the field-side curved portion 57C extends are each connected to the straight portion 57G. In a plan view, both ends of the field-side curved portion 57D in the direction in which the field-side curved portion 57D extends are each connected to the straight portion 57H. As shown in FIGS. 8 and 10 , the field-side curved portions 57A-57D and the straight portions 57E-57H are smoothly connected.

[0131] The field-side curved portions 57A-57D and the straight portions 57E-57H are connected by lines L1 and L2. In other words, the lines L1 and L2 are the boundaries between the field-side curved portions 57A-57D and the straight portions 57E-57H. Therefore, in the example shown in FIG. 8, the corner portions 57P of the field regions 56A-56D are formed by the field-side curved portions 57A-57D. In the example shown in FIG. 8, the line L1 extends along the Y direction. The line L2 extends along the X direction.

[0132] The corner portion 55P of the well region 54 includes a well-side curved portion 55A. The well-side curved portion 55A includes an inner edge 55AA and an outer edge 55AB. The outer edge 55AB of the well-side curved portion 55A has an arc shape centered on a first center of curvature CP1 in a plan view. The first center of curvature CP1 is located at a different position from the second center of curvature CP2. The first center of curvature CP1 is located closer to the center of the chip 12 than the second center of curvature CP2. Both the first center of curvature CP1 and the second center of curvature CP2 are located on a straight line LA that divides the apex angle of the corner portion of the chip 12 in half. Here, the apex angle of the corner portion of the chip 12 is the angle of the connection between the first side surface 12C and the third side surface 12E, as shown in FIG. 3, for example. In this case, the apex angle is 90°. Therefore, the straight line LA, which divides the apex angle of the corner portion of the tip 12 in half, is a straight line inclined at 45° with respect to both the first side surface 12C and the third side surface 12E at the connection portion between the first side surface 12C and the third side surface 12E. Therefore, the straight line LA can be considered one of the diagonals of the tip 12. The inner edge 55AA of the well-side curved portion 55A has an arc shape centered on a center of curvature different from both the first center of curvature CP1 and the second center of curvature CP2 in a plan view. In one example, the center of curvature of the inner edge 55AA of the well-side curved portion 55A is located on the straight line LA and is located between the first center of curvature CP1 and the second center of curvature CP2 on the straight line LA. The position of the center of curvature of the inner edge 55AA of the well-side curved portion 55A can be arbitrarily changed. In one example, the center of curvature of the inner edge 55AA of the well-side curved portion 55A may be at the same position as the first center of curvature CP1.

[0133] The first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A is smaller than the second central angle θ2 of the innermost field-side curved portion 57A. In the first embodiment, the second central angle θ2 of the innermost field-side curved portion 57A and the second central angles θ2 of the field-side curved portions 57B to 57D are the same, so the first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A can be said to be smaller than the second central angle θ2 of the field-side curved portions 57B to 57D. In one example, the first central angle θ1 may be 30° or greater and 80° or less. In one example, the ratio (θ1 / θ2) of the first central angle θ1 to the second central angle θ2 may be 0.50 or greater and 0.89 or less. The ratio (θ1 / θ2) is not limited to the above range and can be changed as desired.

[0134] Thus, the length of the outer edge 55AB of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends is shorter than the length of the inner edge 57AA of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends. Therefore, the corner portion 55P of the well region 54 includes the well-side curved portion 55A and a portion of the straight portion 55Q. The straight portion 55Q of the well region 54 extends closer to the straight line LA than the straight portion 57E of the innermost field region 56A. Therefore, it can be said that each of the end portions 55AC, 55AD of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends is closer to the center of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends than the end portions 57AC, 57AD of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends.

[0135] The curvature of the outer edge 55AB of the well-side curved portion 55A is different from the curvature of the inner edge 57AA of the innermost field-side curved portion 57A. In the first embodiment, the curvature of the outer edge 55AB of the well-side curved portion 55A is smaller than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A. Therefore, in the direction from the IGBT region 14 toward the periphery of the chip 12, the distance between the outer edge 55AB of the well-side curved portion 55A and the inner edge 57AA of the innermost field-side curved portion 57A is smallest at both end portions 55AC, 55AD of the well-side curved portion 55A and gradually increases toward the center of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends. The distance between the outer edge 55AB of the well-side curved portion 55A and the inner edge 57AA of the innermost field-side curved portion 57A is greatest at the center of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends. The maximum distance between the outer edge 55AB of the well-side curved portion 55A and the inner edge 57AA of the innermost field-side curved portion 57A is smaller than the minimum distance between the innermost field-side curved portion 57A and the field-side curved portion 57B. Therefore, it can be said that the distance between the outer edge 55AB of the well-side curved portion 55A and the inner edge 57AA of the innermost field-side curved portion 57A is smaller than the distance between the innermost field-side curved portion 57A and the field-side curved portion 57B.

[0136] In one example, the curvature of the outer edge 55AB of the well-side curved portion 55A may be greater than the curvature of the outer edge 57CB of the field-side curved portion 57C. In one example, the curvature of the outer edge 55AB of the well-side curved portion 55A is equal to the curvature of the inner edge 57CA of the field-side curved portion 57C. In this way, the curvature of the outer edge 55AB of the well-side curved portion 55A can be said to be smaller than the curvature of the innermost field-side curved portion 57A and larger than the curvature of the outermost field-side curved portion 57D.

[0137] At the corner portion 55P of the well region 54, the connection portion between the outer periphery of the end 55AC of the well-side curved portion 55A and the straight portion 55Q and the connection portion between the end 55AD of the well-side curved portion 55A and the outer periphery of the straight portion 55Q constitute low-voltage breakdown regions 59A and 59B. The low-voltage breakdown regions 59A and 59B are regions of the well region 54 that are more likely to reach a breakdown voltage (BV) than regions other than the low-voltage breakdown regions 59A and 59B. In other words, the low-voltage breakdown regions 59A and 59B are regions of the well region 54 where an electric field is more likely to concentrate than regions other than the low-voltage breakdown regions 59A and 59B. Thus, the low-voltage breakdown regions 59A and 59B can be said to be regions that are more likely to reach a breakdown voltage and experience breakdown (hereinafter referred to as "BV breakdown").

[0138] As shown in FIG. 10 , the angle formed by the first tangent LT1 at the outer edge 55AB of the end 55AC of the well-side curved portion 55A and the straight portion 55Q extending from the end 55AC is defined as the "first angle AT1." The angle formed by the second tangent LT2 at the outer edge 57AB of the end 57AC of the innermost field-side curved portion 57A and the straight portion 57Q extending from the end 57AC is defined as the "second angle AT2." In this case, the first angle AT1 is greater than the second angle AT2. Here, because the innermost field-side curved portion 57A and the straight portion 57Q are smoothly connected, the second tangent LT2 is approximately parallel to the direction in which the straight portion 57Q extends. Therefore, the second angle AT2 is substantially 0°.

[0139] Alternatively, the tangent to the outer edge 55AB of the end 55AD of the well-side curved portion 55A may be defined as the first tangent LT1, and the angle formed by the first tangent LT1 and the straight portion 55Q extending from the end 55AD may be defined as the first angle AT1. In this case, the first angle AT1 is also greater than the second angle AT2.

[0140] Because the first angle AT1 is greater than the second angle AT2, the ends 55AC, 55AD and the straight portion 55Q are not smoothly connected at the outer edge 55AB of the well-side curved portion 55A. As a result, the shape of the outer edge 54B of the well region 54 changes abruptly at the connection between the outer edge 55AB of the end 55AC of the well-side curved portion 55A and the straight portion 55Q, and at the connection between the outer edge 55AB of the end 55AD of the well-side curved portion 55A and the straight portion 55Q. Due to this abrupt change in the shape of the outer edge 54B of the well region 54, electric field concentration is likely to occur at the connection between the outer edge 55AB of the end 55AC of the well-side curved portion 55A and the straight portion 55Q, and at the connection between the outer edge 55AB of the end 55AD of the well-side curved portion 55A and the straight portion 55Q. Therefore, electric fields are likely to concentrate in the breakdown voltage reduction region 59A, which includes the connection portion between the outer edge 55AB of the end 55AC of the well-side curved portion 55A and the straight portion 55Q, and in the breakdown voltage reduction region 59B, which includes the connection portion between the outer edge 55AB of the end 55AD of the well-side curved portion 55A and the straight portion 55Q.

[0141] The cathode region 110 is disposed at a position facing the reduced breakdown voltage regions 59A and 59B in the thickness direction of the chip 12. An outer edge 111C of the cathode region 110 is disposed closer to the IGBT region 14 than an outer edge 54B of the well region 54. A method for setting the position of the cathode region 110 will be described later.

[0142] In one example, the cathode region 110 is disposed closer to the IGBT region 14 (see FIG. 9 ) than the innermost field region 56A. The cathode region 110 is disposed to face the outer edge 54B of the well region 54 in the thickness direction of the chip 12. More specifically, a corner portion 111P of the cathode region 110 includes a cathode-side curved portion 111A.

[0143] 8 and 10, the outer edge 111C of the cathode side curved portion 111A is located at the same position as the outer edge 55AB of the well side curved portion 55A of the well region 54 in a plan view.

[0144] The outer edge 111C of the cathode-side curved portion 111A has an arc shape centered on a third center of curvature CP3 in a plan view. The third center of curvature CP3 is located at a different position from the second center of curvature CP2. The third center of curvature CP3 is located closer to the center of the chip 12 than the second center of curvature CP2. The first to third centers of curvature CP1 to CP3 are located on a straight line LA. In the example shown in FIG. 10, the third center of curvature CP3 overlaps with the first center of curvature CP1 in a plan view.

[0145] The inner edge 111B of the cathode-side curved portion 111A has an arc shape centered on the third center of curvature CP3 in a plan view. Therefore, it can be said that the cathode-side curved portion 111A has an arc shape centered on the third center of curvature CP3 in a plan view. The curvature of the inner edge 111B of the cathode-side curved portion 111A is greater than the curvature of the outer edge 111C.

[0146] In the example shown in Figures 8 and 10, the third central angle θ3 of the outer edge 111C of the cathode-side curved portion 111A is equal to the first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A. Therefore, the third central angle θ3 is smaller than the second central angle θ2 of the innermost field-side curved portion 57A. It can be said that the third central angle θ3 of the outer edge 111C of the cathode-side curved portion 111A is smaller than the second central angle θ2 of the field-side curved portions 57B to 57D. In one example, the third central angle θ3 may be 30° or greater and 80° or less. In one example, the ratio of the third central angle θ3 to the second central angle θ2 (θ3 / θ2) may be 0.50 or greater and 0.89 or less. Note that the ratio (θ3 / θ2) is not limited to the above range and can be changed as desired.

[0147] Thus, the length of the outer edge 111C of the cathode-side curved portion 111A in the direction in which the cathode-side curved portion 111A extends is shorter than the length of the inner edge 57AA of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends. Therefore, the corner portion 111P of the cathode region 110 includes the cathode-side curved portion 111A and a part of the straight portion 111Q. The straight portion 111Q of the cathode region 110 extends closer to the line LA than the straight portion 57E of the innermost field region 56A. Therefore, it can be said that both end portions 111D, 111E of the cathode-side curved portion 111A in the direction in which the cathode-side curved portion 111A extends are located closer to the center of the cathode-side curved portion 111A in the direction in which the cathode-side curved portion 111A extends than both end portions 57AC, 57AD of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends. The length of the outer edge 111C of the cathode-side curved portion 111A in the direction in which the cathode-side curved portion 111A extends is shorter than the length of the outer edge 55AB of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends.

[0148] In the first embodiment, the curvature of the outer edge 111C of the cathode-side curved portion 111A is smaller than the curvature of the inner edge 57AA of the innermost field-side curved portion 57 A. In the example shown in Figure 10, the curvature of the outer edge 111C of the cathode-side curved portion 111A is equal to the curvature of the outer edge 55AB of the well-side curved portion 55A.

[0149] The angle formed by the third tangent line LT3 at the outer edge 111C of the end 111D of the cathode-side curved portion 111A and the straight portion 111Q extending from the end 111D is defined as the "third angle AT3." In this case, the third angle AT3 is greater than the second angle AT2. The third angle AT3 is equal to the first angle AT1.

[0150] Alternatively, the tangent to the outer edge 111C of the end 111E of the cathode-side curved portion 111A may be defined as a third tangent LT3, and the angle formed by this third tangent LT3 and the straight portion 111Q extending from the end 111E may be defined as a third angle AT3. In this case, the third angle AT3 is also greater than the second angle AT2. The third angle AT3 is equal to the first angle AT1.

[0151] 9 and 11 , the emitter line electrode 96 is disposed at a position facing the cathode region 110 in the thickness direction. It can be said that the emitter line electrode 96 extends along the outer edge 54B of the well region 54, slightly closer to the inner edge 54A of the well region 54 than the outer edge 54B of the well region 54 in a plan view. More specifically, a corner portion 97P of the emitter line electrode 96 includes an emitter-side curved portion 97A.

[0152] The emitter-side curved portion 97A includes an inner edge 97B and an outer edge 97C. The outer edge 97C of the emitter-side curved portion 97A has an arc shape centered at a fourth center of curvature CP4 in a plan view. The fourth center of curvature CP4 is located at a position overlapping with the third center of curvature CP3 in a plan view. Therefore, the fourth center of curvature CP4 is located at a different position from the second center of curvature CP2. The fourth center of curvature CP4 is located closer to the center of the chip 12 than the second center of curvature CP2. The first to fourth centers of curvature CP1 to CP4 are located on a straight line LA in a plan view.

[0153] The inner edge 97B of the emitter-side curved portion 97A has an arc shape centered about the fourth center of curvature CP4 in plan view. Therefore, it can be said that the emitter-side curved portion 97A has an arc shape centered about the fourth center of curvature CP4 in plan view. The curvature of the inner edge 97B of the emitter-side curved portion 97A is greater than the curvature of the outer edge 97C.

[0154] The fourth central angle θ4 of the outer edge 97C of the emitter-side curved portion 97A is smaller than the second central angle θ2 of the innermost field-side curved portion 57A. It can be said that the fourth central angle θ4 of the outer edge 97C of the emitter-side curved portion 97A is smaller than the second central angle θ2 of the field-side curved portions 57B to 57D. In one example, the ratio (θ4 / θ2) of the fourth central angle θ4 to the second central angle θ2 may be 0.50 or greater and 0.89 or less. In one example, the fourth central angle θ4 is equal to the third central angle θ3. In another example, the fourth central angle θ4 is equal to the first central angle θ1. The ratio (θ4 / θ2) is not limited to the above range and can be changed as desired.

[0155] Thus, the length of the outer edge 97C of the emitter-side curved portion 97A in the direction in which the emitter-side curved portion 97A extends is shorter than the length of the inner edge 57AA of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends. Therefore, the corner portion 97P of the emitter-line electrode 96 includes the emitter-side curved portion 97A and a part of the straight portion 97Q. The straight portion 97Q of the emitter-line electrode 96 extends closer to the line LA than the straight portion 57E of the innermost field region 56A. Therefore, it can be said that both end portions 97D, 97E of the emitter-side curved portion 97A in the direction in which the emitter-side curved portion 97A extends are located closer to the center of the emitter-side curved portion 97A in the direction in which the emitter-side curved portion 97A extends than both end portions 57AC, 57AD of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends. The length of the outer edge 97C of the emitter-side curved portion 97A in the direction in which the emitter-side curved portion 97A extends is shorter than the length of the outer edge 55AB of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends.

[0156] 10 and 11 , in the first embodiment, the curvature of the outer edge 97C of the emitter-side curved portion 97A is smaller than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A. The curvature of the outer edge 97C of the emitter-side curved portion 97A is larger than the curvature of the outer edge 55AB of the well-side curved portion 55A. The curvature of the outer edge 97C of the emitter-side curved portion 97A is larger than the curvature of the outer edge 111C of the cathode-side curved portion 111A. In the example shown in FIG. 11 , the curvature of the inner edge 97B of the emitter-side curved portion 97A is smaller than the curvature of the inner edge 111B of the cathode-side curved portion 111A.

[0157] The angle formed by the fourth tangent LT4 at the outer edge 97C of the end 97D of the emitter-side curved portion 97A and the straight portion 97Q extending from the end 97D is defined as the "fourth angle AT4." In this case, the fourth angle AT4 is greater than the second angle AT2 (substantially 0°). The fourth angle AT4 is equal to the first angle AT1. The fourth angle AT4 is equal to the third angle AT3.

[0158] Alternatively, the tangent to the outer edge 97C of the end 97E of the emitter-side curved portion 97A may be defined as a fourth tangent LT4, and the angle formed by this fourth tangent LT4 and the straight portion 97Q extending from the end 97E may be defined as a fourth angle AT4. In this case, the fourth angle AT4 is also greater than the second angle AT2. The fourth angle AT4 is equal to the first angle AT1. The fourth angle AT4 is equal to the third angle AT3.

[0159] As shown in FIG. 11 , each of the corner portions 103P of the field electrodes 102A-102D includes a field electrode-side curved portion 103A-103D. The field electrode-side curved portions 103A-103D are arc-shaped with a common fifth center of curvature CP5 as their center in a plan view. The fifth center of curvature CP5 is located at a different position from the third center of curvature CP3. In one example, the fifth center of curvature CP5 overlaps with the second center of curvature CP2 in a plan view. The fifth center of curvature CP5 is located on a straight line LA.

[0160] In the example shown in FIG. 11 , the fifth central angle θ5 of the arc-shaped field electrode side curved portions 103A-103D is 90°. Because the field electrode side curved portions 103A-103D are arcs with a common fifth center of curvature CP5, their radii of curvature are different from one another. More specifically, the radii of curvature increase in the order of field electrode side curved portions 103A, 103B, 103C, and 103D. In other words, the curvature decreases in the order of field electrode side curved portions 103A, 103B, 103C, and 103D. Furthermore, the lengths of the field electrode side curved portions 103A-103D in the direction in which they extend increase in the order of field electrode side curved portions 103A, 103B, 103C, and 103D. Hereinafter, the innermost field electrode curved portion 103A of the multiple field electrode curved portions 103A to 103D may be referred to as the "innermost field electrode curved portion 103A." The innermost field electrode curved portion 103A includes an inner edge 103AA and an outer edge 103AB.

[0161] The straight portions 103Q of the field electrodes 102A-102D are individually connected to the field electrode side curved portions 103A-103D as corner portions 103P. As shown in Figure 11, the innermost field electrode side curved portion 103A and the straight portion 103Q are smoothly connected. Although not shown, the field electrode side curved portions 103B-103D are also smoothly connected to the straight portion 103Q.

[0162] The innermost field electrode curved portion 103A and the straight portion 103Q are connected by straight lines L1 and L2. In other words, the straight lines L1 and L2 are the boundary between the innermost field electrode curved portion 103A and the straight portion 103Q. Therefore, in the example shown in FIG. 11 , the corner portion 103P of the innermost field electrode 102A is formed by the innermost field electrode curved portion 103A. In the example shown in FIG. 11 , the straight line L1 extends along the Y direction. The straight line L2 extends along the X direction. Although not shown, the relationship between the field electrodes 102B to 102D and the straight portion 103Q is similar to that of the innermost field electrode 102A.

[0163] The fifth central angle θ5 of the field electrode side curved portions 103A-103D is larger than the fourth central angle θ4 of the emitter side curved portion 97A. In other words, the fourth central angle θ4 of the emitter side curved portion 97A is smaller than the fifth central angle θ5 of the field electrode side curved portions 103A-103D. In one example, the ratio of the fourth central angle θ4 to the fifth central angle θ5 (θ4 / θ5) may be 0.50 or greater and 0.89 or less. Note that the ratio (θ4 / θ5) is not limited to the above range and can be changed as desired.

[0164] In this way, the outer edge 97C of the emitter-side curved portion 97A in the extension direction of the emitter-side curved portion 97A is shorter than the inner edge 103AA of the innermost field electrode side curved portion 103A in the extension direction of the innermost field electrode side curved portion 103A. Therefore, it can be said that each of the two end portions 97D, 97E of the emitter-side curved portion 97A in the extension direction of the emitter-side curved portion 97A is located closer to the center of the emitter-side curved portion 97A in the extension direction of the emitter-side curved portion 97A than each of the two end portions 103AC, 103AD of the innermost field electrode side curved portion 103A in the extension direction of the innermost field electrode side curved portion 103A.

[0165] In the first embodiment, the curvature of the outer edge 97C of the emitter-side curved portion 97A is smaller than the curvature of the inner edge 103AA of the innermost field electrode-side curved portion 103A. Therefore, in the direction from the IGBT region 14 toward the periphery of the chip 12, the distance between the outer edge 97C of the emitter-side curved portion 97A and the inner edge 103AA of the innermost field electrode-side curved portion 103A is smallest at both ends 97D, 97E of the emitter-side curved portion 97A and gradually increases toward the center of the emitter-side curved portion 97A in the extension direction of the emitter-side curved portion 97A. The distance between the outer edge 97C of the emitter-side curved portion 97A and the inner edge 103AA of the innermost field electrode-side curved portion 103A is largest at the center of the emitter-side curved portion 97A in the extension direction of the emitter-side curved portion 97A.

[0166] 12 to 14, a method for setting the position of the cathode region 110 will be described. Note that in the following description, for components in the semiconductor device 10 denoted by reference numerals, please refer to the reference numerals of the components of the semiconductor device 10 shown in FIGS.

[0167] When a forward voltage VF of the diode 112 is applied between the emitter electrode 92 and the collector electrode 108, a forward current IF flows through the diode 112. The forward current IF flows, for example, from the inner well-connecting electrode 84A and the outer well-connecting electrode 84B to the cathode region 110. The electrical characteristics of the diode 112 during forward operation vary depending on the position of the cathode region 110.

[0168] FIG. 12 shows the relationship between the forward current IF and the forward voltage VF depending on the position of the cathode region 110. The vertical axis of the graph in FIG. 12 represents the forward current IF (A). The horizontal axis of the graph in FIG. 12 represents the forward voltage VF (V). FIG. 12 shows a first characteristic S1, a second characteristic S2, and a third characteristic S3. The first characteristic S1 represents the characteristic when the cathode region 110 is located at the gate reference position PG. The second characteristic S2 represents the characteristic when the cathode region 110 is located at the first well reference position PW1. The third characteristic S3 represents the characteristic when the cathode region 110 is located at the second well reference position PW2.

[0169] The gate reference position PG is a position directly below the center of the gate line electrode 90. In one example, the gate reference position PG is a position directly below the center of the gate line wiring 70. The gate reference position PG can also be said to be a position facing the gate line electrode 90 in the thickness direction of the chip 12. The gate reference position PG can also be said to be a position facing the gate line wiring 70 in the thickness direction of the chip 12.

[0170] The first well reference position PW1 is a position directly below the inner well connecting electrode 84A. In the case of a single inner well connecting electrode 84A, the first well reference position PW1 is a position directly below the single inner well connecting electrode 84A. In the case of multiple inner well connecting electrodes 84A, the first well reference position PW1 is a position directly below the midpoint between the innermost inner well connecting electrode 84A arranged on the IGBT region 14 side and the outermost inner well connecting electrode 84A arranged on the peripheral edge side of the chip 12.

[0171] The second well reference position PW2 is a position directly below the outer well connecting electrode 84B. In the case of a single outer well connecting electrode 84B, the second well reference position PW2 is a position directly below the single outer well connecting electrode 84B. In the case of multiple outer well connecting electrodes 84B, the second well reference position PW2 is a position directly below the midpoint between the innermost outer well connecting electrode 84B arranged on the IGBT region 14 side and the outermost outer well connecting electrode 84B arranged on the peripheral edge side of the chip 12.

[0172] As shown in FIG. 12 , the forward current IF according to the second characteristic S2 is greater than the forward current IF according to the first characteristic S1. Furthermore, the forward current IF according to the third characteristic S3 is greater than the forward current IF according to the first characteristic S1. Thus, the cathode region 110 is preferably disposed away from the gate reference position PG to prevent a detour current path. Furthermore, considering the first to third characteristics S1 to S3 shown in FIG. 12 , the cathode region 110 is preferably disposed at either or both of the first well reference position PW1 and the second well reference position PW2.

[0173] 13 and 14 are graphs showing the relationship between the position of the cathode region 110 and the forward current I F. The horizontal axis in each of Fig. 13 and Fig. 14 indicates the position of the cathode region 110. The vertical axis in each of Fig. 13 and Fig. 14 indicates the magnitude of the forward current I F.

[0174] 13 and 14 , the forward current IF reaches a first maximum value v1 when the cathode region 110 is located at the first well reference position PW1. The forward current IF reaches a minimum value v2 when the cathode region 110 is located at the gate reference position PG. The forward current IF reaches a second maximum value v3 when the cathode region 110 is located at the second well reference position PW2.

[0175] When the cathode region 110 is located near the midpoint between the first well reference position PW1 and the gate reference position PG, the forward current IF assumes a value near the intermediate value between the first maximum value v1 and the minimum value v2. The value near the intermediate value between the first maximum value v1 and the minimum value v2 is also a value near the first inflection point v4 between the first maximum value v1 and the minimum value v2.

[0176] When the cathode region 110 is located near the midpoint between the gate reference position PG and the second well reference position PW2, the forward current IF assumes a value near the intermediate value between the minimum value v2 and the second maximum value v3. The value near the intermediate value between the minimum value v2 and the second maximum value v3 is also a value near the second inflection point v5 between the minimum value v2 and the second maximum value v3.

[0177] For the above reasons, it is preferable that a prohibited range 122 that prohibits placement of the cathode region 110 near the gate reference position PG is set on the second main surface 12B. It is also preferable that a first allowed range 124 that permits placement of a part or the whole of the cathode region 110 near the first well reference position PW1 is set on the second main surface 12B. It is also preferable that a second allowed range 126 that permits placement of a part or the whole of the cathode region 110 is set near the second well reference position PW2.

[0178] Next, an explanation will be given of setting examples of the prohibited range 122, the first allowed range 124, and the second allowed range 126. Fig. 13 shows the first setting example, and Fig. 14 shows the second setting example. (First Setting Example) In the first setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set separately as the distance between the first well reference position PW1 and the gate reference position PG, and the distance between the second well reference position PW2 and the gate reference position PG.

[0179] 13 , when the cathode region 110 is disposed in a region on the side of the first well reference position PW1, the prohibited range 122 and the first allowed range 124 may be set based on a first reference distance Da between the first well reference position PW1 and the gate reference position PG. Here, the first reference distance Da is an example of a “reference distance as the distance between the center of the gate line electrode and the well connecting electrode.”

[0180] In this case, the prohibited range 122 is set within a range not exceeding half the first reference distance Da from the gate reference position PG. The prohibited range 122 is set on the IGBT region 14 side from the gate reference position PG. In this case, the cathode region 110 is disposed at least half the first reference distance Da from the gate reference position PG toward the first well reference position PW1. In other words, the cathode region 110 is not disposed within a range not exceeding half the first reference distance Da from the gate reference position PG toward the first well reference position PW1.

[0181] On the other hand, the first allowable range 124 is set within a range not exceeding half the first reference distance Da from the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side from the first well reference position PW1. In this case, at least a portion of the cathode region 110 is disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1. In other words, the cathode region 110 has a portion disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1 directly below the inner well connection electrode 84A.

[0182] Furthermore, when the cathode region 110 is disposed in a region on the side of the second well reference position PW2, the prohibited range 122 and the second allowed range 126 are set based on a second reference distance Db between the second well reference position PW2 and the gate reference position PG. Here, the second reference distance Db is an example of a "reference distance as the distance between the center of the gate line electrode and the well connecting electrode."

[0183] In this case, the prohibited range 122 is set within a range not exceeding half the second reference distance Db from the gate reference position PG. The prohibited range 122 is set toward the second well reference position PW2 from the gate reference position PG. In this case, the cathode region 110 is disposed at least half the second reference distance Db away from the gate reference position PG toward the second well reference position PW2. In other words, the cathode region 110 is not disposed within a range not exceeding half the second reference distance Db from the gate reference position PG toward the second well reference position PW2.

[0184] On the other hand, the second allowable range 126 is set within a range not exceeding half the second reference distance Db from the second well reference position PW2. The second allowable range 126 is set on the periphery of the chip 12 and on the gate reference position PG side from the second well reference position PW2. In this case, at least a portion of the cathode region 110 is positioned within a range not exceeding half the second reference distance Db from the second well reference position PW2. In other words, the cathode region 110 has a portion positioned within a range not exceeding half the second reference distance Db from the second well reference position PW2 directly below the outer well connection electrode 84B.

[0185] When the cathode region 110 is positioned in both the region on the first well reference position PW1 side and the region on the second well reference position PW2 side, the prohibited range 122 is set to a range not exceeding 1 / 2 the first reference distance Da from the gate reference position PG toward the first well reference position PW1 side, and a range not exceeding 1 / 2 the second reference distance Db from the gate reference position PG toward the outer well connection electrode 84B side.

[0186] On the other hand, the first allowable range 124 is set within a range not exceeding half the distance of the first reference distance Da with respect to the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side with respect to the first well reference position PW1. On the other hand, the second allowable range 126 is set within a range not exceeding half the distance of the second reference distance Db with respect to the second well reference position PW2. The second allowable range 126 is set on the periphery side of the chip 12 and the gate reference position PG side with respect to the second well reference position PW2.

[0187] The first reference distance Da may be 1 μm or more and 50 μm or less. The first reference distance Da may be set to a value belonging to any of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less. The first reference distance Da is preferably 10 μm or more and 30 μm or less. Furthermore, the first reference distance Da is preferably 10 μm or more and 20 μm or less.

[0188] The second reference distance Db may be less than the first reference distance Da or may be greater than or equal to the first reference distance Da. In one example, the second reference distance Db is greater than the first reference distance Da. The second reference distance Db may be greater than or equal to 1 μm and less than or equal to 100 μm. The second reference distance Db may be set to a value within any of the following ranges: greater than or equal to 1 μm and less than or equal to 5 μm, greater than or equal to 10 μm, greater than or equal to 10 μm, greater than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 30 μm, greater than or equal to 30 μm and less than or equal to 40 μm, greater than or equal to 40 μm and less than or equal to 50 μm, greater than or equal to 50 μm and less than or equal to 60 μm, greater than or equal to 60 μm and less than or equal to 70 μm, greater than or equal to 70 μm and less than or equal to 80 μm, greater than or equal to 80 μm and less than or equal to 90 μm, and greater than or equal to 90 μm and less than or equal to 100 μm. The second reference distance Db is preferably greater than or equal to 10 μm and less than or equal to 60 μm. The second reference distance Db is preferably 20 μm or more and 40 μm or less.

[0189] 14 , when the cathode region 110 is located at an intermediate reference position PW3 immediately below the midpoint between the first well reference position PW1 and the second well reference position PW2, the forward current IF becomes a value close to the minimum value v2.

[0190] The forward current IF becomes a value near the intermediate value between the first maximum value v1 and the minimum value v2 (a value near the first inflection point v4) when the cathode region 110 is located near the point immediately below the midpoint between the first well reference position PW1 and the intermediate reference position PW3. The forward current IF becomes a value near the intermediate value between the second maximum value v3 and the minimum value v2 (a value near the second inflection point v5) when the cathode region 110 is located near the point immediately below the midpoint between the second well reference position PW2 and the intermediate reference position PW3.

[0191] For the above reasons, the prohibited range 122, the first allowed range 124, and the second allowed range 126 may be set based on the third reference distance Dc between the first well reference position PW1 and the second well reference position PW2. The third reference distance Dc is also the sum of the first reference distance Da and the second reference distance Db (Dc = Da + Db) shown in FIG. 16 . That is, in the second setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set based on the third reference distance Dc without using the first reference distance Da and the second reference distance Db. Here, the third reference distance Dc is an example of a "reference distance as the distance between the inner well connecting electrode and the outer well connecting electrode."

[0192] In this case, the prohibited range 122 may be set to a range not exceeding ¼ of the third reference distance Dc from an intermediate reference position PW3 immediately below the midpoint between the first well reference position PW1 and the second well reference position PW2. When the cathode region 110 is positioned in a region on the first well reference position PW1 side, the prohibited range 122 is set on the first well reference position PW1 side using the intermediate reference position PW3 as a reference. When the cathode region 110 is positioned in a region on the second well reference position PW2 side, the prohibited range 122 is set on the second well reference position PW2 side using the intermediate reference position PW3 as a reference.

[0193] On the other hand, the first allowable range 124 is set within a range not exceeding ¼ of the third reference distance Dc with respect to the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side with respect to the first well reference position PW1. On the other hand, the second allowable range 126 is set within a range not exceeding ¼ of the third reference distance Dc with respect to the second well reference position PW2. The second allowable range 126 is set on the periphery side of the chip 12 and the IGBT region 14 side (gate reference position PG side) with respect to the second well reference position PW2.

[0194] 14, the cathode region 110 is disposed at a distance from the intermediate reference position PW3. The cathode region 110 is preferably disposed in an area outside the prohibited range 122. In other words, the cathode region 110 is preferably not disposed within a range that does not exceed ¼ of the third reference distance Dc from the intermediate reference position PW3.

[0195] The cathode region 110 may be located in a region closer to the first well reference position PW1 than the intermediate reference position PW3. In this case, it is preferable that a portion or the entire cathode region 110 be located within the first allowable range 124. That is, it is preferable that the cathode region 110 is not located within a range from the intermediate reference position PW3 toward the inner well connection electrode 84A that does not exceed ¼ of the third reference distance Dc. It is also preferable that the cathode region 110 has a portion located within a range from the first well reference position PW1 toward the intermediate reference position PW3 that does not exceed ¼ of the third reference distance Dc. In this case, it is preferable that the cathode region 110 be located at the first well reference position PW1. That is, it is preferable that the cathode region 110 faces the inner well connection electrode 84A in the thickness direction of the chip 12.

[0196] The cathode region 110 may also be located in a region closer to the second well reference position PW2 than the intermediate reference position PW3. In this case, it is preferable that a portion or the entire cathode region 110 be located within the second allowable range 126. That is, it is preferable that the cathode region 110 is not located within a range from the intermediate reference position PW3 toward the outer well connection electrode 84B that does not exceed ¼ of the third reference distance Dc. It is also preferable that the cathode region 110 has a portion located within a range from the second well reference position PW2 toward the intermediate reference position PW3 that does not exceed ¼ of the third reference distance Dc. In this case, it is preferable that the cathode region 110 be located at the second well reference position PW2. That is, it is preferable that the cathode region 110 faces the outer well connection electrode 84B in the thickness direction of the chip 12.

[0197] (Peak Surge Current IFSM) The relationship between the position of the cathode region 110 and the peak surge current IFSM will be described with reference to Fig. 15. Fig. 15 is a graph showing the relationship between the peak surge current IFSM and the forward voltage VF when the position of the cathode region 110 is adjusted. The vertical axis of Fig. 15 represents the peak surge current IFSM (A), and the horizontal axis of Fig. 15 represents the forward voltage VF (V). The peak surge current IFSM is the peak value of a commercial sine half-wave current (50 Hz or 60 Hz) of one cycle or more that is permissible without causing breakdown.

[0198] 15 shows first to sixth plot points P1 to P6. The first to third plot points P1 to P3 show the characteristics when the cathode region 110 is arranged at a distance from the well region 54 towards the periphery of the chip 12. The positions of the cathode regions 110 approach the well region 54 in the order of the first plot point P1, the second plot point P2, and the third plot point P3.

[0199] The fourth to sixth plot points P4 to P6 show the characteristics when the cathode region 110 is placed in a position facing the well region 54. The positions of the cathode region 110 approach the second well reference position PW2 from the outer edge 54B side of the well region 54 in the order of the fourth plot point P4, the fifth plot point P5, and the sixth plot point P6. The sixth plot point P6 shows the characteristics when the cathode region 110 is placed at the second well reference position PW2. At the first to sixth plot points P1 to P6, the width of the cathode region 110 is fixed to a constant value (10 μm in this case).

[0200] With reference to the first to sixth plot points P1 to P6, the peak surge currents IFSM associated with the fourth to sixth plot points P4 to P6 are greater than the peak surge currents IFSM associated with the first to third plot points P1 to P3. The peak surge current IFSM associated with the sixth plot point P6 is also greater than the peak surge currents IFSM associated with the first to fifth plot points P1 to P5. Therefore, from the perspective of peak surge current IFSM, it is preferable that the cathode region 110 be located in a region immediately below the well region 54. In particular, it is preferable that the cathode region 110 be located at the second well reference position PW2.

[0201] 5 and 16, a first layout example and a second layout example will be described as layout examples of the cathode region 110. Fig. 16 shows the cross-sectional structure of the peripheral portion of the chip 12 together with the cathode region 110 according to the second layout example.

[0202] 5, the semiconductor device 10 may include, as the cathode region 110, a cathode region 110 according to a first layout example that is provided in consideration of the results of FIGS. 12 to 15 described above. The cathode region 110 is disposed along the second main surface 12B at a distance from the gate reference position PG. Specifically, the cathode region 110 is disposed along the second main surface 12B at a distance from the gate reference position PG toward the second well reference position PW2. In other words, the cathode region 110 is disposed so as to face, in the thickness direction of the chip 12, a region that is spaced apart from the gate line electrode 90 toward the outer well connection electrode 84B.

[0203] In the first embodiment, all of the straight line portions 111Q and the corner portions 111P of the cathode region 110 are arranged to face, in the thickness direction of the chip 12, a region spaced closer to the outer well-connecting electrode 84B than the gate line electrode 90. For this reason, it can be said that the cathode region 110 is arranged to face, in the thickness direction of the chip 12, a region spaced closer to the outer well-connecting electrode 84B than the gate line electrode 90 at least in the corner portions 55P of the well region 54.

[0204] The cathode region 110 is located in the second allowed range 126 but is not located in the prohibited range 122. Here, the prohibited range 122 and the second allowed range 126 according to the first or second setting example may be applied. The cathode region 110 is located at the second well reference position PW2. The cathode region 110 includes a portion facing a plurality of outer well connection electrodes 84B in the thickness direction of the chip 12. The cathode region 110 is located at a distance from the gate line electrode 90 toward the second well reference position PW2 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0205] The cathode region 110 is arranged at a distance from a position directly below the center of the gate line wiring 70 toward the second well reference position PW2. The cathode region 110 is arranged at a distance from a position directly below the plurality of gate connection electrodes 80 toward the second well reference position PW2 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The cathode region 110 is arranged at a distance from the gate line wiring 70 toward the second well reference position PW2 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0206] The cathode region 110 is disposed at a distance from a position directly below the outer edge 54B of the well region 54 toward the second well reference position PW2. The cathode region 110 is disposed only in a region of the surface layer portion of the second main surface 12B that faces the well region 54 in the thickness direction of the chip 12.

[0207] 16, the semiconductor device 10 may include a cathode region 110 according to the second layout example as the cathode region 110. The cathode region 110 includes a first cathode region 110A arranged on the first well reference position PW1 side and a second cathode region 110B arranged on the second well reference position PW2 side.

[0208] The first cathode region 110A is disposed at a distance from the gate reference position PG along the second main surface 12B. Specifically, the first cathode region 110A is disposed at a distance from the gate reference position PG along the second main surface 12B toward the first well reference position PW1 (the IGBT region 14 side).

[0209] The first cathode region 110A is located in the first allowed range 124 but is not located in the prohibited range 122. Here, the prohibited range 122 and the first allowed range 124 according to the first or second setting example may be applied. The first cathode region 110A is located at the first well reference position PW1. The first cathode region 110A faces a plurality of inner well connection electrodes 84A in the thickness direction of the chip 12. The first cathode region 110A is located at a distance from the gate line electrode 90 toward the first well reference position PW1 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0210] The first cathode region 110A is disposed at a distance from a position directly below the center of the gate line wiring 70 toward the first well reference position PW1. The first cathode region 110A is disposed at a distance from a position directly below the plurality of gate connection electrodes 80 toward the first well reference position PW1 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The first cathode region 110A is disposed at a distance from the gate line wiring 70 toward the first well reference position PW1 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0211] The first cathode region 110A is preferably disposed at a distance from a position directly below the inner edge 54A of the well region 54 toward the first well reference position PW1, regardless of the first allowable range 124. In other words, the first cathode region 110A is disposed only in a region facing the well region 54 in the thickness direction of the chip 12 in the surface layer portion of the second main surface 12B.

[0212] Furthermore, the first cathode region 110A is preferably arranged at a distance from the plurality of trench gate structures 38 on the peripheral edge side of the chip 12 so as not to face the plurality of trench gate structures 38 in the thickness direction of the chip 12. The first cathode region 110A is preferably arranged at a distance from the trench isolation structure 26 on the peripheral edge side of the chip 12 so as not to face the trench isolation structure 26 in the thickness direction of the chip 12.

[0213] In other words, the first cathode region 110A is preferably disposed at a distance from the IGBT region 14 toward the peripheral edge of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. In other words, the first cathode region 110A is preferably disposed only in the outer peripheral region 18, and not in the IGBT region 14. Therefore, the first cathode region 110A does not face the base region 36 in the thickness direction of the chip 12. In this case, electrical influence from the IGBT region 14 to the diode 112 can be suppressed, and electrical influence from the diode 112 to the IGBT region 14 can also be suppressed. In this way, the first cathode region 110A can be said to be provided in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14 in a plan view.

[0214] The second cathode region 110B is provided in a layout similar to that of the cathode region 110 according to the first layout example shown in Fig. 5. In one example, the second cathode region 110B is disposed at a distance from the intermediate reference position PW3 toward the outer well connection electrode 84B. The second cathode region 110B faces the first cathode region 110A in the surface layer portion of the second main surface 12B, with a part of the collector region 24 sandwiched therebetween.

[0215] In the first and second layout examples, a portion of the collector region 24 faces the gate line wiring 70, the gate connection electrode 80, and the gate line electrode 90 in the thickness direction of the chip 12. It is preferable that a portion of the collector region 24 faces the entire gate line electrode 90 in the thickness direction of the chip 12. It is preferable that a portion of the collector region 24 faces the entire gate line wiring 70 in the thickness direction of the chip 12.

[0216] [Operation of First Embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to FIGS. 17 to 19 . FIG. 17 schematically illustrates the planar structure of the corner portion of the peripheral region 18 of the chip 12 in a semiconductor device 10X of a comparative example. FIG. 18 illustrates the electric field intensity in the peripheral region 18 in the semiconductor device 10X of the comparative example. FIG. 19 illustrates the electric field intensity in the peripheral region 18 in the semiconductor device 10 of the first embodiment. The range RA on the horizontal axis in FIGS. 18 and 19 indicates the arrangement region of the innermost field region 56A in the peripheral region 18. The ranges RB to RD on the horizontal axis in FIGS. 18 and 19 indicate the arrangement regions of the field regions 56B to 56D in the peripheral region 18, respectively. The range RW in FIGS. 18 and 19 indicates the range of the outer edge of the well regions 54, 54X.

[0217] 17 , in the semiconductor device 10X of the comparative example, the shape of the well-side curved portion 55AX of the well region 54X is different from that of the first embodiment. Specifically, the first center of curvature CP1 of the well-side curved portion 55AX is located at the same position as the second center of curvature CP2 of the field-side curved portions 57A-57D of the multiple field regions 56A-56D. Therefore, the curvature of the well-side curved portion 55AX is greater than the curvature of the field-side curved portions 57A-57D.

[0218] 18 and 19, peaks of the electric field strength occur at the outer edges of the well regions 54, 54X and the field regions 56, 56X. In other words, the electric field strength is low in the regions between adjacent field regions 56 among the multiple field regions 56.

[0219] Thus, in the peripheral region 18 of the semiconductor device 10, a parasitic PNP transistor is formed by each of the well region 54, the field region 56, and the channel stop region 58, the drift region 20, and the collector region 24. There is a concern about BV breakdown due to secondary breakdown of these parasitic PNP transistors.

[0220] The well region 54, the field region 56, and the channel stop region 58 have different electric field strengths. Therefore, it is considered that the region with the highest electric field strength among the well region 54, the field region 56, and the channel stop region 58 is more likely to experience BV breakdown. Here, both the well region 54 and the field region 56 are more likely to have a higher electric field strength than the channel stop region 58.

[0221] In addition, as can be seen from FIGS. 18 and 19, peaks of electric field strength occur at the outer edges of the well regions 54, 54X and in the multiple field regions 56, 56X, and therefore BV breakdown due to secondary breakdown of the parasitic PNP transistor in these regions is of particular concern.

[0222] Furthermore, if the cathode region 110 is provided in the surface layer portion of the second main surface 12B, a parasitic PNP transistor is not formed, thereby suppressing BV breakdown. For this reason, it is preferable to provide the cathode region 110 at a position facing the region with the strongest electric field strength among the well regions 54, 54X and the field regions 56, 56X in the thickness direction of the chip 12.

[0223] On the other hand, it is preferable that the cathode region 110 is provided at a position where the characteristics of the diode 112 formed by the cathode region 110 and the well region 54 are enhanced. Specifically, it is preferable that the cathode region 110 is disposed so as to face, in the thickness direction of the chip 12, a region of the well region 54 that is spaced from the gate line electrode 90 toward the outer well-connecting electrode 84B.

[0224] 18 , in the semiconductor device 10X of the comparative example, the position PK corresponding to the maximum electric field strength is located within the range RA corresponding to the innermost field region 56A. Therefore, in the semiconductor device 10X of the comparative example, from the viewpoint of suppressing BV breakdown, the cathode region 110 is disposed at a position facing the innermost field region 56A in the thickness direction of the chip 12. In this case, the characteristics of the diode 112, particularly the forward current IF, are reduced.

[0225] 19 , in the semiconductor device 10 of the first embodiment, the position PK corresponding to the maximum electric field strength is located in a region corresponding to the outer periphery of the well region 54. More specifically, the position PK is located so as to face, in the thickness direction of the chip 12, a region of the well region 54 that is spaced further toward the outer well connection electrode 84B than the gate line electrode 90. Therefore, in the semiconductor device 10 of the first embodiment, the cathode region 110 is located so as to face, in the thickness direction of the chip 12, a region of the well region 54 that is spaced further toward the outer well connection electrode 84B than the gate line electrode 90. This makes it possible to improve the characteristics of the diode 112 while suppressing BV breakdown.

[0226] As described above, in the semiconductor device 10 of the first embodiment, the shape of the corner portion 55P of the well region 54 is set so that an electric field is more likely to concentrate in a region of the well region 54 that is spaced closer to the outer well-connecting electrode 84B than the gate line electrode 90. Specifically, the curvature of the outer edge of the well-side curved portion 55A of the well region 54 is smaller than the curvature of the outer edge of the innermost field-side curved portion 57A of the innermost field region 56A. As a result, near the outer edge 54B of the corner portion 55P of the well region 54, reduced breakdown voltage regions 59A and 59B are formed, which are more likely to concentrate an electric field than the innermost field region 56A. In other words, the reduced breakdown voltage regions 59A and 59B can be said to be formed in a region of the well region 54 that is spaced closer to the outer well-connecting electrode 84B than the gate line electrode 90. Furthermore, by arranging the cathode region 110 so as to face the reduced breakdown voltage regions 59A and 59B in the thickness direction of the chip 12, BV breakdown can be suppressed. Therefore, it is possible to improve the characteristics of the diode 112 and suppress BV breakdown at the same time.

[0227] [Effects of First Embodiment] The semiconductor device 10 of the first embodiment provides the following effects: (1-1) The semiconductor device 10 includes a chip 12 having a first main surface 12A and a second main surface 12B opposite to the first main surface 12A, a peripheral region 18 provided on the periphery of the first main surface 12A, an IGBT region 14 provided on the first main surface 12A inside the peripheral region 18, a p-type well region 54 provided in a surface layer portion of the first main surface 12A in the peripheral region 18 so as to define the IGBT region 14, a plurality of p-type field regions 56A to 56D provided at intervals from the well region 54 on the peripheral side of the chip 12 in the surface layer portion of the first main surface 12A in the peripheral region 18 and arranged apart from each other, and a plurality of p-type field regions 56A to 56D provided in a surface layer portion of the second main surface 12B in the peripheral region 18 and arranged apart from the well region 54. The chip 12 includes an n-type cathode region 110 constituting a diode 112, an insulating film 60 covering at least the well region 54, an emitter electrode 92 arranged on the insulating film 60 so as to be electrically connected to the well region 54, a collector electrode 108 provided on the second main surface 12B so as to be electrically connected to the cathode region 110, a gate line electrode 90 arranged on the insulating film 60 at a distance from an outer edge 54B of the well region 54 toward the IGBT region 14 so as to face the well region 54, and an outer well connection electrode 84B embedded in the insulating film 60 so as to be connected to a region of the well region 54 closer to the outer edge 54B of the well region 54 than the gate line electrode 90. When viewed from the thickness direction of the chip 12, the well region 54 is annular in shape surrounding the IGBT region 14 and has a plurality of corner portions 55P. When viewed in the thickness direction of the chip 12, each of the multiple field regions 56A-56D is annular and surrounds the well region 54, and has multiple corner portions 57P. Each of the multiple corner portions 55P of the well region 54 includes a well-side curved portion 55A. Each of the multiple corner portions 57P in each of the multiple field regions 56A-56D includes field-side curved portions 57A-57D. The curvature of an outer edge 55AB of the well-side curved portion 55A is different from the curvature of an inner edge 57AA of an innermost field-side curved portion 57A, which is the innermost field-side curved portion of the multiple field-side curved portions 57A-57D.The cathode region 110 is disposed so as to face in the thickness direction of the chip 12 at least a region in the corner portion 55P of the well region 54 that is spaced apart from the gate line electrode 90 toward the outer well-connecting electrode 84B.

[0228] With this configuration, a region where an electric field is likely to concentrate is formed near the outer edge 54B of the well region 54, and the cathode region 110 is disposed so as to face this region in the thickness direction of the chip 12, thereby suppressing BV breakdown. In addition, the cathode region 110 is disposed so as to face, in the thickness direction of the chip 12, a region that is spaced closer to the outer well-connecting electrode 84B than the gate line electrode 90 in the corner portion 55P of the well region 54, which is near the outer edge 54B of the well region 54, thereby improving the characteristics of the diode 112. Therefore, the electrical characteristics of the semiconductor device 10 can be improved.

[0229] (1-2) The cathode region 110 includes a portion facing the outer well-connecting electrode 84B in the thickness direction of the chip 12. With this configuration, a current path is formed that linearly connects the outer well-connecting electrode 84B and the cathode region 110, thereby appropriately increasing the forward current I.

[0230] (1-3) The curvature of the outer edge 55AB of the well-side curved portion 55A is smaller than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A. A first angle AT1 formed between a first tangent LT1 to ends 55AC, 55AD of the outer edge 54B of the well region 54 in the direction in which the well-side curved portion 55A extends and a straight portion 55Q extending from the ends 55AC, 55AD is larger than a second angle AT2 formed between a second tangent LT2 to ends 57AC, 57AD of the outer edge 57AB of the innermost field-side curved portion 57A in the direction in which the innermost field-side curved portion 57A extends and a straight portion 57Q extending from the ends 57AC, 57AD.

[0231] According to this configuration, a region where an electric field is likely to concentrate (low breakdown voltage regions 59A, 59B) is formed at the connection between the ends 55AC, 55AD of the well-side curved portion 55A and the straight portion 55Q. Therefore, the cathode region 110 faces the low breakdown voltage regions 59A, 59B in the thickness direction of the chip 12, thereby suppressing BV breakdown.

[0232] (1-4) The first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A is smaller than the second central angle θ2 of the innermost field-side curved portion 57A. With this configuration, the first angle AT1 formed between the first tangent LT1 of the end portions 55AC, 55AD of the well-side curved portion 55A and the straight portion 55Q tends to be larger than the second angle AT2 formed between the second tangent LT2 of the end portions 57AC, 57AD of the innermost field-side curved portion 57A and the straight portion 57Q. This makes it easier to form regions where electric field concentration is likely to occur (low-voltage-resistance regions 59A, 59B) at the connection portions between the end portions 55AC, 55AD of the well-side curved portion 55A and the straight portion 55Q.

[0233] (1-5) Each of the two end portions 55AC, 55AD in the direction in which the well-side curved portion 55A extends is positioned closer to the center of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends than the two end portions 57AC, 57AD in the direction in which the innermost field-side curved portion 57A extends.

[0234] With this configuration, the first angle AT1 formed between the first tangent LT1 of the end portions 55AC, 55AD of the well-side curved portion 55A and the straight portion 55Q tends to be larger than the second angle AT2 formed between the second tangent LT2 of the end portions 57AC, 57AD of the innermost field-side curved portion 57A and the straight portion 57Q. This tends to form regions where an electric field is likely to concentrate (low-voltage-resistance regions 59A, 59B) at the connection portions between the end portions 55AC, 55AD of the well-side curved portion 55A and the straight portion 55Q.

[0235] (1-6) The cathode region 110 is disposed closer to the IGBT region 14 than the innermost field region 56A. With this configuration, the cathode region 110 can be appropriately provided in a region where the characteristics of the diode 112 can be improved while suppressing BV breakdown. This prevents the width of the cathode region 110 from being excessively large, thereby shortening the time required to form the cathode region 110 during the manufacture of the semiconductor device 10.

[0236] (1-7) When viewed in the thickness direction of the chip 12, the cathode region 110 is annular and has multiple corner portions 111P. Each of the multiple corner portions 111P of the cathode region 110 includes a cathode-side curved portion 111A. The curvature of the outer edge 111C of the cathode-side curved portion 111A is equal to the curvature of the outer edge 55AB of the well-side curved portion 55A.

[0237] With this configuration, the cathode region 110 is likely to be disposed opposite the regions (low breakdown voltage regions 59A and 59B) of the well region 54 where electric fields are likely to concentrate in the thickness direction of the chip 12. This makes it easier to suppress BV breakdown.

[0238] (1-8) The cathode region 110 does not face the gate line electrode 90 in the thickness direction of the chip 12. This configuration appropriately prevents the formation of a detour current path that goes around to the region directly below the gate line electrode 90.

[0239] (1-9) The semiconductor device 10 includes an emitter line electrode 96. The emitter line electrode 96 is disposed on the insulating film 60 at a distance from the gate line electrode 90 toward the periphery of the chip 12 so as to be electrically connected to the well region 54 via the outer well-connecting electrode 84B. The cathode region 110 faces the emitter line electrode 96 in the thickness direction of the chip 12.

[0240] This configuration allows the formation of a current path that linearly connects the emitter line electrode 96 and the cathode region 110. This allows the forward current IF of the diode 112 to be increased during forward operation.

[0241] (1-10) The semiconductor device 10 includes a gate line wiring 70 and a gate connection electrode 80. The gate line wiring 70 is disposed inside the insulating film 60 so as to face the well region 54 in the thickness direction of the chip 12. The gate connection electrode 80 is embedded in the insulating film 60 so as to be connected to the gate line wiring 70. The gate line electrode 90 is electrically connected to the gate line wiring 70 via the gate connection electrode 80. The cathode region 110 is disposed along the second main surface 12B at a distance from a position directly below the center of the gate line wiring 70. This configuration can prevent a current detouring path from being formed in the region directly below the gate line wiring 70.

[0242] (1-11) The cathode region 110 does not face the gate connection electrode 80 in the thickness direction of the chip 12. The cathode region 110 does not face the gate line wiring 70 in the thickness direction of the chip 12. This configuration makes it possible to appropriately prevent the formation of a current detouring path that goes around to the region directly below the gate line wiring 70.

[0243] (1-12) The cathode region 110 is disposed only in the surface layer portion of the second main surface 12B in a region facing the well region 54. With this configuration, the current path of the forward current IF of the diode 112 can be limited to the region between the well region 54 and the cathode region 110. Therefore, a decrease in the forward current IF can be appropriately suppressed. In addition, the peak surge current IFSM can be improved.

[0244] (1-13) When the distance between the center of the gate line electrode 90 and the outer well connection electrode 84B is defined as the second reference distance Db, the cathode region 110 is not disposed within a range that does not exceed half the distance from the gate reference position PG of the second reference distance Db. In other words, the cathode region 110 is disposed in an area outside the prohibited area 122. This configuration can prevent the formation of a current detour path that goes around to the area directly below the gate line electrode 90. This can increase the forward current IF.

[0245] (1-14) When the distance between the center of the gate line electrode 90 and the outer well connecting electrode 84B is defined as a second reference distance Db, the cathode region 110 has a portion that is located within a range not exceeding half the range of the second reference distance Db from the second well reference position PW2 directly below the outer well connecting electrode 84B. In other words, when part or all of the cathode region 110 is located in a region on the second well reference position PW2 side, it is located within the second allowable range 126. With this configuration, the current path between the outer well connecting electrode 84B and the cathode region 110 is shortened, thereby making it possible to appropriately increase the forward current IF.

[0246] (1-15) The cathode region 110 includes a portion overlapping the second well reference position PW2. With this configuration, a current path is formed that linearly connects the outer well connecting electrode 84B and the cathode region 110, thereby appropriately increasing the forward current IF.

[0247] (1-16) The cathode region 110 is disposed along the second main surface 12B at a distance from an intermediate reference position PW3 immediately below the middle between the inner well connecting electrode 84A and the outer well connecting electrode 84B.

[0248] This configuration can prevent a current detour path from being formed in the region immediately below the intermediate portion between the inner well-connecting electrode 84A and the outer well-connecting electrode 84B. This increases the forward current IF of the diode 112 during forward operation. This improves the electrical characteristics of the semiconductor device 10.

[0249] (1-17) When the distance between the inner well-connecting electrode 84A and the outer well-connecting electrode 84B is defined as the third reference distance Dc, the cathode region 110 is not positioned within a range that does not exceed ¼ of the distance from the intermediate reference position PW3. In other words, the cathode region 110 is positioned outside the prohibited range 122. This configuration appropriately prevents the formation of a current detour path that goes around to the region immediately below the intermediate position between the inner well-connecting electrode 84A and the outer well-connecting electrode 84B.

[0250] (1-18) The cathode region 110 is disposed at a distance from the intermediate reference position PW3 toward the outer well-connecting electrode 84B. This configuration shortens the current path between the outer well-connecting electrode 84B and the cathode region 110, thereby increasing the forward current IF.

[0251] (1-19) When the distance between the inner well-connecting electrode 84A and the outer well-connecting electrode 84B is defined as a third reference distance Dc, the cathode region 110 has a portion that is located within a range not exceeding one-quarter of the third reference distance Dc from the second well reference position PW2 directly below the outer well-connecting electrode 84B. In other words, when part or all of the cathode region 110 is located in a region on the second well reference position PW2 side, it is located within the second allowable range 126. With this configuration, the current path between the outer well-connecting electrode 84B and the cathode region 110 can be shortened, thereby appropriately increasing the forward current IF.

[0252] 20 to 22, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the shape of the outer edge 54B of the well region 54 in a plan view, the shape of the cathode region 110 in a plan view, and the configuration of the field region 56. In the following, components common to the first embodiment will be assigned the same reference numerals, and their description may be omitted.

[0253] As shown in FIG. 20 , the first center of curvature CP1 of the outer edge 55AB of the well-side curved portion 55A at the corner portion 55P of the well region 54 is located at the same position as the second center of curvature CP2 of the innermost field-side curved portion 57A at the corner portion 57P of the field region 56. Therefore, the radius of curvature of the outer edge 55AB of the well-side curved portion 55A is smaller than the radius of curvature of the inner edge 57AA of the innermost field-side curved portion 57A. In other words, the curvature of the outer edge 55AB of the well-side curved portion 55A is larger than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A. In the second embodiment, the center of curvature of the inner edge 55AA of the well-side curved portion 55A is the first center of curvature CP1. The center of curvature of the outer edge 57AB of the innermost field-side curved portion 57A is the second center of curvature CP2.

[0254] The third center of curvature CP3 of the outer edge 111C of the cathode-side curved portion 111A at the corner portion 111P of the cathode region 110 is located at the same position as the second center of curvature CP2 in a plan view. In other words, the third center of curvature CP3 is located at the same position as the first center of curvature CP1 in a plan view. Therefore, the radius of curvature of the outer edge 111C of the cathode-side curved portion 111A is smaller than the radius of curvature of the inner edge 57AA of the innermost field-side curved portion 57A. In other words, the curvature of the outer edge 111C of the cathode-side curved portion 111A is larger than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A. In addition, in the second embodiment, the radius of curvature of the outer edge 111C of the cathode-side curved portion 111A is equal to the radius of curvature of the outer edge 55AB of the well-side curved portion 55A. That is, the curvature of the outer edge 111C of the cathode-side curved portion 111A is equal to the curvature of the inner edge 57AA of the well-side curved portion 55A. In the second embodiment, the center of curvature of the inner edge 111B of the cathode-side curved portion 111A is the third center of curvature CP3.

[0255] The first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A, the second central angle θ2 of the innermost field-side curved portion 57A, and the third central angle θ3 of the outer edge 111C of the cathode-side curved portion 111A are all equal. Because the second central angle θ2 of the innermost field-side curved portion 57A is equal to the second central angle θ2 of the field-side curved portions 57B to 57D, it can be said that the first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A and the third central angle θ3 of the outer edge 111C of the cathode-side curved portion 111A are equal to the second central angle θ2 of the field-side curved portions 57B to 57D.

[0256] 21 , the fourth center of curvature CP4 of the outer edge 97C of the emitter-side curved portion 97A provided at each corner 97P of the emitter line electrode 96 in the emitter electrode 92 coincides with the second center of curvature CP2 (see FIG. 20 ) of the innermost field-side curved portion 57A at the corner 57P of the field region 56 in a plan view. Therefore, the radius of curvature of the outer edge 97C of the emitter-side curved portion 97A is smaller than the radius of curvature of the inner edge 57AA (see FIG. 20 ) of the innermost field-side curved portion 57A. In other words, the curvature of the outer edge 97C of the emitter-side curved portion 97A is larger than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A.

[0257] The fourth central angle θ4 of the outer edge 97C of the emitter-side curved portion 97A is equal to the first central angle θ1 of the outer edge 55AB of the well-side curved portion 55A, the second central angle θ2 of the innermost field-side curved portion 57A, and the third central angle θ3 of the outer edge 111C of the cathode-side curved portion 111A (see FIG. 20 for all of these). Because the second central angle θ2 of the innermost field-side curved portion 57A is equal to the second central angle θ2 of the field-side curved portions 57B to 57D, it can be said that the fourth central angle θ4 of the outer edge 97C of the emitter-side curved portion 97A is equal to the second central angle θ2 of the field-side curved portions 57B to 57D. Note that in the second embodiment, the central angle of the inner edge 97B of the emitter-side curved portion 97A is equal to the fourth central angle θ4.

[0258] 20 , each of innermost field-side curved portion 57A and field-side curved portions 57B to 57D in corner portion 57P of field region 56 includes a double-diffusion structure including an inner first diffusion region 142 and an outer second diffusion region 144 having a lower p-type impurity concentration than first diffusion region 142. Hereinafter, the p-type impurity concentration of first diffusion region 142 may be referred to as the "first concentration," and the p-type impurity concentration of second diffusion region 144 may be referred to as the "second concentration." The second concentration is lower than the first concentration.

[0259] An inner edge 57AA of the innermost field-side curved portion 57A forms the inner edge of the first diffusion region 142 of the innermost field-side curved portion 57A. An outer edge 57AB of the innermost field-side curved portion 57A forms the outer edge of the second diffusion region 144 of the innermost field-side curved portion 57A. A boundary line between the first diffusion region 142 and the second diffusion region 144 (hereinafter referred to as the "diffusion region boundary line BLA") is provided in the intermediate portion between the inner edge 57AA and the outer edge 57AB in the width direction of the innermost field-side curved portion 57A. The diffusion region boundary line BLA forms the outer edge of the first diffusion region 142 and the inner edge of the second diffusion region 144 of the innermost field-side curved portion 57A.

[0260] Similarly, for the field-side curved portions 57B-57D, inner edges 57BA-57DA of the field-side curved portions 57B-57D form the inner edges of the first diffusion regions 142 of the field-side curved portions 57B-57D. Outer edges 57BB-57DB of the field-side curved portions 57B-57D form the outer edges of the second diffusion regions 144 of the field-side curved portions 57B-57D. A diffusion region boundary line BLB, which is the boundary line between the first diffusion region 142 and the second diffusion region 144, is provided midway between the inner edge 57BA and the outer edge 57BB in the width direction of the field-side curved portion 57B. The diffusion region boundary line BLB forms the outer edge of the first diffusion region 142 and the inner edge of the second diffusion region 144 of the field-side curved portion 57B. Diffusion region boundary lines BLC and BLD are also provided for the field-side curved portions 57C and 57D, as with the field-side curved portion 57B. Here, the width direction of the field-side curved portions 57A to 57D can be defined as a direction perpendicular to the direction in which the field-side curved portions 57A to 57D extend in a plan view.

[0261] Linear portions 57E to 57H in linear portion 57Q of field region 56 include a single diffusion structure formed by a diffusion region having the same second conductivity type impurity concentration as first diffusion region 142. As described above, in the second embodiment, second diffusion region 144 is provided in a plurality of corner portions 57P of a plurality of field regions 56A to 56D, and is not provided in any portion other than these corner portions 57P.

[0262] In the second embodiment, in each of the four corner portions 57P, the widths of the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D are equal to each other. The widths of the first diffusion regions 142 in the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D are equal to each other. The widths of the second diffusion regions 144 in the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D are equal to each other. In the second embodiment, the width of the second diffusion region 144 is equal to the width of the first diffusion region 142. The widths of the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D are equal to the widths of the straight portions 57E to 57H.

[0263] Here, the width of the innermost field-side curved portion 57A can be defined by the dimension in a direction perpendicular to the extension direction of the innermost field-side curved portion 57A in a planar view. The widths of the field-side curved portions 57B to 57D can be defined by the dimension in a direction perpendicular to the extension direction of the field-side curved portions 57B to 57D in a planar view. The widths of the straight portions 57E to 57H can be defined by the dimension in a direction perpendicular to the extension direction of the straight portions 57E to 57H in a planar view. The width of the first diffusion region 142 can be defined by the dimension in a direction perpendicular to the extension direction of the first diffusion region 142 in a planar view. The width of the second diffusion region 144 can be defined by the dimension in a direction perpendicular to the extension direction of the second diffusion region 144 in a planar view.

[0264] In each of the four corner portions 57P, the widths of the innermost field-side curved portion 57A and the field-side curved portions 57B-57D may be different from one another. The widths of the first diffusion regions 142 may be different from one another in the innermost field-side curved portion 57A and the field-side curved portions 57B-57D. The widths of the second diffusion regions 144 may be different from one another in the innermost field-side curved portion 57A and the field-side curved portions 57B-57D. The widths of the innermost field-side curved portion 57A and the field-side curved portions 57B-57D may be different from the widths of the straight portions 57E-57H. In one example, the widths of the innermost field-side curved portion 57A and the field-side curved portions 57B-57D may be greater than the widths of the straight portions 57E-57H.

[0265] 20 and 22, the width of the first diffusion region 142 of the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D is equal to the width of the second diffusion region 144. Also, as shown in FIG. 22, the depth of the second diffusion region 144 of the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D is equal to the depth of the first diffusion region 142.

[0266] The p-type impurity concentration of the well region 54 is higher than the second concentration of the second diffusion regions 144 of the field-side curved portions 57A to 57D. In the second embodiment, the p-type impurity concentration of the well region 54 is equal to the first concentration of the first diffusion regions 142 of the field-side curved portions 57A to 57D. The second concentration of the second diffusion regions 144 is higher than the n-type impurity concentration of the drift region 20.

[0267] In the second embodiment, the field region 56 in the four straight line portions 57Q is linear in plan view, whereas the field region 56 in the four corner portions 57P is curved in plan view. Therefore, electric field concentration is more likely to occur in the four corner portions 57P than in the four straight line portions 57Q. As a result, the breakdown voltage of the four corner portions 57P is lower than that of the straight line portions 57Q.

[0268] However, the innermost field-side curved portion 57A and the field-side curved portions 57B to 57D of each corner portion 57P have a double diffusion structure including an inner first diffusion region 142 and an outer second diffusion region 144 having a lower p-type impurity concentration than the first diffusion region 142. This makes it possible to smooth the equipotential surface at each corner portion 57P, thereby mitigating electric field concentration at each corner portion 57P. This therefore makes it possible to increase the breakdown voltage of each corner portion 57P.

[0269] On the other hand, electric field concentration is likely to occur at each corner portion 55P of the well region 54. Furthermore, since the breakdown voltage of each corner portion 57P of the field region 56 is increased, the breakdown voltage of each corner portion 55P of the well region 54 is lower than that of each corner portion 57P of the field region 56.

[0270] Therefore, in the second embodiment, the cathode region 110 is disposed at a position facing the well region 54 in the thickness direction of the chip 12. More specifically, the cathode region 110 is disposed at the second well reference position PW2, as in the first embodiment. The method for setting the position of the cathode region 110 is the same as in the first embodiment.

[0271] [Effects of Second Embodiment] The semiconductor device 10 of the second embodiment has the following effects: (2-1) The semiconductor device 10 includes a chip 12 having a first main surface 12A and a second main surface 12B opposite to the first main surface 12A, a peripheral region 18 provided on the periphery of the first main surface 12A, an IGBT region 14 provided on the first main surface 12A inside the peripheral region 18, a p-type well region 54 provided in a surface layer portion of the first main surface 12A in the peripheral region 18 so as to define the IGBT region 14, a plurality of p-type field regions 56A to 56D provided at intervals from the well region 54 on the peripheral side of the chip 12 in the surface layer portion of the first main surface 12A in the peripheral region 18 and arranged apart from each other, and a plurality of p-type field regions 56A to 56D provided in a surface layer portion of the second main surface 12B in the peripheral region 18 and arranged apart from the well region 54. The chip 12 includes an n-type cathode region 110 constituting a diode 112, an insulating film 60 covering at least the well region 54, an emitter electrode 92 arranged on the insulating film 60 so as to be electrically connected to the well region 54, a collector electrode 108 provided on the second main surface 12B so as to be electrically connected to the cathode region 110, a gate line electrode 90 arranged on the insulating film 60 at a distance from an outer edge 54B of the well region 54 toward the IGBT region 14 so as to face the well region 54, and an outer well connection electrode 84B embedded in the insulating film 60 so as to be connected to a region of the well region 54 closer to the outer edge 54B of the well region 54 than the gate line electrode 90. When viewed from the thickness direction of the chip 12, the well region 54 is formed in an annular shape surrounding the IGBT region 14 and has a plurality of corner portions 55P. When viewed in the thickness direction of the chip 12, the multiple field regions 56A-56D are annular and surround the well region 54. Each of the multiple field regions 56A-56D has multiple corner portions 57P. Each of the multiple corner portions 57P in each of the field regions 56A-56D includes a field-side curved portion 57A-57D. The field-side curved portion of at least one of the multiple field regions 56A-56D includes a first diffusion region 142 having a first concentration of first-conductivity-type impurities and a second diffusion region 144 having a second concentration of first-conductivity-type impurities that is lower than the first concentration. The second diffusion region 144 is disposed closer to the periphery of the chip 12 than the first diffusion region 142.The first conductivity type impurity concentration in the well region 54 is higher than the second conductivity type impurity concentration. The cathode region 110 is disposed so as to face, in the thickness direction of the chip 12, a region spaced apart from the gate line electrode 90 on the outer well-connecting electrode 84B side at least in the corner portion 55P of the well region 54.

[0272] This configuration smooths the equipotential surfaces in the field-side curved portions 57A-57D where the second diffusion region 144 is provided, thereby alleviating electric field concentration in the field-side curved portions 57A-57D where the second diffusion region 144 is provided. This increases the breakdown voltage of the field region 56. This results in a lower breakdown voltage for the well region 54 than for the field region 56. In other words, a region where electric fields tend to concentrate is formed near the outer edge 54B of the well region 54. The cathode region 110 is then positioned to face this region in the thickness direction of the chip 12. This suppresses BV breakdown. Additionally, the cathode region 110 is positioned to face the region in the thickness direction of the chip 12, which is spaced closer to the outer well connection electrode 84B than the gate line electrode 90 in the corner portion 55P of the well region 54 near the outer edge 54B of the well region 54. This improves the characteristics of the diode 112. Therefore, the electrical characteristics of the semiconductor device 10 can be improved.

[0273] (2-2) Each of the field regions 56A to 56D includes a first diffusion region 142 and a second diffusion region 144. This configuration makes it possible to smooth the equipotential surfaces in each of the field regions 56A to 56D, thereby mitigating electric field concentration in each of the field regions 56A to 56D. This therefore increases the breakdown voltage of each of the field regions 56A to 56D.

[0274] (2-3) The first conductivity type impurity concentration of the well region 54 is equal to the first concentration. With this configuration, the well region 54 is likely to have a lower breakdown voltage than the plurality of field regions 56A to 56D.

[0275] (2-4) Each of the plurality of corner portions 55P of the well region 54 includes a well-side curved portion 55A. Each of the plurality of corner portions 57P of the plurality of field regions 56 includes field-side curved portions 57A to 57D. The well-side curved portion 55A and the field-side curved portions 57A to 57D have the same center of curvature.

[0276] With this configuration, the distance between well-side curved portion 55A and innermost field-side curved portion 57A and the distances between field-side curved portions 57A to 57D can be set according to the respective radii of curvature of well-side curved portion 55A and field-side curved portions 57A to 57D. Therefore, compared to a case where the centers of curvature of well-side curved portion 55A and field-side curved portions 57A to 57D are different from each other, the distance between well-side curved portion 55A and innermost field-side curved portion 57A and the distances between field-side curved portions 57A to 57D can be set more easily.

[0277] <Modifications> The above-described embodiments can be modified as follows: The following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0278] In the first embodiment, the curvature of the outer edge 55AB of the well-side curved portion 55A in the well region 54 can be changed as desired. For example, the curvature of the outer edge 55AB of the well-side curved portion 55A may be greater or smaller than the curvature of the inner edge 57CA of the field-side curved portion 57C. For example, the curvature of the outer edge 55AB of the well-side curved portion 55A may be equal to or greater than the curvature of the outer edge 57CB of the field-side curved portion 57C. For example, the curvature of the outer edge 55AB of the well-side curved portion 55A may be equal to or greater than the curvature of the inner edge 57DA of the field-side curved portion 57D. For example, the curvature of the outer edge 55AB of the well-side curved portion 55A may be equal to or greater than the curvature of the outer edge 57DB of the field-side curved portion 57D.

[0279] 23, the curvature of the outer edge 55AB of the well-side curved portion 55A may be greater than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A in the innermost field region 56A. The curvature of the outer edge 55AB of the well-side curved portion 55A may be greater than the curvature of the inner edge 55AA of the well-side curved portion 55A.

[0280] The first center of curvature CP1 of the outer edge 55AB of the well-side curved portion 55A is positioned differently from the second center of curvature CP2 of the innermost field-side curved portion 57A. More specifically, the first center of curvature CP1 is positioned closer to the periphery of the tip 12 on the straight line LA than the second center of curvature CP2. The center of curvature of the inner edge 55AA of the well-side curved portion 55A may be positioned in the same position as in the first embodiment. Therefore, the center of curvature of the inner edge 55AA of the well-side curved portion 55A is positioned differently from the first center of curvature CP1.

[0281] As in the first embodiment, the two end portions 55AC, 55AD in the direction in which the well-side curved portion 55A extends are positioned closer to the center of the well-side curved portion 55A in the direction in which the well-side curved portion 55A extends than the two end portions 57AC, 57AD in the direction in which the innermost field-side curved portion 57A extends.

[0282] Additionally, the curvature of the outer edge 111C of the cathode curved portion 111A in the cathode region 110 may be greater than the curvature of the inner edge 57AA of the innermost field curved portion 57A in the innermost field region 56A. In one example, the curvature of the outer edge 111C of the cathode curved portion 111A is smaller than the curvature of the inner edge 111B of the cathode curved portion 111A.

[0283] In the first embodiment, the shape of the emitter-side curved portion 97A of the emitter line electrode 96 in plan view can be changed as desired. For example, the fourth center of curvature CP4 of the outer edge 97C of the emitter-side curved portion 97A may be located at a position different from the first center of curvature CP1 of the outer edge 55AB of the well-side curved portion 55A of the well region 54 in plan view. For example, the curvature of the outer edge 97C of the emitter-side curved portion 97A may be equal to or smaller than the curvature of the outer edge 55AB of the well-side curved portion 55A. For example, the curvature of the outer edge 97C of the emitter-side curved portion 97A may be equal to or smaller than the curvature of the outer edge 111C of the cathode-side curved portion 111A.

[0284] In the first embodiment, the positions of the multiple straight line portions 111Q of the cathode region 110 can be changed as desired. For example, the multiple straight line portions 111Q do not need to face the region spaced closer to the outer well-connecting electrode 84B than the gate line electrode 90 in the thickness direction of the chip 12. For example, the multiple straight line portions 111Q may be arranged to face the multiple straight line portions 57Q of the innermost field region 56A in the thickness direction of the chip 12.

[0285] In the second embodiment, the relationship between the width of the first diffusion region 142 and the width of the second diffusion region 144 can be changed as desired. In a first example, as shown in Fig. 24, the width of the second diffusion region 144 may be smaller than the width of the first diffusion region 142. In a second example, as shown in Fig. 25, the width of the second diffusion region 144 may be larger than the width of the first diffusion region 142.

[0286] In the second embodiment, the relationship between the depth of the first diffusion region 142 and the depth of the second diffusion region 144 can be changed as desired. In one example, as shown in FIG. 26 , the depth of the second diffusion region 144 may be deeper than the depth of the first diffusion region 142. Note that in the modified example shown in FIG. 26 , the width of the first diffusion region 142 is greater than the width of the second diffusion region 144, but this is not limited to this. The widths of the first diffusion region 142 and the second diffusion region 144 can each be changed as desired. As in the second embodiment, the widths of the first diffusion region 142 and the second diffusion region 144 may be equal to each other, or the width of the second diffusion region 144 may be greater than the width of the first diffusion region 142.

[0287] In the second embodiment, the formation range of the second diffusion region 144 can be changed as desired. For example, as shown in FIG. 27 , the second diffusion region 144 may include a protrusion region 146 that protrudes from the field-side curved portions 57A-57D in the direction in which the field-side curved portions 57A-57D extend. In the example shown in FIG. 27 , the protrusion region 146 protrudes from the field-side curved portions 57A-57D toward the straight portion 57Q. For example, in the innermost field region 56A, the protrusion region 146 is provided at both ends in the direction in which the innermost field-side curved portion 57A extends. For example, in the field regions 56B-56D, the protrusion region 146 is provided at both ends in the direction in which each of the field-side curved portions 57B-57D extends.

[0288] The protruding region 146 may be provided only at one end of the field-side curved portions 57A-57D in the direction in which they extend. Furthermore, some of the field-side curved portions 57A-57D may not have the protruding region 146. The protruding region 146 does not necessarily have to be provided in all of the field regions 56A-56D, but may be provided in only some of the field regions 56A-56D. In short, it is sufficient that the protruding region 146 is provided in at least one of the field regions 56A-56D.

[0289] In the second embodiment, the second diffusion region 144 does not have to be provided in all of the plurality of field regions 56. The second diffusion region 144 only needs to be provided in the field regions where electric field concentration is likely to occur, i.e., the innermost field-side curved portion 57A and the field-side curved portion 57B. In other words, the second diffusion region 144 does not have to be provided in the field-side curved portions 57C and 57D.

[0290] In the second embodiment, the shape of the well-side curved portion 55A in the well region 54 in a plan view can be changed as desired. In one example, as shown in FIGS. 28 and 29 , the curvature of the outer edge 55AB of the well-side curved portion 55A may be smaller than the curvature of the inner edge 57AA of the innermost field-side curved portion 57A of the innermost field region 56A. In other words, the second embodiment may be combined with the configuration of the well region 54 of the first embodiment. In this case, the cathode-side curved portion 111A in the cathode region 110 may also have the same shape as in the first embodiment. Furthermore, the position of the cathode region 110 may also be the same as in the first embodiment.

[0291] In the second embodiment, the p-type impurity concentration of the well region 54 can be changed as desired. For example, the p-type impurity concentration of the well region 54 may be higher than a first concentration, which is the p-type impurity concentration of the first diffusion region 142. For example, the p-type impurity concentration of the well region 54 may be lower than the first concentration of the first diffusion region 142. Note that when the p-type impurity concentration of the well region 54 is lower than the first concentration, the p-type impurity concentration of the well region 54 may be higher than a second concentration, which is the p-type impurity concentration of the second diffusion region 144, for example.

[0292] In one example, the p-type impurity concentration in the corner portion 55P of the well region 54 may be different from the p-type impurity concentration in the straight portion 55Q. In one example, the p-type impurity concentration in the corner portion 55P may be higher than the p-type impurity concentration in the straight portion 55Q. In one example, the p-type impurity concentration in the corner portion 55P may be higher than the first concentration of the first diffusion region 142.

[0293] In each embodiment, the relationship between the impurity concentrations of the cathode region 110 and the collector region 24 can be changed as desired. In one example, the n-type impurity concentration of the cathode region 110 may be equal to the p-type impurity concentration of the collector region 24. In another example, the n-type impurity concentration of the cathode region 110 may be lower than the p-type impurity concentration of the collector region 24.

[0294] In each embodiment, the cathode region 110 may have a width less than the width of the emitter line electrode 96. Note that the cathode region 110 may have a width equal to or greater than the width of the emitter line electrode 96.

[0295] In each embodiment, the cathode region 110 may extend to a position facing the field regions 56A to 56D in the thickness direction of the chip 12. In one example, the cathode region 110 may extend from the second well reference position PW2 in the thickness direction of the chip 12 to a position facing the innermost field region 56A in the thickness direction of the chip 12.

[0296] In each embodiment, the widths of the multiple field electrodes 102 can be individually changed as desired. In one example, the width of field electrode 102D of the multiple field electrodes 102 may be equal to the widths of field electrodes 102A to 102C. In one example, the width of at least one of field electrodes 102A to 102C may be different from the width of the other field electrodes. In one example, the widths of field electrodes 102A to 102C may be determined according to the widths of field regions 56A to 56C. In one example, when the width of field region 56C is greater than the widths of field regions 56A and 56B, the width of field electrode 102C may be greater than the widths of field electrodes 102A and 102B.

[0297] In each embodiment, the multiple emitter connecting electrodes 76 may be integrated with the emitter pad electrode 94 (emitter electrode 92). In other words, the emitter pad electrode 94 may be disposed on the insulating film 60 so as to extend into the multiple emitter openings 74. In this case, multiple portions of the emitter pad electrode 94 located within the multiple emitter openings 74 are formed as the multiple emitter connecting electrodes 76.

[0298] In each embodiment, the multiple gate connection electrodes 80 may be integrated with the gate electrode 86 (gate line electrode 90). That is, the gate electrode 86 may be disposed on the insulating film 60 so as to extend into the multiple gate openings 78. In this case, multiple portions of the gate electrode 86 located within the multiple gate openings 78 are formed as the multiple gate connection electrodes 80.

[0299] In each embodiment, the multiple inner well connecting electrodes 84A may be integrated with the emitter pad electrode 94 (emitter electrode 92). That is, the emitter pad electrode 94 may be disposed on the insulating film 60 so as to extend into the multiple first well openings 82A. In this case, multiple portions of the emitter pad electrode 94 located within the multiple first well openings 82A are formed as the multiple inner well connecting electrodes 84A.

[0300] In each embodiment, the outer well connecting electrodes 84B may be integrated with the emitter pad electrode 94 (emitter electrode 92). In other words, the emitter pad electrode 94 may be disposed on the insulating film 60 so as to extend into the second well openings 82B. In this case, the portions of the emitter pad electrode 94 located within the second well openings 82B are formed as the outer well connecting electrodes 84B.

[0301] In each embodiment, the multiple field connection electrodes 100 may be integrated with the field electrode 102. In other words, the field electrode 102 may be disposed on the insulating film 60 so as to extend into the multiple field openings 98. In this case, the multiple portions of the field electrode 102 located within the multiple field openings 98 are formed as the multiple field connection electrodes 100.

[0302] In each embodiment, the emitter line electrode 96 may be disposed only in the region facing the well region 54 in the thickness direction of the chip 12. In each embodiment, the width of the gate line electrode 90 may be equal to or smaller than the width of the gate line wiring 70.

[0303] In each embodiment, the formation area of ​​the insulating film 60 can be changed as desired. The insulating film 60 only needs to cover at least the well region 54. In each embodiment, the chip 12 is not limited to a silicon single crystal substrate and can be changed as desired. In one example, the chip 12 may be a single crystal substrate of a wide bandgap semiconductor. For example, the chip 12 may be a SiC (silicon carbide) single crystal substrate, a GaN single crystal substrate, or the like.

[0304] In each embodiment, an n-type semiconductor region may be replaced with a p-type semiconductor region, and a p-type semiconductor region may be replaced with an n-type semiconductor region. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0305] One or more of the various examples described in this disclosure can be combined to the extent that they are not technically inconsistent. The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be in contact with the second element and disposed directly on the second element, but in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0306] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0307] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0308] [Supplementary Note 1] A chip (12) having a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the periphery of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) in the first main surface (12A); a well region (54) of a first conductivity type (p) provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); and a plurality of field regions (56A to 56D / 56) of a first conductivity type (p) provided at intervals from the well region (54) on the peripheral side of the chip (12) in the surface layer portion of the first main surface (12A) of the outer peripheral region (18) and arranged spaced apart from each other. a cathode region (110) of a second conductivity type (n) provided in a surface layer portion of the second main surface (12B) of the peripheral region (18), and constituting a diode (112) together with the well region (54); an insulating film (60) covering at least the well region (54); an emitter electrode (92) arranged on the insulating film (60) so as to be electrically connected to the well region (54); a collector electrode (108) provided on the second main surface (12B) so as to be electrically connected to the cathode region (110); and a gate line electrode (90) arranged on the insulating film (60) at a distance from an outer edge (54B) of the well region (54) toward the IGBT region (14) so ​​as to face the well region (54) in the thickness direction (Z) of the chip (12). an outer well connection electrode (84B) embedded in the insulating film (60) so as to be connected to a region of the well region (54) closer to the outer edge (54B) of the well region (54) than the gate line electrode (90); when viewed in the thickness direction (Z) of the chip (12), the well region (54) is annular so as to surround the IGBT region (14) and has a plurality of corner portions (55P); when viewed in the thickness direction (Z) of the chip (12), each of the plurality of field regions (56) is annular so as to surround the well region (54) and has a plurality of corner portions (57P); each of the plurality of corner portions (55P) of the well region (54) includes a well-side curved portion (55A);a gate line electrode (90) in the corner portion (55P) of the well region (54) and a gate electrode (90) in the well region (54) that is spaced from the gate line electrode (90) toward the outer well-connecting electrode (84B) in the thickness direction (Z) of the chip (12), the cathode region (110) being disposed opposite the gate line electrode (90) in the corner portion (55P) of the well region (54).

[0309] [Supplementary Note 2] The semiconductor device according to Supplementary Note 1, wherein the cathode region (110) includes a portion facing the outer well connection electrode (84B) in the thickness direction (Z) of the chip (12).

[0310] [Supplementary Note 3] The semiconductor device according to Supplementary Note 1 or 2, wherein a curvature of an outer edge (55AB) of the well-side curved portion (55A) is smaller than a curvature of an inner edge (57AA) of the innermost field-side curved portion (57A), and a first angle (AT1) formed between a tangent (LT1) to an end (55AC, 55AD) of the outer edge (54B) of the well region (54) in a direction in which the well-side curved portion (55A) extends and a straight portion (55Q) extending from the end (55AC, 55AD) is larger than a second angle (AT2) formed between a tangent (LT2) to an end (57AC, 57AD) of the outer edge (57AB) of the innermost field-side curved portion (57A) in a direction in which the innermost field-side curved portion (57A) extends and a straight portion (57Q) extending from the end (57AC, 57AD).

[0311] [Supplementary Note 4] The semiconductor device according to Supplementary Note 3, wherein a first central angle (θ1) of an outer edge (55AB) of the well-side curved portion (55A) is smaller than a second central angle (θ2) of the innermost field-side curved portion (57A).

[0312] [Supplementary Note 5] The semiconductor device according to Supplementary Note 3 or 4, wherein the distance between the innermost field-side curved portion (57A) and the well-side curved portion (55A) is smaller than the distance between adjacent field regions among the plurality of field regions (56A to 56D / 56).

[0313] [Appendix 6] The semiconductor device according to any one of appendices 3 to 5, wherein each of the two end portions (55AC, 55AD) in the direction in which the well-side curved portion (55A) extends is disposed closer to the center of the well-side curved portion (55A) in the direction in which the well-side curved portion (55A) extends than each of the two end portions (57AC, 57AD) in the direction in which the innermost field-side curved portion (57A) extends.

[0314] [Supplementary Note 7] The semiconductor device according to Supplementary Note 1 or 2, wherein the curvature of the outer edge (55AB) of the well-side curved portion (55A) is greater than the curvature of the inner edge (57AA) of the innermost field-side curved portion (57A), and each of the two end portions (55AC, 55AD) in the direction in which the well-side curved portion (55A) extends is positioned closer to the center of the well-side curved portion (55A) in the direction in which the well-side curved portion (55A) extends than the two end portions (57AC, 57AD) in the direction in which the innermost field-side curved portion (57A) extends.

[0315] [Supplementary Note 8] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein a center of curvature (CP1) of the well-side curved portion (55A) is different from a center of curvature (CP2) of the innermost field-side curved portion (57A).

[0316] [Supplementary Note 9] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the cathode region (110) is arranged closer to the IGBT region (14) than an innermost field region (56A) of the plurality of field regions (56A to 56D / 56).

[0317] [Supplementary Note 10] The semiconductor device according to Supplementary Note 9, wherein the cathode region (110) is arranged to face an outer edge (54B) of the well region (54) in the thickness direction (Z) of the chip (12).

[0318] [Appendix 11] The semiconductor device according to appendix 10, wherein, when viewed from the thickness direction (Z) of the chip (12), the cathode region (110) is annular having a plurality of corner portions (111P), each of the plurality of corner portions (111P) of the cathode region (110) includes a cathode-side curved portion (111A), and the curvature of an outer edge (111C) of the cathode-side curved portion (111A) is equal to the curvature of an outer edge (55AB) of the well-side curved portion (55A).

[0319] [Supplementary Note 12] The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the first conductivity type impurity concentration of the field region (56A to 56D / 56) is constant in the width direction of the field region (56A to 56D / 56).

[0320] [Supplementary Note 13] The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein each of a plurality of corner portions (57P) in at least one of the plurality of field regions (56A to 56D / 56) includes: a first diffusion region (142) having a first concentration of a first conductivity type impurity; and a second diffusion region (144) arranged on the opposite side of the first diffusion region (142) from the well region (54), the second diffusion region (144) having the first conductivity type impurity concentration of a second concentration lower than the first concentration, wherein the first conductivity type impurity concentration of the well region (54) is higher than the second concentration.

[0321] [Supplementary Note 14] The semiconductor device according to Supplementary Note 13, wherein each of the plurality of field regions (56A to 56D / 56) includes the first diffusion region (142) and the second diffusion region (144).

[0322] [Supplementary Note 15] The semiconductor device according to Supplementary Note 13 or 14, further comprising a second conductivity type drift region (20) provided inside the chip (12), wherein the first conductivity type impurity concentration of the second diffusion region (144) is higher than the second conductivity type impurity concentration of the drift region (20).

[0323] [Supplementary Note 16] The semiconductor device according to any one of Supplementary Notes 13 to 15, wherein the first conductivity type impurity concentration of the well region (54) is equal to the first concentration.

[0324] [Supplementary Note 17] The semiconductor device according to any one of Supplementary Notes 13 to 16, wherein the second diffusion region (144) is provided in a plurality of corner portions (57P) of at least one of the plurality of field regions (56A to 56D / 56), and is not provided in any portion other than the plurality of corner portions (57P).

[0325] [Supplementary Note 18] The semiconductor device according to any one of Supplementary Notes 13 to 16, wherein the second diffusion region (144) includes a protruding region (146) that protrudes from the first diffusion region (142) in a direction in which a corner portion (57P) of the field region (56A to 56D / 56) extends.

[0326] [Supplementary Note 19] The semiconductor device according to any one of Supplementary Notes 13 to 18, wherein each of the plurality of corner portions (55P) of the well region (54) includes a well-side curved portion (55A), and each of the plurality of corner portions (57P) in each of the plurality of field regions (56A to 56D / 56) includes a field-side curved portion (57A), and the well-side curved portion (55A) and the field-side curved portion (57A) have the same center of curvature (CP1 / CP2).

[0327] [Supplementary Note 20] The semiconductor device according to any one of Supplementary Notes 13 to 19, wherein the width of the second diffusion region (144) is equal to the width of the first diffusion region (142).

[0328] [Supplementary Note 21] The semiconductor device according to any one of Supplementary Notes 13 to 19, wherein the width of the second diffusion region (144) is smaller than the width of the first diffusion region (142).

[0329] [Supplementary Note 22] The semiconductor device according to any one of Supplementary Notes 13 to 19, wherein the width of the second diffusion region (144) is greater than the width of the first diffusion region (142).

[0330] [Supplementary Note 23] The semiconductor device according to any one of Supplementary Notes 13 to 22, wherein the first conductivity type impurity concentration in the corner portion (55P) of the well region (54) is higher than the first concentration.

[0331] [Supplementary Note 24] A chip (12) having a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the periphery of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) in the first main surface (12A); a well region (54) of a first conductivity type provided in a surface layer of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); and a plurality of field regions (56A to 56D / 56) of a first conductivity type provided at intervals from the well region (54) on the periphery side of the chip (12) in the surface layer of the first main surface (12A) of the outer peripheral region (18) and arranged spaced apart from each other. a cathode region (110) of a second conductivity type provided in a surface layer portion of the second main surface (12B) of the outer peripheral region (18), and constituting a diode (112) together with the well region (54); an insulating film (60) covering at least the well region (54); an emitter electrode (92) arranged on the insulating film (60) so as to be electrically connected to the well region (54); a collector electrode (108) provided on the second main surface (12B) so as to be electrically connected to the cathode region (110); and a gate line electrode (90) arranged on the insulating film (60) at a distance from the outer edge (54B) of the well region (54) toward the IGBT region (14) so ​​as to face the well region (54). an outer well connection electrode (84B) embedded in the insulating film (60) so as to be connected to a region in the well region (54) closer to the outer edge (54B) of the well region (54) than the gate line electrode (90); when viewed in the thickness direction (Z) of the chip (12), the well region (54) is provided in an annular shape surrounding the IGBT region (14) and has a plurality of corner portions (55P); when viewed in the thickness direction (Z) of the chip (12), the plurality of field regions (56A to 56D / 56) are annular and provided so as to surround the well region (54), and each of the plurality of field regions (56A to 56D / 56) has a plurality of corner portions (57P);Each of a plurality of corner portions (57P) in each of the plurality of field regions (56A to 56D / 56) includes a field-side curved portion (57A), and the field-side curved portion (57A) of at least one of the plurality of field regions (56A to 56D / 56) includes: a first diffusion region (142) having a first concentration of a first conductivity type impurity; and a second diffusion region (144) having a second concentration of the first conductivity type impurity that is lower than the first concentration, the second diffusion region (144) being arranged closer to the periphery of the chip (12) than the first diffusion region (142), and the first conductivity type impurity concentration of the well region (54) being higher than the second concentration, The cathode region (110) is arranged to face a region of the well region (54) at least in the corner portion (55P) of the well region (54) that is spaced closer to the outer well-connecting electrode (84B) than the gate line electrode (90) in the thickness direction (Z) of the chip (12).

[0332] [Supplementary Note 25] The semiconductor device according to Supplementary Note 24, wherein the cathode region (110) includes a portion facing the outer well connection electrode (84B) in the thickness direction (Z) of the chip (12).

[0333] [Supplementary Note 26] The semiconductor device according to Supplementary Note 24 or 25, further comprising a second conductivity type drift region (20) provided inside the chip (12), wherein the first conductivity type impurity concentration of the second diffusion region (144) is higher than the second conductivity type impurity concentration of the drift region (20).

[0334] [Supplementary Note 27] The semiconductor device according to any one of Supplementary Notes 24 to 26, wherein the first conductivity type impurity concentration of the well region (54) is equal to the first concentration.

[0335] [Appendix 28] The semiconductor device according to any one of Appendices 24 to 27, wherein the second diffusion region (144) is provided in a plurality of corner portions (57P) of at least one of the plurality of field regions (56A to 56D / 56), and is not provided in any portion other than the plurality of corner portions (57P).

[0336] [Supplementary Note 29] The semiconductor device according to any one of Supplementary Notes 24 to 27, wherein the second diffusion region (144) includes a protruding region (146) that protrudes from the field-side curved portion (57A) in a direction in which the field-side curved portion (57A) extends.

[0337] [Supplementary Note 30] The semiconductor device according to any one of Supplementary Notes 24 to 29, wherein each of the plurality of corner portions (55P) of the well region (54) includes a well-side curved portion (55A), and the well-side curved portion (55A) and the field-side curved portions (57A to 57D) have the same center of curvature (CP1 / CP2).

[0338] [Supplementary Note 31] The semiconductor device according to any one of Supplementary Notes 24 to 30, wherein the width of the second diffusion region (144) is equal to the width of the first diffusion region (142).

[0339] [Supplementary Note 32] The semiconductor device according to any one of Supplementary Notes 24 to 30, wherein the width of the second diffusion region (144) is smaller than the width of the first diffusion region (142).

[0340] [Supplementary Note 33] The semiconductor device according to any one of Supplementary Notes 24 to 30, wherein the width of the second diffusion region (144) is greater than the width of the first diffusion region (142).

[0341] [Supplementary Note 34] The semiconductor device according to any one of Supplementary Notes 24 to 33, wherein the first conductivity type impurity concentration in the corner portion (55P) of the well region (54) is higher than the first concentration.

[0342] [Supplementary Note 35] The semiconductor device according to any one of Supplementary Notes 1 to 34, wherein the cathode region (110) extends to a position opposite the field region (56A to 56D / 56) in the thickness direction (Z) of the chip (12).

[0343] [Supplementary Note 36] The emitter electrode (92) includes an emitter line electrode (96) provided to face a region of the well region (54) that is closer to an outer edge (54B) of the well region (54) than the gate line electrode (90) in the thickness direction (Z) of the chip (12), the emitter line electrode (96) is annular in shape so as to surround the IGBT region (14) as viewed in the thickness direction (Z) of the chip (12) and has a plurality of corner portions (97P), each of the plurality of corner portions (97P) of the emitter line electrode (96) includes an emitter-side curved portion (97A), and the emitter electrode (92) includes a plurality of field electrodes (102A to 102D / 102) provided on the insulating film (60) and electrically connected to the plurality of field regions (56A to 56D / 56) individually, A semiconductor device as described in any one of appendices 1 to 35, wherein, when viewed from the thickness direction (Z) of the chip (12), the plurality of field electrodes (102A to 102D / 102) are annular in shape surrounding the emitter line electrode (96) and have a plurality of corner portions (103P), each of the plurality of corner portions (103P) in each of the plurality of field electrodes (102A to 102D / 102) includes a field electrode side curved portion (103A), and the curvature of the outer edge (97C) of the emitter side curved portion (97A) is smaller than the curvature of the inner edge (103AA) of the field electrode side curved portion (103A) of an innermost field electrode (102A) that is the innermost field electrode of the plurality of field electrodes (102A to 102D).

[0344] [Supplementary Note 37] The semiconductor device according to Supplementary Note 36, wherein a central angle (θ4) of an outer edge (97C) of the emitter-side curved portion (97A) is smaller than a central angle (θ5) of the field electrode-side curved portion (103A) of the innermost field electrode (102A).

[0345] [Appendix 38] The semiconductor device according to appendix 36 or 37, wherein both ends (97D, 97E) in the direction in which the emitter-side curved portion (97A) extends are positioned closer to the center of the emitter-side curved portion (97A) in the direction in which the emitter-side curved portion (97A) extends than both ends (103AC, 103AD) in the direction in which the field electrode-side curved portion (103A) of the innermost field electrode (102A) extends.

[0346] [Appendix 39] The semiconductor device according to any one of Appendices 1 to 23, wherein the chip (12) is a rectangular flat plate, and both the center of curvature (CP1) of the corner portion (55P) of the well region (54) and the center of curvature (CP2) of the innermost field-side curved portion (57A) are located on a straight line (LA) that divides the apex angle of the corner portion of the chip (12) in half.

[0347] [Appendix 40] The semiconductor device according to appendix 1 or 24, wherein when the distance between the center of the gate line electrode (90) and the outer well connecting electrode (84B) is defined as a reference distance (Db), the cathode region (110) is not disposed within a range that does not exceed 1 / 2 of the reference distance (Db) from a gate reference position (PG) directly below the center of the gate line electrode (90) toward the outer well connecting electrode (84B).

[0348] [Appendix 41] The semiconductor device according to appendix 1 or 24, wherein when the distance between the center of the gate line electrode (90) and the outer well connecting electrode (84B) is defined as a reference distance (Db), the cathode region (110) includes a portion disposed within a range not exceeding ½ of the reference distance (Db) from a second well reference position (PW2) directly below the outer well connecting electrode (84B).

[0349] [Appendix 42] The semiconductor device according to appendix 41, wherein the cathode region (110) is not disposed within a range not exceeding half the reference distance (Db) from a gate reference position (PG) directly below the center of the gate line electrode (90) toward the outer well connection electrode (84B).

[0350] [Supplementary Note 43] The semiconductor device according to any one of Supplementary Notes 40 to 42, wherein the cathode region (110) does not face the gate line electrode (90) in the thickness direction (Z) of the chip (12).

[0351] [Appendix 44] The semiconductor device according to any one of appendices 40 to 43, wherein the cathode region (110) is arranged only in a region facing the well region (54) in a surface layer portion of the second main surface (12B).

[0352] [Appendix 45] The semiconductor device according to any one of Appendices 41 to 44, further comprising: a gate line wiring (70) arranged inside the insulating film (60) so as to face the well region (54); and a gate connection electrode (80) embedded in the insulating film (60) so as to be connected to the gate line wiring (70), wherein the gate line electrode (90) is electrically connected to the gate line wiring (70) via the gate connection electrode (80).

[0353] [Supplementary Note 46] The semiconductor device according to Supplementary Note 45, wherein the cathode region (110) does not face the gate connection electrode (80) in the thickness direction (Z) of the chip (12).

[0354] [Supplementary Note 47] The semiconductor device according to Supplementary Note 45 or 46, wherein the cathode region (110) does not face the gate line wiring (70) in the thickness direction (Z) of the chip (12).

[0355] [Appendix 48] The semiconductor device according to appendix 1 or 24, further comprising an inner well connection electrode (84A) embedded in the insulating film (60) at a distance from the outer well connection electrode (84B) toward the IGBT region (14) so ​​as to be connected to the well region (54), wherein the cathode region (110) is arranged to face a region of the well region (54) at a distance from an intermediate reference position (PW3) immediately below the middle between the inner well connection electrode (84A) and the outer well connection electrode (84B) toward the outer well connection electrode (84B) in a thickness direction (Z) of the chip (12).

[0356] [Appendix 49] The semiconductor device according to Appendix 48, wherein when the distance between the inner well connecting electrode (84A) and the outer well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) is not positioned within a range that does not exceed ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the outer well connecting electrode (84B).

[0357] [Appendix 50] The semiconductor device according to Appendix 48, wherein when the distance between the inner well connecting electrode (84A) and the outer well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) has a portion that is arranged within a range that does not exceed ¼ of the reference distance (Dc) from a second well reference position (PW2) directly below the outer well connecting electrode (84B) toward the intermediate reference position (PW3).

[0358] [Appendix 51] The semiconductor device according to appendix 50, wherein the cathode region (110) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the outer well connecting electrode (84B).

[0359] [Appendix 52] The semiconductor device according to appendix 1 or 24, including an inner well connection electrode (84A) embedded in the insulating film (60) at a distance from the outer well connection electrode (84B) toward the IGBT region (14) so ​​as to be connected to the well region (54), and the cathode region (110) includes: a first cathode region (110A) arranged at a distance from an intermediate reference position (PW3) immediately below the middle between the inner well connection electrode (84A) and the outer well connection electrode (84B) in the well region (54) toward the inner well connection electrode (84A), and a second cathode region (110B) arranged at a distance from the intermediate reference position (PW3) toward the outer well connection electrode (84B).

[0360] [Appendix 53] The semiconductor device according to Appendix 52, wherein when the distance between the inner well connecting electrode (84A) and the outer well connecting electrode (84B) is defined as a reference distance (Dc), the first cathode region (110A) is not positioned within a range that does not exceed ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the inner well connecting electrode (84A).

[0361] [Appendix 54] The semiconductor device according to Appendix 52, wherein when the distance between the inner well connecting electrode (84A) and the outer well connecting electrode (84B) is defined as a reference distance (Dc), the first cathode region (110A) includes a portion disposed within a range not exceeding ¼ of the reference distance (Dc) from a first well reference position (PW1) directly below the inner well connecting electrode (84A) toward the intermediate reference position (PW3).

[0362] [Appendix 55] The semiconductor device according to Appendix 54, wherein the first cathode region (110A) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the inner well connecting electrode (84A).

[0363] [Appendix 56] The semiconductor device described in Appendix 52, wherein when the distance between the inner well connecting electrode (84A) and the outer well connecting electrode (84B) is defined as a reference distance (Dc), the second cathode region (110B) is not positioned within a range that does not exceed ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the outer well connecting electrode (84B).

[0364] [Appendix 57] The semiconductor device according to Appendix 52, wherein when the distance between the inner well connecting electrode (84A) and the outer well connecting electrode (84B) is defined as a reference distance (Dc), the second cathode region (110B) includes a portion disposed within a range not exceeding ¼ of the reference distance (Dc) from a second well reference position (PW2) directly below the outer well connecting electrode (84B) toward the intermediate reference position (PW3).

[0365] [Appendix 58] The semiconductor device according to Appendix 57, wherein the second cathode region (110B) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the outer well connecting electrode (84B).

[0366] [Supplementary Note 59] The semiconductor device according to any one of Supplementary Notes 52 to 58, further comprising a base region (36) of a first conductivity type provided in a surface layer portion of the first main surface (12A) in the IGBT region (14).

[0367] [Supplementary Note 60] The semiconductor device according to Supplementary Note 59, wherein the first cathode region (110A) does not face the base region (36) in the thickness direction (Z) of the chip (12).

[0368] [Supplementary Note 61] The semiconductor device according to Supplementary Note 59 or 60, wherein the well region (54) is deeper than the base region (36).

[0369] [Appendix 62] The semiconductor device according to any one of appendices 59 to 61, wherein the well region (54) has a portion that is drawn from the outer periphery region (18) to the IGBT region (14) and connected to the base region (36).

[0370] [Supplementary Note 63] The semiconductor device according to any one of Supplementary Notes 52 to 62, further comprising a trench gate structure (38) provided on the first main surface (12) in the IGBT region (14).

[0371] [Supplementary Note 64] The semiconductor device according to Supplementary Note 63, wherein the first cathode region (110A) does not face the trench gate structure (38) in the thickness direction (Z) of the chip (12).

[0372] [Supplementary Note 65] The semiconductor device according to Supplementary Note 63 or 64, wherein the well region (54) is drawn from the outer peripheral region (18) to the IGBT region (14) and has a portion covering a bottom wall of the trench gate structure (38).

[0373] [Supplementary Note 66] The semiconductor device according to any one of Supplementary Notes 52 to 65, wherein the first cathode region (110A) is provided in a ring shape surrounding the IGBT region (14).

[0374] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0375] DESCRIPTION OF SYMBOLS 10...Semiconductor device 12...Chip 12A...First main surface 12B...Second main surface 12C-12F...First to fourth side surfaces 14...IGBT region 16...Pad region 18...Periphery region 20...Drift region 22...Buffer region 24...Collector region 26...Trench isolation structure 28...Isolation trench 30...Isolation insulating film 32...Isolation buried electrode 34...IGBT structure 36...Base region 38...Trench gate structure 38A...First end 38B...Second end 40...Gate trench 42...Gate insulating film 44...Gate buried electrode 46...Emitter region 48...Contact hole 50...Contact region 52...Pad well region 54...Well region 54A...Inner edge 54B...Outer edge 55A...Well-side curved portion 55AA...Inner edge 55AB...outer edge 55AC, 55AD...ends 55P...corner portion 55Q...straight portion 56...field region 56A...innermost field region (field region) 56B to 56D...field region 57A...innermost field side curved portion (field side curved portion) 57AA...inner edge 57AB...outer edge 57AC, 57AD...ends 57B to 57D...field side curved portion 57BA to 57DA...inner edge 57BB to 57DB...outer edge 57E to 57H...straight portion 57P...corner portion 57Q...straight portion 58...channel stop region 59A, 59B...lower voltage breakdown region 60...insulating film 62...main surface insulating film 64...interlayer insulating film 66...gate wiring 68...gate pad wiring 70...gate line wiring 72...gate connecting wiring 74...Emitter opening 76...Emitter connecting electrode 78...Gate opening 80...Gate connecting electrode 82...Well opening 82A...First well opening 82AA...Segment opening 82B...Second well opening 84...Well connecting electrode 84A...Inner well connecting electrode 84B...Outer well connecting electrode 86...Gate electrode 88...Gate pad electrode 90...Gate line electrode 90A...Open end 92...Emitter electrode 94...Emitter pad electrode 94A...Emitter lead-out portion 96...Emitter line electrode 97A...Emitter side curved portion 97B...Inner edge 97C...Outer edge 97D,97E...end 97P...corner portion 97Q...straight portion 98...field opening 100...field connection electrode 102...field electrode 102A...innermost field electrode (field electrode) 102B to 102D...field electrodes 102E...field lead-out portion 103A...innermost field electrode side curved portion (field electrode side curved portion) 103B to 103D...field electrode side curved portion 103AA...inner edge 103AB...outer edge 103AC, 103AD...end 103P...corner portion 103Q...straight portion 104...channel stop opening 106...channel stop electrode 108...collector electrode 110...cathode region 110A...first cathode region 110B...second cathode region 111A...cathode side curved portion 111B...inner edge 111C...outer edge 111D, 111E...end portion 111P...corner portion 111Q...straight portion 112...diode 122...prohibited range 124...first allowed range 126...second allowed range 142...first diffusion region 144...second diffusion region 146...extension region W1...cathode region width WF...field region width PW1...first well reference position PW2...second well reference position PW3...intermediate reference position PG...gate reference position PK...position of maximum electric field strength RA...innermost field region range RB to RD...field region range RW...outer edge range of well region v1...first maximum value v2...minimum value v3...second maximum value v4...first inflection point v5...second inflection point Da...first reference distance Db...second reference distance Dc...Third reference distance CP1...First curvature center CP2...Second curvature center CP3...Third curvature center CP4...Fourth curvature center CP5...Fifth curvature center θ1...First central angle θ2...Second central angle θ3...Third central angle θ4...Fourth central angle θ5...Fifth central angle AT1...First angle AT2...Second angle AT3...Third angle AT4...Fourth angle LA...Straight line L1, L2...Straight line LT1...First tangent line LT2...Second tangent line LT3...Third tangent line LT4...Fourth tangent line BLA~BLD...Diffusion area boundary line,

Claims

1. A chip having a first main surface and a second main surface opposite the first main surface; an outer periphery region provided on the periphery of the first main surface; an IGBT region provided inside the outer periphery region on the first main surface; a well region of a first conductivity type provided in a surface layer of the first main surface in the outer periphery region so as to define the IGBT region; a plurality of field regions of the first conductivity type provided in the surface layer of the first main surface in the outer periphery region at intervals from the well region towards the periphery of the chip and arranged spaced apart from each other; a cathode region of a second conductivity type provided in a surface layer of the second main surface in the outer periphery region and forming a diode together with the well region; an insulating film covering at least the well region; an emitter electrode arranged on the insulating film so as to be electrically connected to the well region; and a collector electrode provided on the second main surface so as to be electrically connected to the cathode region. a gate line electrode arranged on the insulating film at a distance from the outer edge of the well region toward the IGBT region so as to face the well region in the thickness direction of the chip; and an outer well connection electrode embedded in the insulating film so as to be connected to a region in the well region closer to the outer edge of the well region than the gate line electrode, wherein when viewed from the thickness direction of the chip, the well region is annular and surrounds the IGBT region, and has a plurality of corner portions; when viewed from the thickness direction of the chip, each of the plurality of field regions is annular and surrounds the well region, and has a plurality of corner portions; each of the plurality of corner portions of the well region includes a well-side curved portion; and each of the plurality of corner portions in each of the plurality of field regions includes a field-side curved portion; and the curvature of the outer edge of the well-side curved portion is different from the curvature of the inner edge of an innermost field-side curved portion that is the innermost field-side curved portion of the plurality of field-side curved portions, the cathode region is disposed so as to face, in a thickness direction of the chip, at least a region in the corner portion of the well region that is spaced closer to the outer well connecting electrode than the gate line electrode.

2. The semiconductor device according to claim 1, wherein the cathode region includes a portion facing the outer well connecting electrode in the thickness direction of the chip.

3. A semiconductor device as described in claim 1 or 2, wherein the curvature of the outer edge of the well-side curved portion is smaller than the curvature of the inner edge of the innermost field-side curved portion, and a first angle formed by a tangent to an end of the outer edge of the well region in the direction in which the well-side curved portion extends and a straight portion extending from said end is larger than a second angle formed by a tangent to an end of the outer edge of the innermost field-side curved portion in the direction in which the innermost field-side curved portion extends and a straight portion extending from said end.

4. The semiconductor device according to claim 3, wherein a first central angle of the outer edge of said well-side curved portion is smaller than a second central angle of said innermost field-side curved portion.

5. The semiconductor device according to claim 3 or 4, wherein the distance between the innermost field-side curved portion and the well-side curved portion is smaller than the distance between adjacent field regions among the plurality of field regions.

6. A semiconductor device according to any one of claims 3 to 5, wherein each of the two end portions in the direction in which the well-side curved portion extends is positioned closer to the center of the well-side curved portion in the direction in which the well-side curved portion extends than each of the two end portions in the direction in which the innermost field-side curved portion extends.

7. A semiconductor device according to claim 1 or 2, wherein the curvature of the outer edge of the well-side curved portion is greater than the curvature of the inner edge of the innermost field-side curved portion, and each of the two end portions in the direction in which the well-side curved portion extends is positioned closer to the center of the well-side curved portion in the direction in which the well-side curved portion extends than the two end portions in the direction in which the innermost field-side curved portion extends.

8. The semiconductor device according to any one of claims 1 to 7, wherein the center of curvature of the well-side curved portion is different from the center of curvature of the innermost field-side curved portion.

9. The semiconductor device according to any one of claims 1 to 8, wherein the cathode region is arranged closer to the IGBT region than an innermost field region, which is the innermost of the plurality of field regions.

10. The semiconductor device according to claim 9, wherein the cathode region is disposed so as to face the outer edge of the well region in the thickness direction of the chip.

11. The semiconductor device according to claim 10, wherein, when viewed in the thickness direction of the chip, the cathode region is annular with a plurality of corner portions, each of the plurality of corner portions of the cathode region includes a cathode-side curved portion, and the curvature of the outer edge of the cathode-side curved portion is equal to the curvature of the outer edge of the well-side curved portion.

12. The semiconductor device according to any one of claims 1 to 11, wherein the concentration of the first conductivity type impurity in the field region is constant in the width direction of the field region.

13. A semiconductor device according to any one of claims 1 to 11, wherein each of a plurality of corner portions in at least one of the plurality of field regions includes: a first diffusion region having a first concentration of a first conductivity type impurity; and a second diffusion region disposed on the opposite side of the first diffusion region from the well region, the second diffusion region having the first conductivity type impurity concentration at a second concentration lower than the first concentration; and wherein the first conductivity type impurity concentration of the well region is higher than the second concentration.

14. A chip having a first main surface and a second main surface opposite the first main surface; an outer periphery region provided on the peripheral edge of the first main surface; an IGBT region provided on the first main surface inside the outer periphery region; a well region of a first conductivity type provided on a surface layer of the first main surface in the outer periphery region so as to partition the IGBT region; a plurality of field regions of a first conductivity type provided on the surface layer of the first main surface in the outer periphery region at intervals from the well region toward the peripheral edge of the chip and arranged spaced apart from each other; a cathode region of a second conductivity type provided on a surface layer of the second main surface in the outer periphery region and forming a diode together with the well region; an insulating film covering at least the well region; an emitter electrode arranged on the insulating film so as to be electrically connected to the well region; a collector electrode provided on the second main surface so as to be electrically connected to the cathode region; and a gate line electrode arranged on the insulating film at a distance from the outer edge of the well region toward the IGBT region so as to face the well region. an outer well connecting electrode buried in the insulating film so as to be connected to a region in the well region closer to the outer edge of the well region than the gate line electrode; wherein, when viewed in the thickness direction of the chip, the well region is provided in an annular shape surrounding the IGBT region and has a plurality of corner portions; when viewed in the thickness direction of the chip, the plurality of field regions are annular and provided to surround the well region; each of the plurality of field regions has a plurality of corner portions; and each of the plurality of corner portions in each of the plurality of field regions includes a field-side curved portion; the field-side curved portion of at least one of the plurality of field regions includes: a first diffusion region having a first concentration of first-conductivity-type impurities; and a second diffusion region having a second concentration of first-conductivity-type impurities lower than the first concentration; the second diffusion region is arranged closer to the periphery of the chip than the first diffusion region; and the first-conductivity-type impurity concentration of the well region is higher than the second concentration;the cathode region is disposed so as to face, in a thickness direction of the chip, at least a region in the corner portion of the well region that is spaced closer to the outer well connecting electrode than the gate line electrode.

15. The semiconductor device according to claim 14, wherein each of the plurality of field regions includes the first diffusion region and the second diffusion region.

16. The semiconductor device according to claim 14 or 15, further comprising a second conductivity type drift region provided inside the chip, wherein the concentration of the first conductivity type impurity in the second diffusion region is higher than the concentration of the second conductivity type impurity in the drift region.

17. The semiconductor device according to any one of claims 14 to 16, wherein the first conductivity type impurity concentration in the well region is equal to the first concentration.

18. A semiconductor device according to any one of claims 14 to 17, wherein the second diffusion region is provided in a plurality of corner portions of at least one of the plurality of field regions, and is not provided in any portion other than the plurality of corner portions.

19. The semiconductor device according to any one of claims 14 to 17, wherein the second diffusion region includes a protruding region that protrudes from the field-side curved portion in the direction in which the field-side curved portion extends.

20. A semiconductor device according to any one of claims 14 to 19, wherein each of a plurality of corner portions of the well region includes a well-side curved portion, and the well-side curved portion and the field-side curved portion have the same center of curvature.

Images