Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device is provided with a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, and an electric field relaxation region provided under the body region, being in contact with the body region, and having the second conductivity type. A gate trench provided with a side surface penetrating the source region and the body region and reaching the drift region, and a bottom surface continuous with the side surface is provided on the first main surface, and the gate trench extends along a first axis parallel to the first main surface. When viewed in cross section perpendicular to the first axis, the silicon carbide substrate has the electric field relaxation regions respectively on both sides of the gate trench, and a first distance between the first main surface and a first virtual plane having the smallest distance between the electric field relaxation regions sandwiching the gate trench therebetween among virtual planes parallel to the first main surface is smaller than a second distance between the first virtual plane and a second virtual plane including a lower end surface of the electric field relaxation region among the virtual planes.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2024-018543 filed on February 9, 2024, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] As one of silicon carbide semiconductor devices, a trench MOSFET (metal oxide semiconductor field effect transistor) having an electric field relaxation layer has been disclosed.

[0004] Japanese Patent Application Publication No. 2021-72359

[0005] A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type provided on the body region so as to be spaced from the drift region; and an electric field relaxation region having the second conductivity type provided below the body region and in contact with the body region; A gate trench is provided having a side surface that reaches a lift region and a bottom surface that is continuous with the side surface, the gate trench extending along a first axis parallel to the first main surface, and in a cross-sectional view perpendicular to the first axis, the silicon carbide substrate has the electric field relaxation regions on both sides of the gate trench, and a first distance between the first main surface and a first imaginary plane parallel to the first main surface at which the distance between the electric field relaxation regions sandwiching the gate trench is smallest is smaller than a second distance between the first imaginary plane and a second imaginary plane that includes a lower end surface of the electric field relaxation region and the first imaginary plane.

[0006] Fig. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Fig. 3 is a schematic view showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to a second embodiment. Fig. 4 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment.

[0007] [Problem to be Solved by the Present Disclosure] In conventional silicon carbide semiconductor devices, it is difficult to ensure a high breakdown voltage while reducing the on-resistance at the same time.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can ensure a high breakdown voltage while reducing on-resistance.

[0009] [Effects of the Present Disclosure] According to the present disclosure, it is possible to ensure a breakdown voltage and reduce an on-resistance at the same time.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are denoted by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually expressed by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of a silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region provided on the body region so as to be spaced from the drift region and having the first conductivity type; and an electric field relaxation region provided below the body region and in contact with the body region and having the second conductivity type, the silicon carbide substrate including: a first main surface; A gate trench is provided having a side surface that reaches the drift region and a bottom surface that is continuous with the side surface, the gate trench extends along a first axis parallel to the first main surface, and in a cross-sectional view perpendicular to the first axis, the silicon carbide substrate has the electric field relaxation region on both sides of the gate trench, and a first distance between the first main surface and a first imaginary plane that is parallel to the first main surface and that makes the distance between the electric field relaxation regions sandwiching the gate trench the smallest is smaller than a second distance between the first imaginary plane and a second imaginary plane that includes a lower end surface of the electric field relaxation region and the first imaginary plane.

[0013] The first distance between the first imaginary plane and the first major surface is smaller than the distance between the second imaginary plane and the first imaginary plane, and the first imaginary plane is the imaginary plane parallel to the first major surface in which the distance between the electric field buffer regions is the smallest. Therefore, electric field concentration near the end of the electric field buffer region close to the second major surface is alleviated, resulting in a high breakdown voltage. Therefore, the effective concentration of the first conductivity type impurity in the portion of the drift region sandwiched between the electric field buffer regions along the second axis may be relatively high, thereby reducing the on-resistance. In this way, it is possible to ensure both a high breakdown voltage and a reduced on-resistance.

[0014] [2] In [1], the concentration of the second conductivity type impurity in the electric field relaxation region may decrease as the region becomes farther from the first imaginary plane. In this case, electric field concentration on a gate electrode provided in a gate trench can be easily suppressed.

[0015] [3] In the configuration of [1] or [2], a third distance between the first main surface and a third imaginary plane, which is a plane on the imaginary plane where the concentration of the first conductivity type impurity in the drift region is greatest, may be smaller than the first distance. In this case, an on-current is likely to flow over a wide range of the drift region, and on-resistance is likely to be reduced.

[0016] [4] In any one of [1] to [3], the second distance may be at least twice the first distance. In this case, electric field concentration is alleviated particularly near the end of the electric field relaxation region close to the second main surface, making it easier to obtain a high breakdown voltage.

[0017] [5] In any one of [1] to [4], the silicon carbide substrate may have an active region provided with the gate trench and a termination region surrounding the active region in a plan view perpendicular to the first main surface, and the electric field relief region may be provided in both the active region and the termination region. In this case, avalanche resistance can be improved.

[0018] [6] In the device of [5], the active region may include a plurality of gate trenches arranged along a second axis parallel to the first main surface and perpendicular to the first axis, the termination region may include a first termination region contacting the active region in a direction parallel to the first axis and a second termination region contacting the active region in a direction parallel to the second axis, and the field relief region may be arranged in both the first termination region and the second termination region. In this case, a higher avalanche capability may be easily obtained.

[0019] [7] In [6], the termination region may have a third termination region in contact with the first termination region and the second termination region, and the electric field relief region may also be provided in the third termination region. In this case, an even higher avalanche resistance is more likely to be obtained.

[0020] [8] In any one of [1] to [7], the conductivity type of the semiconductor between the bottom surface and the second main surface may be the first conductivity type. In this case, the on-resistance is more likely to be reduced.

[0021] [9] In any one of [1] to [8], the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0022] [Embodiments of the Present Disclosure] (First Embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOS field effect transistor (FET) using silicon carbide, and this MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0023] As shown in Figures 1 and 2, the silicon carbide semiconductor device 100 according to the first embodiment mainly has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0024] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0025] The first main surface 1 is a {0001} plane or a {0001} plane tilted at an off angle of 8 degrees or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a (000-1) plane tilted at an off angle of 8 degrees or less in the off direction. The first main surface 1 may be a (0001) plane or a (0001) plane tilted at an off angle of 8 degrees or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 degree or more, or 2 degrees or more. The off angle may be 6 degrees or less, or 4 degrees or less.

[0026] The silicon carbide epitaxial layer 40 mainly includes a drift region 11 , a body region 12 , a source region 13 , an electric field reduction region 14 , and a contact region 18 .

[0027] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. Drift region 11 mainly has a first region 11A and a second region 11B.

[0028] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0029] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0030] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first major surface 1. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and a portion of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first major surface 1 and the second major surface 2. In a cross-sectional view perpendicular to the Y axis, an angle θ1 of the side surfaces 3 with respect to an imaginary plane 34 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The Y axis is an example of the first axis, and the X axis is an example of the second axis.

[0031] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.

[0032] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0033] The electric field relaxation region 14 contains p-type impurities such as aluminum and has p-type conductivity. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 14 is located between adjacent gate trenches 5 along the X-axis. The electric field relaxation region 14 is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The electric field relaxation region 14 is spaced apart from the gate trench 5 along the X-axis than the body region 12 is. The electric field relaxation region 14 is located below the body region 12 and in contact with the body region 12. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 14 overlaps the contact region 18. The contact region 18 may penetrate the body region 12, and the electric field relaxation region 14 may be in contact with the body region 12 and the contact region 18. The electric field relaxation region 14 may extend along the Y-axis. A plurality of electric field relaxation regions 14 are arranged at regular intervals along the X-axis. A plurality of electric field relaxation regions 14 may be provided in a striped pattern. The lower end surface of electric field relaxation region 14 is closer to second main surface 2 than bottom surface 4. That is, second distance L2 between electric field relaxation region 14 and second main surface 2 is smaller than third distance L3 between bottom surface 4 and second main surface 2. The lower end surface of electric field relaxation region 14 is the surface facing silicon carbide single crystal substrate 50. Contact region 18, body region 12, and electric field relaxation region 14 are electrically connected to one another.

[0034] The first region 11A of the drift region 11 is exposed to the side surface 3 and is in contact with the body region 12 and the electric field relaxation region 14. The thickness of the first region 11A is, for example, 0.1 μm or more and 0.6 μm or less. The second region 11B of the drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The first region 11A is located between the second region 11B and the body region 12. The lower end surface of the first region 11A is in contact with the upper end surface of the second region 11B. The second region 11B may be exposed to the side surface 3. The second region 11B may be exposed to the bottom surface 4. The lower end surface of the first region 11A may be on an imaginary plane 34 including the bottom surface 4, or may be closer to the first main surface 1 than the imaginary plane 34.

[0035] The second effective concentration of the n-type impurity in the second region 11B is lower than the first effective concentration of the n-type impurity in the first region 11A. For example, the second effective concentration is 1×10 １６ cm －３ 1x10 or more１７ cm －３ and the first effective concentration is 1×10 １７ cm －３ 1x10 or more １８ cm －３ The first region 11A is sometimes called a current diffusion region. Among imaginary planes parallel to the first main surface 1, an imaginary plane 33 where the concentration of n-type impurities in the drift region 11 is maximum is located in the first region 11A.

[0036] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type.

[0037] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the second region 11B at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 contacts the first region 11A and the second region 11B at the side surface 3. As long as the gate insulating film 81 contacts the first region 11A at the side surface 3, it does not have to contact the second region 11B. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0038] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0039] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0040] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged so that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0041] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0042] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0043] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0044] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a part of source electrode 60 may be provided.

[0045] The effective concentration of the p-type impurity in the contact region 18 may be higher than the effective concentration of the p-type impurity in the body region 12. For example, the effective concentration of the p-type impurity in the contact region 18 may be, for example, 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The effective concentration of p-type impurities in the body region 12 is 5×10 １７ cm －３ 1x10 or more １８ cm－３ The following is the result.

[0046] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 １９ cm －３ The effective concentration of the p-type impurity in the electric field relaxation region 14 is, for example, 2×10 １７ cm －３ 2 x 10 or more １８ cm －３ The following is the result.

[0047] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0048] Drift region 11 has n-type conductivity, and body region 12 and electric field relaxation region 14 have p-type conductivity. Therefore, the boundary between drift region 11 and body region 12 and the boundary between drift region 11 and electric field relaxation region 14 are clear.

[0049] The dimension (hereinafter sometimes referred to as "width") of the electric field relaxation region 14 in the direction along the X axis (short direction) includes a first width W1 at the upper end surface 21, a second width W2 at the lower end surface 22, and a third width W3 on an imaginary plane 31 between the upper end surface 21 and the lower end surface 22. The third width W3 is larger than the first width W1 and the second width W2. The width of the electric field relaxation region 14 monotonically increases from the upper end surface 21 to the imaginary plane 31 and monotonically decreases from the imaginary plane 31 to the lower end surface 22. In other words, the width of the electric field relaxation region 14 is greatest on the imaginary plane 31. Furthermore, the imaginary plane 31 is the imaginary plane parallel to the first main surface 1 where the distance between adjacent electric field relaxation regions 14 along the X axis is smallest. The first width W1 and the second width W2 may be larger than each other or may be equal to each other.

[0050] Furthermore, a first distance L1 between imaginary plane 31 and first main surface 1 is smaller than a second distance L2 between imaginary plane 31 and imaginary plane 32, which is an imaginary plane parallel to first main surface 1 and includes lower end surface 22 of electric field relaxation region 14. Furthermore, imaginary plane 31 is closer to second main surface 2 than the interface between first region 11A and second region 11B of drift region 11. Therefore, a third distance L3 between imaginary plane 33 and first main surface 1 is smaller than the first distance L1. Imaginary plane 31 is an example of a first imaginary plane, imaginary plane 32 is an example of a second imaginary plane, and imaginary plane 33 is an example of a third imaginary plane.

[0051] Such electric field buffer region 14 can be formed, for example, by performing channeling implantation of p-type impurities into n-type drift region 11, and then randomly implanting p-type impurities shallower than the channeling implantation. When electric field buffer region 14 is formed in this manner, the concentration of p-type impurities is greatest on imaginary plane 31 within electric field buffer region 14. For example, the concentration of p-type impurities in electric field buffer region 14 decreases the further away from imaginary plane 31.

[0052] In silicon carbide semiconductor device 100, as described above, first distance L1 between imaginary plane 31 and first main surface 1 is smaller than second distance L2 between imaginary plane 32 and imaginary plane 31. Furthermore, the effective concentration of p-type impurities in electric field relaxation region 14 is set to 2×10 １７ cm －３ 2 x 10 or more １８ cm －３ Hereinafter, the second effective concentration of n-type impurities in the second region 11B of the drift region 11 is defined as 1×10 １６ cm －３ 1x10 or more １７ cm －３By setting the second distance L2 to be equal to or less than the first distance L1, depletion near the lower end of the electric field relaxation region 14 can be promoted during off-state operation. This reduces electric field concentration near the lower end surface of the electric field relaxation region 14, resulting in a high breakdown voltage. Therefore, the effective concentration of n-type impurities in the portion of the drift region 11 sandwiched between the electric field relaxation regions 14 along the X-axis may be relatively high, thereby reducing the on-resistance. Thus, the silicon carbide semiconductor device 100 can ensure both a high breakdown voltage and a reduced on-resistance. In particular, when the second distance L2 is at least twice the first distance L1, the electric field concentration near the lower end surface of the electric field relaxation region 14 is further reduced, making it easier to obtain a higher breakdown voltage. The second distance L2 may be at least 2.5 times the first distance L1, or may be at least 3 times the first distance L1.

[0053] Furthermore, since the electric field in electric field relaxation region 14 is dispersed along the Z axis in a region closer to second main surface 2 than imaginary plane 31, breakdown is unlikely even if a large current flows during short-circuit operation. In this way, silicon carbide semiconductor device 100 can improve the short-circuit resistance.

[0054] When the concentration of p-type impurities in the electric field buffer region 14 decreases as the region moves away from the imaginary plane 31, the electric field concentration in the gate insulating film 81 can be suppressed.

[0055] When the third distance L3 between the imaginary plane 33 and the first main surface 1 is smaller than the first distance L1, the on-current tends to flow over a wide range of the drift region 11, and the on-resistance tends to be further reduced.

[0056] When the conductivity type of the semiconductor (silicon carbide substrate 10) between bottom surface 4 and second main surface 2 along the Z axis is n-type, the on-resistance is more likely to be reduced.

[0057] Second Embodiment A second embodiment will be described. The second embodiment has electric field relaxation regions 14 in the active region and the termination region. FIG. 3 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 3. Barrier metal film 84 is omitted in FIG. 4.

[0058] As shown in FIG. 3 , in a silicon carbide semiconductor device 200 according to the second embodiment, a silicon carbide substrate 10 has an active region 210 and a termination region 220. The active region 210 has a configuration similar to that of the silicon carbide substrate 10 according to the first embodiment, and a plurality of gate trenches 5 are formed in the active region 210. The gate trenches 5 extend along the Y axis, and a plurality of gate trenches 5 are provided at regular intervals along the X axis. The active region 210 has, for example, a square shape with rounded corners in a plan view. The active region 210 may also have a rectangular shape with rounded corners in a plan view. The termination region 220 surrounds the active region 210 in a plan view. The termination region 220 is provided around the active region 210 in a plan view. Termination region 220 has first termination region 221 that contacts active region 210 in a direction parallel to the Y axis, second termination region 222 that contacts active region 210 in a direction parallel to the X axis, and third termination region 223 that contacts first termination region 221 and second termination region 222. First termination region 221 is provided on the +Y side and −Y side of active region 210, second termination region 222 is provided on the +X side and −X side of active region 210, and third termination region 223 is provided at four corners of silicon carbide substrate 10.

[0059] As shown in FIG. 4 , contact region 16 is provided in a surface layer portion of active region 210. Contact region 16 is formed simultaneously with contact region 18, is made of the same material as contact region 18, and has the same depth as contact region 18. Contact region 16 also constitutes first main surface 1. In plan view, contact region 16 is provided in an annular shape, and multiple gate trenches 5 and gate electrodes 82 are located inside contact region 16. The outer edge of contact region 16 is the boundary between active region 210 and termination region 220. In this disclosure, an annular shape includes a single closed curve shape other than a circular annular shape or an elliptical annular shape, such as a rounded rectangular shape.

[0060] A gate insulating film 81 is also provided on the contact region 16, and an electrode film 85 is formed thereon. The electrode film 85 is formed simultaneously with the gate electrode 82 and is made of the same material as the gate electrode 82.

[0061] An interlayer insulating film 83 is provided on the gate insulating film 81 and the electrode film 85 above the contact region 16. A contact hole 91 is formed in the interlayer insulating film 83, reaching the electrode film 85, and a contact hole 92 is formed in the interlayer insulating film 83 and the gate insulating film 81, reaching the contact region 16. The silicon carbide semiconductor device 200 has a gate runner 63 and a source runner 64. The gate runner 63 and the source runner 64 are formed simultaneously with the source electrode 60 and are made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82 and the electrode film 85. The source runner 64 is electrically connected to the source electrode 60 and the contact region 16. In a plan view, the source runner 64 is provided in an annular shape, and the outer edge of the source runner 64 may coincide with the outer edge of the contact region 16. The gate runner 63 is provided between the source electrode 60 and the source runner 64.

[0062] A junction termination extension (JTE) 17 may be provided in a surface layer portion of termination region 220. JTE 17 is provided in an annular shape so as to be in contact with contact region 16. JTE 17 also constitutes first main surface 1. JTE 17 contains a p-type impurity at an effective concentration lower than that of contact region 16. JTE 17 is provided inside the outer edge of silicon carbide substrate 10, and first main surface 1 at the outer edge of silicon carbide substrate 10 is constituted by drift region 11.

[0063] Silicon carbide semiconductor device 200 further has silicon nitride film 87 and polyimide film 88. Silicon nitride film 87 covers the upper surface and side surfaces of interlayer insulating film 83, and polyimide film 88 covers the upper surface and side surfaces of silicon nitride film 87. An opening exposing a portion of source electrode 60 is formed in silicon nitride film 87 and polyimide film 88, and source plating film 86 is formed inside this opening. Silicon nitride film 87 and polyimide film 88 also have an opening (not shown) exposing a portion of a gate electrode (not shown) connected to gate runner 63, and gate plating film (not shown) is formed inside this opening.

[0064] In this embodiment, the electric field relaxation regions 14 are provided not only on both sides of the gate trench 5 in plan view, but also below the contact region 16. In addition, the electric field relaxation regions 14 are also provided in the termination region 220. The electric field relaxation regions 14 below the contact region 16 may be in contact with the contact region 16. The electric field relaxation regions 14 in the termination region 220 may or may not be in contact with the JTE 17. Multiple electric field relaxation regions 14 may be provided in the termination region 220, with some electric field relaxation regions 14 in contact with the JTE 17 and other electric field relaxation regions 14 separated from the JTE 17.

[0065] In termination region 220, electric field relaxation region 14 is provided, for example, in first termination region 221, second termination region 222, and third termination region 223. Electric field relaxation region 14 may be provided only in first termination region 221 and second termination region 222, or electric field relaxation region 14 may be provided only in first termination region 221 or second termination region 222.

[0066] Other configurations of silicon carbide semiconductor device 200 are the same as those of silicon carbide semiconductor device 100 .

[0067] The second embodiment also achieves the same effects as the first embodiment. Furthermore, in the second embodiment, the electric field buffer region 14 is also provided in the termination region 220, thereby improving the avalanche resistance. In particular, when the electric field buffer region 14 is provided in both the first termination region 221 and the second termination region 222, a better avalanche resistance is obtained, and when the electric field buffer region 14 is also provided in the third termination region 223, an even better avalanche resistance is obtained.

[0068] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0069] REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 11A First region 11B Second region 12 Body region 13 Source region 14 Electric field relaxation region 16 Contact region 17 Junction termination structure 18 Contact region 21 Upper end surface 22 Lower end surface 31 Virtual plane (first virtual plane) 32 Virtual plane (second virtual plane) 33 Virtual plane (third virtual plane) 34 Virtual plane 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate runner 64 Source runner 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Electrode film 86 Plating film 87 Silicon nitride film 88 Polyimide film 90, 91, 92 Contact holes 100, 200 Silicon carbide semiconductor device 210 Active region 220 Termination region 221 First termination region 222 Second termination region 223 Third termination region L1 First distance L2 Second distance L3 Third distance P1 First pitch W1 First width W2 Second width W3 Third width X X axis (second axis) Y Y axis (first axis) Z Z axis θ1 Angle

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate has: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type provided on the body region so as to be spaced from the drift region; and an electric field relaxation region having the second conductivity type provided below the body region and in contact with the body region, wherein a gate trench is provided in the first main surface, the gate trench having a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, the gate trench extending along a first axis parallel to the first main surface, and in a cross section perpendicular to the first axis, the silicon carbide substrate has the electric field relaxation region on both sides of the gate trench, a first distance between the first main surface and a first imaginary plane parallel to the first main surface, the first imaginary plane being the smallest distance between the electric field relaxation regions sandwiching the gate trench therebetween, the first distance being smaller than a second distance between the first imaginary plane and a second imaginary plane including a lower end surface of the electric field relaxation region.

2. The silicon carbide semiconductor device according to claim 1, wherein the concentration of the impurity of the second conductivity type in the electric field buffer region decreases with increasing distance from the first imaginary plane.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein a third distance between a third imaginary plane on which the concentration of the impurity of the first conductivity type in the drift region is greatest and the first main surface is smaller than the first distance.

4. The silicon carbide semiconductor device according to claim 1, wherein the second distance is at least twice the first distance.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the silicon carbide substrate has: an active region in which the gate trench is provided; and a termination region surrounding the active region in a plan view from a direction perpendicular to the first main surface; and the electric field relaxation region is provided in both the active region and the termination region.

6. The silicon carbide semiconductor device according to claim 5, wherein a plurality of the gate trenches are provided within the active region along a second axis parallel to the first main surface and perpendicular to the first axis, the termination region having: a first termination region contacting the active region in a direction parallel to the first axis; and a second termination region contacting the active region in a direction parallel to the second axis, and the electric field relaxation region is provided in both the first termination region and the second termination region.

7. The silicon carbide semiconductor device according to claim 6, wherein said termination region has a third termination region in contact with said first termination region and said second termination region, and said electric field reduction region is also provided in said third termination region.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the conductivity type of the semiconductor between said bottom surface and said second main surface is said first conductivity type.

9. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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