Semiconductor device

Abstract

Provided is a semiconductor device comprising: a fist conductivity-type drift region provided on a semiconductor substrate; a second conductivity-type base region; a first conductivity-type emitter region having a doping concentration higher than that of the drift region; a second conductivity-type contact region; a trench contact part; and a plurality of trench parts extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, wherein the plurality of trench parts have a gate trench part and a dummy trench part, and a mesa part between the plurality of trench parts has a contact formation region where the contact region is provided below the emitter region on a side wall of at least one trench part among the plurality of trench parts, and a contact non-formation region where the contact region is not provided below the emitter region on a side wall of the gate trench part.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, semiconductor devices including an N-type emitter region and a P-type contact region have been known (see, for example, Patent Documents 1 and 2). General disclosure

[0003] A first aspect of the present invention provides a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a contact region of the second conductivity type provided above the drift region and having a doping concentration higher than that of the base region; a trench contact portion extending from the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate; and a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate. The plurality of trench portions may include gate trench portions and dummy trench portions. A mesa portion between the plurality of trench portions may include a contact formation region on a sidewall of at least one of the plurality of trench portions, where the contact region is provided below the emitter region, and a contact non-formation region on a sidewall of the gate trench portion, where the contact region is not provided below the emitter region.

[0004] In the semiconductor device described above, the contact formation region may be provided on a side wall of the gate trench portion.

[0005] In any of the above semiconductor devices, the contact formation region may be provided on a side wall of the dummy trench portion.

[0006] In any one of the semiconductor devices described above, a plurality of the contact formation regions may be provided in the mesa portion along the trench extension direction, and the emitter region may be provided continuously across the plurality of contact formation regions.

[0007] In any of the above semiconductor devices, the contact formation regions and the contact non-formation regions may be provided alternately in the trench extension direction.

[0008] In the above semiconductor device, the lower end of the emitter region in the contact formation region may be shallower than the lower end of the emitter region in the non-contact formation region.

[0009] In any of the above semiconductor devices, in the contact formation region, an upper end of the contact region may be in contact with a lower end of the emitter region.

[0010] In any of the above semiconductor devices, in the contact formation region, the entire upper end of the contact region may be in contact with the lower end of the emitter region.

[0011] In any of the above semiconductor devices, in the contact formation region, the length in the depth direction of the contact region that is in contact with the gate trench portion may be greater than the length in the depth direction of the emitter region that is in contact with the gate trench portion.

[0012] In any of the above semiconductor devices, a ratio of the width of the contactless region in the trench extension direction to the width of the contact region in the trench extension direction may be 0.2 or more and 20 or less.

[0013] In any of the above semiconductor devices, the width of the contact formation region in the trench extension direction may be 0.4 μm or more and 8.0 μm or less.

[0014] In any of the above semiconductor devices, the width of the non-contact region in the trench extension direction may be 0.4 μm or more and 1.9 μm or less.

[0015] In any of the above semiconductor devices, the contact formation region may be in contact with the non-contact formation region at both ends in the trench extension direction.

[0016] Any of the above semiconductor devices may further include a plurality of well regions of a second conductivity type, each of which has a doping concentration higher than that of the base region and is provided at both ends of the mesa portion in the trench extension direction. The emitter region may extend in the mesa portion in the trench extension direction, and both ends in the trench extension direction may contact the plurality of well regions.

[0017] Any of the above semiconductor devices may include a contact exposure region on a sidewall of the dummy trench portion, the contact region being provided on the front surface of the semiconductor substrate.

[0018] In any of the above semiconductor devices, the lower end of the contact region may be shallower than the lower end of the base region.

[0019] In any of the above semiconductor devices, the contact region may extend from a sidewall of the dummy trench portion to below a bottom surface of the trench contact portion in the trench arrangement direction and terminate therein.

[0020] In any of the above semiconductor devices, the contact region may extend from a sidewall of the dummy trench portion beyond a bottom surface of the trench contact portion in the trench arrangement direction, and terminate without contacting the gate trench portion.

[0021] In any of the above semiconductor devices, the bottom surface of the trench contact portion may be deeper than the lower end of the emitter region and shallower than the lower end of the base region.

[0022] In any of the above semiconductor devices, the contact formation region in contact with the sidewall of the dummy trench portion may be longer than the width in the trench extension direction of the contact formation region in contact with the gate trench portion, and may be provided extending in the trench extension direction.

[0023] Any of the above semiconductor devices may further include a plug region of a second conductivity type that is provided below the trench contact portion and has a doping concentration higher than that of the contact region.

[0024] In any of the above semiconductor devices, the plug region may be in contact with a bottom surface of the trench contact portion.

[0025] In any of the above semiconductor devices, the plug region may be in contact with both a sidewall of the trench contact portion on the dummy trench portion side and a sidewall of the trench contact portion on the gate trench portion side.

[0026] In any of the above semiconductor devices, the contact region may extend in the trench arrangement direction from the sidewall of the dummy trench portion beyond the bottom surface of the trench contact portion, and terminate without exceeding the end of the plug region on the gate trench portion side.

[0027] Any of the above semiconductor devices may include two adjacent dummy trench portions, and the emitter region may also be provided in a mesa portion sandwiched between the two adjacent dummy trench portions.

[0028] In any of the above semiconductor devices, the mesa portion sandwiched between the two adjacent dummy trench portions may be the contact formation region.

[0029] In any of the above semiconductor devices, in the mesa portion sandwiched between the two adjacent dummy trench portions, the contact region may be provided in contact with only one of the two adjacent dummy trench portions.

[0030] The semiconductor device may include a transistor portion, a non-effective region provided on the outer periphery of the transistor portion, and an edge termination structure provided on the outer periphery of the non-effective region, and the emitter region may be provided on the front surface of the semiconductor substrate in the non-effective region.

[0031] Any of the above semiconductor devices may include a transistor portion and a diode portion.

[0032] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0033] 2B shows an example of a top view of the semiconductor device 100. It is an enlarged view of region A in FIG. 1. It is a diagram showing an example of an XZ cross section including the a-a' cross section in FIG. 2A. It is a diagram showing an example of an XZ cross section including the bb' cross section in FIG. 2A. It is an example of a YZ cross section including the c-c' cross section in FIG. 2A. It is an enlarged view showing an example of an XZ cross section of area Q of the transistor section 70 of the semiconductor device 100 in FIG. 2B. It is an example of a YZ cross section including the gg' cross section in FIG. 2A. It is a top view of a modified example of the semiconductor device 100. It is a diagram showing an example of an XZ cross section including the dd' cross section in FIG. 3A. It is a diagram showing an example of an XZ cross section including the ee' cross section in FIG. 3A. It is an example of a YZ cross section including the ff' cross section in FIG. 3A. It is an enlarged top view of a modified example of the semiconductor device 100. It is an example of an XZ cross section of the semiconductor device 100 shown in FIG. 4A. It is an enlarged view showing an example of an XZ cross section of the semiconductor device 100. It is an enlarged view showing a modified example of the XZ cross section of the semiconductor device 100. It is an enlarged top view of a modified example of the semiconductor device 100. 10A shows an example of an XZ cross section of the semiconductor device 100 shown in FIG. 5A. An enlarged view showing an example of an XZ cross section of the semiconductor device 100. An enlarged top view of a modified example of the semiconductor device 100. An enlarged view showing an example of an XZ cross section of the semiconductor device 100. An example of an xx' cross section in FIG. 1 is shown. An example of a manufacturing method of the semiconductor device 100 is shown. A top view of a semiconductor device 500 of a comparative example is shown. A diagram showing an example of a YZ cross section including the ii' cross section in FIG. 10A. A diagram for explaining a method of designing the semiconductor device 500 of the comparative example. A diagram for explaining an example of a method of designing the semiconductor device 100.

[0034] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0035] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0036] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0037] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0038] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0039] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0040] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N ＡIn this specification, the net doping concentration may be simply referred to as the doping concentration.

[0041] In this specification, the terms P+ type and N+ type refer to a doping concentration higher than that of P type or N type, and the terms P- type and N- type refer to a doping concentration lower than that of P type or N type. In addition, in this specification, the terms P++ type and N++ type refer to a doping concentration higher than that of P+ type or N+ type.

[0042] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be referred to as the net doping concentration. Carriers refer to electron or hole charge carriers. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be referred to as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be referred to as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0043] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0044] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. A decrease in carrier mobility occurs when carriers are scattered due to a disorder in the crystalline structure caused by lattice defects or the like. The reason for the decrease in carrier concentration is as follows. In the SR method, spreading resistance is measured and the carrier concentration is calculated from the measured spreading resistance. At this time, the carrier mobility is calculated using the carrier mobility in the crystalline state. On the other hand, at locations where lattice defects are introduced, the carrier mobility is decreased, but the carrier concentration is calculated using the carrier mobility in the crystalline state. Therefore, the value obtained is lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0045] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is adopted. In this specification, distance and length units may be expressed in cm (centimeter). In this case, various calculations may be performed by converting them to m (meter). Regarding numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 １６ , and the display of 1E-16 is 1×10 －１６ Shows.

[0046] Fig. 1 shows an example of a top view of a semiconductor device 100. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some components of the semiconductor device 100, and some components are omitted. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80.

[0047] The transistor section 70 includes a transistor such as an insulated gate bipolar transistor (IGBT). The diode section 80 includes a diode such as a free wheel diode (FWD). The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT) that has the transistor section 70 and the diode section 80 on the same chip.

[0048] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a diamond substrate, a nitride semiconductor substrate such as gallium nitride, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate. The semiconductor substrate 10 in this example is a silicon substrate. The semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0049] The semiconductor substrate 10 has end edges 102 in a top view. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two pairs of end edges 102 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to one of the end edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has an active region 160 and an edge termination structure 170.

[0050] The active region 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 during operation of the semiconductor device 100. An emitter electrode is provided above the active region 160, but is not shown in FIG.

[0051] At least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD) is provided in the active region 160. In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10.

[0052] In FIG. 1 , the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1 ). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0053] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10.

[0054] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0055] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0056] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of the gate trench portion of the active region 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 112 and the gate trench portion.

[0057] The gate wiring 130 is electrically connected to the gate conductive portion of the transistor portion 70 and applies a gate voltage to the transistor portion 70. The gate wiring 130 is provided so as to surround the outer periphery of the active region 160 in a top view. The gate wiring 130 is electrically connected to a gate pad 112 provided in the edge termination structure portion 170.

[0058] The semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active region 160.

[0059] In the present example, the semiconductor device 100 includes an edge termination structure 170 between the active region 160 and the edge 102 when viewed from above. The edge termination structure 170 in the present example is disposed between the gate wiring 130 and the edge 102. The edge termination structure 170 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 170 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active region 160.

[0060] 2A is an enlarged view of region A in Fig. 1. Region A is a region including the transistor section 70, the diode section 80, and the gate wiring 130. In this example, the gate wiring 130 includes a gate metal layer 50 and a gate runner section 51.

[0061] A boundary region 90 is provided on the front surface 21 of the semiconductor substrate 10 between the transistor section 70 and the diode section 80. The front surface 21 of the semiconductor substrate 10 refers to one of the two opposing main surfaces of the semiconductor substrate 10. The front surface 21 will be described later.

[0062] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 17, an emitter region 12, a base region 14, a contact region 15, and an anode region 19 formed inside the front surface 21 side of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0063] An interlayer insulating film is formed between emitter electrode 52 and gate metal layer 50 and front surface 21 of semiconductor substrate 10, but the interlayer insulating film is omitted in Fig. 2A. In this example, contact holes 54, 55, and 56 are formed in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0064] The emitter electrode 52 is electrically connected to the emitter region 12, the contact region 15, the base region 14, and the anode region 19 on the front surface 21 of the semiconductor substrate 10 through a contact hole 54 opened in the interlayer insulating film. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion.

[0065] The gate metal layer 50 contacts the gate runner 51 through the contact hole 55. The gate runner 51 is made of a semiconductor such as polysilicon doped with impurities. The gate runner 51 is connected to a gate conductive portion in the gate trench 40 on the front surface 21 of the semiconductor substrate 10.

[0066] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound below the region made of aluminum or the like. Each electrode may further have a plug formed by embedding tungsten or the like in a contact hole so as to contact the barrier metal and aluminum or the like.

[0067] The well region 17 is provided so as to overlap with the gate metal layer 50 and the gate runner portion 51. The well region 17 is also provided so as to extend by a predetermined width into an area where it does not overlap with the gate metal layer 50 and the gate runner portion 51. In this example, the well region 17 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate metal layer 50. The well region 17 is a region of a second conductivity type having a doping concentration higher than that of the base region 14. In this example, the base region 14 is P- type, and the well region 17 is P+ type.

[0068] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction on the front surface 21 of the semiconductor substrate 10. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0069] In the transistor section 70, one or more gate trench sections 40 are arranged at predetermined intervals along the arrangement direction of the trenches. The gate conductive section inside the gate trench section 40 is electrically connected to the gate metal layer 50, and a gate potential is applied thereto. In the transistor section 70, one or more dummy trench sections 30 may be arranged at predetermined intervals along the arrangement direction. A potential different from the gate potential is applied to the dummy conductive section inside the dummy trench section 30. The dummy conductive section in this example is electrically connected to the emitter electrode 52, and an emitter potential is applied thereto.

[0070] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along the arrangement direction. The dummy trench sections 30 are arranged at predetermined intervals along the arrangement direction in the diode section 80 and the boundary region 90. Note that the transistor section 70 may not be provided with the dummy trench sections 30 and may be composed of only the gate trench sections 40.

[0071] The gate trench portion 40 in this example may have two extension portions 41 (parts of the trench that are linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41. The extension direction in Figure 2A is the Y-axis direction.

[0072] At least a part of the connection portion 43 is preferably curved in a top view. By connecting the ends of the two extension portions 41 in the Y-axis direction with each other by the connection portion 43, electric field concentration at the ends of the extension portions 41 can be alleviated.

[0073] In the transistor section 70, the dummy trench section 30 is provided between the extension portions 41 of the gate trench section 40. One or more dummy trench sections 30 may be provided between the extension portions 41. The dummy trench section 30 may have a linear shape extending in the extension direction and, like the gate trench section 40, may have an extension portion 31 and a connection portion 33. The semiconductor device 100 may include both linear dummy trench sections 30 without the connection portion 33 and dummy trench sections 30 with the connection portion 33. The direction in which the extension portion 41 of the gate trench section 40 or the extension portion 31 of the dummy trench section 30 extends long in the extension direction is defined as the longitudinal direction of the trench section. The longitudinal direction of the gate trench section 40 or the dummy trench section 30 may coincide with the extension direction. In this example, the extension direction and the longitudinal direction are the Y-axis direction. The arrangement direction of the gate trench portions 40 or dummy trench portions 30 is defined as the short-side direction of the trench portion. The short-side direction may coincide with the arrangement direction. The short-side direction may also be perpendicular to the longitudinal direction. In this example, the longitudinal direction and the short-side direction are perpendicular. In this example, the arrangement direction and the short-side direction are the X-axis direction.

[0074] The gate conductive portion in the gate trench portion 40 is connected to the gate runner portion 51 at a connection portion 43 at the tip of the gate trench portion 40. The gate trench portion 40 may be provided so as to protrude toward the gate runner portion 51 further than the dummy trench portion 30 in the extension direction (Y-axis direction). The protruding portion of the gate trench portion 40 is connected to the gate runner portion 51.

[0075] The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 17 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 17. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0076] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between two adjacent trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portion.

[0077] The boundary region 90 is provided on the diode section 80 side of the transistor section 70. That is, the boundary region 90 is provided adjacent to the diode section 80 in the transistor section 70. The boundary region 90 may have a dummy trench section 30 and may be a region in which a collector region 22 is provided on the back surface side of the semiconductor substrate 10. Both ends of the mesa section of the boundary region 90 in the trench arrangement direction may be in contact with the dummy trench section 30. All of the trench sections in the boundary region 90 may be dummy trench sections 30. The boundary region 90 may also include a gate trench section 40. In this example, the boundary region 90 does not have a first conductivity type emitter region 12 provided in the mesa section on the front surface 21 side of the semiconductor substrate 10. The boundary region 90 may have a base region 14 and an anode region 19 on the front surface 21. The boundary region 90 may have the emitter region 12 or the contact region 15 on the front surface 21. In this example, the boundary region 90 has the anode region 19 and the contact region 15 on the front surface 21. Note that Figure 2A shows the positions of the collector region 22 and the cathode region 82 provided on the back surface side of the semiconductor substrate 10 when projected onto the front surface 21.

[0078] The mesa portion 71 is a mesa portion provided in the transistor portion 70. The mesa portion 81 is a mesa portion provided in the diode portion 80. The mesa portion 91 is a mesa portion provided in the boundary region 90. In this specification, when the term "mesa portion" is simply used, it may refer to any of the mesa portion 71, the mesa portion 81, and the mesa portion 91. The extension portion of each trench portion may be considered to be one trench portion. In other words, the region sandwiched between two extension portions may be considered to be a mesa portion.

[0079] Each mesa portion is provided with a base region 14 or an anode region 19. Of the base regions 14 or anode regions 19 exposed on the front surface 21 of the semiconductor substrate 10 in the mesa portion, the region closest to the gate metal layer 50 is referred to as the base region 14-e or anode region 19-e. While FIG. 2A shows the base region 14-e or anode region 19-e disposed at one end of each mesa portion in the extension direction, a base region 14-e or anode region 19-e is also disposed at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 in a region sandwiched between the base regions 14-e or anode regions 19-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0080] The mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 71 may be provided with a contact region 15 exposed on the front surface 21 of the semiconductor substrate 10.

[0081] The mesa portion 71 of this example has a contact formation region 61 and a contact non-formation region 62. The emitter region 12 has an emitter region 121 and an emitter region 122.

[0082] The emitter region 121 is an example of the emitter region 12 provided in the contact formation region 61. The emitter region 122 is an example of the emitter region 12 provided in the non-contact formation region 62. The emitter region 121 and the emitter region 122 may have the same doping concentration.

[0083] The contact formation region 61 has a contact region 15. The contact formation region 61 of this example has an emitter region 121 on the front surface 21. The contact formation region 61 may be a region in which the contact region 15 is provided below the emitter region 121 on the sidewall of at least one of the multiple trench portions. The contact formation region 61 may be provided on the sidewall of the gate trench portion 40 or on the sidewall of the dummy trench portion 30. Because the contact formation region 61 has the contact region 15 below the emitter region 121, it does not need to function as an inversion layer. The contact formation region 61 of this example is provided extending in the trench arrangement direction from one opposing trench portion to the other opposing trench portion.

[0084] The non-contact region 62 does not have a contact region 15. The non-contact region 62 of this example has an emitter region 122 on the front surface 21. The non-contact region 62 may be a region on the sidewall of the gate trench 40 where no contact region 15 is provided below the emitter region 122. Since the non-contact region 62 does not have a contact region 15 below the emitter region 122, an inversion layer may be formed when the gate is turned on, allowing electrons to be injected. The non-contact region 62 of this example is provided extending in the trench arrangement direction from one opposing trench to the other opposing trench.

[0085] A plurality of contact formation regions 61 may be provided in the mesa portion 71 along the trench extension direction. The emitter region 12 may be provided continuously across the plurality of contact formation regions 61. The contact formation regions 61 and the non-contact formation regions 62 may be provided alternately in the trench extension direction. The contact formation regions 61 may be provided in contact with the non-contact formation regions 62. The contact formation regions 61 in this example are in contact with the non-contact formation regions 62 at both ends in the trench extension direction.

[0086] The mesa portion 81 of the diode portion 80 does not have an emitter region 12, but may have an emitter region 12. In this example, an anode region 19 is provided on the front surface 21 of the mesa portion 81. A contact region 15 may be provided on the front surface 21 of the mesa portion 81. In the region of the front surface 21 of the mesa portion 81 sandwiched between the anode regions 19-e, a contact region 15 may be provided in contact with each anode region 19-e. In the region of the front surface 21 of the mesa portion 81 sandwiched between the contact regions 15, an anode region 19 may be provided. The anode region 19 may be disposed in the entire region sandwiched between the contact regions 15 in the trench extension direction.

[0087] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base region 14-e or the anode region 19-e along the trench extension direction. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, the anode region 19, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e, the anode region 19-e, and the well region 17. The contact holes 54 may be arranged at the center of the mesa portion 71 in the trench arrangement direction (X-axis direction). A trench contact portion 58 is provided in the contact hole 54. The trench contact portion 58 will be described later.

[0088] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the rear surface 23 of the semiconductor substrate 10 and a buffer region 20, which will be described later. In FIG. 2A , a boundary 78 between the cathode region 82 and the collector region 22 is indicated by a dashed line.

[0089] The cathode region 82 is disposed away from the well region 17 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 17) that has a relatively high doping concentration and is formed deep, improving the breakdown voltage and suppressing the injection of holes from the well region 17. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 17 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 17 and the contact hole 54.

[0090] The anode region 19 is provided in the mesa portion 91 of the boundary region 90. The boundary region 90 may have a plurality of mesa portions 91. The mesa portion 91 may have the base region 14 instead of the anode region 19. The anode region 19 will be described later.

[0091] 2B is a diagram showing an example of an XZ cross section including the aa' cross section in FIG. 2A. The XZ cross section including the aa' cross section is an XZ plane passing through the contact formation region 61 in the transistor section 70. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the XZ cross section including the aa' cross section. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0092] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0093] The buffer region 20 is a region of the first conductivity type that is provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. The buffer region 20 in this example is provided closer to the back surface 23 of the semiconductor substrate 10 than the center of the semiconductor substrate 10 in the depth direction. The buffer region 20 in this example is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0094] The collector region 22 and the cathode region 82 are provided on the back surface 23 of the semiconductor substrate 10. The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. A boundary 78 between the collector region 22 and the cathode region 82 may be the boundary between the transistor section 70 and the diode section 80.

[0095] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. At least a portion of the collector electrode 24 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).

[0096] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71. The base region 14 may also be provided in the mesa portion 91. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0097] The anode region 19 is a second conductivity type region provided above the drift region 18 in the mesa portion 91 and the mesa portion 81. The anode region 19 is provided in contact with the dummy trench portion 30. The anode region 19 may be provided in contact with the gate trench portion 40. The depth of the anode region 19 in the depth direction of the semiconductor substrate 10 may be deeper, shallower, or equal to the depth of the base region 14. In this example, the depth of the anode region 19 is equal to the depth of the base region 14.

[0098] The doping concentration of the anode region 19 may be the same as or lower than that of the base region 14. The maximum doping concentration of the anode region 19 may be smaller than or equal to the maximum doping concentration of the base region 14. In this example, the maximum doping concentration of the anode region 19 is smaller than the maximum doping concentration of the base region 14. The integral of the doping concentration of the anode region 19 along the depth direction of the semiconductor substrate 10 may be smaller than or equal to the integral of the doping concentration of the base region 14. In this example, the integral of the doping concentration of the anode region 19 is smaller than the integral of the doping concentration of the base region 14.

[0099] The emitter region 12 is provided closer to the front surface 21 than the drift region 18, and has a higher doping concentration than the drift region 18. The emitter region 12 of this example is provided on the front surface 21. That is, the emitter region 12 of this example is exposed at the front surface 21 of the semiconductor substrate 10. The emitter region 12 of this example is provided above the base region 14 in the mesa portion 71. The emitter region 12 may be provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 does not have to be provided in the mesa portion 91.

[0100] The contact region 15 is a region of the second conductivity type having a higher doping concentration than the base region 14. The contact region 15 is provided above the base region 14. In this example, the contact region 15 is provided below the emitter region 12. In the contact formation region 61, the upper end of the contact region 15 may be in contact with the lower end of the emitter region 12. The entire upper end of the contact region 15 may be in contact with the lower end of the emitter region 12, or a portion of the upper end of the contact region 15 may be in contact with the lower end of the emitter region 12. In this example, in the contact formation region 61, the entire upper end of the contact region 15 is in contact with the lower end of the emitter region 12. In the contact formation region 61, the contact region 15 may extend in the arrangement direction from one to the other of two adjacent trench portions. The contact region 15 may be in contact with at least one sidewall of the gate trench portion 40 or the dummy trench portion 30.

[0101] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. In this example, the accumulation region 16 is, for example, an N-type. The accumulation region 16 is provided in the mesa portion 71. The accumulation region 16 may also be provided in the mesa portion 81 and the mesa portion 91.

[0102] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0103] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions are not limited to those manufactured in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include those formed after the trenches are formed.

[0104] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0105] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 sandwiched between them, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench. Meanwhile, below the emitter region 12, the contact region 15 contacts the sidewall of the gate trench portion 40. In this case, the gate threshold is locally increased in the portion of the sidewall of the gate trench portion 40 that contacts the contact region 15, and a channel formed by an electron inversion layer is not formed. Therefore, electrons are not injected into the drift region 18 in the contact formation region 61.

[0106] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0107] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0108] The trench contact portion 58 is provided in a mesa portion between two adjacent trench portions among the plurality of trench portions, extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The trench contact portion 58 may be provided extending from the upper end of the interlayer insulating film 38 to the inside of the semiconductor substrate 10. The trench contact portion 58 of this example is provided in the contact hole 54. The trench contact portion 58 may have a plug portion 59. The plug portion 59 may be tungsten. The plug portion 59 may be made of the same material as the emitter electrode 52. The trench contact portion 58 may have a barrier metal 53 formed of titanium, a titanium compound, or the like. The semiconductor device 100 of this example can improve latch-up resistance by including the trench contact portion 58.

[0109] The plug region 13 is provided below the trench contact portion 58. In this example, the plug region 13 is in contact with the bottom surface of the trench contact portion 58. The plug region 13 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the plug region 13 has a higher doping concentration than the contact region 15. The doping concentration of the second conductivity type dopant in the plug region 13 may be equal to or lower than the doping concentration of the first conductivity type dopant in the emitter region 12, or may be equal to or higher than the doping concentration of the first conductivity type dopant in the emitter region 12. In this example, the doping concentration of the second conductivity type dopant in the plug region 13 is lower than the doping concentration of the first conductivity type dopant in the emitter region 12.

[0110] The plug region 13 may be provided on the bottom surface of the trench contact portion 58, extending in the trench extension direction. The plug region 13 may be provided on the entire bottom surface of the trench contact portion 58. The plug region 13 may be formed in a region overlapping with a region into which a first conductivity type dopant is ion-implanted to form the emitter region 12, or may be formed in a region overlapping with a region into which a second conductivity type dopant is ion-implanted to form the contact region 15. The plug region 13 may also be provided in the boundary region 90 and the diode portion 80.

[0111] The bottom surface of the trench contact portion 58 may be deeper than the lower end of the emitter region 12. The bottom surface of the trench contact portion 58 may be shallower than the lower end of the base region 14. The bottom surface of the trench contact portion 58 may be shallower or deeper than the lower end of the contact region 15. In this example, the bottom surface of the trench contact portion 58 is deeper than the lower end of the contact region 15.

[0112] Although the semiconductor device 100 of this example does not include a lifetime control unit having a lifetime killer, it may include a lifetime control unit. The semiconductor device 100 may include a lifetime killer region closer to the front surface 21 than the center in the depth direction of the semiconductor substrate 10, or may include a lifetime killer region closer to the back surface 23 than the center in the depth direction of the semiconductor substrate 10.

[0113] 2C is a diagram showing an example of an XZ cross section including the bb' cross section in FIG. 2A. The XZ cross section including the bb' cross section is an XZ plane passing through the non-contact region 62 in the transistor section 70. In this example, differences from the aa' cross section in FIG. 2B passing through the contact region 61 will be particularly described. Other points may be the same as the aa' cross section in FIG. 2B.

[0114] The non-contact region 62 includes an emitter region 122, a plug region 13, a base region 14, and an accumulation region 16 in the mesa portion 71. The non-contact region 62 does not include a contact region 15. The lower surface of the emitter region 122 may be in contact with the upper surface of the base region 14. The bottom surface of the trench contact portion 58 may be deeper than the lower end of the emitter region 122. As will be described later, the lower end of the emitter region 122 may be deeper than the lower end of the emitter region 121.

[0115] Below the emitter region 12 in the contactless region 62, the contact region 15 is not provided, and the base region 14 is in contact with the sidewall of the gate trench portion 40. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40. The electron inversion layer is continuously formed from the portion of the base region 14 that is in contact with the gate trench portion 40 and is in contact with the bottom surface of the emitter region 12 to the portion of the base region 14 that is in contact with the gate trench portion 40 and is in contact with the accumulation region 16. Therefore, electrons are injected from the emitter region 12 into the drift region 18.

[0116] 2D shows an example of a YZ cross section including the c-c' cross section in FIG. 2A. The YZ cross section including the c-c' cross section is a YZ plane passing through the mesa portion 71 of the transistor portion 70. The c-c' cross section may be a YZ plane passing through the mesa portion 71 between the trench contact portion 58 and the gate trench portion 40. The c-c' cross section is a cross section that does not pass through the contact hole 54, but the bottom surface of the trench contact portion 58 is indicated by a dashed line.

[0117] The contact formation region 61 is provided between two adjacent non-contact formation regions 62 in the trench extension direction. The non-contact formation region 62 is provided between two adjacent contact formation regions 61 in the trench extension direction. At the end of the contact formation region 61 adjacent to the non-contact formation region 62, there may be a step at the lower end of the emitter region 121.

[0118] The length L61 is the width in the trench extension direction of the contact formation region 61. The length L61 may be the width in the trench extension direction of the contact formation region 61 that is in contact with the gate trench portion 40. The length L61 in the trench extension direction of the contact formation region 61 may be 0.4 μm or more and 8.0 μm or less.

[0119] The length L62 is the width in the trench extension direction of the non-contact region 62. The length L62 may be the width in the trench extension direction of the non-contact region 62 that contacts the gate trench portion 40. The length L62 in the trench extension direction of the non-contact region 62 may be 0.4 μm or more and 1.9 μm or less.

[0120] The length L62 of the non-contact region 62 in the trench extension direction may be greater than the length L61 of the contact region 61 in the trench extension direction. However, the length L62 of the non-contact region 62 in the trench extension direction may be smaller than or the same as the length L61 of the contact region 61 in the trench extension direction.

[0121] The ratio α is the ratio of the length L62 of the non-contact region 62 in the trench extension direction to the length L61 of the contact region 61 in the trench extension direction. As the ratio α increases, the proportion of the non-contact region 62 that functions as a channel increases, and the channel density increases. As the ratio α decreases, the proportion of the non-contact region 62 decreases, and the channel density decreases. The ratio α may be 0.2 or more and 20 or less.

[0122] The thickness D121 is the width of the emitter region 121 in the depth direction of the semiconductor substrate 10. When the emitter region 121 has a slope on the bottom surface, the thickness D121 may be the width of the emitter region 121 at the shallowest position of the emitter region 121. The thickness D122 is the width of the emitter region 122 in the depth direction of the semiconductor substrate 10.

[0123] The thickness D121 of the emitter region 121 may be smaller than the thickness D122 of the emitter region 122. That is, the lower end of the emitter region 121 may be shallower than the lower end of the emitter region 122. The thickness D121 of the emitter region 121 may be equal to or smaller than the thickness D122 of the emitter region 122. Because the dopant in the emitter region 121 is less likely to diffuse than the dopant in the emitter region 122 due to the influence of the contact region 15, the emitter region 121 may be formed shallower than the emitter region 122.

[0124] The position Pz15 is the distance from the front surface 21 to the bottom end of the contact region 15 in the depth direction of the semiconductor substrate 10.

[0125] Position Pz14 is the position of the lower end of the base region 14 from the front surface 21 in the depth direction of the semiconductor substrate 10. Position Pz14 may be equal to or greater than position Pz15.

[0126] Position Pz15 may be smaller than position Pz 14. That is, the bottom end of contact region 15 may be shallower than the bottom end of base region 14.

[0127] 2E is an enlarged view showing an example of an XZ cross section of an area Q of the transistor portion 70 of the semiconductor device 100 in FIG. 2B. The area Q shows the vicinity of the mesa portion 71 sandwiched between the dummy trench portion 30 and the gate trench portion 40.

[0128] The plug region 13 contacts the bottom surface of the trench contact portion 58. The plug region 13 in this example may contact the sidewall of the trench contact portion 58. The plug region 13 may contact the sidewall of the trench contact portion 58 on the dummy trench portion 30 side, or may contact the sidewall of the trench contact portion 58 on the gate trench portion 40 side. The plug region 13 in this example contacts both the sidewall of the trench contact portion 58 on the dummy trench portion 30 side and the sidewall of the trench contact portion 58 on the gate trench portion 40 side. The sidewall of the trench contact portion 58 in this example contacts the emitter region 121 and the plug region 13.

[0129] The length Lg121 is the length in the depth direction of the emitter region 121 that contacts the gate trench portion 40. The length Lg15 is the length in the depth direction of the contact region 15 that contacts the gate trench portion 40 in the contact formation region 61. The length Lg15 may be greater than the length Lg121. However, the length Lg15 may also be smaller than the length Lg121.

[0130] 2F shows an example of a YZ cross section including the gg' cross section in FIG. 2A. The YZ cross section including the gg' cross section includes a portion of the YZ plane passing through the mesa portion 71 of the transistor portion 70, from the end of the contact hole 54 to the well region 17. Other regions may be the same as the cc' cross section in FIG. 2D. The end of the emitter region 12 in the trench extension direction may be covered with the contact region 15. The end of the plug region 13 in the trench extension direction may be covered with the contact region 15. The contact region 15 provided on the outermost side of the mesa portion 71 may be in contact with the base region 14, and the base region 14 may be exposed on the front surface 21. The base region 14 exposed on the front surface 21 may be in contact with the well region 17. The end of the accumulation region 16 in the trench extension direction may be located below the non-contact region 62, below the contact region 15 provided on the outermost side of the mesa portion 71, below the base region 14 exposed on the front surface 21, or inside the well region 17. In this case, the end of the accumulation region 16 in the trench extension direction is located below the non-contact region 62.

[0131] 3A shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example is an example of an IGBT having a transistor portion 70. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in that the semiconductor device 100 of this example does not include a diode portion 80 and a boundary region 90. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described, and other aspects may be the same as the semiconductor device 100 of FIG. 2A.

[0132] In the semiconductor device 100 of this example, the dopant for forming the emitter region 12 may be ion-implanted into the entire surface of the mesa portion 71. In one example, the dopant for forming the emitter region 12 may be ion-implanted without patterning a mask specifically for the emitter region 12. The dopant for forming the emitter region 12 may be ion-implanted into the entire surface of the semiconductor substrate 10 without using a resist mask. However, an insulating film or the like may function as a mask in a portion of the semiconductor substrate 10, and the dopant for forming the emitter region 12 may not be ion-implanted therein.

[0133] The emitter region 12 may be provided in the mesa portion 71 so as to extend in the trench extension direction, and both ends in the trench extension direction may be in contact with the multiple well regions 17. The doping concentration of the emitter region 12 in the front surface 21 of the semiconductor substrate 10 may be higher than the doping concentration of the well regions 17. As in this example, a contact formation region 61 may be provided on the front surface 21 in a portion where the well region 17 is formed closer to the back surface 23 than the front surface 21. In other words, the contact formation region 61 may also be provided above the well region 17. The emitter regions 121 and the emitter regions 122 may be provided alternately in the trench extension direction between the multiple well regions 17.

[0134] The well region 17 may be provided extending from the outside of the mesa portion 71 to the end of the contact hole 54 in the trench extension direction. On the other hand, the end of the contact hole 54 may be located inside the contact formation region 61, or may be located inside the endmost contact formation region 61 in the Y-axis direction. Multiple well regions 17 may be provided at both ends of the mesa portion 71 in the trench extension direction. That is, the well region 17 may be provided at the end of the mesa portion 71 on the positive side in the Y-axis direction, or at the end of the mesa portion 71 on the negative side in the Y-axis direction. Dopants for forming the emitter region 12 may be ion-implanted into the region where the well region 17 is formed.

[0135] The semiconductor device 100 may include a contact region 15 and a base region 14-e at both ends of the mesa portion 71 in the trench extension direction, as in the semiconductor device 100 of FIG. 2A.

[0136] By forming the emitter region 12 in the contact formation region 61 and the contact non-formation region 62, it is possible to avoid the influence of variations in the mask used to form the emitter region 12 and suppress variations in diffusion of the contact region 15. This suppresses variations in the emitter region 12, reduces variations in the saturation current Isc, and suppresses variations in the short circuit time Tsc.

[0137] 3B is a diagram showing an example of an XZ cross section including the dd' cross section in FIG. 3A. The XZ cross section including the dd' cross section is an XZ plane passing through the contact formation region 61 in the transistor section 70. In this example, differences from the aa' cross section in FIG. 2B will be particularly described, and other points may be the same as the aa' cross section in FIG. 2B. The dd' cross section in this example differs from the aa' cross section in FIG. 2B in that it does not have the diode section 80 and the boundary region 90.

[0138] The contact formation region 61 of this example has an emitter region 121, a contact region 15, a base region 14, and an accumulation region 16 in the mesa portion 71. The contact formation region 61 of this example has a plug region 13, but the plug region 13 does not have to be provided on the bottom surface of the trench contact portion 58.

[0139] The trench contact portion 58 may be in contact with the emitter region 121 and the contact region 15. The sidewall of the trench contact portion 58 in this example is in contact with the emitter region 121 and the contact region 15. The trench contact portion 58 may be in contact with the emitter region 121 and the contact region 15 on the sidewall facing the gate trench portion 40. The trench contact portion 58 may be in contact with the emitter region 121 and the contact region 15 on the sidewall facing the dummy trench portion 30. The bottom surface of the trench contact portion 58 may be in contact with the contact region 15.

[0140] 3C is a diagram showing an example of an XZ cross section including the ee' cross section in FIG. 3A. The XZ cross section including the ee' cross section is an XZ plane passing through the contactless region 62 in the transistor section 70. In this example, differences from the bb' cross section in FIG. 2C will be particularly described, and other points may be the same as the bb' cross section in FIG. 2C. The ee' cross section in this example differs from the bb' cross section in FIG. 2C in that it does not have the diode section 80 and the boundary region 90.

[0141] The non-contact region 62 of this example has an emitter region 122, a base region 14, and an accumulation region 16 in the mesa portion 71. The non-contact region 62 does not have a contact region 15. The non-contact region 62 of this example has a plug region 13, but the plug region 13 does not have to be present on the bottom surface of the trench contact portion 58. The lower end of the emitter region 122 may be deeper than the lower end of the emitter region 121.

[0142] When the plug region 13 is omitted, the trench contact portion 58 may be in contact with the emitter region 122 and the base region 14. In this case, the trench contact portion 58 may be in contact with the emitter region 122 and the base region 14 on a sidewall facing the gate trench portion 40. The trench contact portion 58 may be in contact with the emitter region 122 and the base region 14 on a sidewall facing the dummy trench portion 30. The bottom surface of the trench contact portion 58 may be in contact with the base region 14.

[0143] 3D shows an example of a YZ cross section including the ff' cross section in FIG. 3A. The YZ cross section including the ff' cross section is a YZ plane that passes through the mesa portion 71 of the transistor portion 70. The ff' cross section is a cross section that does not pass through the contact hole 54. The bottom surface of the trench contact portion 58 is indicated by a dashed line. The ff' cross section may be the same as the cc' cross section in FIG. 2D.

[0144] 4A shows an enlarged top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in the region where the contact region 15 is formed. However, the semiconductor device 100 of this example is common to the semiconductor device 100 of FIG. 2A in that the emitter region 12 is present on the front surface 21. Therefore, the top view of the semiconductor device 100 of this example may be the same as the top view of the semiconductor device 100 of FIG. 2A. In this example, differences from the semiconductor device 100 of FIG. 2A will be particularly described.

[0145] This figure shows an enlarged top view of the semiconductor device 100 in which the dummy trenches 30 and the gate trenches 40 are arranged alternately. However, the arrangement of the dummy trenches 30 and the gate trenches 40 is not limited to this example. The dummy trenches 30 may face each other, or the gate trenches 40 may face each other.

[0146] The contact formation region 61 is provided between the dummy trench portion 30 and the contact hole 54 in a top view. The contact formation region 61 is also provided between the gate trench portion 40 and the contact hole 54 in a top view. The non-contact formation region 62 is provided between the gate trench portion 40 and the contact hole 54 in a top view. The non-contact formation region 62 does not have to be provided between the dummy trench portion 30 and the contact hole 54 in a top view. The contact formation region 61 and the non-contact formation region 62 are provided alternately in the trench extension direction between the gate trench portion 40 and the contact hole 54 in a top view.

[0147] The contact formation region 61 in contact with the sidewall of the dummy trench portion 30 is provided extending in the trench extension direction. That is, the contact region 15 in this example is provided between the dummy trench portion 30 and the gate trench portion 40 and extending in the trench extension direction. The contact region 15 may be in contact with the base region 14-e at both ends in the trench extension direction, or may be in contact with the well region 17 at both ends in the trench extension direction. In this specification, "N+ / P+" indicates that the contact region 15 is provided below the emitter region 12.

[0148] The contact formation region 61 in contact with the sidewall of the dummy trench portion 30 may be longer than the width in the trench extension direction of the contact formation region 61 in contact with the gate trench portion 40, and may be provided extending in the trench extension direction. By providing the contact formation region 61 on the sidewall of the dummy trench portion 30 extending in the trench extension direction, latch-up can be more easily suppressed.

[0149] In the semiconductor device 100 of this example, the contact formation regions 61 are formed side by side with the contactless regions 62 in the trench arrangement direction, thereby making it possible to increase the length in the trench extension direction of the contactless regions 62 that function as channels on the sidewalls of the gate trench portions 40. This allows the semiconductor device 100 to adjust the channel density while suppressing latch-up.

[0150] The semiconductor device 100 of this example can adjust the saturation current Isc during a short circuit by changing the ratio α of the contact formation region 61 to the contact non-formation region 62 on the sidewall of the gate trench portion 40. Therefore, the semiconductor device 100 can adjust the saturation current Isc even when the ratio of the dummy trench portion 30 is increased and the gate capacitance Qg is reduced. The semiconductor device 100 can improve dV / dt controllability during turn-on by lowering the gate capacitance Qg. The semiconductor device 100 can improve the channel density and reduce the on-voltage while ensuring a desired gate capacitance Qg.

[0151] 4B shows an example of an XZ cross section of the semiconductor device 100 shown in FIG. 4A. The XZ cross section in this example is an XZ plane passing through the contact formation region 61 and the contactless region 62 in the transistor section 70. The semiconductor device 100 in this example includes the plug region 13, but may not include the plug region 13.

[0152] The trench contact portion 58 provided between the dummy trench portion 30 and the gate trench portion 40 contacts the emitter region 121 and the plug region 13 on the sidewall on the dummy trench portion 30 side, and contacts the emitter region 122 and the plug region 13 on the sidewall on the gate trench portion 40 side. When the plug region 13 is omitted, the trench contact portion 58 may contact the contact region 15 on the sidewall on the dummy trench portion 30 side.

[0153] 4C is an enlarged view showing an example of the XZ cross section of the semiconductor device 100. This figure shows the mesa portion 71 sandwiched between the dummy trench portion 30 and the gate trench portion 40.

[0154] The contact region 15 extends in the trench arrangement direction from the sidewall of the dummy trench portion 30 to below the bottom surface of the trench contact portion 58 and terminates therein. That is, the contact region 15 may be provided spaced apart from the gate trench portion 40.

[0155] The end 150 indicates the position of the contact region 15 that is farthest from the sidewall of the dummy trench portion 30 in the trench arrangement direction. In this example, the end 150 is located at the center of the mesa portion 71 in the trench arrangement direction. In this example, the end 150 is located at the lower end of the plug region 13. The end 150 may be located below the bottom surface of the trench contact portion 58.

[0156] The thickness D15 is the distance from the upper end to the lower end of the contact region 15 in the depth direction of the semiconductor substrate 10. The thickness D15 may be the distance from the upper end to the lower end of the contact region 15 on the sidewall of the dummy trench portion 30. The thickness D15 may be the distance from the upper end of the contact region 15 that is in contact with the lower end of the emitter region 121 to the lower end of the contact region 15.

[0157] The width W15 is the distance from the sidewall of the dummy trench portion 30 in the trench arrangement direction to the end 150 of the contact region 15. In this example, the width W15 is half the mesa width W71 of the mesa portion 71. The width W15 may be smaller than half the mesa width W71 or may be larger than half the mesa width W71.

[0158] The contact region 15 extends in the trench arrangement direction from the sidewall of the dummy trench portion 30 beyond the bottom surface of the trench contact portion 58 and terminates without exceeding the end of the plug region 13 on the gate trench portion 40 side.

[0159] 4D is an enlarged view showing a modified XZ cross section of the semiconductor device 100. This figure shows a mesa portion 71 sandwiched between a dummy trench portion 30 and a gate trench portion 40.

[0160] The contact region 15 extends in the trench arrangement direction from the sidewall of the dummy trench portion 30 beyond the bottom surface of the trench contact portion 58, and terminates without contacting the gate trench portion 40. That is, the end portion 150 may be spaced apart from the sidewall of the gate trench portion 40. The width W15 of the contact region 15 may be smaller than the width W71 of the mesa portion 71. By spaced apart the contact region 15 from the gate trench portion 40, an increase in the threshold voltage can be suppressed.

[0161] In this example, the contact region 15 extends in the trench arrangement direction from the sidewall of the dummy trench portion 30 beyond the bottom surface of the trench contact portion 58, and terminates without passing beyond the plug region 13. An end 150 of the contact region 15 may coincide with the end of the plug region 13 on the gate trench portion 40 side.

[0162] 5A shows an enlarged top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 4A in the region where the contact region 15 is formed. In this example, the differences from the semiconductor device 100 of FIG. 4A will be particularly described.

[0163] The mesa portion 71 sandwiched between two adjacent dummy trench portions 30 is a contact formation region 61. That is, the contact formation region 61 may be provided extending in the trench extension direction in the mesa portion 71 sandwiched between two adjacent dummy trench portions 30. The mesa portion 71 sandwiched between two adjacent dummy trench portions 30 does not have a contact non-formation region 62. Both ends of the contact formation region 61 in the trench extension direction may be in contact with multiple well regions 17, and may be in contact with multiple base regions 14-e. That is, the mesa portion 71 sandwiched between two adjacent dummy trench portions 30 may have a contact region 15 on the entire surface of the region sandwiched between the base regions 14-e, and may have a contact region 15 on the entire surface of the region sandwiched between the well regions 17.

[0164] The mesa portion 71 sandwiched between two adjacent dummy trench portions 30 may have an emitter region 12. In this example, the mesa portion 71 sandwiched between two adjacent dummy trench portions 30 has an emitter region 121. The mesa portion 71 sandwiched between two adjacent dummy trench portions 30 may have the emitter region 121 over the entire surface of the region sandwiched between the base regions 14-e, or may have the emitter region 121 over the entire surface of the region sandwiched between the well regions 17.

[0165] 5B shows an example of an XZ cross section of the semiconductor device 100 shown in FIG. 5A. The XZ cross section in this example is an XZ plane passing through the contact formation region 61 and the contactless region 62 in the transistor section 70. The semiconductor device 100 in this example includes the plug region 13, but may not include the plug region 13. In this example, differences from the semiconductor device 100 in FIG. 4B will be particularly described.

[0166] The trench contact portion 58 provided between two adjacent dummy trench portions 30 may contact the emitter region 121 and the plug region 13 at its sidewall. In the trench contact portion 58 of this example, both sidewalls are in contact with the emitter region 121 and the plug region 13 between two adjacent dummy trench portions 30. If the plug region 13 is omitted, the trench contact portion 58 may contact the contact region 15 at its sidewall and bottom end.

[0167] 6 is an enlarged view showing an example of the XZ cross section of the semiconductor device 100. This drawing shows a mesa portion 71 sandwiched between two adjacent dummy trench portions 30.

[0168] In the mesa portion 71 sandwiched between two adjacent dummy trench portions 30, the contact region 15 may be provided in contact with only one of the two adjacent dummy trench portions 30. Therefore, the thickness D122 of the emitter region 122 is greater than the thickness D121 of the emitter region 121. The emitter region 121 is in contact with one dummy trench portion 30, and the emitter region 122 is in contact with the other dummy trench portion 30.

[0169] In this example, the width W15 is half the mesa width W71, but it may be larger or smaller than half the mesa width W71. Even in the mesa portion 71 sandwiched between two adjacent dummy trench portions 30, the structure of the contact region 15 may be such that the end 150 extends to the end of the plug region 13, as shown in FIG.

[0170] 7A shows an enlarged top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 5A in that it has an emitter region 12 and a contact region 15 on the front surface 21. In this example, the differences from the semiconductor device 100 of FIG. 5A will be particularly described. The semiconductor device 100 of this example has a contact exposure region 63.

[0171] The contact exposed region 63 is a region on the sidewall of the dummy trench portion 30 where the contact region 15 is provided on the front surface 21. The contact exposed region 63 may not have the emitter region 12. That is, the emitter region 12 may not be provided on the front surface 21 on the sidewall of the dummy trench portion 30. The contact exposed region 63 may be provided at a distance from the gate trench portion 40.

[0172] The contact formation region 61 may be provided in contact with the gate trench portion 40. The contact formation region 61 and the non-contact formation region 62 are provided alternately on the sidewall of the gate trench portion 40 in the trench extension direction. By providing the contact exposure region 63, it becomes easier to make the width of the non-contact formation region 62 in the trench extension direction larger than the width of the contact formation region 61 in the trench extension direction.

[0173] 7B is an enlarged view showing an example of the XZ cross section of the semiconductor device 100. This figure shows a mesa portion 71 sandwiched between the dummy trench portion 30 and the gate trench portion 40. The semiconductor device 100 of this example has a contact region 15 on the front surface 21, on the sidewall of the dummy trench portion 30.

[0174] The contact region 15 extends in the depth direction of the semiconductor substrate 10 on the sidewall of the dummy trench portion 30 from the front surface 21 to the upper end of the base region 14. The emitter region 121 in this example is not provided on the sidewall of the dummy trench portion 30 above the contact region 15, but is provided on the sidewall of the gate trench portion 40.

[0175] The thickness D15 is the distance from the upper end to the lower end of the contact region 15 in the depth direction of the semiconductor substrate 10. In this example, the thickness D15 is the distance from the front surface 21 to the lower end of the contact region 15 in the contact exposed region 63.

[0176] The trench contact portion 58 contacts the emitter region 121 and the plug region 13 on the sidewall on the gate trench portion 40 side. The trench contact portion 58 contacts the contact region 15 and the plug region 13 on the sidewall on the dummy trench portion 30 side. The bottom surface of the trench contact portion 58 contacts the plug region 13. The plug region 13 may be omitted.

[0177] The semiconductor device 100 of this embodiment can reduce the effect of mask misalignment of the emitter region 12 while increasing the area where the contact region 15 is formed, thereby reducing latch-up.

[0178] 8 shows an example of a cross section taken along line xx' in FIG. 1. This figure shows a cross section of the vicinity of edge termination structure 170 of semiconductor device 100. Active region 160 may include an ineffective region 162.

[0179] The ineffective region 162 is provided on the outer periphery of the transistor section 70. The ineffective region 162 may have a plurality of dummy trench sections 30. The semiconductor device 100 of this example is formed by ion-implanting the dopant for the emitter region 12 into the entire surface of the semiconductor substrate 10 without using a mask. Therefore, the emitter region 12 is provided on the front surface 21 of the semiconductor substrate 10 in the ineffective region 162. A contact region 15 may be provided below the emitter region 12 in the ineffective region 162.

[0180] Dummy trench portion 30-e is the dummy trench portion provided closest to edge termination structure portion 170 in invalid region 162. Emitter region 12 may be provided on front surface 21 of the mesa portion in contact with dummy trench portion 30-e. The sidewalls and bottom surface of dummy trench portion 30-e may be in contact with well region 17.

[0181] The edge termination structure 170 is provided on the outer periphery of the invalid region 162. The edge termination structure 170 has a guard ring structure and a channel stopper structure.

[0182] The multiple guard ring portions 172 are an example of a guard ring structure. The multiple guard ring portions 172 may be provided on the front surface 21 to surround the active region 160. The guard ring portion 172 is a P+ type semiconductor region formed by ion implantation near the front surface 21. The guard ring portion 172 is electrically connected to an electrode layer 174. The electrode layer 174 may be made of the same material as the gate metal layer 50 or the emitter electrode 52. The depth of the bottom of the guard ring portion 172 may be the same as the depth of the bottom of the well region 17. The depth of the bottom of the guard ring portion 172 may be deeper than the depth of the bottom of the gate trench portion 40 and the dummy trench portion 30. The multiple guard ring portions 172 can spread a depletion layer generated in the active region 160 outside the semiconductor substrate 10, preventing electric field concentration inside the semiconductor substrate 10 and improving the breakdown voltage.

[0183] The channel stopper region 176 and the electrode layer 174 are an example of a channel stopper structure. The channel stopper region 176 is electrically connected to the electrode layer 174 through an opening in the interlayer insulating film 38. The conductivity type of the channel stopper region 176 may be either the first conductivity type or the second conductivity type. In this example, the conductivity type of the channel stopper region 176 is N+ type. The channel stopper region 176 may terminate a depletion layer generated in the active region 160 at the outer edge of the semiconductor substrate 10.

[0184] 9 shows an example of a method for manufacturing the semiconductor device 100. This example shows an example of a method for manufacturing the semiconductor device 100, and the order of the steps may be changed as appropriate.

[0185] In step S100, the anode region 19 is formed above the drift region 18. In step S102, the base region 14 is formed above the drift region 18. If the base region 14 and the anode region 19 have the same doping concentration, the base region 14 and the anode region 19 may be formed simultaneously in a common process. The order of steps S100 and S102 may be reversed.

[0186] In step S104, a plurality of trenches are formed in the front surface 21 of the semiconductor substrate 10. The dummy trenches 30 and the gate trenches 40 may be formed simultaneously in a common process, or the dummy trenches 30 and the gate trenches 40 may be formed separately. Step S104 may be performed before steps 100 and 102.

[0187] In step S106, the accumulation region 16 is formed. In step 108, the emitter region 12 is formed on the front surface 21 of the semiconductor substrate 10. The dopant for the emitter region 12 may be ion-implanted after the dopant for the accumulation region 16 is ion-implanted, or may be ion-implanted before the dopant for the accumulation region 16 is ion-implanted. The dopant for the emitter region 12 may be ion-implanted after the dopant for the contact region 15 is ion-implanted, or may be ion-implanted before the dopant for the contact region 15 is ion-implanted.

[0188] In step S110, the trench contact portion 58 is formed. Before step S110, the interlayer insulating film 38 may be formed and the contact hole 54 may be formed. The plug region 13 may be formed by ion-implanting a dopant of the second conductivity type into the lower end of the contact hole 54 after the contact hole 54 of the trench contact portion 58 is formed. After the plug region 13 is formed, the contact hole 54 may be filled with a barrier metal 53 and a plug portion 59 to form the trench contact portion 58.

[0189] In this example, the trench contact portion 58 is formed after the emitter region 12 is formed, but it may be formed before the emitter region 12 is formed.

[0190] 10A shows a top view of a semiconductor device 500 of a comparative example. The semiconductor device 500 includes an emitter region 512 and a contact region 515. The semiconductor device 500 of this example does not include a trench contact portion 58.

[0191] The emitter regions 512 and the contact regions 515 are alternately provided in the trench extension direction on the front surface 21. The emitter regions 512 extend from the gate trench portions 40 to the dummy trench portions 30 in the trench arrangement direction. The contact regions 515 extend from the gate trench portions 40 to the dummy trench portions 30 in the trench arrangement direction.

[0192] 10B is a diagram showing an example of a YZ cross section including the ii' cross section in FIG. 10A. Although there is a region where the lower end of the emitter region 512 partially overlaps the upper end of the contact region 515, the emitter region 512 is not provided above the contact region 515. Therefore, the channel density may vary due to the influence of mask misalignment between the mask used to ion-implant dopants into the emitter region 512 and the mask used to ion-implant dopants into the contact region 515. L512 indicates the length of the emitter region 512 exposed on the front surface 21 in the trench extension direction. L515 indicates the length of the contact region 515 exposed on the front surface 21 in the trench extension direction.

[0193] 11A is a diagram illustrating a design method for a semiconductor device 500 of a comparative example. The horizontal axis represents the gate ratio R, and the vertical axis represents the length (μm) of the emitter region 512, L512, and the contact region 515, L515, in the trench extension direction. The gate ratio R indicates the number of gate trench portions relative to the total number of trenches. For example, when the gate ratio R is 0.25, three dummy trench portions are provided for one gate trench portion.

[0194] In the semiconductor device 500, in order to maintain a constant saturation current Isc when changing the gate ratio R, it was necessary to fix the length L512 of the emitter region 512 and adjust the length L515 of the contact region 515. In this case, if the proportion of the dummy trench portion is increased and the gate ratio R is reduced, it is necessary to reduce the length L515 of the contact region 515 to maintain a constant saturation current Isc, which may result in a decrease in latch-up resistance. Furthermore, when the gate ratio R is reduced, if an attempt is made to adjust the channel density by reducing the length L515 of the contact region 515 to maintain a constant saturation current Isc, there is a limit to the minimum dimension of the length L515, which may result in manufacturing limitations. On the other hand, in order to increase the saturation current Isc while maintaining a constant gate ratio R, it is necessary to reduce the length L515 of the contact region 515. However, even in this case, there is a limit to the minimum dimension of the length L515, and it is difficult to increase the saturation current Isc while maintaining a constant gate ratio R, especially when the gate ratio R is relatively small (e.g., 0.25 or less).

[0195] FIG. 11B is a diagram illustrating an example of a design method for the semiconductor device 100. The horizontal axis represents the gate ratio R, and the vertical axis represents the length (μm) of the contact region 61 and the non-contact region 62 in the trench extension direction. The semiconductor device 100 can maintain a constant saturation current Isc when changing the gate ratio R by adjusting the ratio between the contact region 61 and the non-contact region 62. In this example, the saturation current Isc can be adjusted by keeping the length L61 of the contact region 61, where the contact region 15 is formed, constant and adjusting the length L62 of the non-contact region 62. Alternatively, the saturation current Isc may be adjusted by adjusting the length L61 while keeping the length L62 constant, or by changing both the length L61 and the length L62. For example, to maintain a constant saturation current Isc and relatively reduce the gate ratio R (e.g., 0.25 or less), the length L62 of the non-contact region 62 may be increased. By providing the trench contact portion 58 that is equal to or deeper than the emitter region 12, the gate ratio R can be easily reduced without reducing the latch-up resistance.

[0196] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0197] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0198] 10...Semiconductor substrate, 12...Emitter region, 13...Plug region, 14...Base region, 15...Contact region, 16...Accumulation region, 17...Well region, 18...Drift region, 19...Anode region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 50...Gate metal layer, 51...Gate runner portion, 52...Emitter electrode, 53...Barrier metal, 54...Contact hole, 55...Contact 1. trench contact portion, 56...contact hole, 58...trench contact portion, 59...plug portion, 61...contact formed region, 62...contact non-formed region, 63...contact exposed region, 70...transistor portion, 71...mesa portion, 78...boundary, 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary region, 91...mesa portion, 100...semiconductor device, 102...edge, 112...gate pad, 121...emitter region, 122...emitter region, 130...gate wiring, 150...edge, 160...active region, 162...invalid region, 170...edge termination structure portion, 172...guard ring portion, 174...electrode layer, 176...channel stopper region, 500...semiconductor device, 512...emitter region, 515...contact region

Claims

1. A semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a contact region of the second conductivity type provided above the drift region and having a doping concentration higher than that of the base region; a trench contact portion extending from the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate; and a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, wherein the plurality of trench portions have gate trench portions and dummy trench portions, and a mesa portion between the plurality of trench portions comprises: a contact formation region, on a sidewall of at least one of the plurality of trench portions, where the contact region is provided below the emitter region; and a non-contact formation region, on a sidewall of the gate trench portion, where the contact region is not provided below the emitter region.

2. The semiconductor device according to claim 1, wherein the contact formation region is provided on a side wall of the gate trench portion.

3. The semiconductor device according to claim 1, wherein the contact formation region is provided on a side wall of the dummy trench portion.

4. The semiconductor device according to claim 1, wherein a plurality of the contact formation regions are provided in the mesa portion along the trench extension direction, and the emitter region is provided continuously across the plurality of contact formation regions.

5. The semiconductor device according to claim 1, wherein the contact formation regions and the contact non-formation regions are provided alternately in the direction in which the trench extends.

6. The semiconductor device according to claim 1, wherein the lower end of said emitter region in said contact formation region is shallower than the lower end of said emitter region in said non-contact formation region.

7. The semiconductor device according to claim 1, wherein in the contact formation region, the upper end of the contact region is in contact with the lower end of the emitter region.

8. The semiconductor device according to claim 1, wherein in the contact formation region, the entire upper end of the contact region is in contact with the lower end of the emitter region.

9. The semiconductor device according to claim 1, wherein in the contact formation region, the length in the depth direction of the contact region in contact with the gate trench portion is greater than the length in the depth direction of the emitter region in contact with the gate trench portion.

10. The semiconductor device according to claim 1, wherein the ratio of the width of said contact-free region in the trench extension direction to the width of said contact-formed region in the trench extension direction is 0.2 or more and 20 or less.

11. The semiconductor device according to claim 1, wherein the width of the contact formation region in the trench extension direction is 0.4 μm or more and 8.0 μm or less.

12. The semiconductor device according to claim 1, wherein the width of the contact-free region in the trench extension direction is 0.4 μm or more and 1.9 μm or less.

13. The semiconductor device according to claim 1, wherein the contact formation region is in contact with the non-contact formation region at both ends in the trench extension direction.

14. The semiconductor device according to claim 1, further comprising: a plurality of well regions of a second conductivity type having a doping concentration higher than that of the base region, the well regions being provided at both ends of the mesa portion in the trench extension direction; the emitter region being provided in the mesa portion so as to extend in the trench extension direction, and both ends in the trench extension direction being in contact with the plurality of well regions.

15. The semiconductor device according to claim 1, wherein the contact region comprises an exposed contact region provided on the front surface of the semiconductor substrate on the sidewall of the dummy trench portion.

16. The semiconductor device according to claim 1, wherein the bottom end of the contact region is shallower than the bottom end of the base region.

17. The semiconductor device according to claim 1, wherein the contact region extends from the sidewall of the dummy trench portion to below the bottom surface of the trench contact portion in the trench arrangement direction and terminates therein.

18. The semiconductor device according to claim 17, wherein the contact region extends from the sidewall of the dummy trench portion beyond the bottom surface of the trench contact portion in the trench arrangement direction and terminates without contacting the gate trench portion.

19. The semiconductor device according to claim 1, wherein the bottom surface of the trench contact portion is deeper than the lower end of the emitter region and shallower than the lower end of the base region.

20. The semiconductor device according to claim 1, wherein the contact formation region in contact with the sidewall of the dummy trench portion is longer than the width in the trench extension direction of the contact formation region in contact with the gate trench portion, and is provided extending in the trench extension direction.

21. The semiconductor device according to any one of claims 1 to 20, further comprising a plug region of a second conductivity type provided below the trench contact portion and having a doping concentration higher than that of the contact region.

22. The semiconductor device according to claim 21, wherein the plug region contacts the bottom surface of the trench contact portion.

23. The semiconductor device according to claim 21, wherein the plug region contacts both a sidewall of the trench contact portion on the dummy trench portion side and a sidewall of the trench contact portion on the gate trench portion side.

24. The semiconductor device according to claim 21, wherein the contact region extends in the trench arrangement direction from the sidewall of the dummy trench portion beyond the bottom surface of the trench contact portion and terminates without exceeding the end of the plug region on the gate trench portion side.

25. The semiconductor device according to any one of claims 1 to 20, comprising two adjacent dummy trench portions, and wherein the emitter region is also provided in a mesa portion sandwiched between the two adjacent dummy trench portions.

26. The semiconductor device according to claim 25, wherein the mesa portion sandwiched between the two adjacent dummy trench portions is the contact formation region.

27. The semiconductor device according to claim 25, wherein in the mesa portion sandwiched between the two adjacent dummy trench portions, the contact region is provided in contact with only one of the two adjacent dummy trench portions.

28. A semiconductor device according to any one of claims 1 to 20, comprising: a transistor section; an ineffective region provided on the outer periphery of the transistor section; and an edge termination structure provided on the outer periphery of the ineffective region, wherein the emitter region is provided on the front surface of the semiconductor substrate in the ineffective region.

29. The semiconductor device according to any one of claims 1 to 20, comprising a transistor section and a diode section.

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