Systems and methods for firmware adaptive chain of trust

Abstract

A computing system such as an immersion cooling tank with immersed servers may require a central controller for operations including task distribution, power management, status monitoring, and other functionality. These functions are often performed by baseboard management controllers (BMCs), which require binary code to operate components that are included in the computing system. A computing system may have a plurality of configurations, each configuration requiring a unique BMC configuration to match the specified functionality. A BMC image is dynamically configured on boot to load firmware modules corresponding to the components currently within a computing system, and a hash is generated and attested to ensure security. A baseboard management controller (BMC) automatically configures a firmware specification based on the components present in a computing system, such as a server disposed within an immersion cooling system. A BMC is configured to query each of the components to which it is communicatively coupled through each of the communications channels communicatively coupling the BMC to each of the components. The BMC receives responses from each component, the responses including metadata identifying the component. The BMC then determines an identifier for the configuration of the computing system and compares the identifier to a superset configuration to determine if the configuration of the computing system is a known configuration. The BMC boots and operates the computing system based on a determination that the configuration of the computing system is a known configuration.

Description

SYSTEMS AND METHODS FOR FIRMWARE ADAPTIVE CHAIN OF TRUSTCROSS-REFERENCE TO RELATED APPLICATION

[0001] This Application claims the benefit of provisional U.S. Application No. 63 / 550,753, filed on February 7, 2024, and entitled “SYSTEMS AND METHODS FOR FIRMWARE ADAPTIVE CHAIN OF TRUST” and U.S. Application No. 63 / 556,222, filed on February 21, 2024, and entitled “METHOD FOR ENVIRONMENT- AGNOSTIC PLATFORM DETECTION” which are hereby incorporated by reference in their entireties.

[0002] In cases where the present application conflicts with a document incorporated by reference, the present application controls.BACKGROUND

[0003] Section 1: As feature sizes and transistor sizes have decreased for integrated circuits (ICs) including chips and semiconductor dies, the amount of heat generated by a single IC, such as a microprocessor, has increased. Computing hardware that has traditionally been air cooled have evolved to ICs needing more heat dissipation than can be provided by air alone. In some cases, immersion cooling of ICs in a tank containing a coolant liquid is employed to maintain ICs at appropriate operating temperatures. These tanks and ICs may function as cloud computing systems that provide high-power computation on demand for processes like artificial intelligence (Al) training and inference.

[0004] One type of immersion cooling is two-phase immersion cooling, in which heat from a semiconductor die is high enough to boil the coolant liquid. The boiling creates a coolant-liquid vapor in the tank, which is condensed by cooling coils back to liquid form. Heat from the semiconductor dies can then be sunk into the liquid-to-gas and gas-to-liquid phase transitions of the coolant liquid.

[0005] These computing systems may use hardware components from a variety of manufacturers, each of which may be managed using a baseboard management controller (BMC). Accessing a BMC inside of an immersion cooling tank during operation may present unique challenges that do not have readily available solutions.

[0006] Section 2: As feature sizes and transistor sizes have decreased for integrated circuits (ICs) including chips and semiconductor dies, the amount of heat generated by a single IC, such as a microprocessor, has increased. Computing hardware that has traditionally been air cooled have evolved to ICs needing more heat dissipation than can be provided by air alone. In some cases, immersion cooling of ICs in a tank containing a coolant liquid is employed to maintain ICs at appropriate operating temperatures. These tanks and ICs may function as cloud computing systems that provide high-power computation on demand for processes like artificial intelligence (Al) training and inference.

[0007] One type of immersion cooling is two-phase immersion cooling, in which heat from a semiconductor die is high enough to boil the coolant liquid. The boiling creates a coolant-liquid vapor in the tank, which is condensed by cooling coils back to liquid form. Heat from the semiconductor dies can then be sunk into the liquid-to-gas and gas-to-liquid phase transitions of the coolant liquid.

[0008] These computing systems may use hardware components from a variety of manufacturers, each of which may be managed using a baseboard management controller (BMC). Manually configuring the firmware of a BMC inside of an immersion cooling tank on each start up or after switching of components may require excess time and resources, which negatively impact the functionality of the immersion cooling system.SUMMARY

[0009] Section 1: BMC firmware is used for managing and monitoring functionality of distributed computing hardware such as cloud servers. An immersion cooling system may use computing hardware components from a variety of manufacturers, and these computing hardware components may have a complex topology and a host of firmware modules to be managed out-of-band by the BMC. From a runtime debug and monitoring perspective, the BMC may require custom functionality in the form of BMC Modules (e.g., Linux kernel drivers or applications) that are unique to each component within an immersion cooling system (e.g., one or more GPUs from a first manufacturer having a first firmware binary, one or more GPUs from a second manufacturer having a second firmware binary, one or more network interface cards from a third manufacturerhaving a third firmware binary, etc.). During BMC boot process, the trust posture of the overall BMC is rooted in a static root of trust via platform root of trust (pROT).

[0010] However, some of the modules in the BMC image may not be shadowed based on a component identification (ID) such as a shelf keeping unit (SKU) ID. Thus, during boot, certain modules may be omitted from the boot process. Further, standard BMC boot loading processes do not include satisfactory security checks that ensure a loaded module has not been tampered with or otherwise replaced with malicious code intended to compromise a computing system. To ensure that only relevant modules are used in BMC firmware, an adaptable chain of trust is disclosed herein.

[0011] Upon boot, a BMC may dynamically load one or more modules specific to hardware components within a computing system such as an immersion cooling system based on identifying data including an SKU ID. Each module may have a system-specific SKU ID identifying a component that the module is associated with. For example, a module may have an SKU ID identifying a GPU for which the module is a driver. Each module may additionally include information, data, or code indicating how the module is to be initialized by the BMC. Additionally, the BMC may include a runtime attestation agent that can query a hash table to compare a checksum (e.g., a hash) of a BMC module binary for the purpose of a trust assertion on the boot process.

[0012] Instead of manually hard-coding modules into a code base for each specific configuration of an immersion cooling computing system, the inventors have appreciated that a BMC image may include a plurality of modules to be dynamically loaded using a component SKU ID, which is linked to a corresponding module SKU ID. This enables multiple unique and dynamically instantiated configurations to be utilized on the fly without laborious recoding of firmware modules. Further, this allows components to be quickly added or removed to an immersion cooling computing system without requiring costly and time-consuming firmware edits.

[0013] In some aspects, the techniques described herein relate to a non-transitory computer-readable medium containing instructions thereon, the instructions configuring a processor to send a query using one or more communications channels communicatively coupled to the processor; receive a response from a first component, the response from the first component including data identifying the first component; based on the dataidentifying the first component, add a first code module to binary code for a baseboard management controller (BMC), the BMC including the processor and the first code module representing instructions for operation of the first component; calculate a checksum of the binary code; compare the checksum of the binary code to a value determined prior to adding the first code module to the binary code; and in response to the checksum matching the value, load the binary code by the processor and operating the first component using the binary code.

[0014] In some aspects, the techniques described herein relate to a method for controlling a computing system including a processor and at least a first component, the method including sending a query using one or more communications channels communicatively coupled to the processor; receiving a response from a first component, the response from the first component including data identifying the first component; based on the data identifying the first component, adding a first code module to binary code for a baseboard management controller (BMC), the BMC including the processor and the first code module representing instructions for operation of the first component; calculating a checksum of the binary code; comparing the checksum of the binary code to a value determined prior to adding the first code module to the binary code; and in response to the checksum matching the value, loading the binary code by the processor and operating the first component using the binary code.

[0015] In some aspects, the techniques described herein relate to a method, wherein the first component includes at least one of a graphics processing unit (GPU), a central processing unit (CPU), a network interface controller (NIC), a memory module, a data processing unit (DPU), a tensor processing unit (TPU), an artificial intelligence (Al) accelerator, a chipset, an integrated circuit, a sensor, or a power controller.

[0016] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein. The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.

[0017] Section 2: BMC firmware is used for managing and monitoring functionality of distributed computing hardware such as cloud servers. An immersion cooling system may use computing hardware components from a variety of manufacturers, and these computing hardware components may have a complex topology and a host of firmware modules to be managed out-of-band by the BMC. From a runtime debug and monitoring perspective, the BMC may require custom functionality in the form of BMC Modules (e.g., Linux kernel drivers or applications) that are unique to each component within an immersion cooling system (e.g., one or more GPUs from a first manufacturer having a first firmware binary, one or more GPUs from a second manufacturer having a second firmware binary, one or more network interface cards from a third manufacturer having a third firmware binary, etc.). During BMC boot process, the trust posture of the overall BMC is rooted in a static root of trust via platform root of trust (pROT).

[0018] Determining a component ID (such as shelf keeping unit (SKU) ID) dynamically without loading a static (and therefore potentially outdated or mismatched) configuration file may pose a challenge to BMC operation of immersion cooling systems when components are replaced, updated, or changed. Further, a static configuration file presents a risk that an immersion cooling system will be rendered inoperable if the configuration file is corrupted or lost.

[0019] Further, this static configuration approach limits node fungibility and prevents hot-swapping of like-but-not-identical components (e.g., swapping a GPU from NVIDIA™ for a GPU from AMD™, or a first model of NVIDIA™ GPU for a second model of NVIDIA™ GPU). Accordingly, the inventors have developed platform-agnostic systems and methods for enabling a BMC to be dynamically configured for a computing system such as an immersion cooling system without requiring time-consuming preprogramming.

[0020] Instead of manually hard-coding modules into a code base for each specific configuration of an immersion cooling computing system, the inventors have appreciated that a BMC image may include a plurality of modules to be dynamically loaded using a component SKU ID, which is linked to a corresponding module SKU ID. This enables multiple unique and dynamically instantiated configurations to be utilized on the fly without laborious recoding of firmware modules. Further, this allows components to bequickly added or removed to an immersion-cooled or air-cooled computing system without requiring costly and time-consuming firmware edits.

[0021] In some aspects, the techniques described herein relate to a non-transitory computer-readable medium containing instructions thereon, the instructions configuring a processor to transmit one or more queries to a plurality of components of a computing system using one or more communications channels communicatively coupled to the processor; receive a first response to the one or more queries from a first component of the plurality of components, the response from the first component including data identifying the first component; receive a second response to the one or more queries from a second component of the plurality of components, the response from the second component including data identifying the second component; determine an identifier for the computing system based on the first response and the second response; and control a physical operation of the computing system by configuring a firmware of at least one of the processor, the first component, or the second component.

[0022] In some aspects, configuring the firmware comprises altering a firmware binary of at least one of the processor, the first component, or the second component by transmitting an indication of a valid system configuration.

[0023] In some aspects, the physical operation includes a cooling operation.

[0024] In some aspects, the cooling operation includes a flow of fluid to transfer heat from the computing system.

[0025] In some aspects, the instructions further configure the processor to alter an operational parameter of at least the first component or the second component by transmitting the identifier for the computing system to the first component and the second component.

[0026] In some aspects, the operational parameter includes at least one of a voltage, a frequency, a current, a power, a period, a temperature, a fluid flow, a resistance, a state of charge, or a filtration rate.

[0027] In some aspects, the instructions further configure the processor to compare the identifier for the computing system to a superset configuration identifier; determine if the identifier for the computing system matches the superset configuration; and in response to the identifier for the computing system not matching the supersetconfiguration, transmitting a notification to an external controller indicating a request for maintenance.

[0028] In some aspects, the techniques described herein relate to a method for automatically configuring a computing system, the method including transmitting, by a processor, one or more queries to a plurality of components of a computing system using one or more communications channels communicatively coupled to the processor; receiving, by the processor, a first response to the one or more queries from a first component of the plurality of components, the response from the first component including data identifying the first component; receiving, by the processor, a second response to the one or more queries from a second component of the plurality of components, the response from the second component including data identifying the second component; determining, by the processor, an identifier for the computing system based on the first response and the second response; and controlling, by the processor, a physical operation of the computing system by configuring a firmware of at least one of the processor, the first component, or the second component.

[0029] In some aspects, configuring the firmware comprises altering a firmware binary of at least one of the processor, the first component, or the second component by transmitting an indication of a valid system configuration.

[0030] In some aspects, the techniques described herein relate to a method, wherein the physical operation includes a cooling operation.

[0031] In some aspects, the techniques described herein relate to a method, wherein the cooling operation includes a movement of fluid to transfer heat from the computing system.

[0032] In some aspects, the techniques described herein relate to a method, further including: altering, by the processor, an operational parameter of at least the first component or the second component by transmitting the identifier for the computing system to the first component and the second component.

[0033] In some aspects, the techniques described herein relate to a method, wherein the operational parameter includes at least one of a voltage, a frequency, a current, a power, a period, a temperature, a fluid flow, a resistance, a state of charge, or a filtration rate.

[0034] In some aspects, the techniques described herein relate to a method, further including comparing, by the processor, the identifier for the computing system to a superset configuration identifier; determining, by the processor, if the identifier for the computing system matches the superset configuration; and in response to the identifier for the computing system not matching the superset configuration, transmitting, by the processor, a notification to an external controller indicating a request for maintenance.

[0035] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein. The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0037] FIG. 1.1 A illustrates a system for computational processing including a server.

[0038] FIG. 1.1B illustrates details of a BMC image in accordance with the present technology.

[0039] FIG. 1.2 illustrates blocks of a method 200 in accordance with the present technology.

[0040] FIG. 1.3 illustrates an exemplary layout of components in a system in accordance with the present technology.

[0041] FIG. 1.4 depicts aspects of an immersion cooling system for dissipating heat from one or more semiconductor die packages via immersion cooling.

[0042] FIG. 2.1 illustrates an immersion-cooled system for computation in accordance with the present technology.

[0043] FIG. 2.2 illustrates a computing system in accordance with the present technology.

[0044] FIG. 2.3 depicts aspects of an immersion cooling system for dissipating heat from one or more heat-generating components such as semiconductor die packages via immersion cooling.DETAILED DESCRIPTION

[0045] Section 1: Systems, methods, and computer readable media are disclosed that are directed toward dynamic and secure management of BMCs for distributed computing systems such as servers within immersion cooling systems. A BMC module in accordance with the present technology may include configuration data. The configuration data may include a module ID, an SKU ID for each of a plurality of components that may or may not be disposed within system 100, and one or more metadata sections. For example, a BMC module may include an SKU ID and corresponding module for a specific model of GPU from a particular manufacturer. If that specific model of GPU is present in a computing system managed by the BMC, the BMC will load the module containing drivers corresponding to that particular model of GPU.

[0046] BMC 110 may be responsible for and configured to manage debugging, fault handling, firmware updating for components, thermal and power management, telemetry, and other suitable functions. Because BMC 110 may be configured to manage a wide variety of components from a wide variety of manufacturers, BMC image 140 may require firmware modules and / or binary code from a wide variety of sources outside of an organization or entity operating BMC 110. This can introduce potential software attack vectors for malicious entities and lead to server 105, BMC 110, or a system to which server 105 or BMC 110 are connected to be compromised. Accordingly, the inventors have developed systems, methods, and non-transitory computer readable media for enabling BMC 110 to dynamically load (equivalently, shadow) modules for components as needed while maintaining a known chain of trust.

[0047] FIG. 1.1 A illustrates a system 100 for computational processing including a server 105. Server 105 may include a baseboard management controller (BMC 110), a plurality of computing hardware (e.g., graphics processing units (GPUs) 120a-p), and one or more additional components such as network interface card (NIC 130). Each GPU of GPUs 120a-p and NIC 130 may be communicatively coupled with BMC 110. BMC 110 may include a BMC image 140 (illustrated in greater detail in FIG. 1.1B), which may be binary code configured to operate BMC 110 and allow BMC 110 to control one or more functions of server 105, including one or more functions of any individual component of server 105 such as GPUs 120a-p and NIC 130.

[0048] Additionally, BMC 110 may be responsible for managing and / or monitoring one or more sensors (e.g., sensors for monitoring voltage, current, temperature, pressure, frequency, flow rate, power, data processing parameters, etc.), one or more accessories such as fans, chillers, power supplies, NICs, storage units such as hard drives, circulation pumps, alarms or other notification devices, lights, and the like. BMC 110 may be configured to control a power level or operation of server 105 based on any suitable parameter such as parameters monitored by sensors recited above.

[0049] BMC 110 may include one or more processors and / or one or more memory modules. Examples of processors that may be included in BMC 110 are a microprocessor (e.g., a central processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), data processing unit (DPU), and the like), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic controller (PLC), or any suitable processing circuitry. Examples of one or more memory modules that may be included in BMC 110 include a dynamic random access memory (DRAM) module, a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a non-volatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable ROM (OTPROM), or the like), or any suitable type of memory module.

[0050] Referring to FIG. 1.1B, a BMC image 140 is described in greater detail. BMC image 140 may be a binary code file or other similar code file providing operatinginstructions for operating BMC 110 and components included in system 100. BMC image may include instructions stored on a non-transitory computer-readable medium configured to cause a processor to perform one or more actions, calculations, methods, or functions.

[0051] BMC image 140 may include an operating system kernel (OS kernel 142). OS kernel 142 may be a program or similar binary code responsible for operating a computing system at a fundamental level. The kernel may be responsible for operating any software running on a processor or computing device such as BMC 110. OS kernel 142 may be responsible for process and memory management, operating, accessing, and maintaining file systems, accessing logic circuitry such as CPUs, memory modules, storage devices, networks, and the like. OS kernel 142 may be further responsible for preventing conflicts between tasks performed by a processor operating OS kernel 142 such as race conditions, memory overflows, and memory overallocation.

[0052] BMC image 140 may further include BMC module area 144. BMC module area 144 may include one or more component firmware modules configured to operate one or more components to which BMC 110 are communicatively coupled. For example, BMC module area 144 may include a component firmware module for operating a GPU such as GPU 120a of system 100. BMC module area 144 may include modules for components that may or may not be included in system 100. For example, a GPU 120a may be manufactured by a first manufacturer and have a first component firmware module. BMC module area 144 may include the first component firmware module as well as a second component firmware module for a second GPU manufactured by a second manufacturer. In an embodiment, BMC 110 may dynamically detect that a first GPU 120a is present in system 100 while a second GPU manufactured by a second manufacturer is not present in system 100. BMC 110 may accordingly load the first component firmware module but not the second component firmware module. BMC 110 may repeat this process as necessary until all of the modules for the components detected in system 100 are shadowed / loaded. In an embodiment, BMC 110 may load a single component firmware module for a plurality of identical components (e.g., a plurality of GPUs having identical designs).

[0053] Each module (e.g., component firmware module 148) may include a plurality of sections. For example, component firmware module 148 may include amodule configuration data section, a module entry point section, and one or more function sections. A module configuration data section may include an SKU ID of a component with which it is associated, vendor information (e.g., information on a manufacturing vendor for a component), component information, and module or firmware version information. Further, a module configuration data section may include metadata indicating how component firmware module 148 is to be loaded or shadowed by a BMC such as BMC 110. BMC 110 may compare data in the module configuration data of component firmware module 148 to BMC configuration data 146 or to an SKU ID retrieved based on field replacement unit (FRU) data. Each component may include a printed circuit board (PCB) or similar motherboard including an EEPROM containing data describing, associated with, or otherwise identifying a component. FRU data may include an SKU ID and / or product name description for a component and may be retrieved by an early boot module such as uBoot 141. A module entry point section may include module metadata such as component compatibility information and entry location for code execution (e.g., a code entry address in memory). A module function section may include application programming interface (API) functionality supported by the module, a list of module functions, and the binary code responsible for executing the functions.

[0054] BMC 110 may include an early boot module that determines SKU IDs of components included in system 100 prior to loading of BMC image 140. In an embodiment, BMC image 140 may include an early boot module. An early boot module may query, read, or otherwise communicate with some, any, or all components included in system 100 and communicatively coupled to BMC 110 and receive a response from those respective components in order to determine an SKU ID. BMC 110 may then parse BMC module area 144 to determine which modules correspond to components with any detected SKU IDs. BMC 110 may then load any component modules 148 containing firmware required to operate components included in system 100.

[0055] FIG. 1.2 illustrates blocks of a method 200 in accordance with the present technology. Method 200 may include blocks 205-275.

[0056] At block 205, the uBoot 141 and BMC kernel 142 are loaded. The uBoot 141 and / or kernel 142 may include one or more tests to evaluate the BMC 110 for faults, errors, status, or operating condition. The uBoot 141 and / or kernel 142 may beresponsible for querying one or more FRUs for component information including SKU ID, product name description, and any other relevant configuration information that BMC 110 may require to load a component of the one or more components.

[0057] At block 210, BMC 110 may query one or more FRUs for component information by sending out a query, ping, or other message along each communication channel that is communicatively coupled to BMC 110 including ethernet, inter-integrated circuit (I2C), fiber optic, RS-232, serial AT attachment (SATA) bus, or other similar serial channel, peripheral component interconnect express (PCIe), compute express link (CXL), or any other channel through which BMC 110 may communicate with FRUs within system 100. For each FRU detected by BMC 110, BMC 110 may determine an associated SKU ID.

[0058] At block 215, BMC 110 determines if there are modules for an associated SKU ID. If yes, the method proceeds to block 225. If no, the method proceeds to block 220.

[0059] At block 220, if BMC 110 determines that there are no BMC modules for a given SKU ID, BMC 110 determines if there are additional SKU IDs remaining that have not been checked. If there are, BMC 110 returns to block 210 and determines the next target SKU ID. If no more BMC modules exist, the method proceeds to block 250.

[0060] At block 225, BMC 110 fetches and parses the module configuration data in component firmware module 148 which may determine how the module should be loaded, which functions are included, other components that a relevant component may interface with, etc.

[0061] At block 230, BMC 110 determines if a loaded BMC module configuration is applicable for a given SKU ID. If so, the method proceeds to block 235. If the loaded BMC module configuration is not applicable for a given SKU ID, the method returns to block 220. Additionally, if a system 100 includes a plurality of identical GPUs, a single module may be sufficient to operate all of the functions of the plurality of GPUs. If BMC 110 has previously loaded a module for the same component (for example for an identical GPU), the method may return to block 220.

[0062] At block 235, the component firmware module 148 is shadowed (e.g., copied from long-term storage such as ROM to short-term BMC memory such as RAM).Shadowing the component firmware module 148 may incorporate the component firmware module 148 into BMC module area 144.

[0063] At block 240, a hash (or checksum) for the component firmware module 148 is calculated and a hash (or checksum) for the BMC image 140 (which now includes the component firmware module 148) is calculated.

[0064] At block 245, a hash for the BMC image 140 may be stored in a hash table in order to update the hash table each time the BMC image 140 is updated upon addition or shadowing of a new component firmware module 148. The method then returns to block 210, and blocks 215-245 are repeated as necessary.

[0065] Once there are no remaining BMC modules to load and a determination of block 220 is negative, the method proceeds to block 250. At block 250, the final hash table is published (e.g., transmitted or made available to an attestation agent (e.g., software) responsible for comparing the final BMC image hash in the hash table to a predetermined value for known configurations of system 100). Each possible BMC image corresponding to a possible configuration of system 100 will be determined ahead of time, and each configuration will have an associated hash value.

[0066] At block 255, the BMC runtime (e.g., the hash corresponding to the final BMC image 140 including all loaded component modules 148) is loaded. The BMC may have a set of checksums or hashes describing a bill of materials (BOM) or inventory for the computing system in which the BMC is disposed. The BMC runtime may be verified on board the BMC itself or may be verified off board (e.g., by an external controller such as a control plane). Additionally, the BMC runtime is signed with a private attestation key that belongs to the BMC and is kept protected.

[0067] At block 260, the attestation agent is loaded.

[0068] At block 265, the attestation agent challenges the hash table by comparing the final BMC image hash to one or more predetermined values corresponding to known configurations of system 100. If the hash table challenge succeeds (z.e., if the final BMC image hash matches one of the predetermined values), the server is powered up at block 270. If the hash table challenge fails (z.e., the final BMC image hash does not match one of the predetermined values), the failure is reported to a secondary controller or entity such as a control plane at block 275, and BMC 110 awaits instructions. The attestation agenthaving a public key associated with the BMC private attestation key will thereby be able to decrypt the signature and see the hashes to confirm the expected list of system components.

[0069] FIG. 1.3 illustrates an exemplary layout of components in a system 300 in accordance with the present technology. A system 300 may include BMC 310, which may correspond to or be analogous to BMC 110 in FIG. 1.1 and BMC 404 in FIG. 1.4, and which may include a BMC image that is the same as or analogous to BMC image 140. BMC 310 may be communicatively coupled with a plurality of GPUs (such as four GPUs as shown), GPUs 320a-d. Each GPU of GPUs 320a-d may have an identical design and therefore may be operable using a single component module corresponding to the particular design and model of GPU for GPUs 320a-d. System 300 may further include network controller 330, DPU 340, memory modules 350a-c, chipset 360, CPU sensors 362a-b, sensors 370a-c, and power controller 380. Each component may have a unique component module, or may share a component module with an identical component such as in the cases of GPU 320a-d and memory modules 350a-c. Each component may be communicatively coupled with BMC 310 through a particular communications protocol, such as inter-integrated circuit (I2C), system management bus (SMBus), platform environment control interface (PECI), serial, universal serial bus (USB), RS-232, serial peripheral interface (SPI), or any suitable communications protocol.

[0070] FIG. 1.4 depicts aspects of an immersion cooling system 400 for dissipating heat from one or more heat-generating components such as semiconductor die packages 405 via immersion cooling. Immersion cooling system 400 may include a BMC 404 analogous to BMC 110 and / or BMC 310. BMC 404 may include a BMC image including binary code for operating one or more elements of immersion cooling system 400.

[0071] Each package 405 can include one or more semiconductor dies that produce heat when the system is in operation. The immersion cooling system 400 in the illustrated example of FIG. 1.4 is a two-phase immersion cooling system, though the invention may also be implemented in a single-phase immersion cooling system. One or more semiconductor die packages 405 may be 3DIC stacks in accordance with the present technology. For example, one or more semiconductor die packages 405 may include alogic IC and at least one memory module bonded to the logic IC using a hybrid bond or micro-bump bond.

[0072] Immersion cooling systems may provide particular advantage to 3DIC stacks due to the lower surface area to volume ratio of a 3DIC stack compared to the individual components of the 3DIC stack (e.g., a bonded logic IC and memory module will have a lower surface area to volume ratio than the combined surface area to volume ratio of the physically separated logic IC and memory module) as well as the additional heat generated by state of the art logic ICs. This lower surface area to volume ratio means waste heat generated by the 3DIC stack may not be as efficiently dissipated and may require better cooling performance than air cooling can provide. Two-phase immersion cooling in particular can provide this additional heat removal required by 3DIC stacks.

[0073] Immersion cooling system 400 includes a container such as tank 420 filled, at least in part, with immersion cooling liquid 464. The immersion cooling system 400 can further include at least one chiller 480 that flows a heat-transfer fluid through at least one condenser coil 470 that is disposed in the tank 420 and headspace 408. Condenser coil 470 and chiller 480 may be part of a heat exchanger. The packages 405 can be mounted on one or more printed circuit boards (PCBs) 457 that are immersed, at least in part, in the immersion cooling liquid 464. Immersion-cooling system 400 may further include a filter 475 disposed adjacent to the tank 420.

[0074] Filter 475 may include a filtration media, a housing, and a pump configured to force immersion cooling liquid 464 through filter 475 to remove contaminants, particulates, or other impurities that may be added to immersion cooling liquid 464 during use. Filter 475 may be housed outside of tank 420 while being in fluidic communication with immersion cooling liquid 464 in tank 420. Alternatively, filter 475 may be submerged within immersion cooling liquid 464 inside of tank 420.

[0075] Immersion cooling liquid 464 may be a hydrocarbon, a fluoroketone, an oil, or a similar dielectric liquid that will act as an insulator while simultaneously transferring heat from package 405 more efficiently than air. An example of immersion cooling liquid 464 is Novec™ 649 produced by 3M™. An exemplary immersion cooling liquid 464 used in accordance with embodiments of the present invention may have a dielectric constant baseline value of about 1.8-2 at a frequency of about 1 kHz.

[0076] In an embodiment of the invention, immersion cooling liquid 464 may be considered unacceptably contaminated if the dielectric constant and / or dielectric loss tangent of immersion cooling fluid being used in an immersion cooling system 400 differs by a threshold amount as compared to unused or pure immersion cooling liquid 464. For example, immersion cooling liquid 464 may be considered unacceptably contaminated or degraded if the dielectric constant and / or dielectric loss tangent differs by a threshold of 10% or more as compared to unused or pure immersion cooling liquid 464. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be 20%, 15%, 5%, 3%, 1%, or any suitable threshold.

[0077] Contamination of the immersion cooling liquid 464 and resulting changes to dielectric constant and / or dielectric loss tangent may alter or negatively impact operation of components within immersion cooling liquid 464 including semiconductor die(s) 450. An altered dielectric constant and / or dielectric loss tangent may result in undesirable cross-talk between components on a PCB, additional noise or reduction in signal strength transmitted along exposed wires of a PCB or semiconductor die(s) 450 submerged in immersion fluid, and / or signal dissipation through the immersion cooling liquid 464. Signal loss may be severe enough that two elements may be effectively represented as being separated by an open circuit despite being physically connected. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be selected based on an observed or inferred effect on one or more submerged semiconductor die(s) 450. For example, an increase in PCIe bit error rate above an error rate baseline may be correlated with an increase in dielectric constant and / or dielectric loss tangent above a dielectric constant and / or dielectric loss tangent baseline. Accordingly, operation of semiconductor die(s) 450 may be throttled or suspended when a dielectric constant and / or dielectric loss tangent of immersion cooling liquid 464 exceeds a predetermined threshold.

[0078] Changes to dielectric constant and / or dielectric loss tangent may be caused by contaminants within immersion cooling liquid 464. In some cases, changes to dielectric constant and / or dielectric loss tangent may be reversed by filtering the contaminants from immersion cooling liquid 464. In some embodiments, upon detecting an increase in dielectric constant and / or dielectric loss tangent of immersion cooling liquid464, controller 402 may instruct filter 475 to increase filtration throughput or notify a user that an immersion cooling liquid 464 filtration media may need to be replaced. If a dielectric constant and / or dielectric loss tangent exceeds a predetermined threshold, controller 402 may throttle or shut down one or more semiconductor die(s) 450, generate a notification that immersion cooling liquid 464 should be replaced, trigger an alarm, etc.

[0079] The illustrated example of FIG. 1.4 is not intended to be to scale. The immersion cooling system 400 may house and provide immersion cooling liquid 464 to tens, hundreds, or even thousands of packages 405. In some cases, the immersion cooling system 400 can be small (e.g., the size of a floor unit air conditioner, approximately 1 meter high, 0.5 meter width, 0.5 meter depth or length). In some implementations, the immersion cooling system can be large (e.g., the size of a van or larger, approximately 2.5 meters high, 2.5 meters width, 4 meters depth or length).

[0080] The immersion cooling system 400 can also include a controller 402 (e.g., a microcontroller, programmable logic controller (PLC), microprocessor, field- programmable gate array, logic circuitry, memory, or some combination thereof) to manage system operation. Controller 402 can perform various system functions such as monitoring temperatures of system components, cooling fluid level, tank access, chiller operation, etc. The controller 402 can further issue commands to control system operation such as executing a start-up sequence, executing a shut-down sequence, assigning workloads among the packages, changing cooling fluid level, changing the temperature of the heat-transfer fluid circulated by the chiller 480, etc. In some implementations, controller 402 can include (or itself be) a baseboard management controller (BMC) 404. That is, the BMC 404 may monitor and control all aspects of system operation for the immersion cooling system 400 in addition to monitoring and controlling workloads of the semiconductor dies 450 in the packages 405 cooled by the system. The immersion cooling system 400 can also include a network interface controller (NIC 403) to allow the system to communicate over a network, such as a local area network or wide area network. The immersion cooling system 400 can further include a fluid sensor array 490 having a plurality of fluid sensors 410. Fluid sensors 410 may include one or more leak detection sensors at least partially submerged in immersion cooling liquid 464.

[0081] The semiconductor die(s) 450 and can be mounted on and attached to a printed circuit board (PCB) 455 (sometimes referred to as a substrate) in device package 405. The package 405 can be made commercially available as an off-the-shelf (OTS) product. The package 405 can be used for single-phase or two-phase immersion cooling of at least one semiconductor die 450, such as a microprocessor (e.g., a central processing unit (CPU) and / or graphics processing unit (GPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application- specific integrated circuit (ASIC), field-programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0082] In the two-phase immersion cooling system 400 of FIG. 1.4, heat flows from the semiconductor die 450 where it is generated into the heat spreader 452. The heat spreader 452 is in thermal contact with an immersion cooling liquid 464 that can flow over and extract heat from the heat spreader 452. The amount of heat delivered by the heat spreader 452 to the immersion cooling liquid 464 is enough to boil the immersion cooling liquid 464 that contacts the heat spreader 452 (creating bubbles 465 and potentially creating froth 467 when bubbles 465 reach the surface of immersion cooling liquid 464). The vapor 466 from the boiled immersion cooling liquid 464 can be cooled and condensed back to liquid droplets 468, for example, by the condenser coil 470. The heat-transfer fluid, such as chilled water, from the chiller 480 can be circulated through the condenser coil 470 to lower the temperature of the condenser coil 470 below the condensation point in the headspace 408 of the tank 420. As a result, vapor 466 condenses on exterior surfaces of the condenser coil 470 and liquid droplets 468 from the condensed vapor can drip and / or flow back to the immersion cooling liquid 464. Although a single condenser coil 470 is depicted in FIG. 1.4, there can be a plurality of condenser coils 470 in tank 420 to condense the vapor 466 into droplets. Some or all of the condenser coils 470 may or may not be located directly over the PCBs 457. Instead, the condenser coil(s) 470 can be located near one or more walls of the tank 420, such that the condenser coil(s) 470 are not directly over the PCBs 457 on which the packages 405 are mounted.

[0083] To improve thermal performance in two-phase immersion cooling system 400, the heat spreader 452 can include a boiling enhancement coating (BEC) on at least one surface. The BEC can be formed from copper or a copper alloy and can be porous, forexample, though BECs can take various forms. In some cases, the BEC is a micro porous copper coating having a thickness from approximately or exactly 50 microns to 500 microns thick (which may be produced by electroplating and / or etching). In some implementations, the BEC comprises a mesh copper layer bonded (e.g., via resistance heating) to at least an outer surface of the heat spreader 452. In some cases, the BEC is applied as particulates to at least one smooth surface of the heat spreader 452 and then subsequently sintered to adhere to one another and to the heat spreader 452. The BEC provides an improved surface area to contact the immersion cooling liquid 464 and can increase the heat transfer coefficient from the heat spreader 452 to the immersion cooling liquid 464 by up to a factor of 15 versus a smooth surface on the heat spreader 452. Accordingly, BECs can increase thermal conductivity to, and accelerate the boiling of, the immersion cooling liquid 464.

[0084] Further implementations of boiling enhancement coatings and enclosures are possible. Additional arrangements, applications, and methods of use of boiling enhancement coatings and enclosures, including with semiconductor dies and 3DIC stacks, are described in the below U.S. Patent Applications.

[0085] U.S. Patent Application No. 18 / 327,615, filed June 1, 2023 and entitled "Boiler Enhancement Coatings with Active Boiling Management,” discloses heat spreader and boiling enhancement enclosure architectures thermally and / or mechanically coupled to one or more semiconductor dies or logic ICs that may be used for passive and / or active management of immersion cooling fluid boiling, including through the use of valves to control pressure of boiling immersion cooling fluid within a boiling enhancement chamber, particularly in paragraphs

[0018] -

[0039] and FIGS. 3-5B. The entirety of U.S. Patent Application No. 18 / 327,615 is incorporated herein by reference.

[0086] U.S. Provisional Patent Application No. 63 / 500,167, filed May 4, 2023 and entitled “Direct to Chip Heat Spreader and Boiler Enhancement Coatings for Microelectronics,” discloses heat spreader and BECs thermally and / or mechanically coupled to one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0015] -

[0033] and FIGS. 2A-4. BEC form factors may include graphite heat spreader architectures, vapor chambers, heat pipes, copper plates, fins, and the like. BEC form factors may be thermally and / or mechanically coupled to the one or moresemiconductor dies, logic ICs, and / or 3DIC stacks through a thermally conductive epoxy, and may have varying dimensions relative to a surface to which the semiconductor dies and / or logic ICs are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 500,167 is incorporated herein by reference.

[0087] U.S. Patent Application No. 18 / 460,091, filed September 1, 2023 and entitled “Direct to Chip Application of Boiling Enhancement Coating,” discloses BECs and methods for applying BECs to semiconductor dies, logic ICs, and / or 3DIC stacks in accordance with the present technology. In particular, paragraphs

[0024] -

[0046] and FIGS. 2A-5 disclose embodiments of BEC layers, adhesives, solders, sintering, laser ablation, meshes, and other BECs and BEC application methods. The entirety of U.S. Patent Application No. 18 / 460,091 is incorporated herein by reference.

[0088] U.S. Provisional Patent Application No. 63 / 506,945, filed June 8, 2023 and entitled “Vapor- Shedding Structures for Boiler Plates in Two-Phase Immersion Cooling Systems,” discloses structures that may be thermally and / or mechanically coupled to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks to enable the shedding of immersion cooling vapors generated from the boiling of immersion cooling fluid during operation of the computing hardware. In particular, paragraphs

[0021] -

[0039] and FIGS. 3A-5 disclose vapor-shedding structures including varying porosities, constituent materials, and geometries relative to the computing hardware on which they are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 506,945 is incorporated herein by reference.

[0089] U.S. Provisional Application No. 63 / 513,828, filed July 14, 2023 and entitled “Grinding Apparatuses and Methods for Mechanically Modifying Surfaces of Processors to Promote Boiling of a Coolant Liquid,” discloses methods for creating boiling enhancement modifications to surfaces such as the surfaces of computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0036] -

[0095] and FIGS. 2A-8. For example, grooves, patterns, gouges, trenches, or other structures may be added to a surface or lid of a processor, semiconductor die, logic IC, 3DIC stack component, and / or BEC to encourage nucleation sites for bubbles of immersion cooling vapor to form during a cooling process, thus decreasing the thermal resistance between the processor, semiconductor die, logic IC, and / or 3DIC stackcomponent and the surrounding immersion cooling fluid. The entirety of U.S. Provisional Application No. 63 / 513,828 is incorporated herein by reference.

[0090] U.S. Provisional Patent Application No. 63 / 513,829, filed July 14, 2023 and entitled “Electrical Connector Having a Heater to Facilitate Boiling of a Coolant Liquid to Improve Signal Integrity in Immersion Cooling Environment,” discloses heaters for promoting boiling of immersion cooling fluid near electrical connectors such as connections between components of a 3DIC stack and enable improved impedances at those connectors, particularly in paragraphs

[0019] -

[0052] and FIGS. 1A-3B. The entirety of U.S. Provisional Patent Application No. 63 / 513,829 is incorporated herein by reference.

[0091] U.S. Provisional Patent Application No. 63 / 603,242, filed November 28, 2023 and entitled “Woven Boiler Enhancement Coatings,” provides additional examples of BECs including woven BECs with variable weave patterns, densities, attachment mechanisms, and materials (including copper and tungsten) that may be attached to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks in order to promote more efficient heat transfer and immersion cooling vapor nucleation, particularly in paragraphs

[0031] -

[0055] and FIGS. 3-7. The entirety of U.S. Provisional Patent Application No. 63 / 603,242 is incorporated herein by reference.CONCLUSION

[0092] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented byway of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0093] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0094] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0095] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0096] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0097] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0098] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a nonlimiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0099] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively,as set forth in the United States Patent Office Manual of Patent Examining Procedures,Section 2111.03.

[0100] Section 2: The present technology is directed toward a converged firmware binary that automatically detects a variety of configurations of a computing system, such as an immersion-cooled server or an air-cooled server, and properly configures the firmware binary for that specific configuration. This automatic detection and configuration may prevent the need for manual reconfiguration of a firmware binary if a server is reconfigured or parts are replaced, reducing repair or maintenance time by 50-75% or more, particularly in datacenters containing hundreds or thousands of such server configurations. A server configuration may have an associated shelf keeping unit ID (SKU ID) that indicates exactly which components are included in the configuration.

[0101] FIG. 2.1 illustrates an immersion-cooled system 2100 for computation in accordance with the present technology. System 2100 may be a server disposed within an immersion-cooled computing system, where some or all of the components of system 2100 are immersed in immersion cooling fluid. System 2100 may correspond to some components of system 2300 of FIG. 2.3.

[0102] System 2100 may include a baseboard management controller (BMC 2105) configured to manage, control the operation of, and monitor components of system 2100 and may function as the central management agent for a server or computing system. BMC 2105 may be responsible for and configured to manage debugging, fault handling, firmware updating for components, thermal and power management, telemetry, and other suitable functions. BMC 2105 may include at least one processor and at least one non- transitory computer-readable medium, the medium containing instructions configuring the processor to perform one or more functions outlined herein.

[0103] BMC 2105 may be communicatively coupled with one or more additional components through communications channels 2110, which may include one or more inter-integrated circuit channels (I2C channel 2111), platform environment control interface channels (PECI channel 2112), local area network / ethernet channels (FAN channel 2113), power management bus (PMbus) channels, system management bus (SMbus) channels, peripheral component interconnect express (PCIe) channels, compute express link (CXE) channels, serial (e.g., RS-2232) channels, universal serial bus (USB)channels, universal asynchronous receiver / transmitter (UART) channels, management component transport protocol (MCTP) channels, or any suitable communications channels.

[0104] BMC 2105 may utilize communications channels 2110 to scan for and detect components within system 2100. BMC 2105 may query, read, or otherwise communicate with some, any, or all components included in system 2100 and communicatively coupled to BMC 2105 and receive a response from those respective components in order to determine an SKU ID. Each component may include metadata identifying information about the component; for example, metadata for each component may include a data structure such as a vector or tuple. A tuple may include a vendor name, a device model, a device type, and an address location in the server (e.g., a communications address and / or a physical location. Each component may have an individual SKU ID, and components may be combined into a superset configuration including metadata of all possible devices and communications addresses. A superset configuration may have its own associated SKU ID.

[0105] System 2100 may utilize two-way communication between BMC 2105 and one or more components of system 2100. For example, upon determining an SKU ID associated with a particular configuration of system 2100, BMC 2105 may transmit the determined SKU ID to the one or more components of system 2100, which may in turn configure the firmware and / or operation of each of the one or more components. For example, BMC 2105 may transmit a determined SKU ID to one or more GPUs such as GPUs 2180a-h, which may indicate to the GPUs how much memory is available from memory modules 2130a-p and / or non-volatile memory express (NVME) storage 2132a-b. This may then determine one or more operational parameters (e.g., data transfer speeds, data storage availability, operational frequency, etc.) for GPUs 2180a-h.

[0106] BMC 2105 may include one or more processors and / or one or more memory modules. Examples of processors that may be included in BMC 2105 are a microprocessor (e.g., a central processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), data processing unit (DPU), and the like), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logiccontroller (PLC), or any suitable processing circuitry. Examples of one or more memory modules that may be included in BMC 2105 include a dynamic random access memory (DRAM) module, a dual in-line memory module (DIMM), a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a non-volatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable ROM (OTPROM), or the like), or any suitable type of memory module.

[0107] System 2100 may include a plurality of components. System 2100 may include processors 2120a-b, which may include CPU head nodes configured to manage one or more computational operations of system 2100 such as data storage, task management, GPU allocation, temperature control, computations, or the like. System 2100 may additionally include a platform controller hub (PCH 2122), which may control data paths, clocking (e.g., operating the system clock), input / output functions, and other operations of system 2100. In an embodiment, CPUs 2120a-b and PCH 2122 may be communicatively coupled to BMC 2105 through a PECI connection 2112.

[0108] System 2100 may include a plurality of memory modules 2130a-p (e.g., DIMMs) and NVME storage 2132a-b (e.g., solid-state drives). These may be used to store data used by CPUs 2120a-b and GPUs 2180a-h (e.g., results of calculations, artificial intelligence models, data one which one or more calculations is to be performed, or the like), firmware for one or more components of system 2100 including BMC 2105, CPUs 2120a-b. GPUs 2180a-h, or other components, status or operational information of one or more components of system 2100, and the like. Memory modules 2130a-p may be communicatively coupled to BMC 2105 through an I2C channel 2111. Additionally or alternatively, some or all of memory modules 2130a-p may be communicatively coupled to BMC 2105 through an SMbus connection.

[0109] System 2100 may include a plurality of sensors 2134a-h. Sensors 2134a-h may be configured to detect a variety of system parameters related to the operation of system 2100 including voltage, current, temperature, flow rate (e.g., air or liquid fluid flow rates), humidity, contaminant presence, dielectric constant, permittivity, permeability, or the like. BMC 2105 may use sensors 2134a-h to monitor a status of system 2100 or one or 1more components of system 2100 and control or alter operational parameters of system 2100 or the one or more components. For example, BMC 2105 may control the operation of a condenser coil by increasing a fluid flow rate inside the condenser coil in response to a temperature detected by one or more of sensors 2134a-h being higher than a threshold. Sensors 2134a-h may be communicatively coupled to BMC 2105 using an I2C channel 2111.

[0110] System 2100 may include a data processing unit (DPU) such as DPU 2140. DPU 2140 may be communicatively coupled to BMC 2105 using LAN channel 2113. DPU 2140 may be an NVIDIA BlueField 3™ BMC software DPU and may control one or more operations of system 2100 in tandem with BMC 2105. DPU 2140 may operate as a satellite BMC that is managed by BMC 2105. DPU 2140 may be embodied as a switch board BMC and / or a GPU BMC.

[0111] System 2100 may further include power distribution boards (PDBs 2150a- b) configured to manage a power distribution to all or some of system 2100. PDBs 2150a- b may operate to distribute power appropriately to the various components of system 2100. PDBs 2150a-b may be communicatively coupled to BMC 2105 using an I2C channel 2111.

[0112] System 2100 may include I2C multiplexer 2160 which may function to split an I2C channel 2111 into a plurality of I2C channels 2111, for example to communicatively couple a plurality of GPUs 2180a-h, PCIe switches 2170a-b, and various modules such as ceder modules 2175a-b. PCIe switches 2170a-b may control data routing and similar data flow paths from components such as GPUs 2180a-h. Ceder modules 2175a-b may provide an interconnection between GPUs 2180a-h. Each of GPUs 2180a-h, PCIe switches 2170a-b, and ceder modules 2175a-b may be communicatively coupled to BMC 2105 using an I2C channel 2111 routed through I2C multiplexer 2160.

[0113] BMC 2105 may transmit one or more queries to a plurality of components of system 2100 using one or more of communications channels 2110. In an embodiment, a query may be determined based on all of the possible components included in the superset configuration. BMC 2105 may receive responses from each component of system 2100 including a first response from a first component and a second response from a second component. In an embodiment, each of the first response and the secondresponse may include metadata for each device represented as a tuple including vendor name, device model, device type, and communications address in the server. BMC 2105 may record the metadata included in each response received by BMC 2105.

[0114] Once BMC 2105 has received responses from each component of system 2100, it will determine an identifier for the system, such as a system SKU ID representing the configuration of the system. The system SKU ID may be determined by calculating a checksum of each firmware binary for each component and using that checksum to determine a system SKU ID. BMC 2105 may then compare the system SKU to a predetermine superset configuration. A superset configuration may include SKU IDs for a plurality of predetermined configurations.

[0115] If BMC 2105 determines that a system configuration matches an SKU ID within the superset configuration, BMC 2105 may proceed with booting and operating system 2100. If BMC 2105 determines that a system SKU ID does not match any preexisting system SKU ID within the superset configuration, BMC 2105 may determine that the system should not be booted or operated, and may transmit a notification to an external controller. For example, the notification may indicate a request for maintenance, an error status, the associated system SKU ID, a location of the server, or any suitable information. The notification may additionally include a list of detected components.

[0116] Once system 2100 has been successfully booted, BMC 2105 may control a physical operation of system 2100 by configuring a firmware of one or more components of system 2100 including BMC 2105, the first component, the second component, or any one or more of the components of system 2100. For example, configuring the firmware may include altering a firmware binary of at least one of BMC 2105, the first component, or the second component by transmitting an indication of a valid system configuration and selecting a firmware binary version corresponding to the valid system configuration. The physical operation may include an operating temperature, a cooling operation (for example a flow of cooling fluid to transfer heat from system 2100), a power level, a voltage, a frequency, a current, a power, a period, a temperature, a resistance, a state of charge, a filtration rate, or the like.

[0117] Additionally or alternatively, BMC 2105 may alter an operational parameter of at least one component of system 2100 by transmitting the identifier to one,some, or all of the components of system 2100. BMC 2105 may broadcast the determined system SKU ID to each component that includes firmware such as any complex programmable logic devices (CPLDs) included in system 2100, satellite BMCs such as switch board BMCs, CPU head node BMCs, or GPU BMCs.

[0118] The operational parameter of the at least one component of system 2100 may include an operating temperature, a cooling operation (for example a flow of cooling fluid to transfer heat from system 2100), a power level, a voltage, a frequency, a current, a power, a period, a temperature, a resistance, a state of charge, a filtration rate, or the like. For example, an identifier may indicate that system 2100 is an immersion cooling server and therefore may indicate to GPUs 2180a-h that they may operate with a first power level, a first temperature, a first frequency, or the like. In an alternative embodiment, an identifier may indicate that a system 2100 is an air-cooled server, and that GPUs 2180a-h may operate with a second power level lower than the first power level, a second temperature lower than the first temperature, a second frequency lower than the first frequency, or the like.

[0119] An advantage of the present technology is that only the superset configuration need be updated to accommodate a valid system configuration. In an embodiment, updating the superset configuration may be as simple as adding a new SKU ID to a superset configuration file.

[0120] FIG. 2.2 illustrates a computing system 2200 in accordance with the present technology. Computing system 2200 may be an air-cooled computing system and may include a plurality of components that are analogous to system 2100 including BMC 2205, CPUs 2220a-b, PCH 2222, memory modules 2230a-h (e.g., DIMMs), NVME 2232a-f, sensors 2234a-h, DPU 2240, PDB 2250a-b, PCIe switches 2270a-d, and GPUs 2280a-p. Each of the foregoing components may be communicatively coupled to BMC 2205 using analogous communications channels to those of system 2100 including I2C channel 2211, PECI channel 2212, and LAN channel 2213.

[0121] Computing system 2200 may additionally include power supply units (PSUs 2255a-b) communicatively coupled to BMC 2205 via SMbus channel 2214, pulse width modulators (PWMs 2258a-b) and fans 2259a-h communicatively coupled to BMC2205 via I2C channel 2211, and switch board BMC 2260 communicatively coupled to BMC 2205 via LAN channel 2213.

[0122] BMC 2205 may perform each of the same functions as BMC 2105 described above in order to automatically determine a configuration of computing system 2200. For example, BMC 2205 may alter an operational parameter of at least one component of system 2200 by transmitting the identifier to one, some, or all of the components of system 2200. BMC 2205 may broadcast the determined system SKU ID to each component that includes firmware such as any complex programmable logic devices (CPLDs) included in system 2200, satellite BMCs such as switch board BMCs, CPU head node BMCs, or GPU BMCs.

[0123] FIG. 2.3 depicts aspects of an immersion cooling system 2300 for dissipating heat from one or more heat-generating components such as semiconductor die packages 2305 via immersion cooling. Each package 2305 can include one or more semiconductor dies that produce heat when the system is in operation. The immersion cooling system 2300 in the illustrated example of FIG. 2.3 is a two-phase immersion cooling system, though the invention may also be implemented in a single-phase immersion cooling system. Immersion cooling system 2300 may include one or more computing systems such as computing system 2100. In an embodiment, BMC 2304 may be analogous to BMC 2105 and / or BMC 2205 and perform some or all of the same functionality described above.

[0124] Immersion cooling system 2300 includes a container such as tank 2320 filled, at least in part, with immersion cooling liquid 2364. The immersion cooling system 2300 can further include at least one chiller 2380 that flows a heat-transfer fluid through at least one condenser coil 2370 that is disposed in the tank 2320 and headspace 2308. Condenser coil 2370 and chiller 2380 may be part of a heat exchanger. The packages 2305 can be mounted on one or more printed circuit boards (PCBs) 2357 that are immersed, at least in part, in the immersion cooling liquid 2364. Immersion-cooling system 2300 may further include a filter 2375 disposed adjacent to the tank 2320.

[0125] Filter 2375 may include a filtration media, a housing, and a pump configured to force immersion cooling liquid 2364 through filter 2375 to remove contaminants, particulates, or other impurities that may be added to immersion coolingliquid 2364 during use. Filter 2375 may be housed outside of tank 2320 while being in fluidic communication with immersion cooling liquid 2364 in tank 2320. Alternatively, filter 2375 may be submerged within immersion cooling liquid 2364 inside of tank 2320.

[0126] Immersion cooling liquid 2364 may be a hydrocarbon, a fluoroketone, an oil, or a similar dielectric liquid that will act as an insulator while simultaneously transferring heat from package 2305 more efficiently than air. An example of immersion cooling liquid 2364 is Novec™ 649 produced by 3M™. An exemplary immersion cooling liquid 2364 used in accordance with embodiments of the present invention may have a dielectric constant baseline value of about 1.8-2 at a frequency of about 1 kHz.

[0127] In an embodiment of the invention, immersion cooling liquid 2364 may be considered unacceptably contaminated if the dielectric constant and / or dielectric loss tangent of immersion cooling fluid being used in an immersion cooling system 2300 differs by a threshold amount as compared to unused or pure immersion cooling liquid 2364. For example, immersion cooling liquid 2364 may be considered unacceptably contaminated or degraded if the dielectric constant and / or dielectric loss tangent differs by a threshold of 10% or more as compared to unused or pure immersion cooling liquid 2364. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be 20%, 15%, 5%, 3%, 1%, or any suitable threshold.

[0128] Contamination of the immersion cooling liquid 2364 and resulting changes to dielectric constant and / or dielectric loss tangent may alter or negatively impact operation of components within immersion cooling liquid 2364 including semiconductor die(s) 2350. An altered dielectric constant and / or dielectric loss tangent may result in undesirable cross-talk between components on a PCB, additional noise or reduction in signal strength transmitted along exposed wires of a PCB or semiconductor die(s) 2350 submerged in immersion fluid, and / or signal dissipation through the immersion cooling liquid 2364. Signal loss may be severe enough that two elements may be effectively represented as being separated by an open circuit despite being physically connected. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be selected based on an observed or inferred effect on one or more submerged semiconductor die(s) 2350. For example, an increase in PCIe bit error rate above an error rate baseline may be correlated with an increase in dielectric constant and / or dielectric losstangent above a dielectric constant and / or dielectric loss tangent baseline. Accordingly, operation of semiconductor die(s) 2350 may be throttled or suspended when a dielectric constant and / or dielectric loss tangent of immersion cooling liquid 2364 exceeds a predetermined threshold.

[0129] Changes to dielectric constant and / or dielectric loss tangent may be caused by contaminants within immersion cooling liquid 2364. In some cases, changes to dielectric constant and / or dielectric loss tangent may be reversed by filtering the contaminants from immersion cooling liquid 2364. In some embodiments, upon detecting an increase in dielectric constant and / or dielectric loss tangent of immersion cooling liquid 2364, controller 2302 may instruct filter 2375 to increase filtration throughput or notify a user that an immersion cooling liquid 2364 filtration media may need to be replaced. If a dielectric constant and / or dielectric loss tangent exceeds a predetermined threshold, controller 2302 may throttle or shut down one or more semiconductor die(s) 2350, generate a notification that immersion cooling liquid 2364 should be replaced, trigger an alarm, etc.

[0130] The illustrated example of FIG. 2.3 is not intended to be to scale. The immersion cooling system 2300 may house and provide immersion cooling liquid 2364 to tens, hundreds, or even thousands of packages 2305. In some cases, the immersion cooling system 2300 can be small (e.g., the size of a floor unit air conditioner, approximately 1 meter high, 0.5 meter width, 0.5 meter depth or length). In some implementations, the immersion cooling system can be large (e.g., the size of a van or larger, approximately 2.5 meters high, 2.5 meters width, 4 meters depth or length).

[0131] The immersion cooling system 2300 can also include a controller 2302 (e.g., a microcontroller, programmable logic controller (PLC), microprocessor, field- programmable gate array, logic circuitry, memory, or some combination thereof) to manage system operation. Controller 2302 can perform various system functions such as monitoring temperatures of system components, cooling fluid level, tank access, chiller operation, etc. The controller 2302 can further issue commands to control system operation such as executing a start-up sequence, executing a shut-down sequence, assigning workloads among the packages, changing cooling fluid level, changing the temperature of the heat-transfer fluid circulated by the chiller 2380, etc. In someimplementations, controller 2302 can include (or itself be) a baseboard management controller (BMC) 2304. That is, the BMC 2304 may monitor and control all aspects of system operation for the immersion cooling system 2300 in addition to monitoring and controlling workloads of the semiconductor dies 2350 in the packages 2305 cooled by the system. The immersion cooling system 2300 can also include a network interface controller (NIC 2303) to allow the system to communicate over a network, such as a local area network or wide area network. The immersion cooling system 2300 can further include a fluid sensor array 2390 having a plurality of fluid sensors 2310. Fluid sensors 2310 may include one or more leak detection sensors at least partially submerged in immersion cooling liquid 2364.

[0132] The semiconductor die(s) 2350 and can be mounted on and attached to a printed circuit board (PCB) 2355 (sometimes referred to as a substrate) in device package 2305. The package 2305 can be made commercially available as an off-the-shelf (OTS) product. The package 2305 can be used for single-phase or two-phase immersion cooling of at least one semiconductor die 2350, such as a microprocessor (e.g., a central processing unit (CPU) and / or graphics processing unit (GPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field- programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0133] In the two-phase immersion cooling system 2300 of FIG. 2.3, heat flows from the semiconductor die 2350 where it is generated into the heat spreader 2352. The heat spreader 2352 is in thermal contact with an immersion cooling liquid 2364 that can flow over and extract heat from the heat spreader 2352. The amount of heat delivered by the heat spreader 2352 to the immersion cooling liquid 2364 is enough to boil the immersion cooling liquid 2364 that contacts the heat spreader 2352 (creating bubbles 2365 and potentially creating froth 2367 when bubbles 2365 reach the surface of immersion cooling liquid 2364). The vapor 2366 from the boiled immersion cooling liquid 2364 can be cooled and condensed back to liquid droplets 2368, for example, by the condenser coil 2370. The heat-transfer fluid, such as chilled water, from the chiller 2380 can be circulated through the condenser coil 2370 to lower the temperature of the condenser coil 2370 below the condensation point in the headspace 2308 of the tank 2320. As a result,vapor 2366 condenses on exterior surfaces of the condenser coil 2370 and liquid droplets 2368 from the condensed vapor can drip and / or flow back to the immersion cooling liquid 2364. Although a single condenser coil 2370 is depicted in FIG. 2.3, there can be a plurality of condenser coils 2370 in tank 2320 to condense the vapor 2366 into droplets. Some or all of the condenser coils 2370 may or may not be located directly over the PCBs 2357. Instead, the condenser coil(s) 2370 can be located near one or more walls of the tank 2320, such that the condenser coil(s) 2370 are not directly over the PCBs 2357 on which the packages 2305 are mounted.

[0134] To improve thermal performance in two-phase immersion cooling system 2300, the heat spreader 2352 can include a boiling enhancement coating (BEC) on at least one surface. The BEC can be formed from copper or a copper alloy and can be porous, for example, though BECs can take various forms. In some cases, the BEC is a micro porous copper coating having a thickness from approximately or exactly 50 microns to 500 microns thick (which may be produced by electroplating and / or etching). In some implementations, the BEC comprises a mesh copper layer bonded (e.g., via resistance heating) to at least an outer surface of the heat spreader 2352. In some cases, the BEC is applied as particulates to at least one smooth surface of the heat spreader 2352 and then subsequently sintered to adhere to one another and to the heat spreader 2352. The BEC provides an improved surface area to contact the immersion cooling liquid 2364 and can increase the heat transfer coefficient from the heat spreader 2352 to the immersion cooling liquid 2364 by up to a factor of 15 versus a smooth surface on the heat spreader 2352. Accordingly, BECs can increase thermal conductivity to, and accelerate the boiling of, the immersion cooling liquid 2364.

[0135] Further implementations of boiling enhancement coatings and enclosures are possible. Additional arrangements, applications, and methods of use of boiling enhancement coatings and enclosures, including with semiconductor dies and 3DIC stacks, are described in the below U.S. Patent Applications.

[0136] U.S. Patent Application No. 18 / 327,615, filed June 1, 2023 and entitled "Boiler Enhancement Coatings with Active Boiling Management,” discloses heat spreader and boiling enhancement enclosure architectures thermally and / or mechanically coupled to one or more semiconductor dies or logic ICs that may be used for passive and / or activemanagement of immersion cooling fluid boiling, including through the use of valves to control pressure of boiling immersion cooling fluid within a boiling enhancement chamber, particularly in paragraphs

[0018] -

[0039] and FIGS. 3-5B. The entirety of U.S. Patent Application No. 18 / 327,615 is incorporated herein by reference.

[0137] U.S. Provisional Patent Application No. 63 / 500,167, filed May 4, 2023 and entitled “Direct to Chip Heat Spreader and Boiler Enhancement Coatings for Microelectronics,” discloses heat spreader and BECs thermally and / or mechanically coupled to one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0015] -

[0033] and FIGS. 2A-4. BEC form factors may include graphite heat spreader architectures, vapor chambers, heat pipes, copper plates, fins, and the like. BEC form factors may be thermally and / or mechanically coupled to the one or more semiconductor dies, logic ICs, and / or 3DIC stacks through a thermally conductive epoxy, and may have varying dimensions relative to a surface to which the semiconductor dies and / or logic ICs are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 500,167 is incorporated herein by reference.

[0138] U.S. Patent Application No. 18 / 460,091, filed September 1, 2023 and entitled “Direct to Chip Application of Boiling Enhancement Coating,” discloses BECs and methods for applying BECs to semiconductor dies, logic ICs, and / or 3DIC stacks in accordance with the present technology. In particular, paragraphs

[0024] -

[0046] and FIGS. 2A-5 disclose embodiments of BEC layers, adhesives, solders, sintering, laser ablation, meshes, and other BECs and BEC application methods. The entirety of U.S. Patent Application No. 18 / 460,091 is incorporated herein by reference.

[0139] U.S. Provisional Patent Application No. 63 / 506,945, filed June 8, 2023 and entitled “Vapor- Shedding Structures for Boiler Plates in Two-Phase Immersion Cooling Systems,” discloses structures that may be thermally and / or mechanically coupled to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks to enable the shedding of immersion cooling vapors generated from the boiling of immersion cooling fluid during operation of the computing hardware. In particular, paragraphs

[0021] -

[0039] and FIGS. 3A-5 disclose vapor-shedding structures including varying porosities, constituent materials, and geometries relative to the computinghardware on which they are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 506,945 is incorporated herein by reference.

[0140] U.S. Provisional Application No. 63 / 513,828, filed July 14, 2023 and entitled “Grinding Apparatuses and Methods for Mechanically Modifying Surfaces of Processors to Promote Boiling of a Coolant Liquid,” discloses methods for creating boiling enhancement modifications to surfaces such as the surfaces of computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0036] -

[0095] and FIGS. 2A-8. For example, grooves, patterns, gouges, trenches, or other structures may be added to a surface or lid of a processor, semiconductor die, logic IC, 3DIC stack component, and / or BEC to encourage nucleation sites for bubbles of immersion cooling vapor to form during a cooling process, thus decreasing the thermal resistance between the processor, semiconductor die, logic IC, and / or 3DIC stack component and the surrounding immersion cooling fluid. The entirety of U.S. Provisional Application No. 63 / 513,828 is incorporated herein by reference.

[0141] U.S. Provisional Patent Application No. 63 / 513,829, filed July 14, 2023 and entitled “Electrical Connector Having a Heater to Facilitate Boiling of a Coolant Liquid to Improve Signal Integrity in Immersion Cooling Environment,” discloses heaters for promoting boiling of immersion cooling fluid near electrical connectors such as connections between components of a 3DIC stack and enable improved impedances at those connectors, particularly in paragraphs

[0019] -

[0052] and FIGS. 1A-3B. The entirety of U.S. Provisional Patent Application No. 63 / 513,829 is incorporated herein by reference.

[0142] U.S. Provisional Patent Application No. 63 / 603,242, filed November 28, 2023 and entitled “Woven Boiler Enhancement Coatings,” provides additional examples of BECs including woven BECs with variable weave patterns, densities, attachment mechanisms, and materials (including copper and tungsten) that may be attached to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks in order to promote more efficient heat transfer and immersion cooling vapor nucleation, particularly in paragraphs

[0031] -

[0055] and FIGS. 3-7. The entirety of U.S. Provisional Patent Application No. 63 / 603,242 is incorporated herein by reference.CONCLUSION

[0143] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0144] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0145] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0146] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0147] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0148] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0149] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elementsspecifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a nonlimiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0150] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A non-transitory computer-readable medium containing instructions thereon, the instructions configuring a processor to: send a query using one or more communications channels communicatively coupled to the processor; receive a response from a first component, the response from the first component comprising data identifying the first component; based on the data identifying the first component, add a first code module to binary code for a baseboard management controller (BMC), the BMC comprising the processor and the first code module representing instructions for operation of the first component; calculate a checksum of the binary code; compare the checksum of the binary code to a value determined prior to adding the first code module to the binary code; and in response to the checksum matching the value, load the binary code by the processor and operating the first component using the binary code.

2. The medium of claim 1, wherein the first component comprises at least one of a graphics processing unit (GPU), a central processing unit (CPU), a network interface controller (NIC), a memory module, a data processing unit (DPU), a tensor processing unit (TPU), an artificial intelligence (Al) accelerator, a chipset, an integrated circuit, a sensor, or a power controller.

3. A method for controlling a computing system comprising a processor and at least a first component, the method comprising: sending a query using one or more communications channels communicatively coupled to the processor; receiving a response from a first component, the response from the first component comprising data identifying the first component;based on the data identifying the first component, adding a first code module to binary code for a baseboard management controller (BMC), the BMC comprising the processor and the first code module representing instructions for operation of the first component; calculating a checksum of the binary code; comparing the checksum of the binary code to a value determined prior to adding the first code module to the binary code; and in response to the checksum matching the value, loading the binary code by the processor and operating the first component using the binary code.

4. The method of claim 3, wherein the first component comprises at least one of a graphics processing unit (GPU), a central processing unit (CPU), a network interface controller (NIC), a memory module, a data processing unit (DPU), a tensor processing unit (TPU), an artificial intelligence (Al) accelerator, a chipset, an integrated circuit, a sensor, or a power controller.

5. A non-transitory computer-readable medium containing instructions thereon, the instructions configuring a processor to: transmit one or more queries to a plurality of components of a computing system using one or more communications channels communicatively coupled to the processor; receive a first response to the one or more queries from a first component of the plurality of components, the response from the first component comprising data identifying the first component; receive a second response to the one or more queries from a second component of the plurality of components, the response from the second component comprising data identifying the second component; determine an identifier for the computing system based on the first response and the second response; and control a physical operation of the computing system by configuring a firmware of at least one of the processor, the first component, or the second component.

6. The medium of claim 5, wherein configuring the firmware comprises altering a firmware binary of at least one of the processor, the first component, or the second component by transmitting an indication of a valid system configuration.

7. The medium of claim 5, wherein the physical operation comprises a cooling operation.

8. The medium of claim 7, wherein the cooling operation comprises a flow of fluid to transfer heat from the computing system.

9. The medium of claim 5, wherein the instructions further configure the processor to: alter an operational parameter of at least one of the first component or the second component by transmitting the identifier for the computing system to the first component and the second component.

10. The medium of claim 9, wherein the operational parameter comprises at least one of a voltage, a frequency, a current, a power, a period, a temperature, a fluid flow, a resistance, a state of charge, or a filtration rate.

11. The medium of claim 5, wherein the instructions further configure the processor to: compare the identifier for the computing system to a superset configuration identifier; determine if the identifier for the computing system matches the superset configuration; and in response to the identifier for the computing system not matching the superset configuration, transmitting a notification to an external controller indicating a request for maintenance.

12. A method for automatically configuring a computing system, the method comprising: transmitting, by a processor, one or more queries to a plurality of components of a computing system using one or more communications channels communicatively coupled to the processor; receiving, by the processor, a first response to the one or more queries from a first component of the plurality of components, the response from the first component comprising data identifying the first component; receiving, by the processor, a second response to the one or more queries from a second component of the plurality of components, the response from the second component comprising data identifying the second component; determining, by the processor, an identifier for the computing system based on the first response and the second response; and controlling, by the processor, a physical operation of the computing system by configuring a firmware of at least one of the processor, the first component, or the second component.

13. The method of claim 12, wherein configuring the firmware comprises altering a firmware binary of at least one of the processor, the first component, or the second component by transmitting an indication of a valid system configuration.

14. The method of claim 12, wherein the physical operation comprises a cooling operation.

15. The method of claim 14, wherein the cooling operation comprises a movement of fluid to transfer heat from the computing system.

16. The method of claim 12, further comprising: altering, by the processor, an operational parameter of at least one of the first component or the second component by transmitting the identifier for the computing system to the first component and the second component.

17. The method of claim 16, wherein the operational parameter comprises at least one of a voltage, a frequency, a current, a power, a period, a temperature, a fluid flow, a resistance, a state of charge, or a filtration rate.

18. The method of claim 12, further comprising: comparing, by the processor, the identifier for the computing system to a superset configuration identifier; determining, by the processor, if the identifier for the computing system matches the superset configuration; and in response to the identifier for the computing system not matching the superset configuration, transmitting, by the processor, a notification to an external controller indicating a request for maintenance.

Images