Nor flash memory, and array structure thereof and manufacturing method therefor

Abstract

Disclosed in the present invention is a NOR flash memory, which is a 2T NOR flash memory in which each memory cell comprises a storage transistor and a source line select transistor. A lower horizontal part of a control gate of the memory cell extends into a first-type doped well region, and has the top surface being lower than the bottom surface of a floating gate; a horizontal channel of the storage transistor is formed on the surface layer of the doped well region below the floating gate; a channel of the source line select transistor is formed vertically within the doped well region located on a lateral side of a vertical part and the lower horizontal part of the control gate; the channel of the storage transistor and the channel of the source line select transistor are arranged in a three-dimensional arrangement structure in which said two channels are perpendicular to each other. The size of the memory cells of the NOR flash memory is further reduced, and the storage density of the NOR flash memory is improved. Also disclosed in the present invention are an array structure of and a manufacturing method for the NOR flash memory.

Description

NOR flash memory and array structure and manufacturing method thereof Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and in particular to a NOR flash memory and an array structure and a manufacturing method thereof. Background Art

[0002] Floating gate memory is a type of non-volatile memory widely used in computer systems, such as flash memory, EEPROM, and EPROM. The improvement in the storage density of memory devices is closely related to advances in semiconductor manufacturing processes. As the feature sizes of semiconductor manufacturing processes continue to shrink, the storage density of memory devices continues to increase. Memory devices with two-dimensional structures (i.e., 2D memory devices) and three-dimensional structures (i.e., 3D memory devices) have been developed.

[0003] The storage unit of the floating gate memory mainly includes a floating gate and a control gate. The floating gate generates an induced voltage using the gate voltage received by the control gate to realize programming / erase operations.

[0004] Flash memory can retain stored data information even when power is off. It has the advantages of small size, low power consumption, and resistance to physical damage, and has therefore been widely used.

[0005] With the development of semiconductor manufacturing technology, the demand for NOR flash memory capacity has gradually increased. How to reduce the area of ​​NOR flash memory storage cells and increase the storage density of NOR flash memory is an issue that the industry needs to continuously improve.

[0006] In a 2T (2Transistor) NOR flash memory array, each memory cell includes a storage transistor and a source line select transistor. Specifically, the drain of the storage transistor is connected to the bit line (BL), while the source is connected to the drain of the source line select transistor. The source of the source line select transistor is connected to the common source line (CSL). The gates of multiple storage transistors in the same row are connected to the same word line (WL).

[0007] The structure of a memory cell of an existing 2T (2Transistor) NOR flash memory is shown in FIG1 . Its control gate 107 is in the shape of a step, consisting of an upper horizontal portion 1071, a vertical portion 1072, and a lower horizontal portion 1073 connected end to end. The upper horizontal portion 1071 is located above the floating gate 105, the vertical portion 1072 is located on one side of the floating gate 105, and the bottom surface of the lower horizontal portion 1073 is flush with the bottom surface of the floating gate 105.

[0008] The NOR flash memory cell shown in FIG1 includes a storage transistor and a source line select transistor. The storage transistor's channel L1 is formed on the surface of the doped well region 1011 below the floating gate 105. The source line select transistor's channel L2 is formed on the surface of the doped well region 1011 below the vertical portion 1072 and the lower horizontal portion 1073 of the control gate 107. The storage transistor channel and the source line select transistor channel are planar structures, making further miniaturization difficult. This makes it difficult to meet the demand for gradually shrinking the cell size of NOR flash memory in the pursuit of high-density storage. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a NOR flash memory and its array structure and manufacturing method, which are conducive to further reducing the storage unit size of the NOR flash memory and improving the storage density of the NOR flash memory.

[0010] In order to solve the above technical problems, the present invention provides a NOR flash memory, whose storage unit includes:

[0011] A first-type doped well region 1011 is formed on the upper portion of the semiconductor substrate 101;

[0012] A channel oxide layer 104 is formed on the top surface of the first-type doped well region 1011;

[0013] A floating gate 105 is formed on the top surface of the channel oxide layer 104;

[0014] The control gate 107 is a stepped structure consisting of an upper transverse portion 1071, a vertical portion 1072, and a lower transverse portion 1073 connected end to end. The upper transverse portion 1071 is located above the floating gate 105, the vertical portion 1072 is located laterally to the floating gate 105, and the bottom and lateral sides of the lower transverse portion 1073 are surrounded by the first-type doped well region 1011. The top surface of the lower transverse portion 1073 is lower than the bottom surface of the floating gate 105.

[0015] An IPO dielectric layer 106 is formed between the upper horizontal portion 1071 of the control gate 107 and the floating gate 105;

[0016] A control gate oxide layer 121 is formed between the vertical portion 1072 and the lower horizontal portion 1073 of the control gate 107, the floating gate 105, and the first-type doped well region 1011;

[0017] The heavily doped source region 120 is formed in the first-type doped well region 1011 and is located directly below the lower lateral portion 1073 ;

[0018] The heavily doped drain region 130 is formed on the surface of the first-type doped well region 1011 and is located on the other side of the floating gate 105 .

[0019] The lower end of the word line plunger WL is connected to the lower horizontal portion 1073;

[0020] The lower end of the bit line plug BL is connected to the drain heavily doped region 130;

[0021] The source power plug VSS is connected to the heavily doped source region 120 .

[0022] Preferably, sidewalls 108 are formed on the outer sides of the vertical portion 1072 , the upper horizontal portion 1071 , and the outer sides of the floating gate 105 .

[0023] Preferably, the first type doping is P-type doping, and the source heavily doped region and the drain heavily doped region are N-type doping; or,

[0024] The first type doping is N-type doping, and the source heavily doped region and the drain heavily doped region are P-type doping.

[0025] Preferably, the IPO dielectric layer 106 is an ONO dielectric stack.

[0026] Preferably, the IPO dielectric layer 106 is a hafnium dioxide HfO 2 -based thin film material and / or a silicon-doped hafnium dioxide Si:HfO 2 material.

[0027] Preferably, the control gate oxide layer 121 is made of silicon oxide.

[0028] Preferably, the thickness of the lower transverse portion 1073 and the upper transverse portion 1071 of the control gate 107 is greater than the thickness of the floating gate 105 .

[0029] Preferably, the top surface of the lower horizontal portion 1073 of the control gate 107 is flush with the bottom surface of the channel oxide layer 104 .

[0030] Preferably, the thickness of the lower horizontal portion 1073 of the control gate 107 is 30 nm to 200 nm.

[0031] To solve the above technical problems, the present invention provides an array structure of a NOR flash memory, which includes M rows and N columns of memory cells, Cij, Ci+1j, Cij+1, and Ci+1j+1 share the same bit line plunger BL, and Ci+1j+1, Ci+2j+1, Ci+1j+2, and Ci+2j+2 share the same bit line plunger BL;

[0032] M and N are both integers greater than 1, i is a natural number less than M-1, and j is a natural number less than N-1;

[0033] Cij is the storage cell at the i-th row and j-th column, Ci+1j is the storage cell at the i+1-th row and j-th column, Cij+1 is the storage cell at the i-th row and j+1-th column, Ci+1j+1 is the storage cell at the i+1-th row and j+1-th column, Ci+2j+1 is the storage cell at the i+2-th row and j+1-th column, Ci+1j+2 is the storage cell at the i+1-th row and j+2-th column, and Ci+2j+2 is the storage cell at the i+2-th row and j+2-th column.

[0034] In order to solve the above technical problems, the present invention provides a method for manufacturing the NOR flash memory, which comprises the following steps:

[0035] S1 shallow trench isolation fabrication of the semiconductor substrate 101 by a CMOS process;

[0036] S2. The semiconductor substrate 101 is subjected to photolithography and first-type ion implantation to form a first-type doped well region 1011 of a memory cell in the memory cell array region of the semiconductor substrate 101;

[0037] S3. Growing a memory cell channel oxide layer 104 on the semiconductor substrate 101;

[0038] S4. A floating gate polysilicon layer 105 is deposited on the channel oxide layer 104;

[0039] S5. IPO dielectric layer 106 is formed on the floating gate polysilicon 105;

[0040] S6. Photolithography and etching are performed to form a memory cell gate stack region and word line trenches 12 are formed on both sides thereof, the word line trenches 12 are probed under the first type doped well region 1011;

[0041] S7 performs a second type of ion implantation to form a heavily doped source region 120 in the first type doped well region 1011 at the bottom of the word line trench 12;

[0042] S8 growth control gate oxide layer 121;

[0043] S9. Deposition control gate 107;

[0044] S10. Photolithography and etching are performed to form a bit line trench 13 in the middle of the memory cell gate stack region, separating the memory cell gate stack region into a pair of memory cell gate stacks. The bottom of the bit line trench 13 is located on the top surface of the first type doped well region 1011.

[0045] S11 performs a second type of ion implantation to form a heavily doped drain region 130 in the first type doped well region 1011 at the bottom of the bit line trench 13;

[0046] S12. Perform subsequent processes to form word line plugs WL, bit line plugs BL, and source power plugs VSS.

[0047] Preferably, in step S12, a CMOS spacer process is first performed to form spacers 14 on the lateral outside of each memory cell gate stack, and then a metal silicide process and a contact hole process are performed to form word line plugs WL, bit line plugs BL and source power plugs VSS.

[0048] Preferably, in step S1, shallow trench isolation is fabricated using a CMOS process on the semiconductor substrate 101 to divide the substrate into a peripheral logic control area and a memory cell array area, and then well lithography and ion implantation of logic and control CMOS devices in the peripheral logic control area are completed before step S2 is performed.

[0049] The NOR flash memory of the present invention is a 2T (2Transistor) NOR flash memory in which each memory cell includes a storage transistor and a source line select transistor. The lower horizontal portion 1073 of the control gate 107 of the memory cell extends into the first-type doped well region 1011, with its top surface lower than the bottom surface of the floating gate 105. The lateral channel L1 of the storage transistor is formed on the surface of the doped well region 1011 below the floating gate 105. The channel L2 of the source line select transistor is formed vertically in the doped well region 1011 on one side of the vertical portion 1072 and the lower horizontal portion 1073 of the control gate 107. The storage transistor channel L1 and the source line select transistor channel L2 are arranged perpendicularly to each other in a three-dimensional structure, which facilitates further reducing the memory cell size of the NOR flash memory and improving the storage density of the NOR flash memory, thereby meeting the demand for gradually shrinking cell sizes in high-density NOR flash memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] FIG1 is a structure of a memory cell of an existing NOR flash;

[0052] FIG2 is a schematic diagram of forming an IPO dielectric layer in a method for manufacturing a NOR flash memory according to an embodiment of the present invention;

[0053] 3 is a schematic diagram of forming word line trenches according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0054] 4 is a schematic diagram of forming a heavily doped source region according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0055] 5 is a schematic diagram of a growth control gate oxide layer according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0056] 6 is a schematic diagram of depositing a control gate according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0057] 7 is a schematic diagram of forming a bit line trench according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0058] 8 is a schematic diagram of forming a heavily doped drain region according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0059] 9 is a schematic diagram of forming word line plugs, bit line plugs and source power plugs according to an embodiment of a method for manufacturing a NOR flash memory of the present invention;

[0060] FIG. 10 is a schematic diagram of an array structure of a NOR flash memory according to an embodiment of the present invention.

[0061] Description of reference numerals in the figures:

[0062] 101 semiconductor substrate; 1011 first-type doped well region; 104 channel oxide layer; 105 floating gate; 107 control gate; 1071 upper horizontal portion; 1072 vertical portion; 1073 lower horizontal portion; 106 IPO dielectric layer; 121 control gate oxide layer; 120 heavily doped source region; 130 heavily doped drain region; WL word line plug lower end connected to lower horizontal portion; BL bit line plug; VSS source power supply plug. DETAILED DESCRIPTION

[0063] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention. Example

[0064] As shown in Figure 9, the storage unit of NOR flash memory includes:

[0065] A first-type doped well region 1011 is formed on the upper portion of the semiconductor substrate 101;

[0066] A tunneling oxide layer 104 is formed on the top surface of the first-type doped well region 1011 ;

[0067] A floating gate 105 is formed on the top surface of the channel oxide layer 104;

[0068] The control gate 107 is a stepped structure consisting of an upper transverse portion 1071, a vertical portion 1072, and a lower transverse portion 1073 connected end to end. The upper transverse portion 1071 is located above the floating gate 105, the vertical portion 1072 is located laterally to the floating gate 105, and the bottom and lateral sides of the lower transverse portion 1073 are surrounded by the first-type doped well region 1011. The top surface of the lower transverse portion 1073 is lower than the bottom surface of the floating gate 105.

[0069] An IPO (inter-polysilicon oxide) dielectric layer 106 is formed between the upper horizontal portion 1071 of the control gate 107 and the floating gate 105;

[0070] A control gate oxide layer 121 is formed between the vertical portion 1072 and the lower horizontal portion 1073 of the control gate 107, the floating gate 105, and the first-type doped well region 1011;

[0071] The heavily doped source region 120 is formed in the first-type doped well region 1011 and is located directly below the lower lateral portion 1073 ;

[0072] The heavily doped drain region 130 is formed on the surface of the first-type doped well region 1011 and is located on the other side of the floating gate 105 .

[0073] The lower end of the word line plunger WL is connected to the lower horizontal portion 1073;

[0074] The lower end of the bit line plug BL is connected to the drain heavily doped region 130;

[0075] The source power plug VSS is connected to the heavily doped source region 120 .

[0076] The NOR flash memory of the first embodiment is a 2T (2Transistor) NOR flash memory in which each memory cell includes a storage transistor and a source line select transistor. The lower horizontal portion 1073 of the control gate 107 of the memory cell extends into the first-type doped well region 1011 and has a top surface lower than the bottom surface of the floating gate 105. The lateral channel L1 of the storage transistor is formed on the surface of the doped well region 1011 below the floating gate 105. The channel L2 of the source line select transistor is formed vertically in the doped well region 1011 on one side of the vertical portion 1072 and the lower horizontal portion 1073 of the control gate 107. The channel L1 of the storage transistor and the channel L2 of the source line select transistor are arranged perpendicular to each other in a three-dimensional structure. This facilitates further reducing the memory cell size of the NOR flash memory and improving the storage density of the NOR flash memory, thereby meeting the demand for gradually reducing the cell size of high-density NOR flash memories. Example

[0077] Based on the NOR flash memory of the first embodiment, spacers 108 are formed on the outer sides of the vertical portion 1072 , the upper horizontal portion 1071 , and the outer sides of the floating gate 105 .

[0078] Preferably, the first type doping is P-type doping, and the source heavily doped region 120 and the drain heavily doped region 130 are N-type doping; or,

[0079] The first type doping is N-type doping, and the heavily doped source region 120 and the heavily doped drain region 130 are P-type doping.

[0080] Preferably, the IPO (inter-polysilicon oxide) dielectric layer 106 is an ONO (Oxide-Nitride-Oxide) dielectric stack.

[0081] Preferably, the IPO (inter-polysilicon oxide) dielectric layer 106 is a hafnium dioxide (HfO2)-based thin film material and / or a silicon-doped hafnium dioxide (Si:HfO2) material. Both the HfO2-based thin film material and the silicon-doped hafnium dioxide (Si:HfO2) material are ferroelectric materials, and their CV curves exhibit a hysteresis effect as shown in FIG6 . By pre-treating the ferroelectric material with a certain negative voltage, the capacitance between the floating gate and the control gate becomes negative, making the ratio of this capacitance to the total capacitance of the NOR flash memory greater than 1. This reduces the gate voltage applied to the control gate, thereby lowering the operating voltage of the NOR flash memory and reducing energy consumption and costs.

[0082] Preferably, the control gate oxide layer 121 is made of silicon oxide.

[0083] Preferably, the thickness of the lower transverse portion 1073 and the upper transverse portion 1071 of the control gate 107 is greater than the thickness of the floating gate 105 .

[0084] Preferably, the top surface of the lower horizontal portion 1073 of the control gate 107 is flush with the bottom surface of the tunneling oxide 104 .

[0085] Preferably, the thickness of the lower horizontal portion 1073 of the control gate 107 is 30 nm to 200 nm. Example

[0086] The method for manufacturing the NOR flash memory of the first or second embodiment comprises the following steps:

[0087] S1. Shallow trench isolation (STI) is fabricated in a normal CMOS process on the semiconductor substrate 101;

[0088] S2. Performing photolithography and first-type ion implantation on the semiconductor substrate 101 to form a first-type doped well region 1011 of a memory cell in the memory cell array region of the semiconductor substrate 101;

[0089] S3. Growing a memory cell channel oxide layer (tunneling oxide growth) 104 on the semiconductor substrate 101;

[0090] S4. Depositing a floating gate polysilicon 105 on the channel oxide layer (tunneling oxide);

[0091] S5 IPO (inter-polysilicon oxide, polysilicon oxide layer between) dielectric layer 106 is formed on the floating gate 105 polysilicon, as shown in Figure 2;

[0092] S6. Photolithography and etching are performed to form a memory cell gate stack region and word line trenches 12 are formed on both sides thereof. The word line trenches 12 are probed under the first type doped well region 1011, as shown in Figure 3;

[0093] S7 performs a second type of ion implantation to form a heavily doped source region 120 in the first type doped well region 1011 at the bottom of the word line trench 12, as shown in Figure 4;

[0094] S8 growth control gate oxide layer 121, as shown in Figure 5;

[0095] S9. Deposition control gate 107, as shown in Figure 6;

[0096] S10. Photolithography and etching are performed to form a bit line trench 13 in the middle of the memory cell gate stack region, separating the memory cell gate stack region into a pair of memory cell gate stacks. The bottom of the bit line trench 13 is located on the top surface of the first-type doped well region 1011, as shown in FIG7 ;

[0097] S11 performs a second type of ion implantation to form a heavily doped drain region 130 in the first type doped well region 1011 at the bottom of the bit line trench 13, as shown in Figure 8;

[0098] S12. Perform subsequent processes to form word line plugs WL, bit line plugs BL, and source power plugs VSS, as shown in FIG9 .

[0099] Preferably, in step S12, a normal CMOS spacer process is first performed to form spacers 14 on the lateral outside of each memory cell gate stack, and then a metal silicide process (Salicide) and a contact hole process (Contact) are performed to form word line plugs WL, bit line plugs BL and source power plugs VSS.

[0100] Preferably, in step S1, shallow trench isolation (STI) is fabricated on the semiconductor substrate 101 using a normal CMOS process to divide the substrate into a peripheral logic control region and a memory cell array region. Then, well lithography and ion implantation of logic and control CMOS devices in the peripheral logic control region are completed before step S2 is performed. Example

[0101] The array structure of the NOR flash memory of the first or second embodiment, as shown in FIG10 , includes M rows and N columns of memory cells, Cij, Ci+1j, Cij+1, and Ci+1j+1 share the same bit line plug BL, and Ci+1j+1, Ci+2j+1, Ci+1j+2, and Ci+2j+2 share the same bit line plug BL;

[0102] M and N are both integers greater than 1, i is a natural number less than M-1, and j is a natural number less than N-1;

[0103] Cij is the storage cell at the i-th row and j-th column, Ci+1j is the storage cell at the i+1-th row and j-th column, Cij+1 is the storage cell at the i-th row and j+1-th column, Ci+1j+1 is the storage cell at the i+1-th row and j+1-th column, Ci+2j+1 is the storage cell at the i+2-th row and j+1-th column, Ci+1j+2 is the storage cell at the i+1-th row and j+2-th column, and Ci+2j+2 is the storage cell at the i+2-th row and j+2-th column.

[0104] In the array structure of the NOR flash memory of the fourth embodiment, four memory cells share one word line plunger WL, and four memory cells share one bit line plunger BL. This has a compact structure, can reduce the demand for word line plungers WL and bit line plungers BL, and is conducive to further reducing the size of the memory cells, which can meet the demand for gradually reducing the cell size of high-density memory devices.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A NOR flash memory, characterized in that: The storage unit includes: A first-type doped well region (1011) is formed on the upper portion of the semiconductor substrate (101); A channel oxide layer (104) is formed on the top surface of the first-type doped well region (1011); A floating gate (105) is formed on the top surface of the channel oxide layer (104); The control gate (107) is in the shape of a step formed by connecting an upper transverse portion (1071), a vertical portion (1072), and a lower transverse portion (1073) end to end in sequence, wherein the upper transverse portion (1071) is located above the floating gate (105), the vertical portion (1072) is located on a lateral side of the floating gate (105), the bottom surface and lateral side surfaces of the lower transverse portion (1073) are surrounded by a first-type doped well region (1011), and the top surface of the lower transverse portion (1073) is lower than the bottom surface of the floating gate (105); An IPO dielectric layer (106) is formed between the upper transverse portion (1071) of the control gate (107) and the floating gate (105); A control gate oxide layer (121) is formed between the vertical portion (1072) and the lower horizontal portion (1073) of the control gate (107), the floating gate (105), and the first-type doped well region (1011); The source heavily doped region (120) is formed in the first-type doped well region (1011) and is located directly below the lower transverse portion (1073); The drain heavily doped region (130) is formed on the surface of the first-type doped well region (1011) and is located on the other lateral side of the floating gate (105); The lower end of the word line plunger (WL) is connected to the lower horizontal portion (1073); The lower end of the bit line plug (BL) is connected to the drain heavily doped region (130); A source power supply plug (VSS) is connected to the source heavily doped region (120).

2. The NOR flash memory according to claim 1, wherein Side walls 108 are formed on the outside of the vertical portion (1072), the upper horizontal portion (1071), and the outside of the floating gate (105).

3. The NOR flash memory according to claim 1, wherein The first type doping is P-type doping, and the source heavily doped region and the drain heavily doped region are N-type doping; or, The first type doping is N-type doping, and the source heavily doped region and the drain heavily doped region are P-type doping.

4. The NOR flash memory according to claim 1, wherein The IPO dielectric layer (106) is an ONO dielectric stack.

5. The NOR flash memory according to claim 1, wherein: The IPO dielectric layer (106) is a hafnium dioxide HfO2-based thin film material and / or a silicon-doped hafnium dioxide Si:HfO2 material.

6. The NOR flash memory according to claim 1, wherein: The control gate oxide layer (121) is silicon oxide.

7. The NOR flash memory according to claim 1, wherein: The thickness of the lower transverse portion (1073) and the upper transverse portion (1071) of the control gate (107) is greater than the thickness of the floating gate (105).

8. The NOR flash memory according to claim 1, wherein: The top surface of the lower transverse portion (1073) of the control gate (107) is flush with the bottom surface of the channel oxide layer (104).

9. The NOR flash memory according to claim 1, wherein: The thickness of the lower transverse portion (1073) of the control gate (107) is 30nm to 200nm.

10. An array structure of a NOR flash memory according to any one of claims 1 to 9, characterized in that: It includes M rows and N columns of memory cells, Cij, Ci+1j, Cij+1, and Ci+1j+1 share the same bit line plug BL, and Ci+1j+1, Ci+2j+1, Ci+1j+2, and Ci+2j+2 share the same bit line plug BL; M and N are both integers greater than 1, i is a natural number less than M-1, and j is a natural number less than N-1; Cij is the storage cell at the i-th row and j-th column, Ci+1j is the storage cell at the i+1-th row and j-th column, Cij+1 is the storage cell at the i-th row and j+1-th column, Ci+1j+1 is the storage cell at the i+1-th row and j+1-th column, Ci+2j+1 is the storage cell at the i+2-th row and j+1-th column, Ci+1j+2 is the storage cell at the i+1-th row and j+2-th column, and Ci+2j+2 is the storage cell at the i+2-th row and j+2-th column.

11. A method for manufacturing a NOR flash memory according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1. Fabricating shallow trench isolation of a semiconductor substrate (101) using a CMOS process; S2. performing photolithography and first-type ion implantation on the semiconductor substrate (101) to form a memory cell first-type doped well region (1011) in a memory cell array region of the semiconductor substrate (101); S3. growing a memory cell channel oxide layer (104) on a semiconductor substrate (101); S4. depositing a floating gate (105) polysilicon on the channel oxide layer (104); S5. forming an IPO dielectric layer (106) on the floating gate (105) polysilicon; S6. Photolithography and etching to form a memory cell gate stack region and word line trenches 12 on both sides thereof, with the bottom of the word line trenches 12 probing into the first type doped well region (1011); S7. performing a second type ion implantation to form a heavily doped source region (120) in the first type doped well region (1011) at the bottom of the word line trench 12; S8. growing a control gate oxide layer (121); S9. Deposition control grid (107); S10. Photolithography and etching are performed to form a bit line trench 13 in the middle of the memory cell gate stack region in the horizontal direction, thereby separating the memory cell gate stack region into a pair of memory cell gate stacks, with the bottom of the bit line trench 13 being located on the top surface of the first type doped well region (1011); S11. performing a second type ion implantation to form a heavily doped drain region (130) in the first type doped well region (1011) at the bottom of the bit line trench 13; S12. Perform subsequent processes to form word line plugs WL, bit line plugs BL, and source power plugs VSS.

12. The method for manufacturing a NOR flash memory according to claim 11, wherein: In step S12, a CMOS spacer process is first performed to form spacers 14 on the lateral outside of each memory cell gate stack, and then a metal silicide process and a contact hole process are performed to form word line plugs (WL), bit line plugs (BL) and source power plugs (VSS).

13. The method for manufacturing a NOR flash memory according to claim 11, wherein: In step S1, shallow trench isolation is fabricated using a CMOS process on the semiconductor substrate (101), and the substrate is divided into a peripheral logic control area and a memory cell array area. Then, well lithography and ion implantation of logic and control CMOS devices in the peripheral logic control area are completed, and then step S2 is performed.

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