Memory

Abstract

Embodiments of the present application relate to the field of memories, and provide a memory, comprising a first phase decoder, a first storage section, and a second storage section. The first storage section and the second storage section are sequentially arranged in a first direction, and the first direction is a bit line extension direction; the first phase decoder is connected to the first storage section and outputs a plurality of first phase signals to the first storage section; and the first phase decoder also outputs the plurality of first phase signals to the second storage section. At least the area of the memory can be reduced.

Description

Memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 18, 2024, with application number 202410181906.1 and application name “Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a memory. Background Art

[0003] With the advancement of semiconductor technology, the requirements for memory integration are becoming increasingly higher, and the demand for smaller sizes is also growing. Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices or equipment. In DRAM and other memories, row and column decoders are required to decode the input address to obtain the address of the specific word line or bit line to be activated in the memory array based on the input address.

[0004] In practical applications, the row decoder in DRAM occupies a large area and consumes high power, and further area and power optimization is needed.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a memory that at least helps to solve the problems of current memories being too large in size and too high in power.

[0007] According to some embodiments of the present application, the embodiments of the present application provide a memory, including a first phase decoder, a first storage segment, and a second storage segment, wherein the first storage segment and the second storage segment are arranged sequentially along a first direction, and the first direction is a bit line extension direction; the first phase decoder is connected to the first storage segment and outputs multiple first phase signals to the first storage segment; the first phase decoder also outputs the multiple first phase signals to the second storage segment.

[0008] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0009] Embodiments of the present application provide a memory that reduces row decoder and memory area by sharing the same phase decoder across different memory segments, while also reducing power consumption associated with excessive device operation. Furthermore, by specifically routing and sharing the phase decoder across different memory segments, channel usage is reduced, achieving area reduction while also maintaining signal timing and drive performance, thereby improving operational reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are exemplarily described by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0011] FIG1 is a schematic diagram of a memory layout according to an embodiment of the present disclosure;

[0012] FIG2 is a schematic block diagram of another memory layout provided by an embodiment of the present disclosure;

[0013] FIG3 is a schematic block diagram of another memory layout provided by an embodiment of the present disclosure;

[0014] FIG4 is a circuit diagram of a sub-word line driver provided by an embodiment of the present disclosure;

[0015] FIG5 is a schematic block diagram of another memory layout provided by an embodiment of the present disclosure;

[0016] FIG6 is a schematic block diagram of another memory layout provided by an embodiment of the present disclosure;

[0017] FIG7 is a schematic diagram of a memory layout according to an embodiment of the present disclosure;

[0018] FIG8 is a schematic diagram of the layout of another memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. For example, the exemplary embodiments provided herein are considered to be capable of being combined with each other in whole or in part to achieve this. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0020] Throughout this specification, when any part is referred to as being "connected" to another part, this includes both the case where the part and the other part are "indirectly connected" to each other due to another part being interposed therebetween, and the case where the part and the other part are "directly connected" to each other. For example, it should be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element, or intervening elements can be present. Furthermore, "electrically connected" conceptually includes both physical connection and physical disconnection.

[0021] It is understood that when terms such as "first" and "second" are used to refer to an element, the element is not limited by them. They may be used only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0022] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0023] Taking DRAM as an example, it includes data / address input / output buffers, row decoders, column decoders, and a memory array. The data / address input / output buffers belong to the peripheral circuit area, while the row decoder, column decoder, and memory array belong to the array circuit area. The memory array is primarily composed of word lines, bit lines, and memory cells. Word lines in the memory array extend along the rows, while bit lines extend along the columns. The intersection of word lines and bit lines represents the memory cells of the memory array.

[0024] To write data into a memory cell or read data from a memory cell, the memory cell must first be addressed. The addressing process begins by inputting the corresponding row address signal and column address signal of the memory cell to be operated into the row / column address buffer. The row decoder (XDEC) then decodes and selects a specific row address line to activate the specific row address. Each row address line is connected to multiple column address lines and memory cells. In order to detect the weak activation signal on the column address line, an additional sense amplifier (SA) is required to amplify this signal. After the row is activated, the column address signal in the column address buffer is decoded by the column decoder (YDEC) to determine the column address, and is then connected to the input / output (IO) line by the corresponding sense amplifier. The memory cell is then activated and available for read and write operations, completing the addressing.

[0025] The row decoder includes a multi-stage row address decoder, a main word line driver (MWD), and a phase decoder (PhDec). It decodes and drives the input row address signal step by step to generate an activation signal for the word line corresponding to the row address. The phase decoder decodes and drives a portion of the input address signal (such as RA[2:0]) to generate a phase signal Fx, which is input to the sub word line driver (SWD) to select a specific word line.

[0026] Figure 1 shows a schematic diagram of a phase decoder-driven memory array. As shown in Figure 1, the memory array includes multiple memory segments (Array Sec), each of which includes multiple memory blocks (MAT). The row decoder XDEC includes multiple phase decoders (PhDec). Each memory segment is driven by two phase decoders (PhDec odd and PhDec even). The odd phase decoder generates eight phase signals (shown as / / X8) to the sub-wordline driver SWD on one side of the memory block MAT. The even phase decoder generates eight phase signals to the sub-wordline driver SWD on the other side of the memory block MAT (black dots in the figure indicate electrically connected nodes). The odd and even phase decoders generate odd and even phase signals, respectively, to the memory segments to drive the sub-wordline drivers on both sides of the memory block MAT. Referring to Figure 1, if a memory block is driven by eight phase signals, the sub-wordline drivers on both sides of the memory block each receive four phase signals and their four inverted phase signals. Therefore, there's a one-to-one correspondence between memory segments and phase decoders, with each memory segment requiring eight phase decoders and 16 phase signal lines. Excessive phase decoder circuits would consume significant row decoder area, leaving ample room for optimization. Furthermore, each memory block requires 16 lines for the phase signal, which complicates routing and limits spacing for other horizontal signal lines. With the increasing demand for higher integration, the phase decoder area and the resulting burden of phase signal lines are becoming increasingly significant.

[0027] Embodiments of the present application provide a memory device that reduces the area of ​​the phase decoder and row decoder by sharing the same phase decoder across different memory segments, while also reducing power consumption associated with operating too many devices. Furthermore, by specifically routing and sharing the phase decoder across different memory segments, channel usage is reduced, achieving area reduction while also maintaining signal timing and drive performance, thereby improving operational reliability.

[0028] FIG2 is a block diagram of a memory provided by an embodiment of the present disclosure. For ease of understanding, the block diagram only shows part of the circuit related to the present disclosure.

[0029] Referring to FIG. 2 , FIG. 2 shows a memory 10 including a first phase decoder 210 , a first memory segment 110 , and a second memory segment 120 . The first memory segment 110 and the second memory segment 120 are arranged sequentially along a first direction Y, where the first direction is the direction in which the bit lines extend. The first phase decoder 210 is connected to the first memory segment 110 and outputs a plurality of first phase signals Fx0-3 to the first memory segment 110 . The first phase decoder 210 also outputs these first phase signals Fx0-3 to the second memory segment 120 .

[0030] The memory includes a memory array 100 and a row decoder 200. The memory array includes multiple memory segments (sections) and a sense amplifier array (SA), arranged along a first direction Y. The memory segment includes multiple memory cells (not shown) arranged in an array, and a drive circuit (not shown) for driving the memory cells. The memory segment extends along a second direction X, which is perpendicular to the first direction Y and is the direction in which the word lines extend. FIG2 also shows a sense amplifier array 130, which is located between the multiple memory segments and is used to amplify signals on the bit lines when reading and writing data in the memory cells to assist in reading and writing. The figure only shows two memory segments 110, 120 and one sense amplifier array 130, but the number of memory segments can be set according to the capacity requirements of the memory. The memory array can include multiple memory segments arranged in sequence along the first direction Y, and multiple sense amplifier arrays can be provided, each sense amplifier array can be located between two memory segments, and the present disclosure is not limited to this.

[0031] The row decoder 200 may include a first phase decoder 210, a main word line driver MWD (not shown), a multi-stage decoding combinational logic circuit (not shown), etc. The row decoder is used to receive multiple row address signals, decode and drive the input row address signals step by step, and generate an activation signal to activate the word line corresponding to the row address.

[0032] The phase decoder circuit may include a decoding and driving circuit, for example, decoding some bits of the input address to obtain a corresponding phase signal Fx and its inverted signal FxB, which is then driven and output to the storage segment, and combined with the main word line signal MWL (not shown in Figure 2) output by the main word line driver to select and drive the corresponding word line. The embodiment of the present disclosure uses a complete phase decoder circuit to decode and drive the three-bit address signals RA0, RA1, and RA2 to obtain 8-bit phase signals Fx0-7 (8 signal lines are represented by / / X8 in the figure) and their inverted signals FxB0-7 as an example. However, the present disclosure does not limit this number. Since the phase signal and its inverted signal always appear in the form of a signal pair, in order to avoid redundancy, the signal pair will be referred to as the phase signal in some places below without affecting clarity.

[0033] Referring to Figure 2 , first phase decoder 210 is connected to first memory segment 110 and outputs a plurality of first phase signals Fx0-3 and their inverted signals FxB0-3 to first memory segment 110. First phase decoder 210 also outputs these first phase signals Fx0-3 and their inverted signals FxB0-3 to second memory segment 120. Consequently, the first phase signals generated by the first phase decoder are shared by both the first and second memory segments, saving the area of ​​the phase decoder and further reducing the area of ​​the row decoder and memory. Furthermore, because the first and second memory segments are adjacent to each other via the sense amplifier array, timing from the first phase decoder to the second memory segment is guaranteed.

[0034] Referring to Figure 2 , the first phase decoder 210 is located on one side of the first memory segment 110 along a second direction X. The second direction is the wordline extension direction. Specifically, the second direction X may be perpendicular to the first direction Y. Based on this arrangement, the first phase signals Fx0-3 and their inverted signals FxB0-3 generated by the first phase decoder can be transmitted to the entire first memory segment via the first phase signal line along the second direction X, thereby selecting and driving the wordlines for the entire first memory segment without requiring line switching or bending.

[0035] The first phase decoder 210 can be directly connected to the second storage segment and transmit the first phase signal Fx / FxB 0-3 to the second storage segment via a signal line. Alternatively, the first phase signal Fx / FxB 0-3 can be transmitted to the second storage segment via a signal line along the first direction Y within the row decoder and then transmitted to the second storage segment via a signal line along the second direction X. This disclosure is not limited to this. The first phase decoder 210 can also transmit the first phase signal Fx / FxB 0-3 to the second storage segment 120 directly via the first direction Y from the first storage segment 110 through the sense amplifier array 130 after transmitting the first phase signal Fx / FxB 0-3 for a certain distance via a partial length of the first phase signal line, as shown in FIG3 .

[0036] Figure 3 shows a memory 10 provided by an embodiment of the present disclosure, wherein the first storage segment 110 includes a first sub-word line driver 111, and the first sub-word line driver 111 is configured to receive the first sub-phase signals Fx0 and Fx2 among a plurality of first phase signals Fx0-3, and to drive the word line according to the first sub-phase signals Fx0 and Fx2; the second storage segment 120 includes a second sub-word line driver 121, and the second sub-word line driver 121 is configured to receive the first sub-phase signals Fx0 and Fx2, and to drive the word line according to the first sub-phase signals Fx0 and Fx2.

[0037] In this embodiment, there may be eight first phase signal lines, each transmitting Fx0-3 and FxB0-3. The first phase signal includes a first sub-phase signal and a second sub-phase signal. The first sub-phase signals may be Fx0 and Fx2, and the second sub-phase signals may be Fx1 and Fx3, respectively. However, the present disclosure is not limited thereto; the first sub-phase signals may also be Fx1, Fx3, or other combinations such as Fx0, Fx1, or Fx2, Fx3. The first phase signal lines transmitting the first sub-phase signals Fx0, Fx2, and their inverted signals FxB0 and FxB2 are electrically connected directly to the first sub-wordline driver 111 in the substrate direction via nodes and jumpers. Simultaneously, the first phase signal lines transmitting the first sub-phase signals Fx0, Fx2, and their inverted signals FxB0 and FxB2 are electrically connected to the second sub-wordline driver 121 via a shared signal line along a first direction Y. The substrate direction is perpendicular to the first and second directions.

[0038] FIG4 illustrates a sub-wordline driver circuit SWD according to an embodiment of the present disclosure. Referring to FIG4 , the sub-wordline driver circuit includes a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 has a first terminal that receives a phase signal Fx, and a second terminal that is connected to the first terminal of the second transistor M2. The control terminal of the first transistor M1 receives a main wordline signal MWL output by the main wordline driver MWD. ​​The second transistor M2 has a first terminal that is connected to the second terminal of the first transistor M1, a second terminal that is connected to ground potential or a negative potential, and a control terminal that is connected to the control terminal of the first transistor M1. The first terminal of the third transistor M3 is connected to the second terminal of the first transistor M1 and the first terminal of the second transistor M2, serving as the output terminal of the sub-wordline driver and outputting the sub-wordline signal SWL. The second terminal of the third transistor M3 is connected to ground potential or a negative potential, and the control terminal of the third transistor M3 receives an inverted signal FxB corresponding to the phase signal. In some embodiments, the first transistor may be a PMOS transistor, and the second and third transistors may be NMOS transistors.

[0039] The sub-word line driver in the embodiment of the present disclosure may adopt the sub-word line driver circuit shown in FIG. 4 , but the present disclosure is not limited thereto, and other types of sub-word line driver circuits may also be adopted.

[0040] FIG5 illustrates a memory device 10 according to an embodiment of the present disclosure. Referring to FIG5 , a first sense amplifier array 130 includes a plurality of first sense amplifiers 132 and a plurality of first sense amplifier driving circuits 131 and 133. The first sense amplifier driving circuits 131 and 133 are configured to drive the plurality of first sense amplifiers 132. The plurality of first sense amplifiers 132 and the plurality of first sense amplifier driving circuits 131 and 133 are alternately arranged along a second direction X, wherein the second direction X is perpendicular to the first direction Y. The first phase signal lines include a first sub-phase signal line and a second sub-phase signal line. A first shared signal line connects the first sub-phase signal lines and is configured to transmit the first sub-phase signals Fx0 and Fx2. The first shared signal line connects the first sub-wordline driver 111 and the second sub-wordline driver 121. The first shared signal line extends along the first direction Y, passes through the sense amplifier driving circuit 121, and its projection in the substrate direction falls within the first sub-wordline driver and the second sub-wordline driver. In FIG5 , the substrate direction is a direction perpendicular to the first direction Y and the second direction X.

[0041] With this arrangement, because both the first and second sub-wordline drivers receive the first sub-phase signal via the first sub-phase signal line in the second direction, and the second sub-wordline driver receives the first sub-phase signal via the first shared signal line in the first direction, the phase decoder circuit area is reduced, and the number of phase signal lines above the first memory segment is halved. Consequently, the number of lanes occupied by the phase signal is reduced, significantly reducing the routing complexity and size constraints of the lateral signal lines. Furthermore, because the first sub-phase signal is directly transmitted to the second sub-wordline driver via the first shared signal line, the routing utilizes the lanes above the sense amplifier driver circuit, eliminating the need to occupy the routing above the memory block. This frees up more lanes for routing other critical signals or for increasing the spacing between the phase signal lines and other critical signal lines. Furthermore, four phase signal lines and their inverted phase signal lines are evenly distributed above each sense amplifier driver circuit, improving timing uniformity while reducing routing complexity.

[0042] Although only one sense amplifier array is shown in the figure, the present disclosure is not limited thereto. The number of sense amplifier arrays, sense amplifiers, and sense amplifier driving circuits can be set accordingly according to the number of storage segments, storage blocks, and storage units.

[0043] In this embodiment, referring to FIG5 , the first storage segment and / or the second storage segment includes at least one storage block, such as the first storage block 112 and the second storage block 122. The first storage block 112 and the second storage block 122 can both be driven by sub-word line drivers located on both sides thereof along a second direction X, and two sub-word line drivers driving the same storage block receive different first phase signals. The second direction X is a word line extension direction. Specifically, the second direction X can be perpendicular to the first direction Y.

[0044] In this embodiment, referring to FIG5 , the first storage segment 110 further includes a first storage block 112 and a third sub-word line driver 113. The first sub-word line driver 111 and the third sub-word line driver 113 are located on different sides of the first storage block 112 along a second direction X, wherein the second direction X is a word line extension direction. Specifically, the second direction X may be perpendicular to the first direction Y. The third sub-word line driver 113 is configured to receive the second sub-phase signals Fx1 and Fx3 of the plurality of first phase signals Fx0-3, and generate a first phase signal Fx1 and a second phase signal Fx3 according to the second sub-phase signals Fx0-3. The signals Fx1 and Fx3 are used to drive the word lines in the first storage block 112; the second storage segment 120 also includes a second storage block 122 and a fourth sub-word line driver 123, and the second sub-word line driver 121 and the fourth sub-word line driver 123 are located on different sides of the second storage block 122 along the second direction X; the fourth sub-word line driver 123 is configured to receive the second sub-phase signals Fx1 and Fx3 among the multiple first phase signals Fx0-3, and drive the word lines in the second storage block 122 according to the second sub-phase signals Fx1 and Fx3.

[0045] The first phase decoder 210 generates multiple first phase signals Fx0-3. The first phase signals include first sub-phase signals Fx0 and Fx2 and second sub-phase signals Fx1 and Fx3. The first memory segment includes multiple memory blocks. For the first memory block 112, its word line is jointly driven by the first sub-word line driver 111 and the third sub-word line driver 113. Specifically, in this embodiment, the first sub-word line driver drives the even-numbered word lines of the first memory block, and the third sub-word line driver drives the odd-numbered word lines of the first memory block. Meanwhile, the second memory segment includes multiple memory blocks. For the second memory block 122, its word line is jointly driven by the second sub-word line driver 121 and the fourth sub-word line driver 123. Specifically, in this embodiment, the second sub-word line driver drives the even-numbered word lines of the second memory block, and the fourth sub-word line driver drives the odd-numbered word lines of the second memory block. The second sub-phase signal line transmitting the second sub-phase signal is transmitted from the third sub-word line driver to the fourth sub-word line driver 123 via the second sense amplifier driver circuit 133. With this arrangement, the word lines of odd addresses and the word lines of even addresses of the memory blocks of each memory segment are respectively distinguished by the sub-word line drivers on both sides along the second direction X, forming a symmetrical driving structure, which is beneficial to improving the driving capability of a single sub-word line driver for the word line, balancing the layout and line channels, and improving signal timing performance.

[0046] FIG6 shows a memory 10 according to an embodiment of the present disclosure. Referring to FIG6 , the memory further includes a second phase decoder 220 , which is located on one side of the second storage segment 120 along the second direction X. The second phase decoder 220 is connected to the second storage segment 210 and outputs a plurality of second phase signals Fx4-7 to the second storage segment.

[0047] The second storage segment receives a plurality of first phase signals Fx0-3 and their inverted signals output by the first phase decoder, and a plurality of second phase signals Fx4-7 and their inverted signals output by the second phase decoder. Specifically, in this embodiment, the second phase decoder 220 is located on one side of the second storage segment 120 along the second direction X. The second storage segment 120 includes at least one storage block 122, which is driven by sub-wordline drivers 121 and 123 located on either side of the second storage segment 120 along the second direction X. The sub-wordline drivers 121 and 123 each receive the first phase signals Fx0-3 and their inverted signals transmitted via the first shared signal line, and the second phase signals Fx4-7 and their inverted signals transmitted directly from the second phase decoder.

[0048] With this arrangement, the phase signal received by the second storage segment and the sub-word line driver therein is partially derived from the second phase decoder and partially derived from the signal generated by the first phase decoder transmitted via the first shared signal line. This saves the phase decoder area required to drive the second storage segment and avoids the use of long-distance horizontal lines to transmit these phase signals, thereby reducing the area of ​​the row decoder and memory, improving the quality of the phase signal, and halving the number of horizontal lines, greatly reducing the wiring difficulty and size limitations of the horizontal signal lines.

[0049] Continuing with FIG6 , the memory device of the present embodiment may further include a third memory segment 140 and a third phase decoder 230. The third memory segment 140 and the first memory segment 110 are located on opposite sides of the second memory segment 120 along the first direction Y. The third memory segment 140 is connected to the second phase decoder 220 and receives the plurality of second phase signals Fx4-7 and their inverted signals FxB4-7 output by the second phase decoder 220. The third memory segment 140 is connected to the third phase decoder 230 and receives the plurality of first phase signals Fx0-3 output by the third phase decoder 230. The third phase decoder is located on one side of the third memory segment along the second direction. The third memory segment 140 drives a word line using the plurality of first phase signals Fx0-3 output by the third phase decoder 230 and the plurality of second phase decoded signals Fx4-7 output by the second phase decoder 220. Specifically, the third storage segment 140 includes at least one storage block 142, which is driven by sub-word line drivers 141 and 143 located on both sides of the storage block along the second direction X. The sub-word line drivers 141 and 143 both receive the second phase signal Fx4-7 and its inverted signal transmitted by the shared signal line and the first phase signal Fx0-3 and its inverted signal directly transmitted by the third phase decoder 230.

[0050] The third storage segment 140 may be connected to the second phase decoder 220 as shown in FIG6 , or may be connected in other ways, such as directly connecting to the second phase decoder 220 and transmitting the second phase signal to the third storage segment via a signal line. Alternatively, the first phase signal Fx / FxB 0-3 may be transmitted to the second storage segment via a signal line along the first direction Y within the row decoder and then transmitted to the second storage segment via a signal line along the second direction X.

[0051] The first phase decoder 210 can be directly connected to the second storage segment and transmit the first phase signal Fx / FxB 0-3 to the second storage segment via a signal line. Alternatively, the first phase signal Fx / FxB 0-3 can be transmitted to the second storage segment via a signal line in the first direction Y within the row decoder and then transmitted to the second storage segment via a signal line in the second direction X. However, this disclosure is not limited to this. The first phase decoder 210 can also transmit the first phase signal Fx / FxB 0-3 to the second storage segment 120 directly via the first direction Y from the first storage segment 110 through the sense amplifier array 130 after transmitting the first phase signal Fx / FxB 0-3 for a certain distance via a partial length of the first phase signal line, as shown in FIG3 .

[0052] Although Figure 6 shows only three memory segments and three phase decoders, the present disclosure is not limited thereto. The memory may further include a fourth memory segment, a fifth memory segment, and so on, as well as a fourth phase decoder, a fifth phase decoder, and so on. The number of memory segments and phase decoders can be adjusted based on the memory capacity. In memories with different numbers of memory segments and phase decoders, different memory segments may receive the same phase-decoded signal. In other words, different memory segments may share phase decoders, thereby reducing the area of ​​the row decoder.

[0053] FIG7 shows a memory according to an embodiment of the present disclosure. Referring to FIG7 , the memory includes a plurality of memory segments section, each memory segment includes a plurality of memory blocks MAT, and in some embodiments, each memory segment includes 8 memory blocks. Each memory block corresponds to two sub-word line drivers that drive its word lines. The two sub-word line drivers are located on both sides of the memory block along the word line direction (the X direction in the figure) to drive the word lines in the memory block in an odd-even alternating manner. Specifically, the sub-word line driver on one side of the memory block can be used only to drive the word lines of odd addresses, and the sub-word line driver on the other side can be used only to drive the word lines of even addresses. Moreover, a sub-word line driver can be shared by the memory blocks on both sides thereof to drive the memory blocks on both sides thereof. Specifically, a sub-word line driver can drive the word lines of the odd addresses of the memory blocks on both sides thereof, or a sub-word line driver can drive the word lines of the even addresses of the memory blocks on both sides thereof.

[0054] Each memory block may have a capacity of 1 Kb, i.e., include 1,000 memory cells. However, the present disclosure is not limited thereto. In other embodiments, the capacity of each memory block may also be 512 bits, 2 Kb, etc. Each memory block is provided with a corresponding sense amplifier array for amplifying the read and write signals of the memory block.

[0055] To avoid redundancy, and provided that no technical solutions conflict, the phase decoder, memory segments, sub-wordline drivers, and other structures in FIG7 , as well as their connection relationships and arrangement, can be referenced to the relevant descriptions in FIG2-6 . For clarity, SWDs are only indicated in certain locations in FIG7 , but it can be understood that the sub-wordline drivers SWDs and memory blocks MAT are arranged in an array in FIG7 .

[0056] In other embodiments, a memory segment may further include an ECC (Error Checking and Correction) memory block. An ECC memory block refers to a memory cell within a memory block used to store ECC data. The capacity of an ECC memory block may be 0.5 times the capacity of a conventional memory block. The connection and positional relationship between the ECC memory block and the sub-wordline driver may be the same as those of a conventional memory block.

[0057] Referring to Figure 7, the memory segments and phase decoders are set in a one-to-one correspondence. Each memory segment can directly receive the phase decoding signal from the corresponding phase decoder and receive the shared phase decoding signal through the shared signal line. Specifically, for the first memory segment Array Sec0, it directly receives the first phase decoder PhDec / PhDecN through the first phase signal line. <4> - <7> The first phase signal Fx / FxB is output <4> - <7> Specifically, for a memory block in the first memory segment, it is driven by the sub-word line drivers located on both sides along the word line direction. The sub-word line driver on one side receives the even-numbered first phase signal and its inverted signal Fx / FxB. <4> 、Fx / FxB <6> The sub-word line driver on the other side receives the odd-numbered first phase signal and its inverted signal Fx / FxB <5> 、Fx / FxB <7> (Black dots represent connections in the figure.) Simultaneously, these phase signals and their inverted signals are transmitted via shared signal lines along the bit line direction (the Y direction in the figure) to the second memory segment, Array Sec1. These shared signal lines are transmitted from the sub-wordline drivers of the first memory segment, through the four lanes above the sense amplifier driver circuit SWC, to the sub-wordline drivers of the second memory segment.

[0058] The sub-word line drivers on both sides of a memory block of the second memory segment receive the even-numbered first phase signal and its inverted signal Fx / FxB transmitted from the shared signal line. <4> 、Fx / FxB <6> , and the second phase decoder PhDec / PhDecN <0> - <3> The second phase signal and its inverted phase signal Fx / FxB directly transmitted through the second phase signal line <0> - <3> The even part of Fx / FxB <0> 、Fx / FxB <2> Another sub-word line driver receives the odd first phase signal and its inverted signal Fx / FxB transmitted from the shared signal line <5> 、Fx / FxB <7> , and the second phase decoder PhDec / PhDecN <0> - <3> The second phase signal and its inverted phase signal Fx / FxB directly transmitted through the second phase signal line <0> - <3> The odd part of Fx / FxB <1> 、Fx / FxB <3> .

[0059] Based on the same principle, other memory segments can also share phase decoders in pairs. This reduces the phase decoder circuit area in the row decoder by nearly half, while doubling the number of horizontal decoding signal lines. Referring to Figure 7, a single memory segment only requires eight units of phase decoder area to generate four phase signals and their four inverted signals (eight units, shown as 8ea). Thus, a single memory segment only requires eight lines for its phase and inverted signals.

[0060] For the first storage segment Array Sec0 at the edge of multiple storage segments, it also needs to receive the second phase signal Fx / FxB <0> - <3> Also referring to FIG7 , the first memory segment Array Sec0 located at the edge also has another corresponding second phase decoder PhDec / PhDecN <0> - <3> (PhDec / PhDecN<3:0> in the figure), the second phase decoder PhDec / PhDecN <0> - <3> Generate multiple second phase signals Fx / FxB <0> - <3> And transmit these signals directly to the first memory segment Array Sec0 through the second phase signal line, so that each sub-word line driver of the first memory segment also fully receives the first phase signal Fx / FxB <4> - <7> and the second phase signal Fx / FxB <0> - <3> Thus, the memory segments located at the edge can also obtain the complete phase signal to drive all sub-wordline drivers and utilize all wordlines and memory cells.

[0061] For the last memory segment Array Sec71 located at the other edge of the multiple memory segments, since there are no other memory segments on the other side along the bit line direction, the phase signal received from the corresponding phase decoder does not need to be shared, and therefore, no shared signal line needs to be connected to its sub-word line driver.

[0062] In the embodiment of Figure 7 , the phase decoder corresponding to each memory segment except the first memory segment only requires eight phase signal decoding drive circuits (i.e., eight units, or 8ea). The first memory segment requires a 16ea phase decoder. Compared to requiring 16ea phase decoders for each memory segment, this significantly reduces the phase decoder circuit area required for the entire memory array.

[0063] 8 , for the first storage segment Array Sec0 at the edge of the plurality of storage segments, it also needs to receive the second phase signal Fx / FxB <0> - <3> To fully drive the sub-word line driver. In order to further reduce the area, the first memory segment is connected to the second phase decoder PhDec / PhDecN correspondingly connected to the second memory segment through a shared signal line. <0> - <3> Specifically, the first memory segment Array Sec0 directly receives the first phase decoder PhDec / PhDecN corresponding thereto via the first phase signal line along the word line direction (X direction in the figure). <4> - <7> The first phase signal Fx / FxB transmitted <4> - <7> At the same time, the first storage segment Array Sec0 is connected to the second storage segment Array Sec1 through a shared signal line along the bit line direction (in the Y direction in the figure) to receive the second phase decoder PhDec / PhDecN corresponding to it received by the second storage segment through the second phase signal line. <0> - <3> The generated plurality of second phase signals Fx / FxB <0> - <3> .

[0064] For other storage segments, the connection and phase signal receiving methods are the same as those in the embodiment of FIG7 , and will not be described in detail here.

[0065] Based on this setting, for the first storage segment located at the edge, only 8 phase signal lines and their inverted signal lines need to be set, and the second phase decoder PhDec / PhDecN set separately for the first storage segment is reduced. <0> - <3> , reducing the area to a greater extent.

[0066] Furthermore, since the phase signal line on the second memory segment Array Sec1 needs to drive the sub-word line drivers of the first to third memory segments, the load to be driven becomes heavier. Therefore, in other embodiments, the driving capability of the driver transistor in the second phase decoder corresponding to the second memory segment Array Sec1 can be increased. For example, the driving capability of the driver transistor in the second phase decoder can be increased by adjusting the width-to-length ratio of the driver transistor so that the width-to-length ratio of the driver transistor in the second phase decoder is larger than the width-to-length ratios of the driver transistors in other phase decoders.

[0067] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A memory (10), characterized in that: It includes a first phase decoder (220), a first storage segment (110), and a second storage segment (120), wherein: The first storage segment and the second storage segment are arranged in sequence along a first direction (Y), where the first direction is a bit line extension direction; The first phase decoder is connected to the first storage segment and outputs a plurality of first phase signals (Fx0-3) to the first storage segment; The first phase decoder further outputs the plurality of first phase signals to the second storage segment.

2. The memory according to claim 1, wherein The first phase decoder is located on one side of the first storage segment along the second direction (X); The second direction is a word line extension direction.

3. The memory according to claim 1, wherein: The first storage segment includes a first sub-word line driver (111), the first sub-word line driver being configured to receive a first sub-phase signal (Fx0, Fx2) among a plurality of first phase signals and perform word line driving according to the first sub-phase signal; The second storage segment includes a second sub-word line driver (121), which is configured to receive the first sub-phase signal and perform word line driving according to the first sub-phase signal.

4. The memory according to claim 3, wherein: A first shared signal line connects the first sub-word line driver and the second sub-word line driver for transmitting the first sub-phase signal. The first shared signal line extends along the first direction, and its projection in the substrate direction falls within the first sub-word line driver and the second sub-word line driver.

5. The memory according to claim 3 or 4, characterized in that: The first storage segment further includes a first storage block (112) and a third sub-word line driver (113), wherein the first sub-word line driver and the third sub-word line driver are located on different sides of the first storage block along a second direction (X), wherein the second direction is a word line extension direction; The third sub-word line driver is configured to receive a second sub-phase signal (Fx1, Fx3) among the plurality of first phase signals and drive a word line in the first memory block according to the second sub-phase signal; The second storage segment further includes a second storage block (122) and a fourth sub-word line driver (123), wherein the second sub-word line driver and the fourth sub-word line driver are located on different sides of the second storage block along the second direction (X); The fourth sub-word line driver is configured to receive the second sub-phase signal and drive the word lines in the second memory block according to the second sub-phase signal.

6. The memory according to any one of claims 1 to 5, characterized in that: The first storage segment or the second storage segment includes at least one storage block (112, 122), each storage block is driven by a sub-word line driver located on both sides thereof along a second direction (X), and two sub-word line drivers driving the same storage block receive different first phase signals; The second direction is a word line extension direction.

7. The memory according to any one of claims 1 to 6, characterized in that: The memory further comprises a second phase decoder (220), the second phase decoder being connected to the second storage segment via a second phase signal line and outputting a plurality of second phase signals to the second storage segment.

8. The memory according to claim 7, wherein: The second phase decoder is located on one side of the second storage segment along the second direction; The second storage segment includes at least one storage block (122), each of the storage blocks is driven by sub-word line drivers located on both sides thereof along the second direction, and each sub-word line driver receives the first phase signal and the second phase signal; The second direction is a word line extension direction.

9. The memory according to claim 7 or 8, characterized in that The memory further comprises a third storage segment (140) and a third phase decoder (230), wherein the third storage segment and the first storage segment are located on opposite sides of the second storage segment along a first direction; The third storage segment is connected to the second phase decoder and receives a plurality of second phase signals output by the second phase decoder; The third storage segment is connected to the third phase decoder and receives a plurality of first phase signals output by the third phase decoder.

10. The memory according to any one of claims 7 to 9, characterized in that: The memory includes a plurality of memory segments sequentially arranged along a first direction, and the first memory segment (Array Sec0) is located at an edge of the plurality of memory segments; The second phase decoder (PhDec / PhDecN <0> - <3> ) connects the first storage segment through the second phase signal line and the shared signal line along the first direction, and outputs a plurality of second phase signals (Fx / FxB <0> - <3> ) to the first storage segment.

11. The memory according to any one of claims 1 to 9, characterized in that: The memory includes a plurality of memory segments sequentially arranged along a first direction, and the first memory segment (Array Sec0) is located at an edge of the plurality of memory segments; The memory also has a second phase decoder (PhDec / PhDecN <0> - <3> ), the second phase decoder is located on one side of the first storage segment along a second direction, wherein the second direction is a word line extension direction; The second phase decoder outputs a plurality of second phase signals to the first storage segment through a second phase signal line along a second direction.

Images