Member for semiconductor manufacturing apparatus

Abstract

The present invention provides a member for a semiconductor manufacturing apparatus, wherein, in a ceramic substrate that includes a central part having a surface for mounting a wafer and an outer peripheral part having a surface for mounting a focus ring, dielectric breakdown risk in the outer peripheral part can be reduced. The member for a semiconductor manufacturing apparatus comprises a ceramic substrate including: a central part having a central part upper surface on which a wafer is mounted; and an outer peripheral part located at a position lower than the central part upper surface on the outer peripheral side of the central part upper surface and having an outer peripheral part upper surface on which the focus ring is mounted. The central part includes: a central part plug placement hole passing through the central part in the vertical direction; and a central part plug embedded in the central part plug placement hole. The outer peripheral part includes: an outer peripheral part plug placement hole passing through the outer peripheral part in the vertical direction; and an outer peripheral part plug embedded in the outer peripheral part plug placement hole and having a relative dielectric constant lower than that of the central part plug.

Description

Semiconductor manufacturing equipment components

[0001] The present invention relates to a member for a semiconductor manufacturing device.

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for holding wafers, controlling their temperature, transporting them, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract the wafer by electrostatic force, and some are also known to have the function of controlling the wafer temperature by flowing gas between the wafer mounting surface and the wafer to be attracted.

[0003] A known component for semiconductor manufacturing equipment includes a ceramic substrate having a wafer-mounting surface, a gas passage that passes through the ceramic substrate in the vertical direction, and a conductive base plate bonded to the underside of the ceramic substrate. During wafer processing, a cooling gas such as helium gas is introduced to the backside of the wafer through the gas passage.

[0004] In such semiconductor manufacturing equipment components, a large potential difference may occur between the wafer and the base plate, which can lead to discharge (dielectric breakdown) between the wafer and the base plate through the gas passage. For this reason, various techniques for placing a plug in the gas passage have been investigated to suppress discharge. The plug is often made of a porous material. Without the plug, for example, when an RF voltage is applied, ionizing gas molecules, resulting in electrons that accelerate and collide with other gas molecules, resulting in a glow discharge and eventually an arc discharge. However, with the plug, the electrons strike the plug before colliding with other gas molecules, suppressing discharge.

[0005] Furthermore, during wafer processing, a focus ring is typically installed on the outer periphery of the wafer to ensure uniform processing of the wafer. For this reason, some semiconductor manufacturing equipment components have a focus ring mounting surface on the outer periphery of the wafer mounting surface. Because the focus ring is used continuously, it is typically thicker than the wafer to maximize its lifespan. Furthermore, since the top surface of the focus ring is to be at the same height as the wafer, the focus ring mounting surface is typically positioned one step lower than the wafer mounting surface.

[0006] In recent years, there has been an increasing need for wafer processing using high-power plasma (e.g., deep etching). Because the focus ring is prone to reach high temperatures during wafer processing using high-power plasma, a semiconductor manufacturing equipment component has been proposed that includes a gas passage extending vertically through the outer periphery where the focus ring mounting surface is located (see FIG. 8 of Patent Document 1). This configuration allows a heat transfer gas to be supplied to the focus ring through the gas passage, thereby cooling the focus ring.

[0007] Patent No. 5357639

[0008] As described above, a technique for cooling a focus ring by providing a gas passage in the outer periphery where the focus ring mounting surface is located is known for semiconductor manufacturing equipment components. However, if the focus ring mounting surface is located one step lower than the wafer mounting surface, the thickness of ceramic substrate 20 will be thinner in the outer periphery where the focus ring mounting surface is located than in the center where the wafer mounting surface is located. Therefore, the vertical length of the gas passage, which corresponds to the thickness of the outer periphery of the ceramic substrate, will also be shorter in the outer periphery, and the electric field strength during wafer processing will be greater, resulting in a higher risk of dielectric breakdown in the outer periphery than in the center.

[0009] In view of the above circumstances, an object of one embodiment of the present invention is to provide a semiconductor manufacturing equipment component including a ceramic substrate having a central portion having a wafer mounting surface and an outer peripheral portion having a focus ring mounting surface, wherein the risk of dielectric breakdown in the outer peripheral portion is reduced.

[0010] The present inventors have conducted extensive research to solve the above problems and have created the present invention, which is exemplified below.

[0011] [Aspect 1] A ceramic substrate for semiconductor manufacturing equipment, comprising: a central portion having a central upper surface for mounting a wafer; and an outer peripheral portion located on the outer periphery of the central upper surface and lower than the central upper surface, the outer peripheral portion having an outer peripheral upper surface for mounting a focus ring, wherein the central portion has central plug placement holes vertically penetrating the central portion and central plugs embedded in the central plug placement holes, and the outer peripheral portion has outer peripheral plug placement holes vertically penetrating the outer peripheral portion and outer peripheral plugs embedded in the outer peripheral plug placement holes, the outer peripheral plugs having a lower dielectric constant than the central plugs. [Aspect 2] The semiconductor manufacturing equipment component according to Aspect 1, wherein the outer peripheral plugs have a dielectric constant of 0.7 times or less the dielectric constant of the central plug. [Aspect 3] The semiconductor manufacturing equipment component according to Aspect 1 or 2, wherein the main component of the central plug is the same as the main component of the ceramic substrate. [Aspect 4] The semiconductor manufacturing equipment component according to any one of Aspects 1 to 3, wherein the outer peripheral plugs contain silica. [Aspect 5] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 4, wherein the central plug and / or the peripheral plug are porous or dense having a flow path therethrough. [Aspect 6] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 5, wherein the thickness of the peripheral portion is 75% or less of the thickness of the central portion.

[0012] A semiconductor manufacturing equipment member according to one embodiment of the present invention can reduce the risk of dielectric breakdown at the outer periphery having the focus ring mounting surface, making the semiconductor manufacturing equipment member suitable for, for example, wafer processing (e.g., deep etching) using high-power plasma.

[0013] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments and is not to be construed as limiting the invention.

[0014] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when the semiconductor manufacturing equipment component's ceramic substrate is placed on a horizontal surface with the upper surface facing up, and do not represent absolute positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0015] 1 and 2, a semiconductor manufacturing equipment member 10 according to one embodiment of the present invention can be used when performing processes such as CVD and etching using plasma on a wafer W. The semiconductor manufacturing equipment member 10 includes a ceramic substrate 20 having a central portion 20a having a central upper surface 21 on which the wafer W is placed, and an outer peripheral portion 20b located on the outer periphery of and lower than the central upper surface 21, the outer peripheral portion 20b having an outer peripheral upper surface 27 on which a focus ring FR is placed.

[0016] The central portion 20a has a central plug arrangement hole 50a that passes through the central portion 20a in the vertical direction and a central plug 55a that is embedded in the central plug arrangement hole 50a. The peripheral portion 20b has a peripheral plug arrangement hole 50b that passes through the peripheral portion 20b in the vertical direction and a peripheral plug 55b that is embedded in the peripheral plug arrangement hole 50b and has a lower dielectric constant than the central plug 55a.

[0017] The semiconductor manufacturing equipment member 10 also includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded together via a bonding layer 40.

[0018] (1-2. Ceramic Substrate) The ceramic substrate 20 can be made of a ceramic material such as an alumina sintered body or an aluminum nitride sintered body.

[0019] The central portion 20a of the ceramic substrate 20 has, for example, a circular central upper surface 21 in a plan view (FIG. 2). The diameter of the central portion 20a can be typically 190 to 450 mm, and more typically 300 to 350 mm.

[0020] A wafer W can be placed on the central upper surface 21. In one embodiment, a plurality of protrusions 22 for placing the wafer W are provided over the entire surface of the central upper surface 21 of the ceramic substrate 20. The shape of the protrusions 22 is not limited, but may be, for example, a cylinder or a rectangular column. An annular seal band 25 may be formed along the outer edge of the central upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the seal band 25 and the upper end surfaces 21a of the plurality of protrusions 22. The seal band 25 and the plurality of protrusions 22 preferably have the same height. The heights of the seal band 25 and the protrusions 22 are, for example, 5 to 100 μm, and typically 10 to 30 μm. The portion of the central upper surface 21 of the ceramic substrate 20 on which the seal band 25 and the protrusions 22 are not provided is referred to as the reference surface 21b.

[0021] The thickness of the central portion 20a of the ceramic substrate 20 is not limited, but is preferably 1 mm or more from the viewpoint of increasing the fixing strength of the central plug 55a. Furthermore, from the viewpoint of reducing the heat transfer and manufacturing costs of the ceramic substrate 20, the thickness is preferably 5 mm or less, more preferably 3 mm or less, and even more preferably 2 mm or less. Therefore, the thickness of the central portion 20a is, for example, preferably 1 to 5 mm, more preferably 1 to 3 mm, and even more preferably 1 to 2 mm.

[0022] The outer peripheral portion 20b of the ceramic substrate 20 has, for example, an outer peripheral upper surface 27 that is annular in plan view and extends around the central portion 20a. The focus ring FR can be mounted on the outer peripheral upper surface 27, which is one step lower than the central upper surface 21. In one embodiment, annular seal bands 28 and 29 are formed along the inner and outer edges of the outer peripheral upper surface 27 of the ceramic substrate 20 to mount the focus ring FR. In this case, the focus ring FR may be supported by the upper end surfaces 27c and 27a of the seal bands 28 and 29. The height of the seal bands 28 and 29 is, for example, 5 to 100 μm, typically 10 to 30 μm. The portion of the outer peripheral upper surface 27 of the ceramic substrate 20 where the seal bands 28 and 29 are not provided is referred to as the reference surface 27b.

[0023] In one embodiment, the thickness of the outer peripheral portion 20b is 75% or less, preferably 60% or less, of the thickness of the central portion 20a. Although there is no particular lower limit for the thickness of the outer peripheral portion 20b relative to the thickness of the central portion 20a, the thickness of the outer peripheral portion 20b is typically 40 to 75% of the thickness of the central portion 20a. More typically, the thickness of the outer peripheral portion 20b is 50 to 60% of the thickness of the central portion 20a.

[0024] The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b may be flush with each other.

[0025] The central plug arrangement hole 50a and the peripheral plug arrangement holes 50b are holes that penetrate the ceramic substrate 20 in the vertical direction. The central plug arrangement hole 50a (peripheral plug arrangement hole 50b) is a gas passage that extends from the lower surface 23 of the ceramic substrate 20 to the reference surface 21b of the central upper surface 21 (reference surface 27b of the peripheral upper surface 27). The horizontal opening diameter (meaning the circular equivalent diameter when the cross section of the plug arrangement hole is not circular) of the central plug arrangement hole 50a (peripheral plug arrangement hole 50b) is not limited, but can be, for example, within a range of 1 to 5 mm, and typically within a range of 3 to 4 mm, at any height position.

[0026] The central plug positioning hole 50a (outer peripheral plug positioning hole 50b) may have the same opening diameter from top to bottom. Alternatively, the central plug positioning hole 50a (outer peripheral plug positioning hole 50b) may have a tapered inner circumferential surface 50a4 (inner circumferential surface 50b4) in which the area of ​​the upper opening 50a1 (upper opening 50b1) is larger than the area of ​​the lower opening 50a2 (lower opening 50b2). Therefore, the central plug positioning hole 50a (outer peripheral plug positioning hole 50b) may have a space shaped like a cylinder, a prism, a truncated cone, or a truncated pyramid, for example. Among these, a space shaped like a truncated cone or a truncated pyramid is preferred.

[0027] The tapered inner peripheral surface 50a4 (50b4) of the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b) makes it easier for the central plug 55a (outer peripheral plug 55b) to stop at a predetermined height position in the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b) when embedding the central plug 55a (outer peripheral plug 55b) in the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b). This results in the advantage that the central plug 55a (outer peripheral plug 55b) can be embedded in the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b) with high positioning accuracy. Furthermore, while the central plug 55a (outer peripheral plug 55b) is difficult to remove downward, it is relatively easy to remove upward. This results in the advantage that the central plug 55a (outer peripheral plug 55b) can be easily replaced. Furthermore, the increased creepage distance also results in the advantage of suppressing discharge.

[0028] A plurality of central plug placement holes 50a (four in FIG. 2 ) are provided. A plurality of peripheral plug placement holes 50b (eight in FIG. 2 ) are also provided. The locations of the central plug placement holes 50a and the peripheral plug placement holes 50b may be appropriately determined taking into consideration uniform gas supply to the entire rear surface of the wafer W and the entire rear surface of the focus ring FR. For example, the central plug placement holes 50a and the peripheral plug placement holes 50b are preferably provided at equal intervals in the circumferential direction. There are no particular limitations on the method for fixing the central plugs 55a (peripheral plugs 55b) to the central plug placement holes 50a (peripheral plug placement holes 50b). For example, the central plugs 55a (peripheral plugs 55b) may be fixed so that the outer peripheral surfaces 55a4 (outer peripheral surfaces 55b4) of the central plugs 55a (peripheral plugs 55b) directly fit into the inner peripheral surfaces 50a4 (inner peripheral surfaces 50b4) of the central plug placement holes 50a (peripheral plug placement holes 50b). As a direct fitting method, the central plug 55a (peripheral plug 55b) is press-fitted into the central plug arrangement hole 50a (peripheral plug arrangement hole 50b) to embed it.

[0029] The central plug 55a (outer peripheral plug 55b) preferably has an outer shape (e.g., cylindrical, prismatic, truncated conical, or truncated pyramidal) that is the same as that of the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b). In this case, to obtain the desired fixing strength, the horizontal cross-sectional diameter of the central plug 55a (outer peripheral plug 55b) at any height position is preferably slightly larger (e.g., about 5 to 20 μm in equivalent circle diameter) than the cross-sectional diameter of the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b) at the same height position. Another example of a direct fitting method is to thread a male thread provided on the outer peripheral surface 55a4 (outer peripheral surface 55b4) of the central plug 55a (outer peripheral plug 55b) into a female thread provided on the inner peripheral surface 50a4 (inner peripheral surface 50b4) of the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b). Furthermore, the outer peripheral surface 55a4 (outer peripheral surface 55b4) of the central plug 55a (outer peripheral plug 55b) may be bonded to the inner peripheral surface 50a4 (inner peripheral surface 50b4) of the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b) via an adhesive. However, a fixing method using an adhesive is prone to a decrease in the fixing strength of the central plug 55a (outer peripheral plug 55b) due to wear or deterioration of the adhesive, so a direct fitting method is preferable. Direct fitting of the two prevents gaps from forming between the central plug 55a (outer peripheral plug 55b) and the central plug arrangement hole 50a (outer peripheral plug arrangement hole 50b) due to deterioration caused by corrosion or erosion of the adhesive. This has the advantage of preventing discharge and plug detachment caused by adhesive deterioration.

[0030] The height position of the upper surface 55a1 (upper surface 55b1) of the central plug 55a (peripheral plug 55b) is not limited. Therefore, it may be the same height as the reference surface 21b (reference surface 27b) of the ceramic substrate 20, or may be a different height. However, it is preferable that the height position of the upper surface 55a1 (upper surface 55b1) of the central plug 55a (peripheral plug 55b) be the same height as the reference surface 21b (reference surface 27b). When the upper surface 55a1 (upper surface 55b1) of the central plug 55a (peripheral plug 55b) is made lower than the reference surface 21b (reference surface 27b), it is preferable to arrange it at a lower position within a range of 0.5 mm or less (preferably 0.2 mm or less, more preferably 0.1 mm or less) in order to suppress the occurrence of discharge. When the upper surface 55a1 (upper surface 55b1) of the central plug 55a (outer peripheral plug 55b) is made higher than the reference surface 21b (reference surface 27b), there are no particular restrictions as long as it is made lower than the upper end surfaces 21a (upper end surfaces 27c, 27a) of the protrusions 22 (seal bands 28 and 29) and the outflow of gas from the central plug 55a (outer peripheral plug 55b) is not hindered.

[0031] There is no particular limitation on the height position of the lower surface 55a2 (lower surface 55b2) of the central plug 55a (peripheral plug 55b), and the lower surface 55a2 (lower surface 55b2) may be the same height as or different from the lower surface 23 of the ceramic substrate 20. For example, the lower surface 55a2 (lower surface 55b2) of the central plug 55a (peripheral plug 55b) may protrude downward from the lower surface 23 of the ceramic substrate 20, or the lower surface 55a2 (lower surface 55b2) of the central plug 55a (peripheral plug 55b) may be positioned above the lower surface 23 of the ceramic substrate 20. However, in either case, it is preferable that at least a portion of the lower surface 55a2 (lower surface 55b2) be in contact with the bonding layer 40 from the viewpoint of suppressing discharge.

[0032] As can be seen from FIG. 1 , the outer peripheral upper surface 27, which constitutes the focus ring mounting surface, is positioned one step lower than the central upper surface 21, which constitutes the wafer mounting surface. Therefore, the thickness of the ceramic substrate 20 is thinner in the outer peripheral portion 20b than in the central portion 20a. Therefore, during wafer processing, a greater electric field strength is applied to the outer peripheral plugs 55b embedded in the outer peripheral plug placement holes 50b than to the central plugs 55a embedded in the central plug placement holes 50a. However, since the outer peripheral plugs 55b have a lower dielectric constant than the central plugs 55a, a voltage drop in the outer peripheral plugs 55b is accelerated. This suppresses a sudden voltage drop near the bottom surface of the outer peripheral plugs 55b, making it less likely for dielectric breakdown to occur. While the present invention is not intended to be limited by theory, such a mechanism can reduce the risk of dielectric breakdown in the outer peripheral portion of the focus ring.

[0033] The above mechanism will be explained in detail. The central plug 55a and the peripheral plug 55b can each be regarded as a pseudo-capacitor. In this case, the capacitance C1 of the central plug 55a can be roughly calculated by the following formula A. The capacitance C2 of the peripheral plug 55b can be roughly calculated by the following formula B. C1 = (ε0 × ε r1 × S1) / d1 ...Equation A (wherein ε0 is the dielectric constant of a vacuum, ε r1 represents the relative dielectric constant of the central plug 55a, S represents the area of ​​the upper surface 55a1 of the central plug 55a, and d represents the thickness of the central portion 20a≈the thickness of the central plug 55a.) C = (ε × ε r2 × S2) / d2 ...Equation B (where ε0 is the dielectric constant of a vacuum, ε r2 represents the relative dielectric constant of the outer plug 55b, S represents the area of ​​the upper surface 55b1 of the outer plug 55b, and d represents the thickness of the outer periphery 20b≈the thickness of the outer plug 55b.)

[0034] Therefore, for example, when the thickness of the outer circumferential portion 20b is half the thickness of the central portion 20a (i.e., d2 = 0.5 × d1) and the area of ​​the upper surface 55a1 of the central plug 55a is the same as the area of ​​the upper surface 55b1 of the outer circumferential plug 55b (S1 = S2), the relative dielectric constants of the outer circumferential plug 55b and the central plug 55a are set to the same (ε r1= ε r2 ), the capacitance of the outer plug 55b becomes twice as large as that of the central plug 55a, thereby reducing the voltage drop in the outer plug 55b. This makes it easier for a sudden voltage drop to occur near the lower surface 55b2 of the outer plug 55b, increasing the risk of dielectric breakdown.

[0035] On the other hand, when the thickness of the outer circumferential portion 20b is half the thickness of the central portion 20a (i.e., d2 = 0.5 × d1) and the area of ​​the upper surface 55a1 of the central plug 55a is the same as the area of ​​the upper surface 55b1 of the outer circumferential plug 55b (S1 = S2), the relative dielectric constant of the outer circumferential plug 55b is set to half that of the central plug 55a (ε r2 = 0.5 × ε r1 ), the electrostatic capacitance of the central plug 55a and the outer plug 55b can be made to be approximately the same. This makes the voltage drop in the outer plug 55b and the central plug 55a to be approximately the same, thereby suppressing a sudden voltage drop near the bottom surface of the outer plug 55b. In this way, ε r1 = ε r2 Compared to the case of (1), the risk of dielectric breakdown near the lower surface 55b2 of the outer peripheral plug 55b can be reduced.

[0036] From the viewpoint of enhancing the effect of reducing the risk of dielectric breakdown in the outer peripheral portion 20b of the ceramic substrate 20, the dielectric constant of the outer peripheral plug 55b is preferably 0.7 times or less, and more preferably 0.5 times or less, the dielectric constant of the central plug 55a. While no particular lower limit is set for the dielectric constant of the outer peripheral plug 55b, it also depends on the ratio of the thickness of the central portion 20a to that of the outer peripheral portion 55b. Considering the typical ratio of the thickness of the outer peripheral portion 20b to that of the central portion 20a and the ease of controlling the dielectric constant, the dielectric constant of the outer peripheral plug 55b is preferably 0.2 times or more and 0.7 times or less, and more preferably 0.2 times or more and 0.5 times or less, the dielectric constant of the central plug 55a.

[0037] In one embodiment, the dielectric constant of the central plug 55a is 7 or more, and the dielectric constant of the peripheral plugs 55b is 5 or less. In a preferred embodiment, the dielectric constant of the central plug 55a is 7 or more, and the dielectric constant of the peripheral plugs 55b is 4 or less. In a more preferred embodiment, the dielectric constant of the central plug 55a is 10 or more, and the dielectric constant of the peripheral plugs 55b is 4 or less. Illustratively, the dielectric constant of the central plug 55a is 7 to 12, and the dielectric constant of the peripheral plugs 55b is 2 to 5. Typically, the dielectric constant of the central plug 55a is 7 to 10, and the dielectric constant of the peripheral plugs 55b is 3 to 4.

[0038] In this specification, the dielectric constant of each of the plugs, such as the central plug 55a and the peripheral plug 55b, is measured using an impedance analyzer (e.g., an impedance analyzer 4291A manufactured by Keysight Technologies) in a room-temperature and room-humidity environment by removing the plug from the ceramic substrate and sandwiching the top and bottom surfaces of the plug between a pair of electrodes. As will be described later, the plug may be formed by stacking multiple plugs made of different materials, and even in this case, the value of the entire plug measured according to the above method is used as the dielectric constant of the plug.

[0039] Ceramics can be used as the material for forming the central plug 55 a and the outer peripheral plug 55 b, and can contain, for example, one or more selected from aluminum oxide, aluminum nitride, silicon carbide, silica, yttria, and zirconia, or can be composed of one or more selected from aluminum oxide, aluminum nitride, silica, yttria, and zirconia excluding impurities.

[0040] Among these, since center plug 55a is often exposed to corrosive gases, it is preferable that it be made of a material with high corrosion resistance. Therefore, center plug 55a preferably contains one or more materials selected from aluminum oxide, aluminum nitride, yttria, and zirconia, more preferably is made of one or two materials selected from aluminum oxide and aluminum nitride excluding impurities, and even more preferably is made of aluminum oxide excluding impurities.

[0041] Furthermore, for the reason of approximating the thermal expansion coefficients and maintaining the fixing strength of the plug, the main component of the central plug 55a is preferably the same as the main component of the ceramic substrate 20. Here, the main component refers to a component that accounts for 50% by mass or more of the target. For example, if the main component of the ceramic substrate 20 is aluminum oxide, it is preferable that the main component of the central plug 55a is also aluminum oxide.

[0042] On the other hand, since the peripheral plug 55b is isolated from corrosive gases by the focus ring, corrosion resistance is not a major consideration. Therefore, it is preferable to select a material that prioritizes a low dielectric constant. Therefore, the peripheral plug 55b preferably contains silica. Furthermore, in order to balance the need for a low dielectric constant and a thermal expansion coefficient that is closer to that of a ceramic substrate, it is more preferable for the peripheral plug 55b to contain silica and aluminum oxide. Furthermore, the peripheral plug 55b can be composed of silica excluding impurities, or it can be composed of silica and aluminum oxide excluding impurities. Examples of silica include quartz. Therefore, it is preferable that the peripheral plug 55b be composed of quartz and aluminum oxide excluding impurities, or quartz excluding impurities.

[0043] The central plug 55a and the peripheral plug 55b can also be constructed by stacking multiple plugs made of different materials in the vertical direction. In this case, the upper plugs can be made of ceramics with a higher volume resistivity than the lower plugs, and the lower plugs can be in contact with a base plate or an electrical conductor to lower the potential of the lower plugs and suppress discharge in the lower plugs, where the space is large and discharge is likely to occur. Specifically, the central plug 55a can have an upper plug made of aluminum oxide and a lower plug made of silicon carbide, and these plugs can be arranged in this order in the plug arrangement hole. Furthermore, the peripheral plug 55b can have an upper plug made of aluminum oxide and a lower plug made of quartz, and these plugs can be arranged in this order in the plug arrangement hole.

[0044] The central plug 55a and the peripheral plug 55b each have gas flow channels 55a3 and 55b3 penetrating therethrough. In one embodiment, the central plug 55a has a structure in which gas flowing in from a lower surface 55a2 of the central plug 55a flows through the gas flow channels 55a3 and flows out from an upper surface 55a1 of the central plug 55a. In another embodiment, the peripheral plug 55b has a structure in which gas flowing in from a lower surface 55b2 of the peripheral plug 55b flows through the gas flow channels 55b3 and flows out from an upper surface 55b1 of the peripheral plug 55b.

[0045] In one embodiment, the gas flow channel 55a3 may be formed in the central plug 55a by forming one or more gas flow channels vertically penetrating a dense body that does not allow gas flow. Similarly, the gas flow channel 55b3 may be formed in the peripheral plug 55b by forming one or more gas flow channels vertically penetrating a dense body that does not allow gas flow. The gas flow channel 55a3 (gas flow channel 55b3) may be configured as a straight line, a curve, or a combination of both. However, from the viewpoint of suppressing discharge, a shape in which the channel length is longer than the thickness (vertical length) of the central plug 55a (peripheral plug 55b), such as a bent shape such as a spiral or zigzag, is preferred. The central plug 55a (peripheral plug 55b) being a dense body means that the porosity of the central plug 55a (peripheral plug 55b) is 5% or less. In this case, the porosity of the central plug 55a (peripheral plug 55b) is preferably 1% or less, and more preferably 0.5% or less.

[0046] Therefore, in one embodiment of the present invention, the central plug 55a is made of dense alumina and has one or more gas flow channels 55a3 formed therein, and the peripheral plug 55b is made of dense quartz and has one or more gas flow channels 55b3 formed therein.

[0047] The porosity of the plugs such as the central plug 55a and the peripheral plug 55b is measured by the following method. The plug is cut so that a cross section passing through the central axis extending in the vertical direction of the plug is exposed. Next, the portion of the cross section excluding the gas flow passages is observed at a magnification of 3000 times using a scanning electron microscope (SEM) at a 2200 μm diameter. 2The area ratio of pores observed in the relevant portion is determined. Specifically, the SEM image is analyzed, and a threshold is determined by discriminant analysis (Otsu's binarization) from the brightness distribution of brightness data of pixels in the image. Then, based on the determined threshold, each pixel in the image is binarized into an object portion and a pore portion, and the area of ​​the object portion and the area of ​​the pore portion are calculated. Then, the ratio of the area of ​​the pore portion to the total area (the total area of ​​the object portion and the pore portion) is determined. Similar measurements are performed at five locations on the same plug, and the average value of the five locations is taken as the porosity of the plug.

[0048] Examples of methods for producing such plugs having gas flow paths in a dense body include a method of firing a compact formed using additive manufacturing techniques such as a 3D printer, and a method of firing a compact formed by mold casting using a master produced by the lost-wax method. Mold casting is disclosed, for example, in Japanese Patent No. 7,144,603.

[0049] Alternatively, the central plug 55a (outer peripheral plug 55b) may be made of a porous material, which serves as the gas flow path 55a3 (gas flow path 55b3). In this case, gas flowing in from the lower surface 55a2 (lower surface 55b2) of the central plug 55a (outer peripheral plug 55b) flows through the gas flow path 55a3 (gas flow path 55b3) formed by a large number of continuous pores and then flows out from the upper surface 55a1 (upper surface 55b1) of the central plug 55a (outer peripheral plug 55b). Because the gas flow path is formed by three-dimensionally (e.g., a three-dimensional network) continuous pores within the porous material, the effective flow path length within the gas flow path 55a3 (gas flow path 55b3) is longer than when the gas flow path 55a3 (gas flow path 55b3) is hollow, which makes it less likely for discharge to occur. In one embodiment, the central plug 55a (outer peripheral plug 55b) may be entirely porous. In another embodiment, the central plug 55a (outer plug 55b) can have a porous gas flow passage formed on the inner circumferential side of the dense outer circumferential surface 55a4 (outer circumferential surface 55b4). One or more gas flow passages can be further formed within the porous gas flow passage.

[0050] Therefore, the gas flow path 55a3 (gas flow path 55b3) may be hollow or porous. It is preferable that at least a portion of the gas flow path 55a3 (gas flow path 55b3) is porous. The gas flow path 55a3 (gas flow path 55b3) being hollow means that the porosity is 100%. The gas flow path 55a3 (gas flow path 55b3) being porous means that the porosity of the gas flow path 55a3 (gas flow path 55b3) is greater than 5% and less than 100%. A high porosity of the gas flow path 55a3 (gas flow path 55b3) is preferable to reduce the airflow resistance. Therefore, the porosity of the gas flow path 55a3 (gas flow path 55b3) is preferably 10% or more, and more preferably 40% or more. On the other hand, the porosity of the gas flow path 55a3 (gas flow path 55b3) is preferably 50% or less in order to increase the flow path length and ensure structural strength. Therefore, the porosity of the gas flow path 55a3 (gas flow path 55b3) is preferably, for example, 10% to 50%, and more preferably 40% to 50%. The porosity of the gas flow path 55a3 (gas flow path 55b3) is measured, for example, by mercury intrusion porosimetry (JIS R1655:2003).

[0051] The porosity of the central plug 55a (outer peripheral plug 55b) can be controlled, for example, by adjusting the content of the pore-forming material in the raw material composition before firing the ceramics that constitutes them. For example, in order to densify the outer peripheral surface 55a4 (outer peripheral surface 55b4) of the central plug 55a (outer peripheral plug 55b), the amount of the pore-forming material near the outer peripheral surface may be partially reduced or not used at all.

[0052] In this specification, when the gas flow paths 55a3 (gas flow paths 55b3) of the central plug 55a (outer plug 55b) are porous, the central plug 55a (outer plug 55b) is treated as a porous body. Therefore, when the flow paths penetrating the dense central plug 55a (outer plug 55b) are porous, the central plug 55a (outer plug 55b) can be recognized as a porous body, or as a dense body having flow paths penetrating the interior.

[0053] An electrode 26a is embedded in the central portion 20a of the ceramic substrate 20. The electrode 26a is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26a is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26a, the wafer W is attracted and fixed to the wafer mounting surface (specifically, the upper end surface 21c of the seal band 25 and the upper end surface 21a of the protrusion 22) by electrostatic attraction. When the DC voltage application is released, the wafer W is released from the wafer mounting surface. The electrode 26a may incorporate a heater electrode (resistive heating element) instead of or in addition to the electrostatic electrode. In this case, a heater power supply is connected to the heater electrode. The central portion 20a of the ceramic substrate 20 may incorporate one layer of electrodes 26a, or two or more layers of electrodes 26a spaced apart.

[0054] An electrode 26b may also be embedded in the outer peripheral portion 20b of the ceramic substrate 20. The electrode 26b is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26b is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26b, the focus ring FR is attracted and fixed to the focus ring mounting surface (specifically, the upper end surface 27c of the seal band 28 and the upper end surface 27a of the seal band 29) by electrostatic attraction. When the DC voltage application is stopped, the focus ring is released from the focus ring mounting surface. The electrode 26b may incorporate a heater electrode (resistive heating element) such as a ring heater instead of or in addition to the electrostatic electrode. In this case, a heater power supply is connected to the heater electrode. The outer peripheral portion 20b of the ceramic substrate 20 may incorporate one layer of electrodes 26b, or two or more layers of electrodes 26b spaced apart from one another.

[0055] (1-3. Base Plate) In one embodiment, the base plate 30 is a circular plate (a circular plate with a diameter equal to or larger than the outer periphery 20b of the ceramic substrate 20) with good electrical and thermal conductivity. Examples of materials for the base plate 30 include metal materials and composite materials of metal and ceramic. Metal materials include Al, Ti, Mo, W, and alloys thereof. Metal and ceramic composite materials include metal matrix composites (MMC) and ceramic matrix composites (CMC). Specific examples of such composite materials include materials containing Si, SiC, and Ti (also referred to as SiSiCTi), materials in which porous SiC is impregnated with Al and / or Si, and composite materials of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material of the ceramic substrate 20. For example, when the ceramic substrate 20 is made of alumina, the base plate is preferably made of SiSiCTi or AlSiC.

[0056] A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include a fluorine-based inert liquid. The refrigerant flow path 32 can be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port, respectively, of an external refrigerant device (not shown). The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0057] The base plate 30 may have a gas supply channel 60a for supplying gas to the gas flow channel 55a3 of the central plug 55a. The base plate 30 may also have a gas supply channel 60b for supplying gas to the gas flow channel 55b3 of the peripheral plug 55b. There are no particular limitations on the configuration of the gas supply channel 60a and the gas supply channel 60b. For example, as shown in FIG. 1 , the gas supply channel 60a may have a recess 61a provided on the upper surface 31 of the base plate 30 and a gas inlet 62a for supplying gas introduced from the lower surface 33 of the base plate 30 to the recess 61a. In this case, when the recess 61a is covered with the bonding layer 40, the bonding layer 40 serves as the upper wall of the gas supply channel 60a. The gas supply channel 60b may have a similar structure. The gas supply channel 60a and the gas supply channel 60b may be connected to each other. Alternatively, gases may flow independently through the gas supply channel 60a and the gas supply channel 60b.

[0058] As shown in FIG. 1 , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 is formed, for example, by thermal compression bonding (TCB). TCB is a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 can be formed, for example, by a metal bonding layer using an Al-Mg bonding material or an Al-Si-Mg bonding material. The bonding layer 40 may also be formed from solder or a metal brazing material. Furthermore, the bonding layer 40 may be formed from a resin adhesive layer instead of a metal bonding layer. Examples of materials for the resin adhesive layer include a silicone resin adhesive, an epoxy resin adhesive, and an acrylic resin adhesive. To improve the uniformity of the thickness of the resin adhesive layer, a spacer (not shown) may be disposed between the upper surface 31 of the base plate 30 and the lower surface 23 of the ceramic substrate 20 .

[0059] The bonding layer 40 has through-holes 42a that communicate with the gas flow passage 55a3 of the central plug 55a and with a gas supply passage 60a for supplying gas to the gas flow passage 55a3 of the central plug 55a. The bonding layer 40 also has through-holes 42b that communicate with the gas flow passage 55b3 of the outer plug 55b and with a gas supply passage 60b for supplying gas to the gas flow passage 55b3 of the outer plug 55b.

[0060] A plurality of through holes 42a (42b) may be provided for one central plug 55a (peripheral plug 55b). In this case, the plurality of through holes 42a (42b) are preferably provided point-symmetrically with respect to the central axis extending in the up-down direction of the central plug 55a (peripheral plug 55b). Providing a plurality of through holes 42a (42b) rather than a single large through hole 42a (42b) allows the size of each through hole 42a (42b) to be smaller, thereby reducing the risk of discharge. Furthermore, providing a plurality of through holes 42a (42b) also ensures the necessary gas flow rate.

[0061] Lift pin holes may also be provided penetrating the semiconductor manufacturing equipment member 10. The lift pin holes are holes for inserting lift pins that move the wafer W up and down relative to the central upper surface 21 of the ceramic substrate 20. When the wafer W is supported by, for example, three lift pins, the lift pin holes are provided in three locations.

[0062] 2. Method of Using the Semiconductor Manufacturing Equipment Component Next, an exemplary method of using the semiconductor manufacturing equipment component 10 configured as described above will be described. First, with the semiconductor manufacturing equipment component 10 installed in a chamber (not shown), a focus ring FR is placed on the outer peripheral upper surface 27 of the ceramic substrate 20, and a wafer W is placed on the central upper surface 21 of the ceramic substrate 20. The chamber is then depressurized using a vacuum pump to adjust the pressure inside the chamber to a predetermined degree of vacuum, and a voltage is applied to the electrodes 26 a and 26 b of the ceramic substrate 20 to generate an electrostatic attraction force, thereby attracting and fixing the wafer W to the wafer mounting surface (specifically, the upper end surface 21 c of the seal band 25 and the upper end surface 21 a of the protrusions 22) and the focus ring FR to the focus ring mounting surface (specifically, the upper end surface 27 c of the seal band 28 and the upper end surface 27 a of the seal band 29).

[0063] Next, a reactive gas atmosphere of a predetermined pressure (e.g., several tens to several hundreds of Pa) is created in the chamber. Under this condition, a high-frequency voltage, such as an RF voltage, is applied between an upper electrode (not shown) provided in the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment member 10 to generate plasma. The surface of the wafer W is processed by the generated plasma. A coolant circulates through the coolant flow path 32 of the base plate 30. A backside gas is introduced from a gas cylinder (not shown) into the gas supply path 60a and the gas supply path 60b. A thermally conductive gas (e.g., He gas) can be used as the backside gas. The backside gas is supplied and sealed in the space between the backside of the wafer W and the reference surface 21b of the wafer mounting surface through the gas supply path 60a and the multiple central plugs 55a. Similarly, the backside gas is supplied and sealed in the space between the backside of the focus ring FR and the reference surface 27b of the focus ring mounting surface through the gas supply path 60b and the multiple peripheral plugs 55b. The presence of this backside gas allows efficient heat conduction between the wafer W and the ceramic substrate 20 and between the focus ring FR and the ceramic substrate 20 .

[0064] By embedding the central plugs 55a and the peripheral plugs 55b in the central plug placement holes 50a and the peripheral plug placement holes 50b, respectively, it is possible to suppress discharge in the central plug placement holes 50a and the peripheral plug placement holes 50b. Without the central plugs 55a (peripheral plugs 55b), electrons generated as a result of ionization of gas molecules by application of RF voltage accelerate and collide with other gas molecules, causing a glow discharge and eventually an arc discharge. However, with the central plugs 55a (peripheral plugs 55b), the electrons hit the central plugs 55a (peripheral plugs 55b) before colliding with other gas molecules, suppressing discharge.

[0065] 3. Manufacturing Method of a Semiconductor Manufacturing Equipment Component Next, a manufacturing example of the semiconductor manufacturing equipment component 10 will be described with reference to FIG. 3. First, a disk-shaped ceramic sintered body 120, which is the base of the ceramic substrate 20, is produced by hot-press sintering a ceramic powder compact (FIG. 3A). The compact may be produced by stacking multiple tape compacts, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 has built-in electrodes 26a and 26b.

[0066] Next, a central plug arrangement hole 50a and an outer peripheral plug arrangement hole 50b are formed by machining the ceramic sintered body 120. Furthermore, a plurality of protrusions 22 and a seal band 25 are formed by laser processing on the upper surface of the ceramic sintered body 120 (FIG. 3B). The timing for forming the plurality of protrusions 22 and the seal band 25 may be after the ceramic substrate 20 and the base plate 30 are joined together.

[0067] In parallel with this, two MMC disk members 131 and 136 are fabricated ( FIG. 3C ). When the ceramic sintered body 120 is made of alumina, the MMC disk members 131 and 136 are preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is roughly the same as that of SiSiCTi or AlSiC. The SiSiCTi MMC disk member can be fabricated, for example, as follows: First, silicon carbide, metallic Si, and metallic Ti are mixed to prepare a powder mixture. Next, the resulting powder mixture is uniaxially pressed to prepare a disk-shaped compact, which is then hot-press sintered in an inert atmosphere to obtain the SiSiCTi MMC disk member.

[0068] Then, grooves 132 that will ultimately become the coolant flow paths 32 are formed by machining in the lower surface of the upper MMC disk member 131. Through holes 133 for introducing the coolant and through holes 134 for discharging the coolant are formed in the lower MMC disk member 136. Additionally, grooves 160 and through holes 161 that will become the gas supply paths 60a and 60b are formed in the upper MMC disk member 131 and the lower MMC disk member 136 by machining (FIG. 3D).

[0069] Next, metal bonding materials 135 and 137 are prepared. The metal bonding materials 135 and 137 preferably have a thickness of approximately 100 μm (e.g., 80 to 240 μm). The metal bonding material 135 has a through hole 90a for connecting the coolant flow paths of the lower MMC disk member 136 and the upper MMC disk member 131. The metal bonding material 135 also has a through hole 90b for connecting the gas supply path 60a (gas supply path 60b) of the lower MMC disk member 136 and the upper MMC disk member 131. The metal bonding material 137 has a through hole 91a for connecting the central plug placement hole 50a with the gas supply path 60a and a through hole 91b for connecting the outer plug placement hole 50b with the gas supply path 60b.

[0070] A metal bonding material 135 is placed between the lower surface of the upper MMC disk member 131 and the upper surface of the lower MMC disk member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disk member 131. Next, the ceramic sintered body 120 is placed on the metal bonding material 137 placed on the upper surface of the upper MMC disk member 131. This results in a stacked body 110 in which the lower MMC disk member 136, the metal bonding material 135, the upper MMC disk member 131, the metal bonding material 137, and the ceramic sintered body 120 are stacked in this order from the bottom ( FIG. 3E ).

[0071] This laminate 110 is heated and pressurized (TCB) to obtain a bonded body 111 ( FIG. 3F ). The bonded body 111 is formed by bonding a ceramic sintered body 120 to the upper surface of a base plate 30 via a bonding layer 40. The base plate 30 is formed by bonding an upper MMC disk member 131 to a lower MMC disk member 136 via the bonding layer 40. The base plate 30 has a coolant flow path 32, a coolant inlet 36, a coolant outlet 38, and gas supply paths 60a and 60b.

[0072] TCB is performed, for example, as follows. That is, the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature. As a result, the metal bonding material becomes a metal bonding layer. As the metal bonding material, an Al-Mg based bonding material or an Al-Si-Mg based bonding material can be used. For example, when TCB is performed using an Al-Si-Mg based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of about 100 μm.

[0073] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, and seal bands 28 and 29 are formed by laser processing (FIG. 3F), thereby completing the ceramic substrate 20 having a central portion 20a and an outer periphery 20b.

[0074] Next, central plugs 55a and peripheral plugs 55b are embedded in the central plug placement holes 50a and peripheral plug placement holes 50b of the ceramic substrate 20, respectively (FIG. 3F). Alternatively, a paste-like ceramic mixture serving as precursors of the central plugs 55a and peripheral plugs 55b may be poured into the central plug placement holes 50a and peripheral plug placement holes 50b of the ceramic substrate 20 and fired to form the central plugs 55a and peripheral plugs 55b. Thereafter, the semiconductor manufacturing equipment member 10 is completed by appropriately performing processes such as adjusting the overall shape.

[0075] 1 is shown as an integrated product, it may have a structure in which two members are bonded with a metal bonding layer as shown in FIG. 3F , or a structure in which three or more members are bonded with a metal bonding layer. When forming the bonding layer 40 using a metal bonding material 137, an insulating film may be formed on the side surface of the base plate 30 by thermal spraying either before or after bonding to the ceramic substrate 20. When forming the bonding layer 40 using a resin adhesive sheet, the resin melts, so it is sufficient to form the insulating film by thermal spraying before bonding to the ceramic substrate 20.

[0076] DESCRIPTION OF SYMBOLS 10: MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS 20: CERAMIC SUBSTRATE 20a: CENTRAL PORTION 20b: PERIPHERAL PORTION 21: CENTRAL PORTION UPPER SURFACE 21a: UPPER END SURFACE 21b: REFERENCE SURFACE 21c: UPPER END SURFACE 22: PROJECTION 23: LOWER SURFACE 25: SEAL BAND 26a: ELECTRODE 26b: ELECTRODE 27: PERIPHERAL PORTION UPPER SURFACE 27a: UPPER END SURFACE 27b: REFERENCE SURFACE 27c: UPPER END SURFACE 28: SEAL BAND 29: SEAL BAND 30: BASE PLATE 31: UPPER SURFACE 32: REFRIGERANTIC FLOW FLOW 33: LOWER SURFACE 36: REFRIGERANTIC FLOW IN PORTION 38: REFRIGERANTIC FLOW PORTION 40: JOINTING LAYER 42a: THROUGH HOLE 42b: THROUGH HOLE 50a: CENTRAL PORTION PLUG ARRANGEMENT HOLE 50a1: UPPER OPENING 50a2 : Lower opening 50a4 : Inner peripheral surface 50b : Outer peripheral plug placement hole 50b1 : Upper opening 50b2 : Lower opening 50b4 : Inner peripheral surface 55a : Central plug 55a1 : Upper surface 55a2 : Lower surface 55a3 : Gas flow path 55a4 : Outer peripheral surface 55b : Outer peripheral plug 55b1 : Upper surface 55b2 : Lower surface 55b3 : Gas flow path 55b4 : Outer peripheral surface 60a : Gas supply path 60b : Gas supply path 61a : Recess 62a : Gas inlet 90a : Through hole 90b : Through hole 91a : Through hole 91b : Through hole 110 : Laminated body 111 : Bonded body 120 : Sintered ceramic body 131 : MMC disc member 132: Groove 133: Through hole 134: Through hole 135: Metal bonding material 136: MMC disc member 137: Metal bonding material 160: Groove 161: Through hole FR: Focus ring W: Wafer

Claims

1. A component for semiconductor manufacturing equipment comprising: a ceramic substrate having a central portion having a central upper surface on which a wafer is placed, and a peripheral portion located on the outer periphery of the central upper surface and lower than the central upper surface, having a peripheral upper surface on which a focus ring is placed, wherein the central portion has central plug placement holes that pass through the central portion in the vertical direction and central plugs embedded in the central plug placement holes, and the peripheral portion has peripheral plug placement holes that pass through the peripheral portion in the vertical direction and peripheral plugs that are embedded in the peripheral plug placement holes and have a lower dielectric constant than the central plugs.

2. A member for semiconductor manufacturing equipment according to claim 1, wherein the relative dielectric constant of said outer plug is 0.7 times or less the relative dielectric constant of said central plug.

3. A member for semiconductor manufacturing equipment according to claim 1, wherein the main component of said central plug is the same as the main component of said ceramic substrate.

4. The semiconductor manufacturing equipment member according to claim 1, wherein the outer peripheral plug contains silica.

5. A semiconductor manufacturing equipment member according to claim 1, wherein the central plug and / or the peripheral plug are porous or dense with a flow path passing through the interior.

6. A member for semiconductor manufacturing equipment according to claim 1, wherein the thickness of the outer periphery is 75% or less of the thickness of the central portion.

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