Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component in which stress concentration on a laminate can be suppressed during mounting implementation to suppress occurrence of a crack in the laminate.　This multilayer ceramic electronic component comprises a multilayer ceramic capacitor and bumps. The multilayer ceramic capacitor has: a laminate including a plurality of laminated dielectric layers and having a first main surface and a second main surface that face each other in a height direction, a first side surface and a second side surface that face each other in a width direction orthogonal to the height direction, and a first end surface and a second end surface that face each other in a length direction orthogonal to the height direction and the width direction; a first external electrode disposed on at least the first end surface and the second main surface of the laminate; and a second external electrode disposed on at least the second end surface and the second main surface of the laminate. The bumps are disposed on the respective surfaces of the first external electrode and the second external electrode on the second main surface side of the laminate. Assuming that the thickness of the bump in the height direction is t1 and the thickness of the laminate in the height direction is t2, a condition of 0.5 < t1 / t2 < 0.75 is satisfied.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, electronic devices such as mobile phones and portable music players have become smaller and thinner. Accordingly, the multilayer ceramic electronic components mounted in these smaller and thinner electronic devices have also become smaller and thinner.

[0003] Such a multilayer ceramic capacitor, which is a multilayer ceramic electronic component, has a dielectric chip in which dielectric ceramics such as barium titanate and internal electrodes are alternately stacked, and external electrodes formed to cover each longitudinal end of the dielectric chip, as disclosed in Patent Document 1 (see Patent Document 1). The multilayer ceramic capacitor disclosed in Patent Document 1 is a low-profile multilayer ceramic capacitor with a height of, for example, 150 μm or less. When mounting such a multilayer ceramic capacitor on a substrate, a mounter is used to mount it on the substrate.

[0004] JP 2014-183186 A

[0005] However, when a low-profile multilayer ceramic capacitor is mounted on a mounting board using the nozzle of a mounter, the impact during mounting can cause cracks in the laminate of the multilayer ceramic capacitor, potentially resulting in poor insulation or the like.

[0006] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic electronic component that can suppress stress concentration on the laminate during mounting and can suppress the occurrence of cracks in the laminate.

[0007] a multilayer ceramic capacitor including: a laminate including a plurality of stacked dielectric layers according to the present invention, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first end faces and second end faces opposing each other in a length direction perpendicular to the height and width directions; first external electrodes disposed on at least the first end faces and the second main surfaces of the laminate; and second external electrodes disposed on at least the second end faces and the second main surfaces of the laminate; and bumps disposed on the surfaces of the first and second external electrodes, respectively, on the second main surface side of the laminate, wherein when the thickness of the bump in the height direction is t1 and the thickness of the laminate in the height direction is t2, the multilayer ceramic electronic component satisfies the condition 0.5<t1 / t2<0.75.

[0008] According to the multilayer ceramic electronic component of the present invention, the multilayer ceramic electronic component includes bumps disposed on the surfaces of the first external electrodes and the second external electrodes on the second main surface side of the laminate, and when the thickness of the bumps in the height direction is t1 and the thickness of the laminate in the height direction is t2, the condition of 0.5 < t1 / t2 < 0.75 is satisfied. Therefore, particularly when a thin multilayer ceramic electronic component is mounted on a mounting board, an impact on the multilayer ceramic electronic component from the mounter nozzle is transmitted to the bumps, and damage to the laminate due to stress concentration at the edge portions of the external electrodes located on the main surface side of the multilayer ceramic capacitor caused by the impact can be mitigated.

[0009] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress stress concentration on the laminate during mounting and prevent cracks from occurring in the laminate.

[0010] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is an external perspective view showing an example of a multilayer ceramic electronic component according to a first embodiment of the present invention; FIG. 2 is a right side view showing an example of a multilayer ceramic electronic component according to the first embodiment of the present invention; FIG. 3 is a front view showing an example of a multilayer ceramic electronic component according to the first embodiment of the present invention; FIG. 4 is a bottom view showing an example of a multilayer ceramic electronic component according to the first embodiment of the present invention; FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1; FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1; FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1; FIG. 8 is an external perspective view showing an example of a multilayer ceramic electronic component according to a first modified example of the first embodiment of the present invention; FIG. 9 is a right side view showing an example of a multilayer ceramic electronic component according to a first modified example of the first embodiment of the present invention; FIG. 11 is a front view showing an example of a multilayer ceramic electronic component according to a first modified example of the first embodiment of the present invention; FIG. 12 is a bottom view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a first modified example of the first embodiment of the present invention; FIG. 13 is a cross-sectional view taken along line XII-XII in FIG. 8; FIG. 14 is a cross-sectional view taken along line XIII-XIII in FIG. 8; FIG. 15 is a cross-sectional view taken along line XIV-XIV in FIG. 8; 15. A right side view showing an example of a multilayer ceramic electronic component according to a second modified example of the first embodiment of the present invention. A front view showing an example of a multilayer ceramic electronic component according to a second modified example of the first embodiment of the present invention. A bottom view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second modified example of the first embodiment of the present invention. A cross-sectional view taken along line XIX-XIX in FIG. 15. A cross-sectional view taken along line XX-XX in FIG. 8. A cross-sectional view taken along line XXI-XXI in FIG. 8. An external perspective view showing an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention. A right side view showing an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention. A front view showing an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention. A bottom view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention.22. A cross-sectional view taken along line XVI-XVI in FIG. 22. A diagram showing a state in which the multilayer ceramic electronic component according to the first embodiment of the present invention is mounted on a mounting substrate. An external perspective view showing an example of a multilayer ceramic electronic component according to a second embodiment of the present invention. A front view showing an example of a multilayer ceramic electronic component according to the second embodiment of the present invention. A bottom view showing an example of a multilayer ceramic electronic component according to the second embodiment of the present invention. A cross-sectional view taken along line XXX-XXX in FIG. 28. A cross-sectional view taken along line XXXI-XVIII in FIG. 28. A cross-sectional view taken along line XXXII-XXXII in FIG. 28. An exploded perspective view of the laminate shown in FIG. 28. An external perspective view showing an example of a multilayer ceramic electronic component according to a first modified example of the second embodiment of the present invention. A front view showing an example of a multilayer ceramic electronic component according to a modified example of the second embodiment of the present invention. A bottom view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a modified example of the second embodiment of the present invention. A cross-sectional view taken along line XXXVII-XXXVII in FIG. 35. A cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 35.

[0012] An example of a multilayer ceramic electronic component according to a first embodiment of the present invention will now be described.

[0013] A. First Embodiment 1. Multilayer Ceramic Electronic Component An example of a multilayer ceramic electronic component 10 according to an embodiment of the present invention will be described. In this embodiment, the multilayer ceramic electronic component 10 includes a multilayer ceramic capacitor 10A and bumps 40.

[0014] FIG. 1 is an external perspective view showing an example of a multilayer ceramic electronic component according to a first embodiment of the present invention. FIG. 2 is a right side view showing an example of a multilayer ceramic electronic component according to the first embodiment of the present invention. FIG. 3 is a front view showing an example of a multilayer ceramic electronic component according to the first embodiment of the present invention. FIG. 4 is a bottom view showing an example of a multilayer ceramic electronic component according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1.

[0015] The multilayer ceramic capacitor 10A has a laminate 12 and external electrodes 24. The configuration of each will be described below in the order of the laminate 12 and the external electrodes 24.

[0016] The laminate 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face each other in a height direction x, a first side surface 12c and a second side surface 12d that face each other in a width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The corners and ridges of the laminate 12 are rounded. The corners refer to the intersections of three adjacent surfaces of the laminate 12, and the ridges refer to the intersections of two adjacent surfaces of the laminate 12. Furthermore, unevenness or the like may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0017] As shown in Figure 5, the laminate 12 has, in the height direction x connecting the first main surface 12a and the second main surface 12b, an effective layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b.

[0018] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12, and is an assembly of a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0019] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12, and is an assembly of a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0020] The area sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the effective layer portion 15a.

[0021] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed mainly of BaTiO3, CaTiO3, SrTiO3, CaZnO3, etc. Sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components.

[0022] The number of dielectric layers 14 is not particularly limited, but is preferably 5 to 2000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably 0.30 μm to 5.0 μm.

[0023] 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0024] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a that faces the second internal electrode layer 16b, and a first lead electrode portion 20a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. An end of the first lead electrode portion 20a is led out to and exposed at the first end face 12e.

[0025] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0026] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0027] The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the width of the first extraction electrode portion 20a of the first internal electrode layer 16a may be formed to be the same width, or one of them may be formed to be narrower in width.

[0028] The second internal electrode layer 16b is arranged on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged. The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, and a second extraction electrode portion 20b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to a second end face 12f of the laminate 12. The second extraction electrode portion 20b has an end portion extended to and exposed at the second end face 12f.

[0029] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0030] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0031] The width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the width of the second extraction electrode portion 20b of the second internal electrode layer 16b may be formed to be the same width, or one of them may be formed to be narrower in width.

[0032] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The internal electrode layer 16 may further contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 14.

[0033] Furthermore, the first internal electrode layer 16 a and the second internal electrode layer 16 b may contain Sn. By containing Sn in the first internal electrode layer 16 a and the second internal electrode layer 16 b, electric field concentration at the interface between the first internal electrode layer 16 a and the second internal electrode layer 16 b and the dielectric layer 14 can be alleviated, leading to improvement in high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is contained in only one of the first internal electrode layer 16 a and the second internal electrode layer 16 b.

[0034] The thickness of the internal electrode layers 16, i.e., the first internal electrode layers 16a and the second internal electrode layers 16b, is preferably 0.30 μm or more and 1.0 μm or less. The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 5 or more and 2000 or less.

[0035] Furthermore, as shown in FIG. 5, the laminate 12 includes ends (hereinafter referred to as "L gaps") 22b of the laminate 12 formed between the end of the first internal electrode layer 16a opposite the first extraction electrode portion 20a and the second end face 12f, and between the end of the second internal electrode layer 16b opposite the second extraction electrode portion 20b and the first end face 12e.

[0036] As shown in FIG. 5 , the laminate 12 includes side portions (hereinafter referred to as “W gaps”) 22 a of the laminate 12 formed between one end of the first opposing electrode portion 18 a and the second opposing electrode portion 18 b in the width direction y and the first side surface 12 c, and between the other end of the first opposing electrode portion 18 a and the second opposing electrode portion 18 b in the width direction y and the second side surface 12 d.

[0037] The dimensions of the laminate 12 are not particularly limited, but it is preferable that the dimension in the length direction z is 0.2 mm to 3.2 mm, the dimension in the width direction y is 0.10 mm to 2.50 mm, and the dimension in the height direction x is 0.04 mm to 0.30 mm. In particular, it is preferable that the length of the laminate 12 in the height direction x is 110 μm or less.

[0038] As shown in FIGS. 1 to 4, external electrodes 24 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0039] The external electrode 24 includes a main surface electrode 26 and a plating layer 28 formed to cover the main surface electrode 26 .

[0040] The external electrode 24 includes a first external electrode 24a and a second external electrode 24b.

[0041] The first external electrode 24a is disposed on the surface of the first end face 12e of the laminate 12, and extends from the first end face 12e to be disposed on a portion of the second main face 12b. In this case, the first external electrode 24a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a. Furthermore, the first external electrode 24a is not disposed on a portion of the first main face 12a, a portion of the first side face 12c, or a portion of the second side face 12d. Therefore, the first external electrode 24a is L-shaped in cross section.

[0042] The second external electrode 24b is disposed on the surface of the second end face 12f of the laminate 12, and extends from the second end face 12f to be disposed on a portion of the second main surface 12b. In this case, the second external electrode 24b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b. Furthermore, the second external electrode 24b is not disposed on a portion of the first main surface 12a, a portion of the first side surface 12c, or a portion of the second side surface 12d. Therefore, the second external electrode 24b is L-shaped in cross section.

[0043] Within the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 24a connected to the first internal electrode layer 16a and the second external electrode 24b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0044] The principal surface electrode 26 has a first principal surface electrode 26a1 and a second principal surface electrode 26b1. The first principal surface electrode 26a1 and the second principal surface electrode 26b1 are formed of thin film layers made up of a plurality of thin film electrodes in order to further improve performance.

[0045] The first principal surface electrode 26a1 is formed so as to cover a portion of the second principal surface 12b on the side of the first end face 12e of the laminate 12.

[0046] The second principal surface electrode 26b1 is formed so as to cover a portion of the second principal surface 12b on the second end surface 12f side of the laminate 12.

[0047] The principal surface electrode 26 formed of a thin film layer is preferably formed by a thin film formation method such as sputtering or vapor deposition. In particular, the principal surface electrode 26 formed of a thin film layer is preferably a sputtered electrode formed by sputtering. Electrodes formed by sputtering will be described below.

[0048] When the principal surface electrode 26 is formed by a sputtering electrode, it is preferable to form the sputtering electrode directly on a part of the second principal surface 12 b of the laminate 12 .

[0049] The principal surface electrodes 26 may also contain metals such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. In this case, the principal surface electrodes 26 preferably contain, as a co-material, the same dielectric material as the dielectric ceramic contained in the dielectric layers 14. By including the co-material, the shrinkage behavior of the principal surface electrodes 26 during firing can be made closer to the shrinkage behavior of the laminate 12, and peeling of the principal surface electrodes 26 from the laminate 12 can be prevented.

[0050] The plating layer 28 includes a first plating layer 28a and a second plating layer 28b. The first plating layer 28a is disposed so as to cover the first principal surface electrode 26a1 disposed on the second principal surface 12b and extend from the second principal surface 12b to cover the first end surface 12e. The second plating layer 28b is disposed so as to cover the second principal surface electrode 26b1 disposed on the second principal surface 12b and extend from the second principal surface 12b to cover the second end surface 12f.

[0051] The plating layer 28 may be formed of multiple layers. Preferably, the plating layer 28 includes a lower plating layer 30 that covers the principal surface electrode 26 and an upper plating layer 32 that is disposed so as to cover the lower plating layer 30. Of the plating layers 28, the upper plating layer 32 includes at least one selected from, for example, Ni, Sn, Cu, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0052] The lower plating layer 30 includes a first lower plating layer 30a and a second lower plating layer 30b. The lower plating layer 30 is disposed on the main surface electrode 26 and on the first end face 12e and the second end face 12f.

[0053] The first lower layer plating layer 30a is arranged on the first end surface 12e of the laminate 12 where no main surface electrode is arranged, and is further arranged so as to cover the first main surface electrode 26a1 arranged on the second main surface 12b.

[0054] The second lower layer plating layer 30b is arranged on the second end surface 12f of the laminate 12 where no main surface electrode is arranged, and is further arranged so as to cover the second main surface electrode 26b1 arranged on the second main surface 12b.

[0055] The thickness of each lower plating layer 30 is preferably 2 μm or more and 11 μm or less.

[0056] The upper plating layer 32 includes a first upper plating layer 32a and a second upper plating layer 32b.

[0057] The first upper-layer plating layer 32a is disposed so as to cover the first lower-layer plating layer 30a. Specifically, the first upper-layer plating layer 32a is disposed on the first end face 12e of the surface of the first lower-layer plating layer 30a, and preferably extends to the second main surface 12b of the surface of the first lower-layer plating layer 30a.

[0058] The second upper-layer plating layer 32b is disposed so as to cover the second lower-layer plating layer 30b. Specifically, the second upper-layer plating layer 32b is disposed on the second end face 12f of the surface of the second lower-layer plating layer 30b, and preferably extends to the second main surface 12b of the surface of the second lower-layer plating layer 30b.

[0059] The thickness of each upper plating layer 32 is preferably 2 μm or more and 11 μm or less.

[0060] In this embodiment, the lower plating layer 30 is a Ni plating layer, and the upper plating layer 32 is a Sn plating layer, forming a two-layer structure. By using a Ni plating layer for the lower plating layer 30, it is possible to prevent the main surface electrodes 26 from being eroded by solder when mounting the multilayer ceramic electronic component 10 on a mounting substrate. By using a Sn plating layer for the upper plating layer 32, it is possible to improve the wettability of solder when mounting the multilayer ceramic electronic component 10 on a mounting substrate, thereby facilitating mounting of the multilayer ceramic electronic component 10.

[0061] The bumps 40 provided on the multilayer ceramic electronic component 10 include a first bump 40a and a second bump 40b.

[0062] The first bump 40a is disposed on the surface of the first external electrode 24a facing the second main surface 12b, and the second bump 40b is disposed on the surface of the second external electrode 24b facing the second main surface 12b.

[0063] In the multilayer ceramic electronic component 10 according to the present invention, the second main surface 12b serves as a mounting surface facing the mounting substrate.

[0064] The bump 40 is primarily composed of an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni and Sn as a low-melting-point metal. The intermetallic compound is preferably an intermetallic compound formed by the reaction of Sn with a Cu-Ni alloy. Such an intermetallic compound has the advantages of a fast reaction rate and minimal change in shape during formation. Ag may also be included as a high-melting-point metal constituting the intermetallic compound. By using an intermetallic compound for the bump 40, when stress concentration due to impact from the mounter is transmitted to the bump 40, the bump 40 can achieve a hardness that can further mitigate stress concentration on the laminate 12 at the edge of the external electrode located on the main surface of the multilayer ceramic capacitor on the mounting surface side.

[0065] When the thickness of each of the first bump 40a and the second bump 40b in the height direction x is t1 and the thickness of the laminate 12 in the height direction x is t2, the condition 0.5<t1 / t2<0.75 is satisfied.

[0066] Furthermore, the thickness t1 of each of the first bump 40a and the second bump 40b in the height direction x is preferably 20 μm or more and 30 μm or less.

[0067] Here, the thickness t1 of each of the first bump 40 a and the second bump 40 b in the height direction x, and the thickness t2 of the laminate 12 in the height direction x are measured, for example, by observing the appearance with a digital microscope (VHX-8000 manufactured by Keyence Corporation) at a magnification of 500 times or more and 2000 times or less.

[0068] When the dimension of each of the first bump 40a and the second bump 40b in the width direction y is w1 and the dimension of the laminate 12 in the width direction y is t2, it is preferable to satisfy the condition 0.6<w1 / w2<0.9.

[0069] Here, the dimension w1 in the width direction y of each of the first bump 40a and the second bump 40b, and the thickness t2 in the width direction y of the laminate 12 are measured, for example, by observing the appearance with a digital microscope (Keyence Corporation: VHX-8000) at a magnification of 500 times or more and 2000 times or less.

[0070] The Vickers hardness (HV) of the first bump 40a and the second bump 40b is preferably 30 or more and 40 or less. This allows the bump 40 to further mitigate the stress concentration on the laminate 12 at the edge of the external electrode located on the main surface side of the multilayer ceramic capacitor on the mounting surface side when stress concentration due to impact from the mounter is transmitted to the bump 40. Here, the Vickers hardness is determined by a measurement method in accordance with JIS Z 2244.

[0071] The dimension in the length direction z of the multilayer ceramic capacitor 10A including the laminate 12, the first external electrode 24a, and the second external electrode 24b is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10A including the laminate 12, the first external electrode 24a, and the second external electrode 24b is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10A including the laminate 12, the first external electrode 24a, and the second external electrode 24b is defined as dimension W.

[0072] According to the multilayer ceramic electronic component 10 shown in FIG. 1 , in the multilayer ceramic capacitor 10A, the first bump 40 a is arranged on the surface of the first external electrode 24 a that faces the second main surface 12 b, and the second bump 40 b is arranged on the surface of the second external electrode 24 b that faces the second main surface 12 b. When the thickness of each of the first bump 40 a and the second bump 40 b in the height direction x is t1 and the thickness of the laminate 12 in the height direction x is t2, the condition of 0.5 < t1 / t2 < 0.75 is satisfied. In particular, when the thin multilayer ceramic electronic component 10 is mounted on a mounting board, an impact on the multilayer ceramic electronic component 10 by the mounter nozzle is transmitted to the bump 40, and damage to the laminate that is caused by stress concentration at the edge portions of the external electrodes that are located on the main surface side of the multilayer ceramic capacitor due to the impact can be mitigated.

[0073] 2. Modifications of the First Embodiment Hereinafter, modifications (first to third modifications) of the multilayer ceramic electronic component according to the first embodiment will be described. In these modifications, components corresponding to those in the above-described embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0074] (1) First Modification First, a multilayer ceramic electronic component 110 according to a first modification of the first embodiment will be described. FIG. 8 is an external perspective view showing an example of a multilayer ceramic electronic component according to a first modification of the first embodiment of the present invention. FIG. 9 is a right side view showing an example of a multilayer ceramic electronic component according to a first modification of the first embodiment of the present invention. FIG. 10 is a front view showing an example of a multilayer ceramic electronic component according to a first modification of the first embodiment of the present invention. FIG. 11 is a bottom view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to a first modification of the first embodiment of the present invention. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 8. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 8.

[0075] The multilayer ceramic electronic component 110 according to the first modification includes a multilayer ceramic capacitor 110A and bumps 40.

[0076] In the multilayer ceramic capacitor 110A according to the first modification, the external electrodes 124 are arranged not only on the first end face 12 e and the second end face 12 f and the first main face 12 a and the second main face 12 b, but also on the first side face 12 c and the second side face 12 d, as shown in Fig. 8. In addition, as shown in Fig. 14, the shape of the lead electrode portion of the internal electrode layer 16 is also different.

[0077] 12 and 13, the internal electrode layer 16 includes first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0078] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a opposing the second internal electrode layer 16b, and a first extraction electrode portion 20a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e side of the laminate 12. As shown in Fig. 13, the first extraction electrode portion 20a has an end portion that is extracted and exposed to the first end face 12e, a portion of the first side face 12c, and a portion of the second side face 12d.

[0079] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the surface of the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, and a second extraction electrode portion 20b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second end face 12f side of the laminate 12. As shown in Fig. 13, the second extraction electrode portion 20b has an end portion that is extended to and exposed at the second end face 12f, a portion of the first side face 12c, and a portion of the second side face 12d.

[0080] This allows the lower plating layer 30 to be formed also on the first and second lead electrode portions 20 a and 20 b exposed on the first and second side surfaces 12 c and 12 d, respectively, and as a result, the external electrodes 124 can be formed also on the first and second side surfaces 12 c and 12 d.

[0081] The external electrode 124 includes a principal surface electrode 26 and a plating layer 28 formed to cover the principal surface electrode 26 .

[0082] The external electrode 124 includes a first external electrode 124a and a second external electrode 124b.

[0083] The first external electrode 124a is disposed on the surface of the first end face 12e, part of the first main face 12a, part of the second main face 12b, and part of the first side face 12c and part of the second side face 12d of the laminate 12. In this case, the first external electrode 124a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0084] The second external electrode 124b is disposed on the surface of the second end face 12f of the laminate 12, on a portion of the first main face 12a and a portion of the second main face 12b, and on a portion of the first side face 12c and a portion of the second side face 12d. In this case, the second external electrode 124b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0085] The principal surface electrode 26 includes a first principal surface electrode 26a1, a second principal surface electrode 26b1, a third principal surface electrode 26a2, and a fourth principal surface electrode 26b2. The first principal surface electrode 26a1, the second principal surface electrode 26b1, the third principal surface electrode 26a2, and the fourth principal surface electrode 26b2 are formed of thin film layers made up of a plurality of thin film electrodes to further improve performance.

[0086] The first principal surface electrode 26a1 is formed to cover a portion of the second principal surface 12b on the first end face 12e side of the laminate 12. The third principal surface electrode 26a2 is formed to cover a portion of the first principal surface 12a on the first end face 12e side of the laminate 12. The first external electrode 124a has the first principal surface electrode 26a1 and the third principal surface electrode 26a2.

[0087] The second principal surface electrode 26b1 is formed so as to cover a portion of the second principal surface 12b on the second end surface 12f side of the laminate 12. The fourth principal surface electrode 26b2 is formed so as to cover a portion of the first principal surface 12a on the second end surface 12f side of the laminate 12. The second external electrode 124b has the second principal surface electrode 26b1 and the fourth principal surface electrode 26b2.

[0088] The plating layer 28 includes a first plating layer 28a and a second plating layer 28b. The first plating layer 28a is disposed so as to cover the first principal surface electrode 26a1 and the third principal surface electrode 26a2. The second plating layer 28b is disposed so as to cover the second principal surface electrode 26b1 and the fourth principal surface electrode 26b2. The structure of the plating layer 28 of the multilayer ceramic capacitor 110A according to the first modified example is the same as the structure of the plating layer 28 of the multilayer ceramic capacitor 10A.

[0089] The bumps 40 provided on the multilayer ceramic electronic component 110 include a first bump 40a and a second bump 40b.

[0090] The first bump 40a is disposed on the surface of the first external electrode 24a facing the second main surface 12b, and the second bump 40b is disposed on the surface of the second external electrode 24b facing the second main surface 12b.

[0091] The multilayer ceramic electronic component 110 according to the first modified example shown in Fig. 8 has the same effects as the multilayer ceramic electronic component 10 shown in Fig. 1. That is, the external electrodes 124 are disposed on the first main surface and both side surfaces 12c, 12d of the multilayer ceramic capacitor 110A of the multilayer ceramic electronic component 110, and therefore, solder wets and rises onto the external electrodes 124 during mounting, thereby maintaining the adhesive strength to the mounting board.

[0092] (2) Second Modification Next, a multilayer ceramic electronic component 210 according to a second modification will be described. FIG. 15 is an external perspective view showing an example of a multilayer ceramic electronic component according to a second modification of the first preferred embodiment of the present invention. FIG. 16 is a right side view showing an example of a multilayer ceramic electronic component according to a second modification of the first preferred embodiment of the present invention. FIG. 17 is a front view showing an example of a multilayer ceramic electronic component according to a second modification of the first preferred embodiment of the present invention. FIG. 18 is a bottom view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to a second modification of the first preferred embodiment of the present invention. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 15. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 8. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 8.

[0093] The multilayer ceramic electronic component 210 according to the second modification includes a multilayer ceramic capacitor 210A and bumps 40.

[0094] 19 and 20, the internal electrode layer 16 includes first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0095] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a opposing the second internal electrode layer 16b, and a first extraction electrode portion 20a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e side of the laminate 12. As shown in Fig. 21 , the first extraction electrode portion 20a has an end portion that is extracted and exposed to the first end face 12e, a portion of the first side face 12c, and a portion of the second side face 12d. The dimension in the longitudinal direction z of the exposed portion of the first extraction electrode portion 20a of the first internal electrode layer 16a, which is extracted to a part of the first side surface 12c and a part of the second side surface 12d, is shorter than the dimension in the longitudinal direction z of the exposed portion of the first extraction electrode portion 20a of the first internal electrode layer 16a shown in Figure 14, which is extracted to a part of the first side surface 12c and a part of the second side surface 12d.

[0096] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the surface of the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b that faces the first internal electrode layer 16a, and a second extraction electrode portion 20b that is located on one end side of the second internal electrode layer 16b and extends from the second opposing electrode portion 18b to the second end face 12f side of the laminate 12. As shown in Fig. 21 , the second extraction electrode portion 20b has an end portion that is extended to and exposed at the second end face 12f, a portion of the first side face 12c, and a portion of the second side face 12d. The dimension in the longitudinal direction z of the exposed portion of the second extraction electrode portion 20b of the second internal electrode layer 16b, which is extracted to a part of the first side surface 12c and a part of the second side surface 12d, is shorter than the dimension in the longitudinal direction z of the exposed portion of the second extraction electrode portion 20b of the second internal electrode layer 16b shown in Figure 14, which is extracted to a part of the first side surface 12c and a part of the second side surface 12d.

[0097] 15 and 19, the multilayer ceramic capacitor 210A according to the second modification has external electrodes 224 that are L-shaped in cross section. The external electrodes 224 have a first external electrode 224a and a second external electrode 224b.

[0098] 15 , in a multilayer ceramic capacitor 210A that is a multilayer ceramic electronic component according to a second modification, a first external electrode 224a that is L-shaped in cross section is disposed on the surface of the first end face 12e and extends from the first end face 12e to the second main face 12b. The first external electrode 224a is disposed so as to cover the first lead electrode portion 20a of the first internal electrode layer 16a that is exposed from the first end face 12e to the first side face 12c and the second side face 12d. In this case, the first external electrode 224a may be disposed so that a portion thereof wraps around onto the first main face 12a.

[0099] 15 , in the multilayer ceramic capacitor 210A, a second external electrode 224b having an L-shaped cross section is disposed on the surface of the second end face 12f and extends from the second end face 12f onto the second main face 12b. The second external electrode 224b is disposed from the second end face 12f to cover the second extraction electrode portion 20b of the second internal electrode layer 16b exposed on the first side face 12c and the second side face 12d. In this case, the second external electrode 224b may be disposed so that a portion thereof wraps around onto the first main face 12a.

[0100] The first external electrode 224a may be arranged on the surface of the first end face 12e and extend from the first end face 12e to be arranged on the first principal face 12a, and the second external electrode 224b may be arranged on the surface of the second end face 12f and extend from the second end face 12f to be arranged on the first principal face 12a. In this case, the first external electrode 224a may be arranged so that a portion thereof wraps around onto the second principal face 12b, and the second external electrode 224b may be arranged so that a portion thereof wraps around onto the second principal face 12b. In this case, only the third principal face electrode and the fourth principal face electrode are arranged on the first principal face 12a.

[0101] The bumps 40 provided on the multilayer ceramic electronic component 210 include a first bump 40a and a second bump 40b.

[0102] The first bump 40a is disposed on the surface of the first external electrode 24a facing the second main surface 12b, and the second bump 40b is disposed on the surface of the second external electrode 24b facing the second main surface 12b.

[0103] Furthermore, the structure of the plating layer 28 of the multilayer ceramic capacitor 210A according to the second modification is the same as the structure of the plating layer 28 of the multilayer ceramic capacitor 10A.

[0104] The multilayer ceramic electronic component 210 according to the second modification shown in Fig. 15 provides the same effects as those of the multilayer ceramic electronic component 110 shown in Fig. 8, and also provides the following effect: The size of the area of ​​the external electrodes 224 arranged on both side surfaces 12c, 12d of the multilayer ceramic capacitor 210A of the multilayer ceramic electronic component 210 is smaller than the size of the area of ​​the external electrodes 124 arranged on both side surfaces 12c, 12d of the multilayer ceramic capacitor 110A of the multilayer ceramic electronic component 110 shown in Fig. 8. This prevents solder from wetting up to the upper surface (first main surface 12a) during mounting, and maintains the adhesive strength to the mounting board.

[0105] (3) Third Modification Next, a multilayer ceramic electronic component 310 according to a third modification will be described.

[0106] Fig. 22 is an external perspective view showing an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention. Fig. 23 is a right side view showing an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention. Fig. 24 is a front view showing an example of a multilayer ceramic electronic component according to a third modified example of the first embodiment of the present invention. Fig. 25 is a bottom view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the third modified example of the first embodiment of the present invention. Fig. 26 is a cross-sectional view taken along line XVI-XVI in Fig. 22.

[0107] The multilayer ceramic electronic component 310 according to the third modification includes a multilayer ceramic capacitor 310A and bumps 40.

[0108] 26 , the internal electrode layers 16 have first internal electrode layers 16 a and second internal electrode layers 16 b. The first internal electrode layers 16 a and the second internal electrode layers 16 b are alternately stacked with the dielectric layers 14 interposed therebetween. The configuration of the internal electrode layers 16 is similar to the configuration of the internal electrode layers 16 of the multilayer ceramic capacitor 210A that constitutes the multilayer ceramic electronic component 210 according to the second modified example.

[0109] 22 and 26, a multilayer ceramic capacitor 310A according to the third modification has external electrodes 324 that are L-shaped in cross section. The external electrodes 324 have a first external electrode 324a and a second external electrode 324b.

[0110] 22 , in a multilayer ceramic capacitor 310A, which is a multilayer ceramic electronic component according to the third modification, a first external electrode 324a having an L-shaped cross section is disposed on the surface of the first end face 12e and extends from the first end face 12e to be disposed on the second main face 12b. The first external electrode 324a is disposed so as to cover the first lead electrode portion 20a of the first internal electrode layer 16a that is exposed from the first end face 12e to the first side face 12c and the second side face 12d. In this case, the first external electrode 324a is disposed so as not to reach the first main face 12a.

[0111] 15, the multilayer ceramic capacitor 210A has a second external electrode 324b that is L-shaped in cross section and disposed on the surface of the second end face 12f, extending from the second end face 12f and disposed on the second main face 12b. The second external electrode 324b is disposed from the second end face 12f to cover the second extraction electrode portion 20b of the second internal electrode layer 16b that is exposed on the first side face 12c and the second side face 12d. In this case, the second external electrode 324b is disposed so as not to reach the first main face 12a.

[0112] The bumps 40 provided on the multilayer ceramic electronic component 310 include a first bump 40a and a second bump 40b.

[0113] The first bump 40a is disposed on the surface of the first external electrode 24a facing the second main surface 12b, and the second bump 40b is disposed on the surface of the second external electrode 24b facing the second main surface 12b.

[0114] The multilayer ceramic electronic component 310 according to the third modification shown in Fig. 22 achieves the same effects as the multilayer ceramic electronic component 210 shown in Fig. 15 , and also achieves the following effect: That is, the size of the area of ​​the external electrodes 224 arranged on both side surfaces 12 c, 12 d of the multilayer ceramic capacitor 210A of the multilayer ceramic electronic component 210 is smaller than the size of the area of ​​the external electrodes 124 arranged on both side surfaces 12 c, 12 d of the multilayer ceramic capacitor 110A of the multilayer ceramic electronic component 110 shown in Fig. 8 , and therefore, solder is prevented from wetting up to the upper surface (first main surface 12 a) during mounting, making it possible to maintain the adhesive strength to the mounting board and further reduce the amount of solder.

[0115] Next, a description will be given of a state in which the multilayer ceramic electronic component 10 is mounted on a mounting substrate 60 using a mounter nozzle 70. Fig. 27 is a diagram showing a state in which the multilayer ceramic electronic component according to the first embodiment of the present invention is mounted on a mounting substrate.

[0116] As shown in FIG. 27 , the multilayer ceramic electronic component 10 according to the first embodiment is sucked using a mounter nozzle 70 and mounted on a mounting substrate 60. The mounting substrate 60 includes a substrate core material 62 and conductive lands 64. The substrate core material 62 may be, for example, a substrate made of a material in which a base material made of a mixture of glass fabric (cloth) and glass nonwoven fabric is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramic and glass. The substrate core material 62 may be a substrate made of a single layer, or may be configured as a substrate made of a laminate of multiple layers.

[0117] One main surface of the core material 62 of the substrate is provided with conductor lands 64 and constitutes a substrate-side mounting surface 62 a on which the multilayer ceramic electronic component 10 is mounted.

[0118] The conductor land 64 includes a first conductor land 64 a and a second conductor land 64 b. The first conductor land 64 a is electrically connected and mechanically joined to the first external electrode 24 a of the multilayer ceramic capacitor 10A by a bonding material. The second conductor land 64 b is electrically connected and mechanically joined to the second external electrode 24 b of the multilayer ceramic capacitor 10A by a bonding material.

[0119] The material of the conductor land 64 is not particularly limited, but metals such as copper, gold, palladium, and platinum can be used. The thickness of the conductor land 64, i.e., the dimension in the height direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less, for example. The bonding material can be, for example, solder.

[0120] The multilayer ceramic capacitor 10A is mounted on the mounting substrate 60 so that the second main surface 12b faces the substrate-side mounting surface 62a. That is, the multilayer ceramic capacitor 10A is bonded to the mounting substrate 60 via the bonding material at the bumps 40 provided on the plating layer 28.

[0121] In this manner, when the multilayer ceramic capacitor 10A is sucked by the mounter nozzle 70 during mounting, the first main surface 12a of the multilayer ceramic capacitor 10A comes into contact with the mounter nozzle 70. When the bumps 40 come into contact with the mounting substrate 60 (conductor lands 64), they also come into contact with the mounter nozzle 70. This makes it possible to reduce the concentration of stress on the ends of the external electrodes 24 arranged on the second main surface 12b side of the multilayer ceramic capacitor 10A during mounting.

[0122] In this case, when the distance B between the bump 40 and the center line indicating the center of the multilayer ceramic electronic component 10 in the longitudinal direction z is defined as B, and the distance R between the conductor land 64a and the center line indicating the center between the conductor land 64a and the conductor land 64b in the longitudinal direction z is defined as R, it is preferable that the relationship between the distance B and the distance R satisfy the condition R≦B.

[0123] 3. Method for Manufacturing the Multilayer Ceramic Electronic Component A method for manufacturing the multilayer ceramic electronic component 10 according to the first embodiment will now be described. First, a method for manufacturing the multilayer ceramic capacitor 10A of the multilayer ceramic electronic component 10 will be described.

[0124] First, ceramic green sheets and a conductive paste for the internal electrodes are prepared. The ceramic green sheets and the conductive paste for the internal electrode layers contain a binder (e.g., a known organic binder) and a solvent (e.g., a known organic solvent).

[0125] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the ceramic green sheets by, for example, screen printing or gravure printing, to form an internal electrode pattern. Specifically, a conductive paste layer is formed by applying a paste made of a conductive material to the ceramic green sheets by a method such as the printing method described above. The conductive paste is, for example, a paste made of a metal powder to which an organic binder and an organic solvent have been added. Regarding the ceramic green sheets, ceramic green sheets for outer layers, on which no internal electrode pattern is printed, are also prepared.

[0126] Then, a laminated sheet is produced using the ceramic green sheets on which these internal electrode patterns are formed. That is, a predetermined number of ceramic green sheets for outer layers on which no internal electrode pattern is formed are laminated, and ceramic green sheets on which internal electrode patterns corresponding to the first internal electrode layer 16 a and those on which internal electrode patterns corresponding to the second internal electrode layer 16 b are formed are alternately laminated thereon, and a predetermined number of ceramic green sheets for outer layers on which no internal electrode pattern is formed are further laminated thereon to produce a laminated sheet.

[0127] Furthermore, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to prepare a laminated block.

[0128] The laminated block is then cut to a predetermined size to obtain laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0129] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0130] Next, a principal surface electrode 26 made of a thin film layer is formed on a portion of the second principal surface 12b of the laminate 12. The principal surface electrode 26, which is a thin film layer, can be formed by, for example, a sputtering method. In other words, the principal surface electrode 26, which is a thin film layer, is composed of a sputtered electrode. The sputtered electrode can be formed of a metal containing at least one selected from Ni, Cr, Cu, Ti, etc.

[0131] Thereafter, an underlayer plating layer 30 is formed so as to directly cover the principal surface electrode 26 made of a thin film layer and the first end face 12e and the second end face 12f of the laminate 12 on which the principal surface electrode 26 is not disposed. When forming the underlayer plating layer 30, electroplating using an electroplating bath containing an additive or electroless plating by a displacement reaction is performed.

[0132] Subsequently, an upper plating layer 32 is formed on the surface of the lower plating layer 30. The upper plating layer 32 contains at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc., and is formed as a single layer or multiple layers.

[0133] Preferably, the lower plating layer 30 is formed of a Ni plating layer, and the upper plating layer 32 is formed of a Sn plating layer so as to cover the lower plating layer 30 .

[0134] Next, a method for forming bumps 40 on the multilayer ceramic capacitor 10A in order to manufacture the multilayer ceramic electronic component 10 will be described.

[0135] First, a metal material paste containing at least one high-melting-point metal selected from Cu and Ni and Sn as a low-melting-point metal is prepared as the material for the bumps 40. Then, the metal material paste is formed into a desired pattern using a squeegee by screen printing on the multilayer ceramic capacitors 10A arranged on a holding substrate. For this purpose, for example, a masking jig is prepared and placed on the multilayer ceramic capacitors 10A arranged on the holding substrate. The masking jig includes, for example, a mask plate having a rectangular shape in a plan view. The masking plate has a plurality of through holes penetrating from one main surface to the other main surface. Each of the through holes has a rectangular shape in a plan view. The size of the rectangular shape in a plan view determines the size of the bumps 40. Then, a metal material paste that will become the first bump 40a is applied to the second main surface 12b side of the first external electrode 24a of the multilayer ceramic capacitor 10A, and a metal material paste that will become the second bump 40b is applied to the second main surface 12b side of the second external electrode 24b.

[0136] When forming the bumps 40, inkjet printing may also be used as a method for applying the metal material paste.

[0137] In this manner, the multilayer ceramic electronic component 10 shown in FIG. 1 can be manufactured.

[0138] B. Second Embodiment 1. Multilayer Ceramic Electronic Component An example of a multilayer ceramic electronic component 510 according to a second embodiment of the present invention will be described. In this embodiment, the multilayer ceramic electronic component 510 includes a multilayer ceramic capacitor 510A and bumps 540 and 541.

[0139] Fig. 28 is an external perspective view showing an example of a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig. 29 is a front view showing an example of a multilayer ceramic electronic component according to the second embodiment of the present invention. Fig. 30 is a bottom view showing an example of a multilayer ceramic electronic component according to the second embodiment of the present invention. Fig. 31 is a cross-sectional view taken along line XXXI-XXXI in Fig. 28. Fig. 32 is a cross-sectional view taken along line XXXII-XXXII in Fig. 28. Fig. 33 is a cross-sectional view taken along line XXXIII-XXXIII in Fig. 28. Fig. 34 is an exploded perspective view of the laminate shown in Fig. 28.

[0140] The multilayer ceramic capacitor 510A includes a laminate 512 and external electrodes 524 and 525 .

[0141] The laminate 512 includes a plurality of dielectric layers 514 and a plurality of internal electrode layers 516. The laminate 512 has a first main surface 512a and a second main surface 512b that face each other in a height direction x, a first side surface 512c and a second side surface 512d that face each other in a width direction y that is perpendicular to the height direction x, and a third side surface 512e and a fourth side surface 512f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The first main surface 512a and the second main surface 512b extend along the width direction y and the length direction z, respectively. The first side surface 512c and the second side surface 512d extend along the height direction x and the width direction y, respectively. The third side surface 512e and the fourth side surface 512f extend along the height direction x and the length direction y, respectively. Therefore, the height direction x is the direction connecting the first main surface 512a and the second main surface 512b, the width direction y is the direction connecting the first side surface 512c and the second side surface 512d, and the length direction z is the direction connecting the third side surface 512e and the fourth side surface 512f.

[0142] Furthermore, it is preferable that the corners and ridges of the laminate 512 are rounded. Here, a corner is a portion where three surfaces of the laminate 512 intersect, and a ridge is a portion where two surfaces of the laminate 512 intersect.

[0143] As shown in Figures 31 and 32, the laminate 512 has, in the height direction x connecting the first main surface 512a and the second main surface 512b, an effective layer portion 515a in which a plurality of internal electrode layers 516 face each other, a first outer layer portion 515b1 formed from a plurality of dielectric layers 514 located between the first main surface 512a and the internal electrode layer 516 located closest to the first main surface 512a, and a second outer layer portion 515b2 formed from a plurality of dielectric layers 514 located between the second main surface 512b and the internal electrode layer 516 located closest to the second main surface 512b.

[0144] The first outer layer portion 515b1 is located on the first main surface 512a side of the laminate 512, and is an assembly of multiple dielectric layers 514 located between the first main surface 512a and the internal electrode layer 516 closest to the first main surface 512a.

[0145] The second outer layer portion 515b2 is located on the second main surface 512b side of the laminate 512, and is an assembly of multiple dielectric layers 514 located between the second main surface 512b and the internal electrode layer 516 closest to the second main surface 512b.

[0146] The region sandwiched between the first outer layer portion 515b1 and the second outer layer portion 515b2 is the effective layer portion 515a. The thickness of the first outer layer portion 515b1 and the second outer layer portion 515b2 is preferably 3 μm or more and 15 μm or less. The region sandwiched between the outer layer portions 515b1 and 515b2 is the effective layer portion 515b. In other words, the effective layer portion 515a is the region where the internal electrode layers 416 are stacked.

[0147] The dielectric layer 514 can be formed of, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics whose main components are BaTiO3, CaTiO3, SrTiO3, and CaZnO3. Subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components.

[0148] The number of dielectric layers 514 is not particularly limited, but is preferably 5 to 2000, including the first outer layer portion 515b1 and the second outer layer portion 515b2. The thickness of the dielectric layers 514 is preferably 0.30 μm to 5.0 μm.

[0149] 31 to 34, the internal electrode layer 516 includes a plurality of first internal electrode layers 516a and a plurality of second internal electrode layers 516b. The first internal electrode layers 516a and the second internal electrode layers 516b are alternately stacked with the dielectric layer 514 interposed therebetween.

[0150] The first internal electrode layer 516a is disposed on the surface of the dielectric layer 514. The first internal electrode layer 516a faces the first main surface 512a and the second main surface 512b, has a first opposing electrode portion 518a facing the second internal electrode layer 516b, and is laminated in the direction connecting the first main surface 512a and the second main surface 512b.

[0151] The second internal electrode layer 516b is disposed on a surface of a dielectric layer 514 different from the dielectric layer 514 on which the first internal electrode layer 516a is disposed. The second internal electrode layer 516b has a second opposing electrode portion 518b opposing the first main surface 512a and the second main surface 512b, and is laminated in a direction connecting the first main surface 512a and the second main surface 512b.

[0152] 31 to 34 , the first internal electrode layer 516a is extended by a first extension electrode portion 520a to the first side surface 512c and the third side surface 512e of the laminate 512, and is extended by a second extension electrode portion 520b to the second side surface 512d and the fourth side surface 512f of the laminate 512. Note that the width of the first extension electrode portion 520a extended to the first side surface 512c may be approximately equal to the width of the first extension electrode portion 520a extended to the third side surface 512e, and the width of the second extension electrode portion 520b extended to the second side surface 512d may be approximately equal to the width of the second extension electrode portion 520b extended to the fourth side surface 512f. That is, the first extraction electrode portion 520 a is extracted to the third side surface 512 e side of the laminate 512 , and the second extraction electrode portion 520 b is extracted to the fourth side surface 512 f side of the laminate 512 .

[0153] The second internal electrode layer 516b is extended to the first side surface 512c and the fourth side surface 512f of the laminate 512 by the third extension electrode portion 521a, and is extended to the second side surface 512d and the third side surface 512e of the laminate 512 by the fourth extension electrode portion 521b. The width of the third extension electrode portion 521a extended to the first side surface 512c may be approximately equal to the width of the third extension electrode portion 521a extended to the fourth side surface 512f, and the width of the fourth extension electrode portion 521b extended to the second side surface 512d may be approximately equal to the width of the fourth extension electrode portion 521b extended to the third side surface 512e. In other words, the third extension electrode portion 521a is extended to the fourth side surface 512f side of the laminate 512, and the fourth extension electrode portion 521b is extended to the second side surface 512d side of the laminate 512.

[0154] Furthermore, when the multilayer ceramic capacitor 510A is viewed from the stacking direction, it is preferable that a straight line connecting the first extraction electrode portion 520a and the second extraction electrode portion 520b of the first internal electrode layer 516a intersects with a straight line connecting the third extraction electrode portion 521a and the fourth extraction electrode portion 521b of the second internal electrode layer 516b.

[0155] Furthermore, on the side surfaces 512c, 512d, 512e, and 512f of the laminate 512, it is preferable that the first extraction electrode portion 520a of the first internal electrode layer 516a and the fourth extraction electrode portion 521b of the second internal electrode layer 516b are extracted to opposing positions, and that the second extraction electrode portion 520b of the first internal electrode layer 516a and the third extraction electrode portion 521a of the second internal electrode layer 516b are extracted to opposing positions.

[0156] The internal electrode layers 516 may be made of a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing one of these metals, such as an Ag-Pd alloy. The internal electrode layers 516 may further contain dielectric particles having the same composition as the ceramics contained in the dielectric layers 514.

[0157] Furthermore, the first internal electrode layer 516 a and the second internal electrode layer 516 b may contain Sn. By containing Sn in the first internal electrode layer 516 a and the second internal electrode layer 516 b, it is possible to alleviate electric field concentration at the interface between the first internal electrode layer 516 a and the second internal electrode layer 516 b and the dielectric layer 514, leading to improvement in high-temperature load reliability. In this case, even if Sn is contained in only one of the internal electrode layers 516, either the first internal electrode layer 516 a or the second internal electrode layer 516 b, it is possible to sufficiently exhibit the effect.

[0158] The number of laminated internal electrode layers 516 is preferably 20 to 80. The average thickness of the internal electrode layers 516 is preferably 0.2 μm to 2.0 μm.

[0159] As shown in FIG. 33, the laminate 512 also includes a side portion (L gap) 522b of the laminate 512 formed between one end of the first opposing electrode portion 518a in the longitudinal direction z and the third side surface 512e, and between the other end of the second opposing electrode portion 518b in the longitudinal direction z and the fourth side surface 512f.

[0160] Furthermore, as shown in FIG. 33, the laminate 512 includes a side portion (W gap) 522a of the laminate 512 formed between one end in the width direction y of the first opposing electrode portion 518a and the first side surface 512c, and between the other end in the width direction y of the second opposing electrode portion 518b and the second side surface 512d.

[0161] As shown in FIGS. 28 to 33, external electrodes 524 and 525 are disposed on the laminate 512.

[0162] The external electrode 524 includes a principal surface electrode 526 and a plating layer 528 formed so as to cover the principal surface electrode 526. The external electrode 525 includes a principal surface electrode 527 and a plating layer 529 formed so as to cover the principal surface electrode 527.

[0163] The external electrode 524 includes a first external electrode 524a and a second external electrode 524b.

[0164] The first external electrode 524a is disposed so as to cover the first lead electrode portion 520a on the first side surface 512c and the third side surface 512e, and so as to cover parts of the first main surface 512a and the second main surface 512b. The first external electrode 524a is electrically connected to the first lead electrode portion 520a of the first internal electrode layer 516a.

[0165] The second external electrode 524b is disposed so as to cover the second lead electrode portion 520b on the second side surface 512d and the fourth side surface 512f, and so as to cover a part of the first main surface 512a and the second main surface 512b. The second external electrode 524b is electrically connected to the second lead electrode portion 520b of the first internal electrode layer 516a.

[0166] The external electrode 525 includes a third external electrode 525a and a fourth external electrode 525b.

[0167] The third external electrode 525a is arranged so as to cover the third lead electrode portion 521a on the first side surface 512c and the fourth side surface 512f, and is arranged so as to cover parts of the first main surface 512a and the second main surface 512b. The third external electrode 525a is electrically connected to the third lead electrode portion 521a of the second internal electrode layer 516b.

[0168] The fourth external electrode 525b is disposed so as to cover the fourth extraction electrode portion 521b on the second side surface 512d and the third side surface 512e, and so as to cover parts of the first principal surface 512a and the second principal surface 512b. The fourth external electrode 525b is electrically connected to the fourth extraction electrode portion 521b of the second internal electrode layer 516b.

[0169] In the laminate 512, a capacitance is formed by the first opposing electrode portion 518a of the first internal electrode layer 516a and the second opposing electrode portion 518b of the second internal electrode layer 516b opposing each other via the dielectric layer 514. Therefore, a capacitance can be obtained between the first external electrode 524a and the second external electrode 524b to which the first internal electrode layer 516a is connected and the third external electrode 525a and the fourth external electrode 525b to which the second internal electrode layer 516b is connected, thereby exhibiting the characteristics of a capacitor.

[0170] The principal surface electrode 526 includes a first principal surface electrode 526a1, a second principal surface electrode 526b1, a third principal surface electrode 526a2, and a fourth principal surface electrode 526b2. The first principal surface electrode 526a1, the second principal surface electrode 526b1, the third principal surface electrode 526a2, and the fourth principal surface electrode 526b2 are formed of thin film layers made up of a plurality of thin film electrodes to further improve performance.

[0171] The first principal surface electrode 526a1 is formed to cover a portion of the second principal surface 512b at a corner where the second principal surface 512b, the first side surface 512c, and the third side surface 512e intersect. The second principal surface electrode 526b1 is formed to cover a portion of the second principal surface 512b at a corner where the second principal surface 512b, the second side surface 512d, and the fourth side surface 512f intersect. The third principal surface electrode 526a2 is formed to cover a portion of the first principal surface 512a at a corner where the first principal surface 512a, the first side surface 512c, and the third side surface 512e intersect. The fourth principal surface electrode 526b2 is formed to cover a portion of the first principal surface 512a at a corner where the first principal surface 512a, the second side surface 512d, and the fourth side surface 512f intersect.

[0172] The principal surface electrode 527 includes a fifth principal surface electrode 527a1, a sixth principal surface electrode 527b1, a seventh principal surface electrode 527a2, and an eighth principal surface electrode 527b2. These fifth principal surface electrode 527a1, sixth principal surface electrode 527b1, seventh principal surface electrode 527a2, and eighth principal surface electrode 527b2 are formed of thin film layers made up of a plurality of thin film electrodes to further improve performance.

[0173] The fifth principal surface electrode 527a1 is formed to cover a portion of the second principal surface 512b at a corner where the second principal surface 512b, the first side surface 512c, and the fourth side surface 512f intersect. The sixth principal surface electrode 527b1 is formed to cover a portion of the second principal surface 512b at a corner where the second principal surface 512b, the second side surface 512d, and the third side surface 512e intersect. The seventh principal surface electrode 527a2 is formed to cover a portion of the first principal surface 512a at a corner where the first principal surface 512a, the first side surface 512c, and the fourth side surface 512f intersect. The eighth principal surface electrode 527b2 is formed to cover a portion of the second principal surface 512b at a corner where the second principal surface 512b, the second side surface 512d, and the third side surface 512e intersect.

[0174] The principal surface electrodes 526, 527 formed from thin film layers are preferably formed by a thin film formation method such as sputtering or vapor deposition. In particular, the principal surface electrodes 526, 527 formed from thin film layers are preferably sputtered electrodes formed by sputtering. Electrodes formed by sputtering will be described below.

[0175] When the principal surface electrodes 526 and 527 are formed by sputtering, it is preferable to form the sputtered electrodes directly on a part of the first principal surface 512 a and a part of the second principal surface 512 b of the laminate 512 .

[0176] The principal surface electrodes 526, 527 may also contain a metal such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au. In this case, the principal surface electrodes 526, 527 preferably contain, as a common material, the same dielectric material as the dielectric ceramic contained in the dielectric layer 514. By including the common material, the shrinkage behavior of the principal surface electrodes 526, 527 during firing can be made closer to the shrinkage behavior of the laminate 512, and peeling of the principal surface electrodes 526, 527 from the laminate 512 can be prevented.

[0177] The plating layer 528 includes a first plating layer 528a and a second plating layer 528b. The first plating layer 528a is disposed so as to cover the first principal surface electrode 526a1 and the third principal surface electrode 526a2. The second plating layer 528b is disposed so as to cover the second principal surface electrode 526b1 and the fourth principal surface electrode 526b2.

[0178] The plating layer 529 includes a third plating layer 529a and a fourth plating layer 529b. The third plating layer 529a is disposed so as to cover the fifth principal surface electrode 527a1 and the seventh principal surface electrode 527a2. The fourth plating layer 529b is disposed so as to cover the sixth principal surface electrode 527b1 and the eighth principal surface electrode 528b2.

[0179] The plating layer 528 and the plating layer 529 may each be formed of multiple layers. Preferably, the plating layer 528 includes a lower plating layer 530 covering the principal surface electrode 526 and an upper plating layer 532 arranged to cover the lower plating layer 530. Similarly, the plating layer 529 includes a lower plating layer 531 covering the principal surface electrode 527 and an upper plating layer 533 arranged to cover the lower plating layer 531. Of the plating layers 528, the upper plating layer 532 includes at least one selected from, for example, Ni, Sn, Cu, Ag, Pd, an Ag—Pd alloy, Au, etc. Similarly, of the plating layers 529, the upper plating layer 533 includes at least one selected from, for example, Ni, Sn, Cu, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0180] The lower plating layer 530 includes a first lower plating layer 530a and a second lower plating layer 530b.

[0181] The first lower layer plating layer 530a is arranged on the first side 512c and third side 512e of the laminate 512 where no principal surface electrodes are arranged, and further arranged so as to cover the first principal surface electrode 526a1 arranged on the second principal surface 512b and the third principal surface electrode 526a2 arranged on the first principal surface 512a.

[0182] The second lower layer plating layer 530b is arranged on the second side surface 512d and the fourth side surface 512f of the laminate 512 where no principal surface electrodes are arranged, and further arranged so as to cover the second principal surface electrode 526b1 arranged on the second principal surface 512b and the fourth principal surface electrode 526b2 arranged on the first principal surface 512a.

[0183] The lower plating layer 531 includes a third lower plating layer 531a and a fourth lower plating layer 531b.

[0184] The third lower layer plating layer 531a is arranged on the first side 512c and fourth side 512f of the laminate 512 where no principal surface electrodes are arranged, and is further arranged so as to cover the fifth principal surface electrode 527a1 arranged on the second principal surface 512b and the seventh principal surface electrode 527a2 arranged on the first principal surface 512a.

[0185] The fourth lower layer plating layer 531b is arranged on the second side 512d and the third side 512e of the laminate 512 where no principal surface electrodes are arranged, and is further arranged so as to cover the sixth principal surface electrode 527b1 arranged on the second principal surface 512b and the eighth principal surface electrode 527b2 arranged on the first principal surface 512a.

[0186] The thickness of each of the lower plating layers 530, 531 is preferably 2 μm or more and 11 μm or less.

[0187] The upper plating layer 532 includes a first upper plating layer 532a and a second upper plating layer 532b.

[0188] The first upper plating layer 532a is disposed so as to cover the first lower plating layer 530a. Specifically, the first upper plating layer 532a is disposed on the first side surface 512c and the third side surface 512e of the surface of the first lower plating layer 530a, and preferably extends to the first main surface 512a and the second main surface 512b of the surface of the first lower plating layer 530a.

[0189] The second upper plating layer 532b is disposed so as to cover the second lower plating layer 530b. Specifically, the second upper plating layer 532b is disposed on the second side surface 512d and the fourth side surface 512f of the surface of the second lower plating layer 530b, and preferably extends to the first main surface 512a and the second main surface 512b of the surface of the second lower plating layer 530b.

[0190] The upper plating layer 533 includes a third upper plating layer 533a and a fourth upper plating layer 533b.

[0191] The third upper plating layer 533a is disposed so as to cover the third lower plating layer 531a. Specifically, the third upper plating layer 533a is disposed on the first side surface 512c and the fourth side surface 512f of the surface of the third lower plating layer 531a, and preferably extends to the first main surface 512a and the second main surface 512b of the surface of the third lower plating layer 531a.

[0192] The fourth upper plating layer 533b is disposed so as to cover the fourth lower plating layer 531b. Specifically, the fourth upper plating layer 533b is disposed on the second side surface 512d and the third side surface 512e of the surface of the fourth lower plating layer 531b, and preferably extends to the first main surface 512a and the second main surface 512b of the surface of the fourth lower plating layer 531b.

[0193] In this embodiment, the lower plating layers 530, 531 are Ni plating layers, and the upper plating layers 532, 533 are Sn plating layers, forming a two-layer structure. By using Ni plating layers for the lower plating layers 530, 531, it is possible to prevent the main surface electrodes 526, 527 from being eroded by solder when mounting the multilayer ceramic electronic component 10 on a mounting substrate. By using Sn plating layers for the upper plating layers 532, 533, it is possible to improve the wettability of solder when mounting the multilayer ceramic electronic component 510 on a mounting substrate, thereby facilitating mounting of the multilayer ceramic electronic component 510.

[0194] The thickness of each of the upper plating layers 532, 533 is preferably 2 μm or more and 11 μm or less.

[0195] The bumps 540 included in the multilayer ceramic electronic component 510 include a first bump 540a and a second bump 540b. The bumps 541 included in the multilayer ceramic electronic component 510 include a third bump 541a and a fourth bump 541b.

[0196] The first bump 540a is disposed on the surface of the first external electrode 524a facing the second main surface 512b, and the second bump 540b is disposed on the surface of the second external electrode 524b facing the second main surface 512b.

[0197] The third bump 541a is disposed on the surface of the third external electrode 525a facing the second main surface 512b, and the fourth bump 541b is disposed on the surface of the fourth external electrode 525b facing the second main surface 512b.

[0198] In the multilayer ceramic electronic component 510 according to the present invention, the second main surface 512b serves as the mounting surface facing the mounting substrate.

[0199] The bumps 540, 541 are primarily composed of an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni and Sn as a low-melting-point metal. The intermetallic compound is preferably an intermetallic compound formed by the reaction of Sn with a Cu-Ni alloy. Such an intermetallic compound has the advantages of a fast reaction rate and minimal change in shape during its formation. The high-melting-point metal constituting the intermetallic compound may further contain Ag.

[0200] When the thickness of each of the first bump 540a, the second bump 540b, the third bump 541a, and the fourth bump 541b in the height direction x is t1 and the thickness of the laminate 12 in the height direction x is t2, the condition 0.5<t1 / t2<0.75 is satisfied.

[0201] Here, the thickness t1 of each of the first bump 540 a, the second bump 540 b, the third bump 541 a, and the fourth bump 541 b in the height direction x, and the thickness t2 of the laminate 512 in the height direction x are measured, for example, by observing the appearance with a digital microscope (VHX-8000 manufactured by Keyence Corporation) at a magnification of 500 times or more and 2000 times or less.

[0202] When the dimension in the width direction y of each of the first bump 540a, the second bump 540b, the third bump 541a, and the fourth bump 541b is w3 and the dimension in the width direction y of the laminate 512 is w4, it is preferable to satisfy the condition 1 / 5<w3 / w4<1 / 4.

[0203] When the dimension of each of the first bump 540a, the second bump 540b, the third bump 541a, and the fourth bump 541b in the longitudinal direction z is w5 and the dimension of the laminate 512 in the longitudinal direction z is w6, it is preferable to satisfy the condition 1 / 5<w5 / w6<1 / 4.

[0204] Here, the dimension w3 in the width direction y of each of the first bump 540a, the second bump 540b, the third bump 541a, and the fourth bump 541b, and the thickness w4 in the width direction y of the laminate 512 are measured, for example, by observing the exterior with a digital microscope (VHX-8000, manufactured by Keyence Corporation) at a magnification of 500 to 2000 times. Similarly, the dimension w5 in the length direction z of each of the first bump 540a, the second bump 540b, the third bump 541a, and the fourth bump 541b, and the thickness w6 in the length direction z of the laminate 512 are measured, for example, by observing the exterior with a digital microscope (VHX-8000, manufactured by Keyence Corporation) at a magnification of 500 to 2000 times.

[0205] The Vickers hardness (HV) of the first bump 540a, the second bump 540b, the third bump 541a and the fourth bump 541b is preferably 30 or more and 40 or less.

[0206] The dimension in the length direction z of the multilayer ceramic capacitor 510A including the laminate 512 and the external electrodes 524, 525 is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 510A including the laminate 12 and the external electrodes 524, 525 is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 510A including the laminate 12 and the external electrodes 524, 525 is defined as dimension W. The dimensions of the multilayer ceramic capacitor 510A are preferably such that the dimension L in the length direction z is 0.1 mm or more and 6.0 mm or less, and the dimension W in the width direction y is 0.1 mm or more and 6.0 mm or less. Here, it is preferable that 7 / 10≦L / W≦10 / 7. This gives the multilayer ceramic capacitor a substantially tetragonal shape, thereby increasing the degree of freedom in mounting.

[0207] According to the multilayer ceramic electronic component 510 shown in FIG. 27, in a multilayer ceramic capacitor 510A, a first bump 540a is arranged on the surface of the first external electrode 524a facing the second main surface 12b, a second bump 540b is arranged on the surface of the second external electrode 524b facing the second main surface 12b, a third bump 541a is arranged on the surface of the third external electrode 525a facing the second main surface 512b, and a fourth bump 541b is arranged on the surface of the fourth external electrode 525b facing the second main surface 512b. When the thickness in the height direction x of each of the first bump 540b, the third bump 541a, and the fourth bump 541b is taken as t1 and the thickness in the height direction x of the laminate 12 is taken as t2, the condition 0.5<t1 / t2<0.75 is satisfied, and therefore, particularly when the thin multilayer ceramic electronic component 510 is mounted on a mounting board, the impact of the mounter nozzle on the multilayer ceramic electronic component 10 is transmitted to the bump 40, and damage to the laminate due to stress concentration at the edge portions of the external electrodes located on the main surface side of the multilayer ceramic capacitor caused by the impact can be mitigated.

[0208] 2. Modification of the Second Embodiment Next, a multilayer ceramic capacitor according to a modification of the second embodiment of the present invention will be described. FIG. 35 is an external perspective view showing an example of a multilayer ceramic electronic component according to a first modification of the second embodiment of the present invention. FIG. 36 is a front view showing an example of a multilayer ceramic electronic component according to a modification of the second embodiment of the present invention. FIG. 37 is a bottom view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to a modification of the second embodiment of the present invention. FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 35. FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. 35.

[0209] In the multilayer ceramic electronic component 610 shown in FIG. 35, the same components as those in the multilayer ceramic electronic component 610 shown in FIGS. 28 to 34 are designated by the same reference numerals, and the description thereof will be omitted.

[0210] The multilayer ceramic electronic component 610 according to the second modification includes a multilayer ceramic capacitor 610A and bumps 540.

[0211] The multilayer ceramic capacitor 610A includes a rectangular parallelepiped laminate 512 and external electrodes 624 and 625 .

[0212] The external electrode 624 includes a principal surface electrode 526 and a plating layer 528 formed so as to cover the principal surface electrode 526. The external electrode 625 includes a principal surface electrode 527 and a plating layer 529 formed so as to cover the principal surface electrode 527.

[0213] The external electrodes 624 include a first external electrode 624b and a second external electrode 624b.

[0214] The first external electrode 624a is disposed so as to cover the first lead electrode portion 520a on the first side surface 512c and the third side surface 512e, and is disposed so as to cover a part of the second main surface 512b. The first external electrode 624a is electrically connected to the first lead electrode portion 520a of the first internal electrode layer 516a.

[0215] The second external electrode 624b is disposed so as to cover the second lead electrode portion 520b on the second side surface 512d and the fourth side surface 512f, and so as to cover a part of the second main surface 512b. The second external electrode 624b is electrically connected to the second lead electrode portion 520b of the first internal electrode layer 516a.

[0216] The external electrodes 625 include a third external electrode 625a and a fourth external electrode 625b.

[0217] The third external electrode 625a is disposed so as to cover the third lead electrode portion 521a on the first side surface 512c and the fourth side surface 512f, and is disposed so as to cover a part of the second main surface 512b. The third external electrode 625a is electrically connected to the third lead electrode portion 521a of the second internal electrode layer 516b.

[0218] The fourth external electrode 625b is disposed so as to cover the fourth extraction electrode portion 521b on the second side surface 512d and the third side surface 512e, and is disposed so as to cover a part of the second main surface 512b. The fourth external electrode 625b is electrically connected to the fourth extraction electrode portion 521b of the second internal electrode layer 516b.

[0219] The plating layer 528 includes a first plating layer 528a and a second plating layer 528b. The first plating layer 528a is disposed so as to cover the first principal surface electrode 526a1. The second plating layer 528b is disposed so as to cover the second principal surface electrode 526b1.

[0220] The plating layer 529 includes a third plating layer 529a and a fourth plating layer 529b. The third plating layer 529a is disposed so as to cover the fifth principal surface electrode 527a1. The fourth plating layer 529b is disposed so as to cover the sixth principal surface electrode 527b1. The structure of the plating layers 530, 531 of the multilayer ceramic capacitor 610A according to this modification is the same as the structure of the plating layers 530, 531 of the multilayer ceramic capacitor 510A.

[0221] The bumps 540 included in the multilayer ceramic electronic component 610 include a first bump 540a and a second bump 540b. The bumps 541 included in the multilayer ceramic electronic component 510 include a third bump 541a and a fourth bump 541b.

[0222] The first bump 540a is disposed on the surface of the first external electrode 524a facing the second main surface 512b, and the second bump 540b is disposed on the surface of the second external electrode 524b facing the second main surface 512b.

[0223] The third bump 541a is disposed on the surface of the third external electrode 525a facing the second main surface 512b, and the fourth bump 541b is disposed on the surface of the fourth external electrode 525b facing the second main surface 512b.

[0224] 35 provides the same effects as the multilayer ceramic electronic component 510 described above, as well as the following effects. Specifically, because the external electrodes 624, 625 are not formed on the first main surface 12a, the thickness of the laminate 512 can be increased accordingly, thereby improving the strength of the multilayer ceramic capacitor 610A and increasing the capacitance per volume. Furthermore, because solder is prevented from wetting onto the upper surface (first main surface 512a) of the multilayer ceramic capacitor 610A during mounting, the thickness of the laminate 512 can be increased accordingly.

[0225] 3. Method for Manufacturing the Multilayer Ceramic Electronic Component Next, a method for manufacturing the multilayer ceramic electronic component 510 according to the second embodiment will be described. First, a method for manufacturing the multilayer ceramic capacitor 510A of the multilayer ceramic electronic component 510 will be described.

[0226] First, ceramic green sheets and a conductive paste for the internal electrodes are prepared. The ceramic green sheets and the conductive paste for the internal electrodes contain a binder (e.g., a known organic binder) and a solvent (e.g., an organic solvent).

[0227] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the ceramic green sheets by, for example, screen printing or gravure printing, to form an internal electrode pattern as shown in Figure 33. Specifically, a conductive paste layer is formed by applying a paste made of a conductive material to the ceramic green sheets by a method such as the printing method described above. The conductive paste is, for example, a paste made of a metal powder to which an organic binder and an organic solvent have been added. Note that, regarding the ceramic green sheets, ceramic green sheets for outer layers on which no internal electrode pattern is printed are also prepared.

[0228] Then, a laminated sheet is produced using the ceramic green sheets on which these internal electrode patterns have been formed. That is, a predetermined number of ceramic green sheets for outer layers on which no internal electrode patterns have been formed are stacked, and ceramic green sheets on which internal electrode patterns corresponding to the first internal electrode layer 516a and ceramic green sheets on which internal electrode patterns corresponding to the second internal electrode layer 516b have been formed are alternately stacked thereon, and a predetermined number of ceramic green sheets on which no internal electrode patterns have been formed are further stacked thereon to produce a laminated sheet.

[0229] Furthermore, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to prepare a laminated block.

[0230] The laminated block is then cut to a predetermined size to produce a laminated chip, which may have its corners and ridges rounded by barrel polishing or the like.

[0231] Next, the laminated chip is fired to produce laminate 512. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1300° C. or lower.

[0232] At this time, the first extraction electrode portion 520a of the first internal electrode layer 516a is exposed from the first side surface 512c and the third side surface 512e of the laminate 512, and the third extraction electrode portion 521a of the second internal electrode layer 516b is exposed from the first side surface 512c and the fourth side surface 512f of the laminate 512. Furthermore, the second extraction electrode portion 520b of the first internal electrode layer 516a is exposed from the second side surface 512d and the fourth side surface 512f of the laminate 512, and the fourth extraction electrode portion 521b of the second internal electrode layer 516b is exposed from the second side surface 512d and the third side surface 512e of the laminate 512.

[0233] Next, principal surface electrodes 526, 527 made of thin-film electrode layers are formed on a portion of the first principal surface 512a and a portion of the second principal surface 512b of the laminate 512. The principal surface electrodes 526, 527, which are thin-film layers, can be formed by, for example, a sputtering method. In other words, the principal surface electrodes, which are thin-film layers, are composed of sputtered electrodes. The sputtered electrodes can be formed of a metal containing at least one selected from Ni, Cr, Cu, Ti, etc.

[0234] When external electrodes 624 and 625 are formed such that no external electrodes are disposed on the first principal surface 512a, as in the multilayer ceramic capacitor 610A, principal surface electrodes 526 and 527 are not formed on the first principal surface 512a.

[0235] Then, a Cu plating layer, which is the first underlayer plating layer 530a, is formed on the first side surface 512c and the third side surface 512e of the laminate 512 on which no principal surface electrodes are arranged, and further covering the first principal surface electrode 526a1 arranged on the second principal surface 512b and the third principal surface electrode 526a2 arranged on the first principal surface 512a, and a Cu plating layer, which is the second underlayer plating layer 530b, is formed on the second side surface 512d and the fourth side surface 512f of the laminate 512 on which no principal surface electrodes are arranged, and further covering the second principal surface electrode 526b1 arranged on the second principal surface 512b and the fourth principal surface electrode 526b2 arranged on the first principal surface 512a. Furthermore, a Cu plating layer serving as a third underlayer plating layer 531a is formed so as to cover the fifth principal surface electrode 527a1 arranged on the second principal surface 512b and the seventh principal surface electrode 527a2 arranged on the first principal surface 512a, which are disposed on the first side surface 512c and the fourth side surface 512f of the laminate 512 where no principal surface electrodes are disposed, and further, the Cu plating layer serving as a fourth underlayer plating layer 531b is formed so as to cover the sixth principal surface electrode 527b1 arranged on the second principal surface 512b and the eighth principal surface electrode 527b2 arranged on the first principal surface 512a, which are disposed on the second side surface 512d and the third side surface 512e of the laminate 512 where no principal surface electrodes are disposed. The underlayer plating layers 530a, 530b, 531a, and 531b are formed by electroplating using an electroplating bath containing an additive, or by electroless plating by a displacement reaction.

[0236] Next, an upper plating layer 532 is formed on the surface of the lower plating layer 530, and an upper plating layer 533 is formed on the surface of the lower plating layer 531. The upper plating layers 532, 533 contain at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc., and are formed as a single layer or multiple layers. Preferably, the upper plating layers 532, 533 are formed as two layers, with a Ni plating layer and a Sn plating layer formed on the Ni plating layer. In this manner, external electrodes 524, 525 are formed, as shown in FIG. 27 .

[0237] Next, a method for forming bumps 540 and 541 on the multilayer ceramic capacitor 510A in order to manufacture the multilayer ceramic electronic component 510 will be described.

[0238] First, a metal material paste containing at least one high-melting-point metal selected from Cu and Ni and Sn as a low-melting-point metal is prepared as the material for the bumps 540 and 541. Then, the metal material paste is formed into a desired pattern using a squeegee by screen printing on the multilayer ceramic capacitors 510A aligned on the holding substrate. For this purpose, for example, a masking jig is prepared and placed on the multilayer ceramic capacitors 510A aligned on the holding substrate. The masking jig includes, for example, a mask plate having a rectangular shape in a plan view. The masking plate has a plurality of through holes penetrating from one main surface to the other main surface. Each of the through holes has a rectangular shape in a plan view. The size of the rectangular shape in a plan view determines the size of the bumps 540 and 541. Then, a metal material paste to form the first bump 540a is applied to the second main surface 512b side of the first external electrode 524a of the multilayer ceramic capacitor 510A, and a metal material paste to form the second bump 540b is applied to the second main surface 12b side of the second external electrode 524b. Similarly, a metal material paste to form the third bump 541a is applied to the second main surface 512b side of the third external electrode 525a of the multilayer ceramic capacitor 510A, and a metal material paste to form the fourth bump 541b is applied to the second main surface 12b side of the fourth external electrode 525b.

[0239] When forming the bumps 540 and 541, inkjet printing may also be used as a method for applying the metal material paste.

[0240] In this manner, a multilayer ceramic electronic component 510 as shown in FIG. 28 is manufactured.

[0241] As described above, although the embodiments of the present invention have been disclosed in the above description, the present invention is not limited thereto. In other words, various changes can be made to the above-described embodiments and modifications in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such changes are included in the present invention.

[0242] <1> A multilayer ceramic electronic component comprising: a laminate including a plurality of stacked dielectric layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first end faces and second end faces opposing each other in a length direction perpendicular to the height direction and the width direction; first external electrodes arranged on at least the first end faces and the second main surfaces of the laminate; and second external electrodes arranged on at least the second end faces and the second main surfaces of the laminate; and bumps arranged on surfaces of the first external electrodes and the second external electrodes on the second main surface side of the laminate, wherein when a thickness of the bump in the height direction is t1 and a thickness of the laminate in the height direction is t2, a condition of 0.5<t1 / t2<0.75 is satisfied.

[0243] <2> A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated dielectric layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and third and fourth side surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; and at least four external electrodes arranged on two or more of six surfaces of the laminate, namely the first and second main surfaces, the first and second side surfaces, and the third and fourth side surfaces; and bumps arranged on surfaces of the at least four external electrodes on the second main surface side of the laminate, wherein when a thickness of the bump in the height direction is t1 and a thickness of the laminate in the height direction is t2, a condition of 0.5<t1 / t2<0.75 is satisfied.

[0244] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the bumps have a Vickers hardness (HV) of 30 or more and 40 or less.

[0245] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the bumps are made of an intermetallic compound.

[0246] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the dimension of the laminate in the height direction is 110 μm or less.

[0247] The present invention relates to a multilayer ceramic electronic component, and can be effectively used in particular when mounting the multilayer ceramic electronic component on a mounting board using a mounter.

[0248] 10, 110, 210, 310, 510, 610 Multilayer ceramic electronic component 10A, 110A, 210A, 310A, 510A, 610A Multilayer ceramic capacitor 12, 512 Laminate 12a, 512a First main surface 12b, 512b Second main surface 12c, 512c First side surface 12d, 512d Second side surface 12e First end surface 12f Second end surface 512e Third side surface 512f Fourth side surface 14, 514 Dielectric layer 15a, 515a Effective layer portion 15b1, 515b1 First outer layer portion 15b2, 515b2 Second outer layer portion 16, 516 Internal electrode layer 16a, 516a First internal electrode layer 16b, 516b Second internal electrode layer 18a, 518a First opposing electrode portion 18b, 518b Second opposing electrode portion 20a, 520a First lead electrode portion 20b, 520b Second lead electrode portion 521a Third lead electrode portion 521b Fourth lead electrode portion 22a, 522a Side portion (W gap) 22b, 522b End portion (L gap) 24, 124, 224, 324, 524, 525, 624, 625 External electrode 24a, 124a, 224a, 324a, 524a, 624a First external electrode 24b, 124b, 224b, 324b, 524b, 624b Second external electrode 525a, 625a Third external electrode 525b, 625b Fourth external electrode 26, 526, 527 Principal surface electrode 26a1, 526a1 First principal surface electrode 26b1, 526b1 Second principal surface electrode 26a2, 526a2 Third principal surface electrode 26b2, 526b2 Fourth principal surface electrode 527a1 Fifth principal surface electrode 527b1 Sixth principal surface electrode 527a2 Seventh principal surface electrode 527b2 Eighth principal surface electrode 28, 528, 529 Plating layer 28a, 528a First plating layer 28b, 528b Second plating layer 529a Third plating layer 529b Fourth plating layer 30, 530, 531 Underlayer plating layer 30a, 530a First underlayer plating layer 30b, 530b Second lower plating layer 531a Third lower plating layer 531b Fourth lower plating layer 32, 532, 533 Upper plating layer 32a, 532a First upper plating layer32b, 532b Second upper plating layer 533a Third upper plating layer 533b Fourth upper plating layer 40, 540, 541 Bump 40a, 540a First bump 40b, 540b Second bump 541a Third bump 541b Fourth bump 60 Mounting substrate 62 Core material of substrate 62a Substrate-side mounting surface 64 Conductive land 64a First conductive land 64b Second conductive land 70 Mounter nozzle x Height direction y Width direction z Length direction

Claims

1. A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated dielectric layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first end faces and second end faces opposing each other in a length direction perpendicular to the height direction and the width direction; first external electrodes arranged on at least the first end faces and the second main surfaces of the laminate; and second external electrodes arranged on at least the second end faces and the second main surfaces of the laminate; and bumps arranged on the surfaces of the first external electrodes and the second external electrodes on the second main surface side of the laminate, wherein when the thickness of the bump in the height direction is t1 and the thickness of the laminate in the height direction is t2, the condition of 0.5<t1 / t2<0.75 is satisfied.

2. A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated dielectric layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a third side surface and a fourth side surface opposing each other in a length direction perpendicular to the height direction and the width direction; and at least four external electrodes arranged on two or more of six surfaces of the laminate, namely the first main surface and the second main surface, the first side surface and the second side surface, and the third side surface and the fourth side surface; and bumps arranged on the surfaces of the at least four external electrodes on the second main surface side of the laminate, wherein when the thickness of the bump in the height direction is t1 and the thickness of the laminate in the height direction is t2, the condition of 0.5<t1 / t2<0.75 is satisfied.

3. A multilayer ceramic electronic component according to claim 1 or 2, wherein the Vickers hardness (HV) of the bumps is 30 or more and 40 or less.

4. A multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the bumps are made of an intermetallic compound.

5. A multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the height of the laminate is 110 µm or less.

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