Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: at least one semiconductor unit; a heat dissipation member to which the semiconductor unit is fixed; and a first bonding layer interposed between the semiconductor unit and the heat dissipation member. The semiconductor unit includes: a substrate; a semiconductor element mounted on the substrate; and a sealing resin covering the semiconductor element and part of the substrate. The heat dissipation member includes: a main surface facing a first side in a first direction; and, in a second direction intersecting the first direction, a first surface located on a first side in the second direction and a second surface located on a second side in the second direction, with the main surface interposed therebetween. The first bonding layer is fixed to the main surface and is located between the first surface and the second surface in the second direction.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] An example of a conventional semiconductor device is disclosed in Patent Document 1. The semiconductor device described in this document includes a conductive substrate, a semiconductor element, and a sealing resin.

[0003] A semiconductor device may be used in a state where the conductive substrate is fixed to a heat dissipation member such as a heat sink.

[0004] JP 2023-166572 A

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device and a method for manufacturing the semiconductor device. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can more appropriately bond a substrate and a heat dissipation member.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: one or more semiconductor units; a heat dissipation member to which the semiconductor units are fixed; and a first bonding layer interposed between the semiconductor units and the heat dissipation member. The semiconductor units include a substrate, a semiconductor element mounted on the substrate, and a sealing resin covering a portion of the substrate and the semiconductor element. The heat dissipation member includes a main surface facing a first side in a first direction, and a first surface located on a first side and a second surface located on a second side, sandwiching the main surface in a second direction intersecting the first direction. The first bonding layer is fixed to the main surface and is located between the first surface and the second surface in the second direction.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes the steps of: preparing a heat dissipation member including a main surface facing a first side in a first direction, and a first surface located on the first side and a second surface located on the second side of the main surface in a second direction intersecting the first direction; placing a first bonding layer on the main surface between the first surface and the second surface in the second direction; and bonding the heat dissipation member and a substrate via the first bonding layer by solid-state diffusion bonding.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a right side view of the semiconductor device shown in FIG. 1. FIG. 4 is a front view of the semiconductor device shown in FIG. 1. FIG. 5 is a rear view of the semiconductor device shown in FIG. 1. FIG. 6 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 7 is a partial plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a partial cross-sectional view taken along line X-X in FIG. 7. FIG. 11 is a partial cross-sectional view taken along line XI-XI in FIG. 7. FIG. 12 is a partial enlarged cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 13 is a partial enlarged cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial cross-sectional view taken along line XIV-XIV in FIG. 7. FIG. 15 is a partial cross-sectional view taken along line XV-XV in FIG. 7. 16 is a partially enlarged cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a plan view of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 20 is a plan view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 21 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 23 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 25 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 26 is a system configuration diagram of a vehicle including the semiconductor device according to the first embodiment of the present disclosure. FIG. 27 is a partially enlarged cross-sectional view of a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 28 is a partially enlarged cross-sectional view of the first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 29 is a partially enlarged cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure.FIG. 30 is a partially enlarged cross-sectional view of a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 31 is a partially enlarged cross-sectional view of a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 32 is a partially enlarged cross-sectional view of a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 33 is a partially plan view of a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 34 is a partially plan view of a sixth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 35 is a partially plan view of a seventh modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 36 is a perspective view of an eighth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 37 is a partially cross-sectional view of a semiconductor device according to the second embodiment of the present disclosure. FIG. 38 is a partially cross-sectional view of a semiconductor device according to the second embodiment of the present disclosure. FIG. 39 is a partially enlarged cross-sectional view of a semiconductor device according to the second embodiment of the present disclosure. FIG. 40 is a partially plan view of a semiconductor device according to the second embodiment of the present disclosure. FIG. 41 is a partially cross-sectional view of a first modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 42 is a partially cross-sectional view of a second modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 43 is a partially cross-sectional view of a semiconductor device according to the third embodiment of the present disclosure. 44 is a partial cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 45 is a partial cross-sectional view of a first modified example of the semiconductor device according to the fourth embodiment of the present disclosure. FIG. 46 is a perspective view of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 47 is a partial cross-sectional view of a semiconductor device according to the fifth embodiment of the present disclosure. FIG. 48 is a partial cross-sectional view of a semiconductor device according to the fifth embodiment of the present disclosure. FIG. 49 is a partially enlarged cross-sectional view of a semiconductor device according to the fifth embodiment of the present disclosure. FIG. 50 is a perspective view of a method for manufacturing a semiconductor device according to the fifth embodiment of the present disclosure. FIG. 51 is a perspective view of a first modified example of the semiconductor device according to the fifth embodiment of the present disclosure.

[0010] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] 1 to 16, a semiconductor device B10 according to a first embodiment of the present disclosure will be described. The semiconductor device B10 includes one or more semiconductor units A10, a heat dissipation member 70, and a first bonding layer 19. The number of the one or more semiconductor units A10 is not limited in any way and may be one or more. In this embodiment, the number of the one or more semiconductor units A10 is one.

[0014] The semiconductor unit A10 includes a substrate 11, a plurality of semiconductor elements 20, and a sealing resin 50. The semiconductor unit A10 may further include a first power terminal 13, a second power terminal 14, a third power terminal 15, a plurality of signal terminals 16, a first conductive member 31, and a second conductive member 32. The plurality of signal terminals 16 may include a first signal terminal 161, a second signal terminal 162, a third signal terminal 171, a fourth signal terminal 172, two fifth signal terminals 181, and two sixth signal terminals 182. The semiconductor unit A10 may further include a thermistor 23.

[0015] There are no limitations on the number and arrangement of the first power terminals 13 and the second power terminals 14. In the following description, an example will be described in which the semiconductor unit A10 includes one first power terminal 13 and two second power terminals 14.

[0016] 7 to 9, for ease of understanding, the sealing resin 50 is shown through and the heat dissipation member 70 is omitted. In FIGS. 7 to 9, the sealing resin 50 is shown by an imaginary line (two-dot chain line). In FIG. 8, for ease of understanding, the second conductive member 32 is also omitted. In FIG. 9, for ease of understanding, the first conductive member 31 and the second conductive member 32 are also omitted.

[0017] In these figures, for example, the thickness direction of the substrate 11 is defined as the first direction z. One side of the first direction z is defined as the first side z1, and the other side is defined as the second side z2. Also, for example, a direction intersecting the first direction z is defined as the second direction x. One side of the second direction x is defined as the first side x1, and the other side is defined as the second side x2. Also, for example, a direction intersecting the first direction z and the second direction x is defined as the third direction y. One side of the third direction y is defined as the first side y1, and the other side is defined as the second side y2.

[0018] The semiconductor device B10 converts DC power input to the first power terminal 13 and the second power terminal 14 into AC power using a plurality of semiconductor elements 20. The converted AC power is input from each of two third power terminals 15 to a power supply target such as a motor.

[0019] As shown in Figures 10, 11, 14, and 15, the sealing resin 50 covers the substrate 11, the first conductive layer 121, the second conductive layer 122, the multiple semiconductor elements 20, the first conductive member 31, and the second conductive member 32. The sealing resin 50 also covers a portion of each of the first power terminal 13, the third power terminal 15, and the second power terminal 14. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in Figures 3 to 5, the sealing resin 50 may have a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, and multiple recesses 55.

[0020] 10, 11, 14, and 15, the top surface 51 faces a first side z1 in the first direction z, and the bottom surface 52 faces a second side z2 in the first direction z.

[0021] 3 and 4, the first side surface 53 and the second side surface 54 are spaced apart from each other in the second direction x. The first side surface 53 faces a first side x1 in the second direction x, and the second side surface 54 faces a second side x2 in the second direction x.

[0022] 2, 4, and 5, each of the multiple recesses 55 is recessed from the top surface 51 and either the first side surface 53 or the second side surface 54. The multiple recesses 55 include a first recess 55A, two second recesses 55B, and two third recesses 55C. The first recess 55A and the two second recesses 55B are each connected to the first side surface 53. In the third direction y, the first recess 55A is located between the two second recesses 55B. The two third recesses 55C are connected to the second side surface 54. The two third recesses 55C are spaced apart from each other in the third direction y.

[0023] As shown in Figures 10, 11, 14, and 15, the substrate 11 is bonded to the heat dissipation member 70 via a first bonding layer 19. In the semiconductor unit A10, the substrate 11 may be formed, for example, from a DBC (Direct Bonded Copper) substrate. The substrate 11 may have an insulating layer 111, a metal layer 112, a first conductive layer 121, and a second conductive layer 122. A portion of the substrate 11 is covered with a sealing resin 50.

[0024] 10 , 11 , 14 , and 15 , the metal layer 112 has a back surface 1121 and multiple end surfaces 1122. The back surface 1121 faces a second side z2 in the first direction z. The multiple back surfaces 1121 are connected to a first side z1 in the first direction z relative to the back surface 1121. The metal layer 112 may contain copper (Cu). As viewed in the first direction z, the metal layer 112 may be located inward from a periphery 111A of the insulating layer 111.

[0025] As shown in Figures 10, 11, 14, and 15, the insulating layer 111 is located between the metal layer 112 and the first and second conductive layers 121 and 122 in the first direction z. The metal layer 112 is fixed to the insulating layer 111. The insulating layer 111 may include a material with relatively high thermal conductivity. The insulating layer 111 may include ceramics such as aluminum nitride (AlN). The insulating layer 111 may be composed of an insulating resin sheet in addition to ceramics.

[0026] As shown in FIGS. 10 , 11 , 14 , and 15 , the first conductive layer 121 and the second conductive layer 122 are located on the opposite side of the insulating layer 111 from the metal layer 112 in the first direction z. Each of the first conductive layer 121 and the second conductive layer 122 is fixed to the insulating layer 111. As shown in FIGS. 8 and 9 , each of the first conductive layer 121 and the second conductive layer 122 may be located inward from the periphery 111A of the insulating layer 111. Each of the first conductive layer 121 and the second conductive layer 122 may include copper. The first conductive layer 121 and the second conductive layer 122 are spaced apart from each other in the second direction x. The dimension of each of the first conductive layer 121 and the second conductive layer 122 in the first direction z may be greater than the dimension of the insulating layer 111 in the first direction z. The first conductive layer 121 has a first mounting surface 121A facing a first side z1 in the first direction z. The second conductive layer 122 has a second mounting surface 122A facing the first side z1 in the first direction z. The first mounting surface 121A and the second mounting surface 122A face the plurality of semiconductor elements 20.

[0027] As shown in FIGS. 7 to 9 , each of the multiple semiconductor elements 20 is mounted on either the first conductive layer 121 or the second conductive layer 122. The multiple semiconductor elements 20 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Alternatively, the multiple semiconductor elements 20 may be switching elements such as IGBTs (Insulated Gate Bipolar Transistors) or diodes. In the description of the semiconductor unit A10, the multiple semiconductor elements 20 are n-channel MOSFETs with a vertical structure. The multiple semiconductor elements 20 include a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide (SiC).

[0028] 9 , in the semiconductor unit A10, the multiple semiconductor elements 20 may include multiple first semiconductor elements 21 and multiple second semiconductor elements 22. The structure of each of the multiple second semiconductor elements 22 may be identical to the structure of each of the multiple first semiconductor elements 21. The multiple first semiconductor elements 21 are mounted on a first mounting surface 121A of the first conductive layer 121. The multiple first semiconductor elements 21 are arranged along the third direction y. The multiple second semiconductor elements 22 are mounted on a second mounting surface 122A of the second conductive layer 122. The multiple second semiconductor elements 22 may be arranged along the third direction y.

[0029] As shown in FIGS. 9 and 12 , each of the plurality of first semiconductor elements 21 can have a first electrode 211 , a second electrode 212 , a first gate electrode 213 and a first detection electrode 214 .

[0030] 12 , the first electrode 211 faces the first mounting surface 121A of the first conductive layer 121. A current corresponding to the power before being converted by the first semiconductor element 21 can flow through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the first semiconductor element 21. The first electrode 211 is conductively bonded to the first mounting surface 121A via the second bonding layer 29. As a result, the first electrode 211 of each of the multiple first semiconductor elements 21 is electrically connected to the first conductive layer 121.

[0031] 12 , the second electrode 212 is located on a first side z1 in the first direction z. The first electrode 211 and the second electrode 212 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the first semiconductor element 21 can flow through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the first semiconductor element 21.

[0032] 12 , the first gate electrode 213 is located on a first side z1 in the first direction z. The first gate electrode 213 is located on the same side as the second electrode 212 in the first direction z. A gate voltage for driving the first semiconductor element 21 can be applied to the first gate electrode 213. As shown in FIG. 9 , the area of ​​the first gate electrode 213 may be smaller than the area of ​​the second electrode 212 when viewed in the first direction z.

[0033] 9 , the first detection electrode 214 is located on the first side z1 in the first direction z. The first detection electrode 214 may be located next to the first gate electrode 213 in the third direction y. A voltage equivalent to the voltage applied to the second electrode 212 may be applied to the first detection electrode 214. The area of ​​the first detection electrode 214 may be approximately equal to the area of ​​the first gate electrode 213 as viewed in the first direction z.

[0034] As shown in FIGS. 9 and 13 , each of the plurality of second semiconductor elements 22 can have a third electrode 221 , a fourth electrode 222 , a second gate electrode 223 and a second detection electrode 224 .

[0035] 13 , the third electrode 221 faces the second mounting surface 122A of the second conductive layer 122. A current corresponding to the power before being converted by the second semiconductor element 22 can flow through the third electrode 221. In other words, the third electrode 221 corresponds to the drain electrode of the second semiconductor element 22. The third electrode 221 is conductively bonded to the second mounting surface 122A via the first bonding layer 19. As a result, the third electrode 221 of each of the multiple second semiconductor elements 22 is electrically connected to the second conductive layer 122.

[0036] 13 , the fourth electrode 222 is located on the first side z1 in the first direction z. The third electrode 221 and the fourth electrode 222 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the second semiconductor element 22 can flow through the fourth electrode 222. In other words, the fourth electrode 222 corresponds to the source electrode of the second semiconductor element 22.

[0037] 13 , the second gate electrode 223 is located on the first side z1 in the first direction z. The second gate electrode 223 is located on the same side as the fourth electrode 222 in the first direction z. A gate voltage for driving the second semiconductor element 22 can be applied to the second gate electrode 223. As shown in FIG. 9 , the area of ​​the second gate electrode 223 may be smaller than the area of ​​the fourth electrode 222 when viewed in the first direction z.

[0038] 9 , the second detection electrode 224 is located on the first side z1 in the first direction z. The second detection electrode 224 may be located on both sides of the second gate electrode 223 in the third direction y. A voltage equivalent to the voltage applied to the fourth electrode 222 may be applied to the second detection electrode 224. When viewed in the first direction z, the area of ​​the second detection electrode 224 may be approximately equal to the area of ​​the second gate electrode 223.

[0039] As shown in FIG. 9 , the first power terminal 13 may be located on a first side x1 relative to the plurality of first semiconductor elements 21 in the second direction x. The first power terminal 13 is disposed on the substrate 11. The first power terminal 13 may be conductively bonded to the first conductive layer 121. As a result, the first power terminal 13 is electrically connected to the first electrodes 211 of the plurality of first semiconductor elements 21 via the first conductive layer 121. The first power terminal 13 may be a P terminal (positive electrode) to which DC power to be converted is input. As shown in FIG. 2 , the first power terminal 13 is exposed from a top surface 51 of the sealing resin 50. As viewed in the first direction z, the first power terminal 13 may be surrounded by a periphery 501 of the sealing resin 50 and positioned inward from the periphery of the top surface 51. As shown in FIG. 11 , the first power terminal 13 has a first connection surface 131 exposed from the sealing resin 50. The first connection surface 131 faces the first side z1 in the first direction z. As shown in Figures 5 and 11 , in the semiconductor unit A10, the first connection surface 131 is housed in a first recess 55A among the multiple recesses 55 in the sealing resin 50. In addition to the configuration of the first power terminal 13 in the semiconductor unit A10, the first power terminal 13 may be configured to protrude from the first side surface 53 of the sealing resin 50 in the second direction x.

[0040] As shown in FIG. 9 , each of the two second power terminals 14 may be located on a first side x1 relative to the plurality of first semiconductor elements 21 in the second direction x. The two second power terminals 14 are disposed on the substrate 11. Each of the two second power terminals 14 is disposed on the insulating layer 111. Each of the two second power terminals 14 is electrically connected to the fourth electrodes 222 of the plurality of second semiconductor elements 22. The two second power terminals 14 may be N terminals (negative electrodes) to which DC power to be converted is input. The second power terminals 14 are spaced apart from each other in the third direction y. The first power terminal 13 is located between the two second power terminals 14 in the third direction y. As shown in FIG. 2 , each of the two second power terminals 14 is exposed from the top surface 51 of the sealing resin 50. As viewed in the first direction z, each of the two second power terminals 14 is surrounded by a periphery 501 of the sealing resin 50 and is located inward from the periphery of the top surface 51. As shown in FIG. 10 , each of the two second power terminals 14 has a second connection surface 141 exposed from the sealing resin 50. The second connection surface 141 faces a first side z1 in the first direction z. As shown in FIGS. 5 and 10 , in the semiconductor unit A10, the two second connection surfaces 141 are individually accommodated in two second recesses 55B among the multiple recesses 55 in the sealing resin 50. In addition to the configuration of two second power terminals 14 in the semiconductor unit A10, two second power terminals 14 may be configured such that each protrudes from the first side surface 53 of the sealing resin 50 in the second direction x.

[0041] As shown in FIG. 9 , each of the two third power terminals 15 is located on the second side x2 in the second direction x. The two third power terminals 15 are disposed on the substrate 11. Each of the two third power terminals 15 is conductively bonded to the second conductive layer 122. As a result, each of the two third power terminals 15 is electrically connected to the third electrodes 221 of the second semiconductor elements 22 via the second conductive layer 122. AC power converted by the semiconductor elements 20 can be output from each of the two third power terminals 15. In the semiconductor unit A10, the two third power terminals 15 are spaced apart from each other in the third direction y. As shown in FIG. 2 , each of the two third power terminals 15 is exposed from the top surface 51 of the sealing resin 50. As viewed in the first direction z, each of the two third power terminals 15 is surrounded by the periphery 501 of the sealing resin 50 and is located inward from the periphery of the top surface 51. 10 , each of the two third power terminals 15 has a third connection surface 151 exposed from the sealing resin 50. The third connection surface 151 faces the first side z1 in the first direction z. As shown in FIGS. 4 and 10 , in the semiconductor unit A10, the two third connection surfaces 151 are individually housed in two third recesses 55C among the multiple recesses 55 in the sealing resin 50. In addition to the configuration of two third power terminals 15 in the semiconductor unit A10, two third power terminals 15 may be configured such that each protrudes from the second side surface 54 of the sealing resin 50 in the second direction x.

[0042] 12 , the first wiring 61 is bonded to a first mounting surface 121A of the first conductive layer 121. The first wiring 61 is located on the opposite side of the plurality of second semiconductor elements 22 with respect to the plurality of first semiconductor elements 21 in the second direction x. The first wiring 61 is electrically connected to the plurality of first semiconductor elements 21 and the first conductive layer 121. As shown in FIGS. 9 and 12 , the first wiring 61 may include a first mounting layer 611, a first metal layer 612, two first gate wiring layers 613, a first detection wiring layer 614, a first temperature detection wiring layer 615, and a second detection wiring layer 616.

[0043] 9 , the first mounting layer 611 includes two first gate wiring layers 613, a first detection wiring layer 614, two first temperature detection wiring layers 615, and a second detection wiring layer 616. The first mounting layer 611 is an insulator. The first mounting layer 611 includes, for example, ceramics. Alternatively, the first mounting layer 611 may be made of an insulating resin sheet.

[0044] As shown in FIG. 12 , the first metal layer 612 is located on the second side z2 relative to the first mounting layer 611 in the first direction z. The first metal layer 612 is fixed to the first mounting layer 611. The first metal layer 612 contains copper. The first metal layer 612 is bonded to the first mounting surface 121A via a third bonding layer 39. The third bonding layer 39 contains a metal. The third bonding layer 39 may be solder. The third bonding layer 39 may contain tin (Sn). Alternatively, the third bonding layer 39 may be a sintered body of metal particles containing silver (Ag) or the like.

[0045] 9 and 12 , the two first gate wiring layers 613 are located on a first side z1 in the first direction z with respect to the first mounting layer 611. The two first gate wiring layers 613 are fixed to the first mounting layer 611. Of the two first gate wiring layers 613, one of the first gate wiring layers 613 is conductively bonded to a plurality of first wires 41. The plurality of first wires 41 are individually conductively bonded to the first gate electrodes 213 of the plurality of first semiconductor elements 21. Furthermore, a plurality of sixth wires 46 are connected to each of the two first gate wiring layers 613. As a result, each of the two first gate wiring layers 613 is electrically connected to the first gate electrodes 213 of the plurality of first semiconductor elements 21.

[0046] 9 and 12 , the first detection wiring layer 614 is located on a first side z1 in the first direction z with respect to the first mounting layer 611. The first detection wiring layer 614 is fixed to the first mounting layer 611. A plurality of second wires 42 are connected to the first detection wiring layer 614. Furthermore, the plurality of second wires 42 are individually conductively bonded to the first detection electrodes 214 of the plurality of first semiconductor elements 21. As a result, the first detection wiring layer 614 is electrically connected to the first detection electrodes 214 of the plurality of first semiconductor elements 21.

[0047] 9 , the two first temperature detection wiring layers 615 are located on a first side z1 in the first direction z with respect to the first mounting layer 611. The two first temperature detection wiring layers 615 are fixed to the first mounting layer 611. The two first temperature detection wiring layers 615 are adjacent to each other in the third direction y.

[0048] 9, the second detection wiring layer 616 is located on a first side z1 in the first direction z with respect to the first mounting layer 611. The second detection wiring layer 616 is fixed to the first mounting layer 611.

[0049] 13 , the second wiring 62 is bonded to the second mounting surface 122A of the second conductive layer 122. The second wiring 62 is located on the second side x2 in the second direction x with respect to the plurality of second semiconductor elements 22. The second wiring 62 is electrically connected to the plurality of second semiconductor elements 22 and the second conductive layer 122. As shown in FIGS. 9 and 13 , the second wiring 62 may include a second mounting layer 621, a second metal layer 622, two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626.

[0050] 9 , the second mounting layer 621 includes two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626. The second mounting layer 621 is an insulator. The second mounting layer 621 includes, for example, ceramics. Alternatively, the second mounting layer 621 may be made of an insulating resin sheet.

[0051] 13 , the second metal layer 622 is located on the second side z2 of the second mounting layer 621 in the first direction z. The second metal layer 622 is fixed to the second mounting layer 621. The second metal layer 622 may include copper. The second metal layer 622 may be fixed to the second mounting surface 122A via a third bonding layer 39.

[0052] 9 and 13 , the two second gate wiring layers 623 are located on a first side z1 in the first direction z with respect to the second mounting layer 621. The two second gate wiring layers 623 are fixed to the second mounting layer 621. Of the two second gate wiring layers 623, one of the second gate wiring layers 623 is connected to a plurality of fourth wires 44. The plurality of fourth wires 44 are individually conductively bonded to the second gate electrodes 223 of the plurality of second semiconductor elements 22. Furthermore, a plurality of seventh wires 47 are connected to each of the two second gate wiring layers 623. As a result, each of the two second gate wiring layers 623 is electrically connected to the second gate electrodes 223 of the plurality of second semiconductor elements 22.

[0053] 9 and 13 , the third detection wiring layer 624 is located on a first side z1 in the first direction z with respect to the second mounting layer 621. The third detection wiring layer 624 is fixed to the second mounting layer 621. A plurality of fifth wires 45 are connected to the third detection wiring layer 624. Furthermore, the plurality of fifth wires 45 are individually conductively bonded to the second detection electrodes 224 of the plurality of second semiconductor elements 22. As a result, the third detection wiring layer 624 is electrically connected to the second detection electrodes 224 of the plurality of second semiconductor elements 22.

[0054] 9 , the two second temperature detection wiring layers 625 are located on a first side z1 in the first direction z with respect to the second mounting layer 621. The two second temperature detection wiring layers 625 are fixed to the second mounting layer 621. The two second temperature detection wiring layers 625 are adjacent to each other in the third direction y.

[0055] 9, the fourth detection wiring layer 626 is located on a first side z1 in the first direction z with respect to the second mounting layer 621. The fourth detection wiring layer 626 is fixed to the second mounting layer 621.

[0056] As shown in FIGS. 12 and 13 , each of the multiple sleeves 63 is conductively bonded to either the first wiring 61 or the second wiring 62 via a third bonding layer 39. The third bonding layer 39 may be, for example, solder. The multiple sleeves 63 are made of a conductive material such as metal. Each of the multiple sleeves 63 may have a cylindrical shape extending in the first direction z. As shown in FIGS. 2 and 11 , each of the multiple sleeves 63 may have an end surface 631 facing the first side z1 in the first direction z. The end surface 631 may be exposed from the top surface 51 of the sealing resin 50, which will be described later.

[0057] 8 and 9, one of the two thermistors 23 is conductively joined to the two first temperature detection wiring layers 615 of the first wiring 61. The other of the two thermistors 23 is conductively joined to the two second temperature detection wiring layers 625 of the second wiring 62. The two thermistors 23 are used as temperature detection sensors for the semiconductor unit A10.

[0058] Each of the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, and the two sixth signal terminals 182 may be a metal pin extending in the first direction z, as shown in FIG. 3 . These terminals protrude from the top surface 51 of the sealing resin 50. Furthermore, these terminals may be individually press-fitted into a plurality of sleeves 63. As a result, each of these terminals is supported by one of the plurality of sleeves 63 and is electrically connected to one of the first wiring 61 and the second wiring 62.

[0059] 9 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two first gate wiring layers 613 of the first wiring 61. This allows the first signal terminal 161 to be electrically connected to the first gate electrodes 213 of the multiple first semiconductor elements 21 via the two first gate wiring layers 613. A gate voltage for driving the multiple first semiconductor elements 21 can be applied to the first signal terminal 161.

[0060] 9 and 11 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two second gate wiring layers 623 of the second wiring 62. This allows the second signal terminal 162 to be electrically connected to the second gate electrodes 223 of the multiple second semiconductor elements 22 via the two second gate wiring layers 623. A gate voltage for driving the multiple second semiconductor elements 22 can be applied to the second signal terminal 162.

[0061] As shown in Fig. 2 , the third signal terminal 171 is located adjacent to the first signal terminal 161 in the third direction y. As shown in Figs. 9 and 11 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the first detection wiring layer 614 of the first wiring 61. This allows the third signal terminal 171 to be electrically connected to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 via the first detection wiring layer 614. A voltage equivalent to the voltage applied to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 can be applied to the third signal terminal 171.

[0062] As shown in Fig. 2 , the fourth signal terminal 172 is located adjacent to the second signal terminal 162 in the third direction y. As shown in Fig. 9 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the third detection wiring layer 624 of the second wiring 62. This allows the fourth signal terminal 172 to be electrically connected to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 via the third detection wiring layer 624. A voltage equivalent to the voltage applied to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 can be applied to the fourth signal terminal 172.

[0063] As shown in Fig. 2 , the two fifth signal terminals 181 are located on the opposite side of the third signal terminal 171 from the first signal terminal 161 in the third direction y. The two fifth signal terminals 181 are adjacent to each other in the third direction y. As shown in Fig. 9 , the two fifth signal terminals 181 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two first temperature detection wiring layers 615 of the first wiring 61. As a result, the two fifth signal terminals 181 are electrically connected to the two thermistors 23 that are conductively joined to the two first temperature detection wiring layers 615 of the two thermistors 23.

[0064] As shown in Fig. 2 , the two sixth signal terminals 182 are located on the opposite side of the second signal terminal 162 from the fourth signal terminal 172 in the third direction y. The two sixth signal terminals 182 are adjacent to each other in the third direction y. As shown in Fig. 9 , the two sixth signal terminals 182 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two second temperature detection wiring layers 625 of the second wiring 62. As a result, the two sixth signal terminals 182 are electrically connected to the two thermistors 23 that are conductively joined to the two second temperature detection wiring layers 625 of the two thermistors 23.

[0065] As shown in FIGS. 8 and 12 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the plurality of first semiconductor elements 21 and the second mounting surface 122A of the second conductive layer 122. As a result, the second electrodes 212 of the plurality of first semiconductor elements 21 are electrically connected to the second conductive layer 122. The first conductive member 31 contains copper. The first conductive member 31 may be a component formed using a metal plate material. As shown in FIG. 5 , the first conductive member 31 may have a main portion 311, a plurality of first bonding portions 312, a plurality of first connecting portions 313, a second bonding portion 314, and a second connecting portion 315.

[0066] The main portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 8 , the main portion 311 extends in the third direction y. The main portion 311 straddles between the first conductive layer 121 and the second conductive layer 122.

[0067] 8 and 12 , the multiple first bonding portions 312 are individually bonded to the second electrodes 212 of the multiple first semiconductor elements 21. Each of the multiple first bonding portions 312 faces the second electrode 212 of one of the multiple first semiconductor elements 21.

[0068] 8 and 12 , the multiple first connecting portions 313 are connected to the main portion 311 and the multiple first bonding portions 312. The multiple first connecting portions 313 are spaced apart from one another in the third direction y. As viewed in the third direction y, the multiple first connecting portions 313 are inclined in a direction away from the first mounting surface 121A of the first conductive layer 121 as they extend from the multiple first bonding portions 312 toward the main portion 311.

[0069] 8 and 11 , the second bonding portion 314 is bonded to the second mounting surface 122A of the second conductive layer 122. The second bonding portion 314 faces the second mounting surface 122A. The second bonding portion 314 extends in the third direction y. The dimension of the second bonding portion 314 in the third direction y may be equal to the dimension of the main portion 311 in the third direction y.

[0070] 8 and 11 , the second connecting portion 315 is connected to the main portion 311 and the second joint portion 314. When viewed in the third direction y, the second connecting portion 315 is inclined in a direction away from the second mounting surface 122A of the second conductive layer 122 as it extends from the second joint portion 314 toward the main portion 311. The dimension of the second connecting portion 315 in the third direction y may be equal to the dimension of the main portion 311 in the third direction y.

[0071] 12 , a third bonding layer 39 is located between the second electrode 212 of each of the multiple first semiconductor elements 21 and each of the multiple first bonding portions 312. The third bonding layer 39 electrically conductively bonds each of the multiple first bonding portions 312 to the second electrode 212 of each of the multiple first semiconductor elements 21. The third bonding layer 39 may be, for example, solder. As shown in FIG. 11 , the third bonding layer 39 is located between the second mounting surface 122A of the second conductive layer 122 and the second bonding portion 314. The third bonding layer 39 electrically conductively bonds the second mounting surface 122A to the second bonding portion 314.

[0072] As shown in FIGS. 7 and 13 , the second conductive member 32 is conductively bonded to the second electrodes 212 of the plurality of second semiconductor elements 22 and the two second power terminals 14. As a result, the second electrodes 212 of the plurality of second semiconductor elements 22 are electrically connected to the second power terminals 14. The second conductive member 32 contains copper. The second conductive member 32 may be a component formed using a metal plate material. As shown in FIG. 7 , the second conductive member 32 may have two main portions 321, a plurality of third joint portions 322, a plurality of third connecting portions 323, a plurality of intermediate portions 326, and a cross beam portion 327.

[0073] As shown in Fig. 7 , the two main portions 321 are spaced apart from each other in the third direction y. The two main portions 321 extend in the second direction x. As shown in Fig. 10 , the two main portions 321 are arranged parallel to the first mounting surface 121A of the first conductive layer 121 and the second mounting surface 122A of the second conductive layer 122. The two main portions 321 are spaced apart from the first mounting surface 121A and the second mounting surface 122A more than the main portion 311 of the first conductive member 31.

[0074] 7 , the intermediate portions 326 are spaced apart from one another in the third direction y and are located between the two main portions 321 in the third direction y. The intermediate portions 326 extend in the second direction x. The dimension of each of the intermediate portions 326 in the second direction x may be smaller than the dimension of each of the two main portions 321 in the second direction x.

[0075] 13 , the multiple third bonding portions 322 are individually bonded to the second electrodes 212 of the multiple second semiconductor elements 22. Each of the multiple third bonding portions 322 faces the fourth electrode 222 of one of the multiple second semiconductor elements 22.

[0076] 7 and 15 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the third direction y. Furthermore, the multiple third connecting portions 323 are connected to either of the two main portions 321 and the multiple intermediate portions 326. When viewed in the second direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the second mounting surface 122A of the second conductive layer 122 as it moves from either of the multiple third joint portions 322 toward either of the two main portions 321 or the multiple intermediate portions 326.

[0077] As shown in Fig. 7 , the cross beam portion 327 extends in the third direction y. As shown in Fig. 15 , when viewed in the first direction z, the cross beam portion 327 includes regions that overlap with each of the multiple first joint portions 312 of the first conductive member 31. Both sides of the cross beam portion 327 in the third direction y are individually connected to the two main portions 321.

[0078] 13 , a third bonding layer 39 is located between each fourth electrode 222 of the multiple second semiconductor elements 22 and each of the multiple third bonding portions 322. The third bonding layer 39 electrically conductively bonds each of the multiple third bonding portions 322 to each of the multiple fourth electrodes 222 of the multiple second semiconductor elements 22. As shown in FIG. 10 , a third bonding layer 39 is located between two second power terminals 14 and two main portions 321. The third bonding layer 39 electrically conductively bonds each of the two second power terminals 14 to each of the two main portions 321.

[0079] The heat dissipation member 70 is used to cool the semiconductor unit A 10. The heat dissipation member 70 contains a metal. The heat dissipation member 70 may contain, for example, aluminum (Al).

[0080] 3 to 6 and 10 to 16 , the heat dissipation member 70 has a main surface 700, a first surface 701, and a second surface 702. The heat dissipation member 70 may have a third surface 703 and a fourth surface 704. The heat dissipation member 70 may have a fifth surface 705 and a sixth surface 706. The heat dissipation member 70 may have a base 71, a heat dissipation portion 72, and a protrusion 73.

[0081] The main surface 700 faces the first side z1 in the first direction z. The main surface 700 may be a flat surface.

[0082] The first surface 701 and the second surface 702 are located on either side of the main surface 700 in the second direction x. The first surface 701 is located on a first side x1 in the second direction x with respect to the main surface 700. The second surface 702 is located on a second side x2 in the second direction x with respect to the main surface 700. The first surface 701 and the second surface 702 may be connected to the main surface 700 and include at least a portion located on a first side z1 in the first direction z with respect to the main surface 700. The entire first surface 701 and the second surface 702 may be located on the first side z1 in the first direction z with respect to the main surface 700. The first surface 701 and the second surface 702 face each other in the second direction x.

[0083] The third surface 703 and the fourth surface 704 are located on both sides of the main surface 700 in the third direction y. The third surface 703 is located on a first side y1 in the third direction y with respect to the main surface 700. The fourth surface 704 is located on a second side y2 in the third direction y with respect to the main surface 700. The third surface 703 and the fourth surface 704 may be connected to the main surface 700 and include at least a portion located on a first side z1 in the first direction z from the main surface 700. The entire third surface 703 and the fourth surface 704 may be located on the first side z1 in the first direction z from the main surface 700. The third surface 703 and the fourth surface 704 face each other in the third direction y.

[0084] The fifth surface 705 is located on a first side z1 in the first direction z from the main surface 700. The fifth surface 705 is connected to the first surface 701. The fifth surface 705 includes a portion located on a first side x1 in the second direction x from the first surface 701.

[0085] The fifth surface 705 is connected to the second surface 702. The fifth surface 705 includes a portion located on the second side x2 in the second direction x with respect to the second surface 702.

[0086] The fifth surface 705 is connected to the third surface 703. The fifth surface 705 includes a portion located on the first side y1 in the third direction y with respect to the third surface 703.

[0087] The fifth surface 705 is connected to the fourth surface 704. The fifth surface 705 includes a portion located on the second side y2 in the third direction y with respect to the fourth surface 704.

[0088] In the illustrated example, both ends of the first surface 701 and the second surface 702 in the third direction y are connected to the third surface 703 and the fourth surface 704. The first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 may be rectangular when viewed in the first direction z.

[0089] Each of the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 may be a flat surface, a concave surface, a convex surface, a curved surface, etc. In the illustrated example, each of the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 is a flat surface.

[0090] In the illustrated example, the fifth surface 705 has a rectangular ring shape when viewed in the first direction z. The fifth surface 705 is located outward from the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 when viewed in the first direction z.

[0091] The base 71 has a flat plate shape. The base 71 includes a main surface 700. The base 71 may have a peripheral edge 711 and a plurality of end surfaces 712. Each of the end surfaces 712 faces, for example, in the second direction x or the third direction y.

[0092] As shown in FIGS. 3 to 5 , the heat dissipation portion 72 is connected to the base 71. The heat dissipation portion 72 protrudes from the base 71 toward the second side z2 in the first direction z. The specific hole configuration of the heat dissipation portion 72 is not limited in any way, and in the illustrated example, the heat dissipation portion 72 may be a plurality of fins. The plurality of fins may each extend in the third direction y and may be arranged at equal intervals in the second direction x. A heat dissipation member 70 configured in this manner may be used in a state where it is attached to another box-shaped member (not shown). The box-shaped member and the heat dissipation member 70 may form a flow path through which a cooling medium can flow, for example.

[0093] 6 , 10 , 11 , and 14 to 16 , the protrusion 73 protrudes from the main surface 700 to a first side z1 in the first direction z. In the illustrated example, the protrusion 73 includes a first surface 701, a second surface 702, a third surface 703, a fourth surface 704, and a fifth surface 705. In the illustrated example, the protrusion 73 may have a rectangular ring shape when viewed in the first direction z.

[0094] 10, 11, and 14 to 16, the first bonding layer 19 is interposed between the main surface 700 of the heat dissipation member 70 and the back surface 1121 of the metal layer 112. The main surface 700 and the back surface 1121 may be bonded by solid-state diffusion bonding with the first bonding layer 19 sandwiched therebetween.

[0095] The specific configuration of first bonding layer 19 is not limited in any way, and the material constituting the surface of first bonding layer 19 may be the same as or different from the materials constituting main surface 700 and back surface 1121. When the material constituting the surface of first bonding layer 19 is the same as the material constituting main surface 700 and back surface 1121, these surfaces may be made of, for example, Ag (silver). First bonding layer 19 may include a base layer containing, for example, Al (aluminum), and two surface layers arranged on both sides of the base layer in first direction z and containing, for example, Ag (silver).

[0096] The first bonding layer 19 may be fixed to the main surface 700 and the back surface 1121 by solid-state diffusion bonding. The first bonding layer 19 is located between the first surface 701 and the second surface 702 in the second direction x. The first bonding layer 19 may be located between the third surface 703 and the fourth surface 704 in the third direction y. The first bonding layer 19 may be located in a region surrounded by the protrusion 73 as viewed in the first direction z. The first bonding layer 19 may protrude from the back surface 1121 as viewed in the first direction z. In the illustrated example, the substrate 11 may be located inside the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 as viewed in the first direction z. The size of the back surface 1121 in the second direction x and the third direction y may be the same as (or approximately the same as) the size of the first bonding layer 19 in the second direction x and the third direction y, or may be smaller. In the illustrated example, the size of the rear surface 1121 in the second direction x and the third direction y is smaller than the size of the first bonding layer 19 in the second direction x and the third direction y.

[0097] 10 , 11 , and 14 to 16 , in this embodiment, the first surface 701 and the second surface 702 are covered with sealing resin 50. The sealing resin 50 may be filled in the area sandwiched between the first surface 701 and the second surface 702 and the substrate 11. In this embodiment, the third surface 703 and the fourth surface 704 are covered with sealing resin 50. The sealing resin 50 may be filled in the area sandwiched between the third surface 703 and the fourth surface 704 and the substrate 11. The main surface 700 is in contact with the sealing resin 50. The bottom surface 52 may be in contact with the main surface 700.

[0098] The height H1 in the first direction z of the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 may be smaller than the height H0, which is the distance between the main surface 700 and the insulating layer 111. The specific sizes of the heights H0 and H1 are not limited in any way. The height H0 may be, for example, 0.2 mm to 5.0 mm. The height H1 may be, for example, 0.1 mm to 4.0 mm.

[0099] The angle α1 between the first surface 701 and the main surface 700 may be larger than the angle α0 between the end surface 1122 and the main surface 700. The angle α0 may be, for example, 45° to 90°. The angle α1 may be, for example, 45° to 100°, and in the illustrated example, may be 90°. The relationship between these angles α0 and α1 may apply to the relationship between the end surface 1122 and the second surface 702, the third surface 703, and the fourth surface 704.

[0100] In the illustrated example, the protrusion 73 may be entirely covered by the sealing resin 50. The fifth surface 705 may be entirely covered by the sealing resin 50. A periphery 501 of the sealing resin 50 may be located outward from the protrusion 73 and the fifth surface 705 when viewed in the first direction z. A portion of the sixth surface 706 may be covered by the sealing resin 50.

[0101] Next, an example of a method for manufacturing the semiconductor device B10 will be described with reference to FIGS.

[0102] Fig. 17 is a plan view of the heat dissipation member 70 as viewed from the first side z1 in the first direction z. As shown in Figs. 17 and 18 , the heat dissipation member 70 is prepared. The heat dissipation member 70 has the main surface 700, first surface 701, and second surface 702 described above. The heat dissipation member 70 may have a third surface 703 and a fourth surface 704. The heat dissipation member 70 may have a fifth surface 705 and a sixth surface 706. The heat dissipation member 70 may have a base 71, a heat dissipation portion 72, and a protrusion 73.

[0103] Next, as shown in FIGS. 19 and 20 , the first bonding layer 19 is placed. The size of the first bonding layer 19 in the second direction x may be the same as (or approximately the same as) or slightly smaller than the distance in the second direction x between the first surface 701 and the second surface 702. The size of the first bonding layer 19 in the third direction y may be the same as (or approximately the same as) or slightly smaller than the distance in the third direction y between the third surface 703 and the fourth surface 704. The first bonding layer 19 is placed on the main surface 700. The first bonding layer 19 is placed between the first surface 701 and the second surface 702 in the second direction x. The first bonding layer 19 is placed between the third surface 703 and the fourth surface 704 in the third direction y.

[0104] Next, as shown in FIGS. 21 and 22 , the heat dissipation member 70 and the substrate 11 are bonded via the first bonding layer 19 by solid-phase diffusion bonding. For example, as shown in FIG. 21 , the substrate 11 is placed on the first bonding layer 19. The size of the back surface 1121 of the substrate 11 in the second direction x may be smaller than the distance in the second direction x between the first surface 701 and the second surface 702 and may be smaller than the size of the first bonding layer 19 in the second direction x. The size of the back surface 1121 in the third direction y may be smaller than the distance in the third direction y between the third surface 703 and the fourth surface 704 and may be smaller than the size of the first bonding layer 19 in the third direction y. The back surface 1121 of the substrate 11 is abutted against the main surface 700. The back surface 1121 of the substrate 11 is placed between the first surface 701 and the second surface 702 in the second direction x. The rear surface 1121 of the substrate 11 is placed between the third surface 703 and the fourth surface 704 in the third direction y.

[0105] 22 , the rear surface 1121 of the substrate 11 is pressed against the main surface 700 of the heat dissipation member 70 with the first bonding layer 19 sandwiched therebetween. The pressure applied at this time is of a magnitude that can perform solid-phase diffusion bonding between the heat dissipation member 70 and the substrate 11 via the first bonding layer 19. The temperatures of the heat dissipation member 70, the first bonding layer 19, and the substrate 11 may be heated to a temperature that allows solid-phase diffusion bonding.

[0106] The process of placing the first bonding layer 19 and the process of bonding the heat dissipation member 70 and the substrate 11 via the first bonding layer 19 by solid-state diffusion bonding may be performed sequentially at different times, or may be performed together at the same (or approximately the same) time.

[0107] 23 , for example, a first power terminal 13, two second power terminals 14, a third power terminal 15, a first wiring 61, a second wiring 62, a plurality of sleeves 63, a plurality of semiconductor elements 20, a plurality of first wires 41, a plurality of second wires 42, a plurality of fourth wires 44, a plurality of fifth wires 45, a plurality of sixth wires 46, a plurality of seventh wires 47, a first conductive member 31, a second conductive member 32, etc. are attached appropriately to the substrate 11. Note that in the illustrated example, a plurality of signal terminals 16 have not yet been attached.

[0108] Next, as shown in FIG. 24 , the mold Md is placed on the heat dissipation member 70. The mold Md has a cavity m1. The mold Md is placed so that the cavity m1 accommodates the substrate 11 and the above-mentioned components attached to the substrate 11. Furthermore, the mold Md may be placed so that the cavity m1 accommodates the protrusion 73. A bottom surface m2 of the mold Md facing the second side z2 in the first direction z may be pressed against the sixth surface 706. An edge m3 of the cavity m1 may be located outward from the protrusion 73 when viewed in the first direction z. The edge m3 may be in contact with the sixth surface 706.

[0109] 25, the cavity m1 is filled with a resin material and the resin material is cured, thereby forming the sealing resin 50.

[0110] Thereafter, for example, the signal terminals 16 may be press-fitted into the sleeves 63. Through the above steps, the semiconductor device B10 is obtained.

[0111] Next, a vehicle C equipped with the semiconductor device B10 will be described with reference to Fig. 26. The vehicle C is, for example, an electric vehicle (EV).

[0112] As shown in Fig. 26, vehicle C includes an on-board charger 81, a storage battery 82, and a drive system 83. Power is supplied to the on-board charger 81 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 81 via a wired connection. The on-board charger 81 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 81 is stepped up by the converter and then supplied to the storage battery 82. The stepped-up voltage is, for example, 600 V.

[0113] The drive system 83 drives the vehicle C. The drive system 83 includes an inverter 831 and a drive source 832. The semiconductor device B10 constitutes part of the inverter 831. Power stored in the storage battery 82 is supplied to the inverter 831. The power supplied from the storage battery 82 to the inverter 831 is DC power. Alternatively, unlike the power system shown in FIG. 26 , a step-up DC-DC converter may be further provided between the storage battery 82 and the inverter 831. The inverter 831 converts DC power into AC power. The inverter 831 including the semiconductor device B10 is connected to the drive source 832. The drive source 832 includes an AC motor and a transmission. When the AC power converted by the inverter 831 is supplied to the drive source 832, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle C. This drives the vehicle C. To drive the vehicle C, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the semiconductor device B10 in the inverter 831 is necessary to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0114] Next, the effects of the method for manufacturing the semiconductor device B10 and the semiconductor unit A10 will be described.

[0115] The heat dissipation member 70 has a first surface 701 and a second surface 702. The first bonding layer 19 is located between the first surface 701 and the second surface 702 in the second direction x. This makes it possible to reduce misalignment of the first bonding layer 19 with respect to the heat dissipation member 70 in the second direction x in the manufacturing method of the semiconductor device B10. This allows the substrate 11 and the heat dissipation member 70 to be more appropriately bonded.

[0116] The heat dissipation member 70 has a protective layer 793 and a fourth surface 704. The first bonding layer 19 is located between the first surface 701 and the second surface 702 in the third direction y. This makes it possible to reduce misalignment of the first bonding layer 19 with respect to the heat dissipation member 70 in the third direction y in the manufacturing method of the semiconductor device B10. This allows the substrate 11 and the heat dissipation member 70 to be more appropriately bonded.

[0117] The heat dissipation member 70 has protrusions 73. This allows the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 to be appropriately positioned.

[0118] After bonding the substrate 11 and the heat dissipation member 70 via the first bonding layer 19, the semiconductor element 20 is mounted and the sealing resin 50 is formed. Therefore, when bonding the substrate 11 and the heat dissipation member 70, other components can be prevented from interfering with the bonding process.

[0119] The sealing resin 50 covers the protrusion 73, and the peripheral edge 501 is located outside the protrusion 73. This makes it possible to reliably abut the bottom surface m2 of the mold Md against the sixth surface 706 when forming the semiconductor device B10, as shown in FIG. 24 , and the sealing resin 50 can be formed more reliably and easily.

[0120] 16, the height H1 is smaller than the height H0, which makes it possible to ensure an insulating distance between the fifth surface 705 and the first conductive layer 121.

[0121] The first power terminal 13, the second power terminal 14, and the third power terminal 15 do not protrude from the sealing resin 50 as viewed in the first direction z. This makes it possible to prevent the first power terminal 13, the second power terminal 14, and the third power terminal 15 from interfering with the mold Md when forming the sealing resin 50 shown in Figures 24 and 25. For example, after forming the sealing resin 50 shown in Figure 1 etc., another conductive member that protrudes from the sealing resin 50 as viewed in the first direction z may be attached to at least one of the first power terminal 13, the second power terminal 14, and the third power terminal 15.

[0122] The signal terminals 16 protrude from the top surface 51 of the sealing resin 50. By adopting this configuration, it is possible to ensure a longer creepage distance from the signal terminals 16 to the heat dissipation member 70.

[0123] 27 to 48 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0124] 27 and 28 show a first modified example of the semiconductor device B 10. In the semiconductor device B11 of this modified example, the relationship between the sealing resin 50 and the protrusions 73 is different from that in the above-described example.

[0125] In this modified example, a portion of the protrusion 73 is covered with the sealing resin 50. The peripheral edge 501 is located on the fifth surface 705. The sixth surface 706 is exposed from the sealing resin 50. In the manufacturing method of the semiconductor unit A11, the edge m3 of the mold Md illustrated in FIGS. 24 and 25 is located on the fifth surface 705. The relationship between the sealing resin 50 and the first surface 701 may be applied to the relationships between the sealing resin 50 and the second surface 702, the third surface 703, and the fourth surface 704.

[0126] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this modification, the relationship between the protrusions 73 and the sealing resin 50 is not limited in any way.

[0127] 29 and 30 show a second modified example of the semiconductor device B 10. In the semiconductor device B12 of this modified example, the relationship between the sealing resin 50 and the protrusions 73 is different from that in the above-described example.

[0128] In this modified example, a portion of the protrusion 73 is covered with the sealing resin 50. The peripheral edge 501 is located at the boundary between the first surface 701 and the fifth surface 705. The fifth surface 705 is exposed from the sealing resin 50. In the manufacturing method of the semiconductor unit A11, the edge m3 of the mold Md illustrated in FIGS. 24 and 25 is located at the boundary between the fifth surface 705 and the first surface 701. The relationship between the sealing resin 50 and the first surface 701 may be applied to the relationships between the sealing resin 50 and the second surface 702, the third surface 703, and the fourth surface 704.

[0129] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this modification, the relationship between the protrusions 73 and the sealing resin 50 is not limited in any way.

[0130] 31 shows a third modification of the semiconductor device B 10. In the semiconductor device B13 of this modification, the configuration regarding the angle α1 differs from the above-described examples.

[0131] In this modification, angle α1 is smaller than 90° and larger than angle α0. The relationship between angle α0 and angle α1 may be applied to the relationship between end surface 1122 and second surface 702, third surface 703, and fourth surface 704.

[0132] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. When the substrate 11 illustrated in Fig. 21 is placed on the first bonding layer 19, for example, if the substrate 11 is shifted to the first side x1 in the second direction x, the end surface 1122 may abut on the boundary between the first surface 701 and the fifth surface 705 shown in Fig. 31. By making the angle α1 smaller than 90°, the position of the substrate 11 shifted to the first side x1 in the second direction x can be adjusted to the second side x2 in the second direction x.

[0133] 32 shows a fourth modification of the semiconductor device B 10. In the semiconductor device B 14 of this modification, the configurations of the protrusion 73 and the fifth surface 705 are different from those in the above-described example.

[0134] In this modified example, a portion of the fifth surface 705 connected to the first surface 701 is inclined with respect to the second direction x and is located closer to the second side z2 in the first direction z as it moves toward the first side x1 in the second direction x. A portion of the fifth surface 705 connected to the second surface 702 may be inclined with respect to the second direction x and may be located closer to the second side z2 in the first direction z as it moves closer to the second side x2 in the second direction x. A portion of the fifth surface 705 connected to the third surface 703 may be inclined with respect to the third direction y and may be located closer to the second side z2 in the first direction z as it moves closer to the first side y1 in the third direction y. A portion of the fifth surface 705 connected to the fourth surface 704 may be inclined with respect to the third direction y and may be located closer to the second side z2 in the first direction z as it moves closer to the second side y2 in the third direction y. An outer edge of the fifth surface 705 as viewed in the first direction z may contact the sixth surface 706. In this case, the cross-sectional shape of the protrusion 73 can be a triangle. Alternatively, the cross-sectional shape of the protrusion 73 can be a trapezoid.

[0135] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this modification, the specific configurations of the protrusion 73 and the fifth surface 705 are not limited in any way.

[0136] 33 shows a fifth modified example of the semiconductor device B10. For ease of understanding, the semiconductor unit is omitted from the drawing. In the semiconductor device B15 of this modified example, the configurations of the protrusion 73, the first surface 701, the second surface 702, the third surface 703, the fourth surface 704, and the fifth surface 705 are different from those of the above-described example.

[0137] In this modified example, the heat dissipation member 70 has a plurality of protrusions 73. Two of the protrusions 73 extend along the second direction x, and the other two protrusions 73 extend along the third direction y. The two protrusions 73 extending along the third direction y include a first surface 701 and a second surface 702. The two protrusions 73 extending along the second direction x include a third surface 703 and a fourth surface 704. Corresponding to the four protrusions 73, the heat dissipation member 70 may have four fifth surfaces 705.

[0138] The main surface 700 of this modified example may be a surface surrounded by a first surface 701, a second surface 702, a third surface 703, and a fourth surface 704, as well as imaginary lines extending from these surfaces, when viewed in the first direction z.

[0139] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. According to this modification, in the step of forming the sealing resin 50 shown in Figures 24 and 25 , the resin material for forming the sealing resin 50 can easily spread between the plurality of protrusions 73 and among the first conductive layer 121 and the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704.

[0140] 34 shows a sixth modified example of the semiconductor device B10. For ease of understanding, the semiconductor unit is omitted from the drawing. In the semiconductor device B16 of this modified example, the configurations of the protrusion 73, the first surface 701, the second surface 702, the third surface 703, the fourth surface 704, and the fifth surface 705 are different from those of the above-described example.

[0141] In this modified example, the heat dissipation member 70 has a plurality of protrusions 73. Each protrusion 73 is L-shaped and has portions extending along the second direction x and the third direction y. In the illustrated example, the four protrusions 73 are positioned so as to correspond to the four corners of the first bonding layer 19.

[0142] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. According to this modification, in the step of forming the sealing resin 50 shown in Figures 24 and 25 , the resin material for forming the sealing resin 50 can easily spread between the plurality of protrusions 73 and among the first conductive layer 121 and the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704.

[0143] 35 shows a seventh modified example of the semiconductor device B10. For ease of understanding, the semiconductor unit is omitted from the figure. In the semiconductor device B17 of this modified example, the heat dissipation member 70 has two protrusions 73. The two protrusions 73 are spaced apart in the second direction x. One of the protrusions 73 includes a first surface 701, and the other protrusion 73 includes a second surface 702. The heat dissipation member 70 does not need to have the third surface 703 or the fourth surface 704.

[0144] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. According to this modification, the first bonding layer 19 can be positioned in the second direction x in the step of placing the first bonding layer 19 illustrated in FIGS.

[0145] As can be seen from the semiconductor devices B15 to B17, the specific configuration of the protrusions 73 and the like is not limited in any way.

[0146] 36 shows an eighth modified example of the semiconductor device B10. The semiconductor device B18 of this modified example includes a semiconductor unit A18. The arrangement of the multiple signal terminals 16 of the semiconductor unit A18 differs from the example described above. In this modified example, the multiple signal terminals 16 are positioned offset to one side with respect to the center of the sealing resin 50 in the second direction x. In the illustrated example, the multiple signal terminals 16 are positioned offset to the second side x2 in the second direction x, and are closer to the third power terminal 15 than the first power terminal 13 and the second power terminal 14.

[0147] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this modification, the specific configuration of the plurality of signal terminals 16 is not limited in any way.

[0148] 37 to 40 show a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device B20 according to this embodiment differs from the above-described embodiment mainly in the configuration of the heat dissipation member 70. For ease of understanding, the semiconductor unit A20 is omitted from FIG. 40. The semiconductor unit A20 may have a configuration similar to that of the above-described semiconductor unit A11, for example.

[0149] In this embodiment, the heat dissipation member 70 has a recess 74. The recess 74 includes a main surface 700, a first surface 701, a second surface 702, a third surface 703, and a fourth surface 704, and is recessed from a fifth surface 705 toward a second side z2 in the first direction z. The specific shape of the protrusion 73 is not limited in any way, and in the illustrated example, it is rectangular. The first bonding layer 19 is housed in the protrusion 73.

[0150] The periphery 501 of the sealing resin 50 is located on the fifth surface 705 and is located outside the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 when viewed in the first direction z.

[0151] This embodiment allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. The heat dissipation member 70 has the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704. Various configurations can be adopted, such as a configuration including protrusions 73 or a configuration including recesses 74.

[0152] 41 shows a first modified example of the semiconductor device B20. For ease of understanding, the semiconductor unit is omitted from the drawing. In the semiconductor device B21 of this modified example, the recess 74 has an extension 741.

[0153] When viewed in the first direction z, the extending portion 741 extends from a region surrounded by the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 and imaginary lines extending from these surfaces. In the illustrated example, the recess 74 includes four extending portions 741. The four extending portions 741 are each L-shaped and are located corresponding to the four corners of the first bonding layer 19.

[0154] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. According to this modification, in the step of forming the sealing resin 50 shown in FIGS. 24 and 25 , the resin material for forming the sealing resin 50 can be easily spread from the multiple extension portions 741 to between the first conductive layer 121 and the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704.

[0155] 42 shows a second modified example of the semiconductor device B20. For ease of understanding, the semiconductor unit is omitted from the drawing. In the semiconductor device B22 of this modified example, each of the four extension portions 741 has: Two of the extension portions 741 extend along the second direction x, and the other two of the extension portions 741 extend along the third direction y. The four extension portions 741 are spaced apart from one another.

[0156] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. According to this modification, in the step of forming the sealing resin 50 shown in FIGS. 24 and 25 , the resin material for forming the sealing resin 50 can be easily spread from the multiple extension portions 741 to between the first conductive layer 121 and the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704.

[0157] 43 shows a semiconductor device according to a third embodiment of the present disclosure. The semiconductor device B30 of this embodiment differs from the above-described embodiments in the configuration of the heat dissipation section 72. The heat dissipation section 72 of this embodiment includes a plurality of flow paths 721. The plurality of flow paths 721, for example, penetrate the heat dissipation section 72 in the second direction x and can allow a cooling medium to flow. The semiconductor unit A30 may have a configuration similar to that of the above-described semiconductor unit A10, for example.

[0158] This embodiment allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this embodiment, there is no limitation on the specific configuration of the heat dissipation portion 72. Furthermore, the heat dissipation member 70 may not have the heat dissipation portion 72.

[0159] 44 shows a semiconductor device according to a fourth embodiment of the present disclosure. A semiconductor device B40 of this embodiment includes a plurality of semiconductor units A40.

[0160] The plurality of semiconductor units A40 are fixed to one heat dissipation member 70. The specific configuration of the semiconductor unit A40 is not limited in any way and may be, for example, the same configuration as the semiconductor unit A10 described above. The heat dissipation member 70 may have a plurality of first surfaces 701, second surfaces 702, third surfaces 703, and fourth surfaces 704 corresponding to the plurality of semiconductor units A40. In the illustrated example, the heat dissipation member 70 may have a plurality of protrusions 73 corresponding to the plurality of semiconductor units A40. Each protrusion 73 may be, for example, rectangular or annular when viewed in the first direction z.

[0161] This embodiment allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. By providing a plurality of semiconductor units A40 fixed to one heat dissipation member 70, the semiconductor device B40 can be made smaller.

[0162] 45 shows a first modified example of the semiconductor device B40. The semiconductor device B41 of this modified example includes a plurality of semiconductor units A41. The specific configuration of the semiconductor units A41 is not limited in any way, and may be the same as the configuration of the semiconductor unit A11 described above, for example.

[0163] The semiconductor units A41 adjacent to each other in the third direction y are positioned across one protrusion 73. The semiconductor units A41 adjacent to each other in the third direction y share one protrusion 73.

[0164] This embodiment allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. Adjacent semiconductor units A41 share one protrusion 73, which allows for further reduction in the size of the semiconductor device B41 in the third direction y.

[0165] 46 to 49 show a semiconductor device according to a fifth embodiment of the present disclosure. In a semiconductor device B50 of this embodiment, the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 are not covered with the sealing resin 50. However, the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704 may be in contact with a portion of the sealing resin 50. In a semiconductor unit A50, a first power terminal 13, two second power terminals 14, and two third power terminals 15 protrude from the sealing resin 50 as viewed in the z direction. The first power terminal 13 and the two second power terminals 14 protrude from the sealing resin 50 toward a first side x1 in the second direction x. The two third power terminals 15 protrude from the sealing resin 50 toward a second side x2 in the second direction x. The components of the semiconductor unit A50 other than the first power terminal 13, the second power terminal 14, and the third power terminal 15 may be similar to those of the semiconductor units A10 to A41 described above.

[0166] The first bonding layer 19 may be larger than the rear surface 1121 and may extend outside the periphery 501 of the sealing resin 50 when viewed in the z direction. There may be gaps between the sealing resin 50 and the first surface 701, the second surface 702, the third surface 703, and the fourth surface 704. The height H1 of the protrusion 73 may be smaller than the height H0, or may be larger than the height H0, different from the example shown in the figure.

[0167] A method for manufacturing semiconductor device B50 will be described with reference to Fig. 50. In the method for manufacturing semiconductor device B50, a step of mounting a semiconductor element 20 on substrate 11 and a step of forming a sealing resin 50 covering semiconductor element 20 are performed before a step of bonding substrates 11 and 70 via first bonding layer 19 by solid-state diffusion bonding. Before the above-mentioned bonding step by solid-state diffusion bonding, an intermediate product may be formed in which a plurality of signal terminals 16 has been removed from semiconductor unit A50.

[0168] Next, a first bonding layer 19 is placed on the main surface 700 of the heat dissipation member 70. Next, the heat dissipation member 70 and the substrate 11 of the intermediate product are bonded via the first bonding layer 19 by solid-state diffusion bonding. Thereafter, a plurality of signal terminals 16 are attached to the intermediate product by press-fitting or the like. With the above configuration, the semiconductor device B50 is obtained.

[0169] This embodiment allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this embodiment, an intermediate product of the semiconductor unit A50 may be formed before the step of bonding the substrates 11 and 70 via the first bonding layer 19 by solid-state diffusion bonding. The manufacturing method of this embodiment reduces interference between the first power terminal 13, the second power terminal 14, and the third power terminal 15, which protrude from the sealing resin 50, and other components.

[0170] 51 shows a first modified example of the semiconductor device B50. The semiconductor device B51 of this modified example includes a semiconductor unit A51. The arrangement of the multiple signal terminals 16 of the semiconductor unit A51 differs from the example described above. In this modified example, the multiple signal terminals 16 are positioned offset to one side with respect to the center of the sealing resin 50 in the second direction x. In the illustrated example, the multiple signal terminals 16 are positioned offset to the second side x2 in the second direction x, and are closer to the third power terminal 15 than the first power terminal 13 and the second power terminal 14.

[0171] This modification allows for more appropriate bonding of the substrate 11 and the heat dissipation member 70. As can be understood from this modification, the specific configuration of the plurality of signal terminals 16 is not limited in any way.

[0172] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0173] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1: A semiconductor device comprising: one or more semiconductor units (A10); a heat dissipation member (70) to which the semiconductor units (A10) are fixed; and a first bonding layer (19) interposed between the semiconductor unit (A10) and the heat dissipation member (70), wherein the semiconductor unit (A10) includes: a substrate (11); a semiconductor element (20) mounted on the substrate (11); and a sealing resin (50) covering a portion of the substrate (11) and the semiconductor element (20), and the heat dissipation member (70) includes: a main surface (700) facing a first side (z1) in a first direction (z), and a first surface (701) located on a first side (x1) and a second surface (702) located on a second side (x2) of the main surface (700) in a second direction (x) intersecting the first direction (z), The semiconductor device (B10) according to Appendix 1, wherein the first bonding layer (19) is fixed to the main surface (700) and is located between the first surface (701) and the second surface (702) in the second direction (x). Appendix 2. The semiconductor device (B10) according to Appendix 1, wherein the heat dissipation member (70) includes a third surface (703) located on a first side (y1) and a fourth surface (704) located on a second side (y2) of the main surface (700) in a third direction (y) intersecting the first direction (z) and the second direction (x), and the first bonding layer (19) is located between the third surface (703) and the fourth surface (704) in the third direction (y). Appendix 3. The semiconductor device (B10) according to any one of Supplementary Notes 1 to 3, wherein the substrate (11) includes an insulating layer (111), a first conductive layer (121) located on the first side (z1) in the first direction (z) with respect to the insulating layer (111), and a second conductive layer (122) located on the second side (z2) in the first direction (z) with respect to the insulating layer (111), and wherein a height (H1) of the first surface (701) in the first direction (z) is smaller than a height (H0) that is the distance between the main surface (700) and the insulating layer (111) in the first direction (z).Appendix 5. The semiconductor device (B10) according to Appendix 3, wherein the semiconductor unit (A10) includes a first power terminal (13), a second power terminal (14), and a third power terminal (15), and the first power terminal (13), the second power terminal (14), and the third power terminal (15) do not protrude from the sealing resin (50) when viewed in the first direction (z). Appendix 6. The semiconductor device (B10) according to Supplementary Note 4 or 5, wherein the heat dissipation member (70) includes a fifth surface (705) that is connected to the outside in the second direction (x) with respect to the first surface (701) and the second surface (702) and is located on the first side (z1) in the first direction (z) from the main surface (700), and the heat dissipation member (70) includes a protrusion (73) that includes the first surface (701), the second surface (702), and the fifth surface (705), and a sixth surface (706) that is located on the outside in the second direction (x) with respect to the protrusion (73) and is located on the second side (z2) in the first direction (z) from the fifth surface (705).Supplementary Note 7. The semiconductor device (B10) according to Supplementary Note 6, wherein the protrusion (73) is covered with the sealing resin (50), and a periphery (501) of the sealing resin (50) is located on the sixth surface (706).Supplementary Note 8. The semiconductor device (B11) according to Supplementary Note 7, wherein the periphery (501) is located on the fifth surface (705). Supplementary Note 9. The heat dissipation member (70) includes a fifth surface (705) that is connected to the first surface (701) and the second surface (702) on the outside in the second direction (x) and is located on the first side (z1) in the first direction (z) from the main surface (700), and the heat dissipation member (70) includes a recess (74) that includes the first surface (701), the second surface (702), and the fifth surface (705). Supplementary Note 10. The semiconductor device (B50) according to any one of Supplementary Notes 1 to 3, wherein the first surface (701) and the second surface (702) are not covered with the sealing resin (50).Supplementary Note 11. The semiconductor device (B50) according to Supplementary Note 10, wherein the semiconductor unit (A10) includes a first power terminal (13), a second power terminal (14), and a third power terminal (15), and the first power terminal (13), the second power terminal (14), and the third power terminal (15) protrude from the sealing resin (50) when viewed in the first direction (z). Supplementary Note 12. The semiconductor device (B40) according to any one of Supplements 1 to 11, comprising a plurality of the semiconductor units (A40). Supplementary Note 13. A method for manufacturing a semiconductor device (B10), comprising the steps of: preparing a heat dissipation member (70) including a main surface (700) facing a first side (z1) in a first direction (z), and a first surface (701) located on a first side (x1) and a second surface (702) located on a second side (x2) of the main surface (700) in a second direction (x) intersecting the first direction (z); placing a first bonding layer (19) on the main surface (700) between the first surface (701) and the second surface (702) in the second direction (x); and bonding the heat dissipation member (70) and a substrate (11) via the first bonding layer (19) by solid-state diffusion bonding. A method for manufacturing a semiconductor device (B10) according to Supplementary Note 13, comprising, after the step of bonding by solid-state diffusion bonding, a step of mounting a semiconductor element (20) on the substrate (11), and a step of forming a sealing resin (50) covering the substrate (11). Supplementary Note 15. A method for manufacturing a semiconductor device (B50) according to Supplementary Note 13, further comprising, before the step of bonding by solid-state diffusion bonding, a step of mounting a semiconductor element (20) on the substrate (11) and a step of forming a sealing resin (50) covering the semiconductor element (20), thereby forming a semiconductor unit (A50). Supplementary Note 16. The semiconductor device (B10) according to any of Supplements 1 to 15, wherein the semiconductor unit (A10) comprises a plurality of signal terminals (16), and the plurality of signal terminals (16) protrude from the sealing resin (50) towards the first side (z1) in the first direction (z). Supplementary Note 17. The semiconductor unit (A10) according to any one of appendices 1 to 16, wherein the first bonding layer (19) is larger than the back surface (1121) of the metal layer (112) when viewed in the first direction (z).Supplementary Note 18. The semiconductor device (B50) according to Supplementary Note 10 or 11, wherein the first bonding layer (19) is larger than the semiconductor unit (A50) when viewed in the first direction (z). Supplementary Note 19. The semiconductor device (B10) according to any one of Supplements 4 to 9, wherein the first bonding layer (19) is in contact with the sealing resin (50). Supplementary Note 20. The semiconductor device (B50) according to Supplementary Note 10 or 11, wherein the first bonding layer (19) is exposed from the sealing resin (50). Supplementary Note 21. A vehicle (C) comprising: a drive source (832); and the semiconductor device (B10) according to any one of Supplements 1 to 20, wherein the semiconductor device (B10) is electrically connected to the drive source (832).

[0174] A10, A11, A18, A40, A41, A50, A51: Semiconductor unit B10, B11, B12, B13, B14, B15, B16, B17, B18, B20, B21, B22, B30, B40, B41, B50, B51: Semiconductor device C: Vehicle 11: Substrate 13: First power terminal 14: Second power terminal 15: Third power terminal 16: Signal terminal 19: First bonding layer 20: Semiconductor element 21: First semiconductor element 22: Second semiconductor element 23: Thermistor 29: Second bonding layer 31: First conductive member 32: Second conductive member 39: Third bonding layer 41: First wire 42: Second wire 44: Fourth wire 45: Fifth wire 46: Sixth wire 47: Seventh wire 50: Sealing resin 51: Top surface 52: Bottom surface 53: First side surface 54: Second side surface 55: Recess 55A: First recess 55B: Second recess 55C: Third recess 61: First wiring 62: Second wiring 63: Sleeve 70: Heat dissipation member 71: Base 72: Heat dissipation portion 73: Protrusion 74: Recess 81: On-board charger 82: Storage battery 83: Drive system 111: Insulating layer 111A: Periphery 112: Metal layer 121: First conductive layer 121A: First mounting surface 122: Second conductive layer 122A: Second mounting surface 131: First connecting surface 141: Second connecting surface 151: Third connecting surface 161: First signal terminal 162: Second signal terminal 171: Third signal terminal 172: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 211: First electrode 212: Second electrode 213: First gate electrode 214: First detection electrode 221: Third electrode 222: Fourth electrode 223: Second gate electrode 224: Second detection electrode 311: Main portion 312: First bonding portion 313: First connecting portion 314: Second bonding portion 315: Second connecting portion 321: Main portion 322: Third bonding portion 323: Third connecting portion 326: Middle portion 327: Cross beam portion 501: Periphery 611: First mounting layer 612: First metal layer 613: First gate wiring layer 614: First detection wiring layer 615: First temperature detection wiring layer 616: Second detection wiring layer 621: Second mounting layer 622: Second metal layer 623: Second gate wiring layer 624: Third detection wiring layer625: Second temperature detection wiring layer 626: Fourth detection wiring layer 631: End surface 700: Main surface 701: First surface 702: Second surface 703: Third surface 704: Fourth surface 705: Fifth surface 706: Sixth surface 711: Periphery 712: End surface 721: Flow path 741: Extension portion 793: Protective layer 831: Inverter 832: Driving source 1121: Back surface 1122: End surface H0, H1: Height Md: Mold m1: Cavity m2: Bottom surface m3: Edge x: Second direction x1: First side x2: Second side y: Third direction y1: First side y2: Second side z: First direction z1: First side z2: Second side α0, α1: Angle

Claims

1. A semiconductor device comprising: one or more semiconductor units; a heat dissipation member to which the semiconductor units are fixed; and a first bonding layer interposed between the semiconductor units and the heat dissipation member, wherein the semiconductor units include a substrate; a semiconductor element mounted on the substrate; and a sealing resin covering a portion of the substrate and the semiconductor element, wherein the heat dissipation member includes a main surface facing a first side in a first direction, and a first surface located on the first side and a second surface located on the second side, sandwiching the main surface in a second direction intersecting the first direction, and the first bonding layer is fixed to the main surface and is located between the first surface and the second surface in the second direction.

2. The semiconductor device described in claim 1, wherein the heat dissipation component includes a third surface located on a first side of the main surface and a fourth surface located on a second side thereof in a third direction intersecting the first direction and the second direction, and the first bonding layer is located between the third surface and the fourth surface in the third direction.

3. The semiconductor device according to claim 1 or 2, wherein the substrate includes an insulating layer, a first conductive layer located on the first side of the insulating layer in the first direction, and a second conductive layer located on the second side of the insulating layer in the first direction, and the height of the first surface in the first direction is smaller than the height that is the distance between the main surface and the insulating layer in the first direction.

4. The semiconductor device according to claim 1, wherein the first surface and the second surface are covered with the sealing resin.

5. The semiconductor device according to claim 3, wherein the semiconductor unit includes a first power terminal, a second power terminal, and a third power terminal, and the first power terminal, the second power terminal, and the third power terminal do not protrude from the sealing resin when viewed in the first direction.

6. A semiconductor device as described in claim 4 or 5, wherein the heat dissipation member includes a fifth surface that is connected to the outside of the first surface and the second surface in the second direction and is located on the first side of the main surface in the first direction, and the heat dissipation member includes a protrusion that includes the first surface, the second surface, and the fifth surface, and a sixth surface that is located on the outside of the protrusion in the second direction and is located on the second side of the fifth surface in the first direction.

7. The semiconductor device according to claim 6, wherein the protrusion is covered with the sealing resin, and the periphery of the sealing resin is located on the sixth surface.

8. The semiconductor device according to claim 7, wherein said periphery is located on said fifth surface.

9. The semiconductor device described in claim 4 or 5, wherein the heat dissipation member includes a fifth surface that is connected to the outside in the second direction relative to the first surface and the second surface and is located on the first side in the first direction relative to the main surface, and the heat dissipation member includes a recess that includes the first surface, the second surface, and the fifth surface.

10. The semiconductor device according to any one of claims 1 to 3, wherein the first surface and the second surface are not covered with the sealing resin.

11. The semiconductor device according to claim 10, wherein the semiconductor unit includes a first power terminal, a second power terminal, and a third power terminal, and the first power terminal, the second power terminal, and the third power terminal protrude from the sealing resin when viewed in the first direction.

12. The semiconductor device according to any one of claims 1 to 11, comprising a plurality of said semiconductor units.

13. A method for manufacturing a semiconductor device, comprising the steps of: preparing a heat dissipation member including a main surface facing a first side in a first direction, and a first surface located on the first side and a second surface located on the second side of the main surface in a second direction intersecting the first direction; placing a first bonding layer on the main surface between the first surface and the second surface in the second direction; and bonding the heat dissipation member and a substrate via the first bonding layer by solid-state diffusion bonding.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising the steps of: mounting a semiconductor element on the substrate; and forming a sealing resin to cover the substrate, after the step of bonding by solid phase diffusion bonding.

15. The method for manufacturing a semiconductor device according to claim 13, further comprising, before the step of bonding by solid-phase diffusion bonding, a step of mounting a semiconductor element on the substrate and a step of forming a sealing resin to cover the semiconductor element, thereby forming a semiconductor unit.

Images