Semiconductor element and multilayer structure

Abstract

[Problem] The present invention suppresses performance variation. [Solution] This semiconductor device includes: a first semiconductor chip; a second semiconductor chip which is superposed on the first semiconductor chip and has a size that is the same as the size of the first semiconductor chip; a third semiconductor chip which is superposed on the first semiconductor chip or the second semiconductor chip and has a size that is different from the size of the first semiconductor chip and the second semiconductor chip; and a member which covers the third semiconductor chip and is provided so as to embed a layer of the third semiconductor chip. A surface on the reverse side of the member from the third semiconductor chip has a shape that corresponds to the third semiconductor chip.

Description

Semiconductor element and laminated structure

[0001] FIELD Embodiments according to the present disclosure relate to semiconductor devices and stacked structures.

[0002] In some cases, a material is embedded between a plurality of chips and then polished (chip embedding and planarization process) (see Patent Document 1).

[0003] JP 2015-53469 A

[0004] However, the chip embedding process is difficult and may result in undulations due to the chip shape, which may lead to variations in performance.

[0005] Therefore, the present disclosure provides a semiconductor element and a stacked structure that can suppress performance variations.

[0006] In order to solve the above problems, according to the present disclosure, there is provided a semiconductor element comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and having the same size as the first semiconductor chip; a third semiconductor chip stacked on the first semiconductor chip or the second semiconductor chip and having a size different from the sizes of the first semiconductor chip and the second semiconductor chip; and a member covering the third semiconductor chip and provided to embed a layer of the third semiconductor chip, wherein the surface of the member opposite to the third semiconductor chip has a shape corresponding to the third semiconductor chip.

[0007] The member may be a first insulating film.

[0008] The surface of the member opposite to the third semiconductor chip may have a convex shape that protrudes toward the opposite side to the third semiconductor chip at a position corresponding to the position of the third semiconductor chip.

[0009] The semiconductor device may further include a support substrate facing the member, wherein a surface of the support substrate facing the member has a shape that is an inverse of a shape of a surface of the member opposite to the third semiconductor chip.

[0010] One of the first semiconductor chip and the second semiconductor chip opposite the third semiconductor chip may have a semiconductor substrate, and a surface of the semiconductor substrate may have a shape different from the shape of the surface of the member opposite the third semiconductor chip.

[0011] The surface of the semiconductor substrate may have a substantially flat shape.

[0012] The third semiconductor chip may be provided as one chip.

[0013] The component may include a plurality of third semiconductor chips stacked on the same layer, the plurality of third semiconductor chips having the same shape, and the surface of the component opposite to the third semiconductor chips having a shape corresponding to the arrangement and shape of the third semiconductor chips.

[0014] The component may include a plurality of third semiconductor chips stacked on the same layer, the plurality of third semiconductor chips having different shapes, and the surface of the component opposite to the third semiconductor chips may have a shape corresponding to the arrangement and shape of the third semiconductor chips.

[0015] The third semiconductor chips may have different heights, and the surface of the member opposite to the third semiconductor chips may have a shape corresponding to the height of the third semiconductor chips.

[0016] The member may include a conductive film that embeds a layer of the third semiconductor chip, and a second insulating film that covers the third semiconductor chip and the conductive film.

[0017] The member may further include a third insulating film covering a side surface of the third semiconductor chip.

[0018] The member may further include a fourth insulating film containing a resin and embedding a layer of the third semiconductor chip together with the conductive film, and the fourth insulating film may be provided closer to the first semiconductor chip and the second semiconductor chip than the conductive film.

[0019] The semiconductor device may include a plurality of the third semiconductor chips stacked on the same layer, and the conductive film may be provided between the plurality of third semiconductor chips and have a first trench that penetrates the member in the stacking direction of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip.

[0020] The conductive film may have a plurality of second trenches extending from the second insulating film side to the inside of the conductive film.

[0021] The semiconductor device may include a plurality of third semiconductor chips stacked on the same layer, the plurality of third semiconductor chips having different heights, and a portion of the conductive film may be provided between the third semiconductor chip and the second insulating film depending on the height of the third semiconductor chip.

[0022] The semiconductor device may include a plurality of the third semiconductor chips stacked in the same layer, the third semiconductor chips having at least one dummy chip, and the second insulating film covering the dummy chip.

[0023] According to the present disclosure, there is provided a stacked structure comprising: a first wafer; a second wafer stacked on the first wafer; a fourth semiconductor chip stacked on the first wafer or the second wafer; and a member that covers the fourth semiconductor chip and is provided so as to embed a layer of the fourth semiconductor chip, wherein the surface of the member opposite the fourth semiconductor chip has a shape corresponding to the fourth semiconductor chip.

[0024] The component may include a plurality of the fourth semiconductor chips stacked on the same layer, the plurality of fourth semiconductor chips having the same shape, and the surface of the component opposite to the fourth semiconductor chips may have a shape corresponding to the arrangement and shape of the fourth semiconductor chips.

[0025] The component may include a plurality of fourth semiconductor chips stacked on the same layer, the plurality of fourth semiconductor chips having different shapes, and the surface of the component opposite to the fourth semiconductor chips may have a shape corresponding to the arrangement and shape of the fourth semiconductor chips.

[0026] 1A . FIG. 1B . FIG. 1C . FIG. 1D . FIG. 1E . FIG. 1F . FIG. 1G . FIG. 1H . FIG. 1H . FIG. 2A . FIG. 2B . FIG. 2C . FIG. 2D . FIG. 4D is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG. 4D. FIG. 4C is a cross-sectional view showing an example of a configuration of a semiconductor element according to a modified example of the third embodiment. FIG. 4D is a cross-sectional view showing an example of a configuration of a semiconductor element according to the fourth embodiment. FIG. 4G is a top view showing an example of a configuration of a trench according to the fourth embodiment. FIG. 4H is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG. 8A. FIG. 8B is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG. 8C. FIG. 8D is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG. 8E. FIG. 8F is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG. 8G. FIG. 8H is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG.16A is a cross-sectional view showing an example of a method for manufacturing a semiconductor element, subsequent to FIG. 8I. FIG. 16B is a cross-sectional view showing an example of a configuration of a semiconductor element according to a fifth embodiment. FIG. 16C is a cross-sectional view showing an example of a configuration of a semiconductor element according to a sixth embodiment. FIG. 16D is a cross-sectional view showing an example of a configuration of a hole according to a tenth embodiment. FIG. 16D is a top view showing an example of a configuration of a hole according to a tenth embodiment. FIG. 16C is a cross-sectional view showing an example of a configuration of a hole according to a sixth embodiment. FIG. 16D is a top view showing an example of a configuration of a trench and a hole according to the eleventh embodiment.

[0027] Hereinafter, embodiments of a semiconductor device and a stacked structure will be described with reference to the drawings. The following description will focus on the main components of the semiconductor device and the stacked structure, but the semiconductor device and the stacked structure may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] (First Embodiment) A stacked image sensor as a solid-state imaging device is obtained, for example, by bonding a pixel chip to a logic chip that has an AD (Analog to Digital) circuit and a logic circuit mounted thereon. The stacked chip structure, or so-called stacked structure, is a structure in which at least two chips, a pixel chip and a logic chip, are stacked. The pixel chip is an example of a first semiconductor chip. The logic chip is an example of a second semiconductor chip. The pixel chip and the logic chip are electrically connected via connecting portions such as vias, Cu-Cu junctions, and bumps.

[0029] Although a solid-state imaging device will be described below, semiconductor elements other than a solid-state imaging device may also be used. In this case, the first semiconductor chip does not have to be a pixel chip, and the second semiconductor chip does not have to be a logic chip.

[0030] 1A to 1I are cross-sectional views showing an example of a method for manufacturing a semiconductor device 101 according to the first embodiment.

[0031] The method for manufacturing the semiconductor element 101 according to the first embodiment is, for example, a chip-on-wafer (CoW) process. 1A to 1I show a part of the stacked structure 100 before the semiconductor elements 101 are separated into individual pieces.

[0032] First, as shown in FIG. 1A, the pixel wafer W1 and the logic wafer W2 are bonded together. The pixel wafer W1 is an example of a first wafer (first semiconductor wafer). The logic wafer W2 is an example of a second wafer (second semiconductor wafer).

[0033] The pixel wafer W1 has a semiconductor substrate 11, an insulating layer 12, and a pad 13. The pixel wafer W1 includes, for example, a photoelectric conversion element (not shown).

[0034] The insulating layer 12 is provided below the semiconductor substrate 11 .

[0035] The pads 13 are provided so as to be exposed from the insulating layer 12 and are electrically connected to wiring within the pixel wafer W1.

[0036] The logic wafer W2 includes a semiconductor substrate 21, an insulating layer 22a, and pads 23a. The logic wafer W2 includes, for example, a logic element (not shown).

[0037] The insulating layer 22 a is provided on the semiconductor substrate 21 .

[0038] The pads 23a are provided so as to be exposed from the insulating layer 22a and are electrically connected to the wiring in the logic wafer W2.

[0039] Furthermore, the pads 13 of the pixel wafer W1 are bonded to the pads 23a of the logic wafer W2.

[0040] Next, the semiconductor substrate 21 of the logic wafer W2 is thinned as shown in Fig. 1B, which is upside down from Fig. 1A.

[0041] Next, as shown in FIG. 1C, an insulating layer 22b, pads 23b, and vias 24 are formed on the logic wafer W2.

[0042] The insulating layer 22 b is provided on the semiconductor substrate 21 .

[0043] The pads 23b are provided so as to be exposed from the insulating layer 22b and are electrically connected to the wiring in the logic wafer W2.

[0044] The vias 24 are provided to penetrate the semiconductor substrate 21. The vias 24 are, for example, through-silicon vias (TSVs). The vias 24 electrically connect the wiring in the insulating layer 22a and the wiring in the insulating layer 22b.

[0045] Next, as shown in FIG. 1D , the logic wafer W2 and a plurality of semiconductor chips CH are bonded together. The semiconductor chips CH are provided, for example, on a chip layer CHL on the logic wafer W2. The chip layer CHL is a layer of the semiconductor chips CH. In the example shown in FIG. 1D , two semiconductor chips CH are shown. However, three or more semiconductor chips CH may be provided. The semiconductor chips CH are an example of a third semiconductor chip and a fourth semiconductor chip.

[0046] The semiconductor chip CH has a semiconductor substrate 31, an insulating layer 32, and pads 33. The semiconductor chip CH includes a plurality of semiconductor chips of the same type. The semiconductor chip CH includes, for example, a logic chip CH1 including a logic element. Note that the logic element is not shown in the figure.

[0047] The insulating layer 32 is provided below the semiconductor substrate 31 .

[0048] The pads 33 are provided so as to be exposed from the insulating layer 32 and are electrically connected to wiring within the semiconductor chip CH.

[0049] Furthermore, the pads 23b of the logic wafer W2 are bonded to the pads 33 of the semiconductor chip CH.

[0050] 1E, the semiconductor chips CH are thinned, an insulating film 40 is formed on the logic wafer W2 and the semiconductor chips CH, and the insulating film 40 is planarized. The insulating film 40 fills the chip layer CHL, i.e., fills the spaces between the semiconductor chips CH. The insulating film 40 is also provided so as to cover the semiconductor chips CH. Therefore, the integrated insulating film 40 covers the semiconductor chips CH and also fills the chip layer CHL. The insulating film 40 is made of, for example, SiO ２ The insulating film 40 is formed by, for example, CVD (Chemical Vapor Deposition). ２ The insulating film 40 may be formed by, for example, chemical mechanical polishing (CMP), and may contain a resin. The resin may be applied by, for example, spin coating. The insulating film 40 may be planarized by, for example, CMP (Chemical Mechanical Polishing).

[0051] 1E, undulations occur on the upper surface of the insulating film 40 according to the shape and arrangement of the semiconductor chip CH. That is, the height of the upper surface of the insulating film 40 differs depending on whether or not the semiconductor chip CH is present. The surface of the insulating film 40 opposite the semiconductor chip CH has a shape corresponding to the semiconductor chip CH. More specifically, the surface of the insulating film 40 opposite the semiconductor chip CH has a convex shape that protrudes toward the opposite side of the semiconductor chip CH at a position corresponding to the position of the semiconductor chip CH.

[0052] Next, as shown in FIG. 1F, the insulating film 40 and the support substrate 50 are bonded together.

[0053] As shown in FIG. 1F, since the thickness of the support substrate 50 is substantially constant, undulations similar to those on the top surface of the insulating film 40 occur on the top surface of the support substrate 50 .

[0054] 1G, the upper surface of the support substrate 50 is ground. The support substrate 50 is ground to such an extent that no problems occur during transportation. The support substrate 50 is ground by, for example, grinding.

[0055] 1G, the waviness of the upper surface of the support substrate 50 is removed. Therefore, the support substrate 50 has thin and thick portions according to the waviness of the upper surface of the insulating film 40.

[0056] Next, as shown in FIG. 1H, the semiconductor substrate 11 of the pixel wafer W1 is thinned. Note that FIG. 1H is upside down compared to FIG. 1G. The thinning of the semiconductor substrate 11 is performed by, for example, a combination of grinding, wet processing, and CMP. Furthermore, for example, LPE (Local Planarization Etching) may be performed between the grinding, wet processing, and CMP. LPE is also called local planarization. In LPE, processing is performed based on thickness information of the semiconductor substrate 11 of the pixel wafer W1.

[0057] Next, as shown in FIG. 1I, on-chip lenses L and color filters F are formed on the semiconductor substrate 11 of the pixel wafer W1.

[0058] Thereafter, the pixel wafer W1 and the logic wafer W2 are diced into a plurality of chips, thereby forming solid-state imaging devices (semiconductor elements 101).

[0059] In the example shown in FIG. 1I, one solid-state imaging device (semiconductor element 101) has one semiconductor chip CH (one logic chip CH1). However, one solid-state imaging device (semiconductor element 101) may have multiple semiconductor chips CH (multiple logic chips CH1) stacked on the same layer (chip layer CHL). In this case, the multiple semiconductor chips CH have the same shape. The surface of the insulating film 40 opposite the semiconductor chip CH has a shape corresponding to the arrangement and shape of the semiconductor chip CH.

[0060] The pixel wafer W1 is singulated into the pixel chips. The logic wafer W2 is singulated into the logic chips. The pixel chips and the logic chips have the same horizontal size. The horizontal size of the semiconductor chip CH is smaller than the horizontal sizes of the pixel chips and the logic chips.

[0061] As described above, according to the first embodiment, the surface of the insulating film 40 opposite to the semiconductor chip CH has a shape corresponding to the semiconductor chip CH. In the step shown in FIG. 1G , undulations on the upper surface of the support substrate 50 are removed. This pushes the variations (undulations) toward the support substrate 50 side, thereby making it possible to improve the flatness of the semiconductor substrate 11 side of the pixel wafer W1.

[0062] As shown in FIG. 1I, the thickness of the semiconductor substrate 11 of the pixel wafer W1 is approximately constant regardless of the position.

[0063] Furthermore, the surface of the support substrate 50 facing the insulating film 40 has a shape that is the inverse of the shape of the surface of the insulating film 40 opposite the semiconductor chip CH. Therefore, the surface of the support substrate 50 facing the insulating film 40 has a concave shape, i.e., an inverse convex shape.

[0064] The surface of the semiconductor substrate 11 has a shape different from the shape of the surface of the insulating film 40 opposite to the semiconductor chip CH. More specifically, the surface of the semiconductor substrate 11 has a substantially flat shape.

[0065] The laminated structure 100 is not limited to three layers, and may have a laminated structure of four or more layers.

[0066] 1E, the height 40h of the waviness of the lower surface of the insulating film 40 (height in the vertical direction (stacking direction of the stacked structure 100)) is, for example, about 1 μm. In the process shown in FIG. 1G, the total thickness variation (TTV) of the upper surface of the support substrate 50 is, for example, about 0.2 μm.

[0067] 2A and 2B are cross-sectional views showing an example of a method for manufacturing a semiconductor element 101 according to a comparative example. The comparative example differs from the first embodiment in that the step of grinding the support substrate 50 shown in Fig. 1G is not performed. The step shown in Fig. 2A is performed after the same steps as those shown in Figs. 1A to 1F.

[0068] After the support substrate 50 is bonded (see FIG. 1F), the semiconductor substrate 11 of the pixel wafer W1 is thinned as shown in FIG. 2A. Note that in FIG. 2A and subsequent figures, the top and bottom are reversed from FIG. 1F.

[0069] 2A, undulations occur on the upper and lower surfaces of the semiconductor substrate 11 of the pixel wafer W1. The thickness of the semiconductor substrate 11 of the pixel wafer W1 is approximately constant regardless of the position.

[0070] Next, as shown in FIG. 2B, on-chip lenses L and color filters F are formed on the semiconductor substrate 11 of the pixel wafer W1.

[0071] In the process shown in FIG. 2A (thinning the semiconductor substrate 11), for example, a processing method that keeps the thickness of the semiconductor substrate (total wafer thickness) constant may be used. The above-described LPE processes the semiconductor substrate 11 of the pixel wafer W1 based on thickness information of the semiconductor substrate 11. Therefore, undulations on the upper surface of the insulating film 40 that occur during the embedding and planarization process (the process shown in FIG. 1E) are transferred to the surface of the semiconductor substrate 11 of the pixel wafer W1. Grinding, such as grinding, is included in backside reference processing. When the pixel wafer W1 is subjected to grinding, the portions of the pixel wafer W1 corresponding to the thick regions of the insulating film 40 are finished thinner than the portions corresponding to the thin regions of the insulating film 40. As a result, similar to LPE, undulations on the upper surface of the insulating film 40 that occur during the embedding and planarization process (the process shown in FIG. 1E) are transferred to the surface of the semiconductor substrate 11 of the pixel wafer W1.

[0072] As shown in FIG. 2A, the surface of the insulating film 40 opposite to the semiconductor chip CH is substantially flat.

[0073] 2A, problems may arise in subsequent processes. For example, if the upper surface of the semiconductor substrate 11 is substantially flat and undulations are transferred to the lower surface of the semiconductor substrate 11, the optical path length will vary depending on the position on the semiconductor substrate 11. This will result in variations in performance.

[0074] 1G, in the first embodiment, the support substrate 50 is ground before the semiconductor substrate 11 of the pixel wafer W1 is thinned. This pushes the variations (waviness) toward the support substrate 50, thereby improving the flatness of the semiconductor substrate 11 side of the pixel wafer W1. As a result, it is possible to suppress the variations in performance.

[0075] 3A to 3E are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second embodiment. The second embodiment differs from the first embodiment in that the semiconductor chip CH includes a plurality of semiconductor chips of different types. The process shown in FIG. 3A is performed after the same process as in FIGS. 1A to 1D.

[0076] After bonding the semiconductor chip CH (see FIG. 1D), the semiconductor chip CH is thinned, an insulating film 40 is formed on the logic wafer W2 and the semiconductor chip CH, and the insulating film 40 is planarized.

[0077] The semiconductor chip CH includes a plurality of different types of semiconductor chips. The semiconductor chip CH includes, for example, a logic chip CH1 including logic elements and a memory chip CH2 including memory elements. The memory chip CH2 is, for example, smaller in horizontal size than the logic chip CH1. The memory chip CH2 is, for example, taller in the vertical direction than the logic chip CH1. The semiconductor chip CH may also include a semiconductor chip having other functions, such as an AI (artificial intelligence) chip (not shown) including an AI element.

[0078] 3A, undulations occur on the upper surface of the insulating film 40 according to the shape and arrangement of the semiconductor chips CH. The upper surface of the insulating film 40 above the memory chip CH2 has undulations of a different shape from the undulations on the upper surface of the insulating film 40 above the logic chip CH1. Because the memory chip CH2 is vertically higher than the logic chip CH1, the undulations of the insulating film 40 above the memory chip CH2 are higher than the undulations of the insulating film 40 above the logic chip CH1. Therefore, the shape of the undulations on the upper surface of the insulating film 40 changes depending on the type of semiconductor chip CH.

[0079] Next, as shown in Fig. 3B, the insulating film 40 is bonded to the support substrate 50. The process shown in Fig. 3B is similar to the process shown in Fig. 1F.

[0080] Next, as shown in Fig. 3C, the upper surface of the support substrate 50 is ground. The process shown in Fig. 3C is similar to the process shown in Fig. 1G.

[0081] Next, as shown in Fig. 3D, the semiconductor substrate 11 of the pixel wafer W1 is thinned. The process shown in Fig. 3D is similar to the process shown in Fig. 1H.

[0082] Next, as shown in Fig. 3E, on-chip lenses L and color filters F are formed on the semiconductor substrate 11 of the pixel wafer W1. The process shown in Fig. 3E is similar to the process shown in Fig. 1I.

[0083] As shown in FIG. 3E, the shape of the undulations on the surface of the support substrate 50 facing the insulating film 40 also changes depending on the type of semiconductor chip CH.

[0084] Thereafter, the pixel wafer W1 and the logic wafer W2 are diced into a plurality of chips, thereby forming solid-state imaging devices (semiconductor elements 101).

[0085] In the example shown in FIG. 3E , one solid-state imaging device (semiconductor element 101) has one semiconductor chip CH (one memory chip CH2). However, one solid-state imaging device (semiconductor element 101) may have multiple semiconductor chips CH stacked on the same layer (chip layer CHL). In this case, the multiple semiconductor chips CH have different shapes. In other words, one solid-state imaging device (semiconductor element 101) may have multiple semiconductor chips CH, at least some of which are of different types.

[0086] Furthermore, at least some of the semiconductor chips CH may have different heights. The surface of the insulating film 40 opposite to the semiconductor chip CH has a shape corresponding to the height of the semiconductor chip CH.

[0087] As in the second embodiment, the semiconductor chip CH may include a plurality of semiconductor chips of different types, and in this case, the same effects as in the first embodiment can be obtained.

[0088] 4A to 4E are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a third embodiment. The third embodiment differs from the first embodiment in that the semiconductor chip CH is covered and the chip layer CHL is embedded with a member 60 that is different from the insulating film 40. The step shown in FIG. 4A is performed after the same steps as those shown in FIGS. 1A to 1D.

[0089] After bonding the semiconductor chip CH (see FIG. 1D), the semiconductor chip CH is thinned, an insulating film 63 is formed on the logic wafer W2 and on the side surfaces of the semiconductor chip CH, a conductive film 61 is formed on the insulating film 63 so as to fill the spaces between the semiconductor chips CH, and the semiconductor chip CH and the conductive film 61 are planarized.

[0090] The insulating film 63 includes, for example, SiN.

[0091] The conductive film 61 is, for example, a Si film. The conductive film 61 includes polysilicon, amorphous silicon, doped silicon, or a stack of at least two of these. The flatness can be improved by thinning the chip Si by Si CMP or Si dry etching, for example.

[0092] In the example shown in FIG. 4A, the upper surface of the semiconductor chip CH is exposed from the conductive film 61 and the insulating film 63, and the upper surface of the conductive film 61 has a concave shape.

[0093] Next, as shown in FIG. 4B, an insulating film 62 is formed on the semiconductor chip CH and the conductive film 61, and the insulating film 62 and the support substrate 50 are bonded together.

[0094] As shown in FIG. 4B, since the thickness of the support substrate 50 is substantially constant, undulations similar to those on the upper surface of the conductive film 61 occur on the upper surface of the support substrate 50 .

[0095] Details of the steps shown in FIGS. 4A and 4B will be described later with reference to FIGS. 8A to 8G, 8I, and 8J in the fourth embodiment.

[0096] Next, as shown in Fig. 4C, the upper surface of the support substrate 50 is ground. The process shown in Fig. 4C is similar to the process shown in Fig. 1G.

[0097] Next, as shown in Fig. 4D, the semiconductor substrate 11 of the pixel wafer W1 is thinned. The process shown in Fig. 4D is the same as the process shown in Fig. 1H.

[0098] Next, as shown in Fig. 4E, on-chip lenses L and color filters F are formed on the semiconductor substrate 11 of the pixel wafer W1. The process shown in Fig. 4E is similar to the process shown in Fig. 1I.

[0099] Thereafter, the pixel wafer W1 and the logic wafer W2 are diced into a plurality of chips, thereby forming solid-state imaging devices (semiconductor elements 101).

[0100] The member 60 that covers the semiconductor chip CH and buries the chip layer CHL has a conductive film 61 and insulating films 62 and 63 .

[0101] The conductive film 61 buries the chip layer CHL.

[0102] The insulating film 62 covers the semiconductor chip CH and the conductive film 61 .

[0103] The insulating film 63 covers the side surfaces of the semiconductor chips CH and also covers the areas of the surface of the logic wafer W2 where the semiconductor chips CH are not provided.

[0104] 4A, it is possible to reduce the variation in the film thickness of the conductive film 61. It is also possible to reduce the amount of removal of the support substrate 50 in the process shown in FIG.

[0105] In the first embodiment, the grinding process improves the global flatness. In the third embodiment, the member 60 having a substantially flat thickness not only improves the global flatness but also suppresses local irregularities between the semiconductor chips CH. Therefore, it is possible to suppress steps near the semiconductor chips CH and suppress distortion that may occur in the image sensor on the front side (pixel wafer W1 side). Note that when the semiconductor chip CH side has an image sensor structure, the Si flatness is directly linked to characteristics such as image quality unevenness.

[0106] Furthermore, if the flatness of the semiconductor chip CH is improved, the characteristics of the image sensor can be improved and a WoWoCoW structure can be achieved in FtoB bonding after rewiring.

[0107] Furthermore, in the third embodiment, the characteristics of the semiconductor element change depending on the configuration and material of the member 60. The configuration and material of the member 60 are selected, for example, to suppress stress when forming a buried film between the semiconductor chips CH and to suppress the effects of an increase in heat source and a decrease in heat dissipation area due to chip stacking. By suppressing stress, it is possible to suppress mobility fluctuations in the central wafer and deterioration of circuit characteristics caused by stress when forming the buried film. Furthermore, by improving heat dissipation, it is possible to suppress deterioration of circuit characteristics.

[0108] The conductive film 61 is made of, for example, SiO ２ In the case where the conductive film 61 is a Si film, a material that suppresses device deterioration in terms of stress, heat dissipation, and flatness is used, compared to SiON and the like. When the conductive film 61 is a Si film, it is easy to ensure the flatness of Si in local flattening processing of Si, and it is easy to perform a dry process for deep trench processing (see the fourth embodiment). Polysilicon is, for example, SiO ２ Compared to silicon, amorphous silicon has a linear thermal expansion coefficient close to that of single crystal silicon and a high thermal conductivity. SiN also has a linear thermal expansion coefficient close to that of single crystal silicon, but amorphous silicon has a good balance between thermal conductivity and processability, for example.

[0109] As in the third embodiment, the semiconductor chip CH may be covered and the chip layer CHL may be embedded with a member 60 other than the insulating film 40. In this case, the same effects as in the first embodiment can be obtained.

[0110] 5 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of the third embodiment. In the modification of the third embodiment, the structure and material of the member 60 are different from those of the third embodiment.

[0111] The member 60 further includes an insulating film 64. The insulating film 64 buries the chip layer CHL together with the conductive film 61. The insulating film 64 includes, for example, a resin.

[0112] The insulating film 64 is provided closer to the pixel wafer W1 and logic wafer W2 than the conductive film 61. That is, the conductive film 61 is provided closer to the surface layer of the semiconductor chip CH (closer to the support substrate 50) than the insulating film 64. This makes it possible to improve flatness (flat processability) and reduce stress.

[0113] As in the modified example of the third embodiment, the structure and material of the member 60 may be changed. In this case, the same effects as those of the third embodiment can be obtained.

[0114] 6 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth embodiment. The fourth embodiment differs from the third embodiment in that a trench is provided in the conductive film 61.

[0115] The conductive film 61 has trenches 611 and 612. The trenches 611 and 612 are provided between a plurality of semiconductor chips CH. The insides of the trenches 611 and 612 may be filled with, for example, an insulating film or may be air gaps.

[0116] The trenches 611 extend from the insulating film 62 side to the central wafer (logic wafer W2) side. That is, the trenches 611 penetrate the conductive film 61 in the stacking direction. The trenches 611 divide the conductive film 61, enabling insulation between the semiconductor chips CH. Note that since insulation is provided by the trenches 611, the insulating film 63 does not need to be provided.

[0117] The trench 612 extends in the stacking direction from the insulating film 62 side to the inside of the conductive film 61. In other words, the trench 612 does not penetrate the conductive film 61. A plurality of trenches 612 are provided. The trenches 612 enable stress dispersion.

[0118] 7 is a top view showing an example of the configuration of trenches 611 and 612 according to the fourth embodiment, as seen from the support substrate 50 side.

[0119] The trench 611 is provided between adjacent semiconductor chips CH when viewed from the stacking direction. The trenches 611 and 612 are provided around the semiconductor chip CH when viewed from the stacking direction.

[0120] 8A to 8J are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment. 8A to 8J show steps from singulating the semiconductor chips CH to bonding the support substrate 50 shown in FIG. 4B. The pixel wafer W1 is omitted from FIGS. 8A to 8J.

[0121] First, as shown in FIG. 8A, the semiconductor chips CH are separated into individual pieces.

[0122] Next, as shown in FIG. 8B, the semiconductor chip CH (for example, the logic chip CH1) and the logic wafer W2 are bonded together.

[0123] 8C, an insulating film 63 is formed. The insulating film 63 functions as, for example, a sidewall protective film. The insulating film 63 is formed by CVD+PR / DRY+EB. As a result, the insulating film 63 is formed on the sidewalls of the semiconductor chips CH and on the logic wafer W2.

[0124] 8D, a conductive film 61 is formed. When the conductive film 61 is made of amorphous silicon, the conductive film 61 is formed by CVD at a temperature of, for example, 300° C. to 400° C. Since the film is formed at a low temperature, it can be applied even after the BEOL process.

[0125] Next, reverse lithography is performed as shown in FIG. 8E.

[0126] 8F, reverse dry etching is performed, thereby planarizing the conductive film 61.

[0127] 8G, planarization is performed, and the semiconductor substrate 31 of the semiconductor chip CH is thinned by using a grinder, silicon CMP, or silicon dry etching.

[0128] Next, as shown in FIG. 8H, trenches 611 (slits) are formed in the conductive film 61. The trenches 611 are formed, for example, by PR+DRY. If the conductive film 61 is a Si film, deep trenches can be formed by Bosch processing. Note that the trenches 612 are omitted in the example shown in FIG. 8H.

[0129] 8I, an insulating film 62 is formed on the conductive film 61 and the semiconductor chip CH. The insulating film 62 functions as, for example, a cap film. In the example shown in FIG. 8I, the inside of the trench 611 is an air gap.

[0130] Next, as shown in FIG. 8J, the insulating film 62 and the support substrate 50 are bonded together.

[0131] As in the fourth embodiment, a trench may be provided in the conductive film 61. In this case, the same effects as in the third embodiment can be obtained.

[0132] 9 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment. The fifth embodiment differs from the third embodiment in that the semiconductor chip CH includes a plurality of semiconductor chips of different types.

[0133] As in the second embodiment, the semiconductor chip CH includes a plurality of different types of semiconductor chips. The semiconductor chip CH includes, for example, a logic chip CH1 including logic elements and a memory chip CH2 including memory elements. The memory chip CH2 according to the fifth embodiment is, for example, vertically lower than the logic chip CH1.

[0134] Depending on the height of the semiconductor chip CH, there are a mixture of semiconductor chips CH having a conductive film 61 provided on the surface thereof and semiconductor chips CH not having the conductive film 61. That is, depending on the height of the semiconductor chip CH, a part of the conductive film 61 is provided between the memory chip CH2 and the insulating film 62. The conductive film 61 is not provided between the logic chip CH1 and the insulating film 62.

[0135] As in the fifth embodiment, the semiconductor chip CH may include a plurality of semiconductor chips of different types, and in this case, the same effects as in the third embodiment can be obtained.

[0136] 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth embodiment. The sixth embodiment is a combination of the fourth and fifth embodiments.

[0137] 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a seventh embodiment. The seventh embodiment differs from the fifth embodiment in that the semiconductor chip CH includes a dummy chip.

[0138] Fig. 12 is a top view showing an example of the configuration of trenches 611, 612 according to the seventh embodiment. Fig. 12 shows a part of the logic wafer W2 or a chip obtained by dividing the logic wafer W2 from the semiconductor chip CH side.

[0139] The semiconductor chip CH includes a dummy chip CH3. The dummy chip CH3 does not have any circuit function. The dummy chip CH3 includes a Si substrate. In the example shown in FIG. 12 , the logic chip CH1 and the dummy chip CH3 have the same thickness in the vertical direction. The dummy chip CH3 is covered with an insulating film 62.

[0140] As in the seventh embodiment, the semiconductor chip CH may include a dummy chip, and in this case, the same effects as in the fifth embodiment can be obtained.

[0141] 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eighth embodiment. The eighth embodiment differs from the first embodiment in that a trench is provided in the insulating film 40.

[0142] The insulating film 40 is made of, for example, SiO ２ Or it contains SiON.

[0143] The insulating film 40 has trenches 41. The trenches 41 are provided between the plurality of semiconductor chips CH. The trenches 41 are formed by, for example, a lithography process.

[0144] The trench 41 can relieve distortion between the insulating film 40 and the semiconductor chip CH. Furthermore, the distortion is reduced, improving positional accuracy. Furthermore, the improved positional accuracy allows for further miniaturization. Furthermore, miniaturization allows for further performance improvement.

[0145] The inside of the trench 41 may be filled with a low-stress film or may be an air gap. The low-stress film may include, for example, an ALD film or amorphous carbon. The ALD film may include, for example, silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide. The low-stress film can reduce overall distortion, which can be expected to reduce misalignment and improve characteristics.

[0146] The arrangement, thickness (width), number, etc. of the trenches 41 may be changed depending on the size, area, depth (thickness), etc. of the semiconductor chip CH to optimize distortion control, i.e., to more appropriately distribute stress.

[0147] The materials of the insulating film 40 and the material inside the trench 41 are not limited to those described above. The insulating film 40 may include, for example, a photosensitive permanent film. Alternatively, the insulating film 40 may include, for example, amorphous carbon, an ALD film, or polyimide, and the inside of the trench 41 may be hollow or include a material other than the material of the insulating film 40.

[0148] As in the eighth embodiment, a trench may be provided in the insulating film 40. In this case, the same effects as in the fourth embodiment can be obtained.

[0149] 14 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of the eighth embodiment. In the modification of the eighth embodiment, the configuration of the trench 41 is different from that of the eighth embodiment.

[0150] In the example shown in FIG. 14, the width of the two trenches on the central side of the four trenches 41 is smaller than the width of the two trenches 41 on the outer side.

[0151] 15 is a top view showing an example of the configuration of the trench 41 according to a modified example of the eighth embodiment, as seen from the support substrate 50 side.

[0152] The wide trench 41 is provided around the semiconductor chip CH when viewed from the stacking direction. The narrow trench 41 is provided around the wide trench 41 when viewed from the stacking direction.

[0153] As in the modified example of the eighth embodiment, the configuration of the trench 41 may be changed. In this case, the same effects as those of the eighth embodiment can be obtained.

[0154] 16A to 16E are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a ninth embodiment. The ninth embodiment differs from the eighth embodiment in that a trench is formed after bonding of the support substrate 50.

[0155] 16A to 16E show the formation of trenches in a COW structure. Although the logic wafer W2 is omitted in FIGS. 16A to 16E, the logic wafer W2 may be provided.

[0156] 16A, a semiconductor chip CH (for example, a logic chip CH1) is COW-bonded onto a pixel wafer W1, and chip bonding distortion occurs.

[0157] 16B, burying and planarizing are performed. For burying and planarizing, for example, an insulating film 40 is used. In addition, stress is generated by the insulating film 40, and the distortion is fixed.

[0158] Next, as shown in FIG. 16C, a trench 41 is formed in the insulating film 40, and the insulating film 40 and the support substrate 50 are bonded together.

[0159] 16D, a trench TR is formed at the position of the trench 41 and connected to the trench 41.

[0160] Next, as shown in FIG. 16E, the inside of the trench TR is filled with a low stress film.

[0161] In the COW structure, the scribe marks may disappear, making it impossible to measure the strain. As a result, even if the trench 41 is formed, accurate strain relaxation may be difficult.

[0162] Therefore, by forming a trench (trench TR) again, it is possible to further adjust the relaxation of the strain depending on the influence of the strain. For example, as in the eighth embodiment, it is possible to select not to form the trench TR while remaining in the process shown in FIG. 16C , or it is possible to select not to form the low-stress film while remaining in the process shown in FIG. 16D .

[0163] As in the ninth embodiment, the trench may be formed after bonding the support substrate 50. In this case, the same effects as in the eighth embodiment can be obtained.

[0164] 17 is a top view showing an example of the configuration of a hole 42 according to a tenth embodiment. The tenth embodiment differs from the eighth embodiment in that a hole 42 is provided instead of the trench 41.

[0165] The insulating film 40 has a hole 42 .

[0166] A plurality of holes 42 are provided in a predetermined pattern. The holes 42 are arranged according to the shape, area, thickness, etc. of the semiconductor chip CH. The holes 42 include holes 421 and 422 with different diameters. The diameter of hole 422 is larger than the diameter of hole 421. The arrangement of holes 421 and 422 makes it possible to adjust the local aperture ratio. This makes it possible to locally alleviate distortion, leading to further distortion reduction.

[0167] 17, the holes 421 are provided around the sides of the semiconductor chip CH. The holes 422 are arranged around the corners of the semiconductor chip CH and along a straight line that runs from the center of the semiconductor chip CH to the corner.

[0168] Distortion tends to increase around the periphery of the semiconductor chip CH. Furthermore, distortion tends to increase locally around the corners of the semiconductor chip CH. The arrangement of the holes 422 shown in FIG. 17 allows for localized relief of distortion at the corners of the semiconductor chip CH. This reduces overall distortion.

[0169] As in the tenth embodiment, holes 42 may be provided instead of the trenches 41. In this case, the same effects as in the eighth embodiment can be obtained.

[0170] 18 is a top view showing an example of the configuration of the hole 42 according to a modification of the tenth embodiment. The modification of the tenth embodiment differs from the tenth embodiment in the shape of the hole 42.

[0171] The shape of the holes 42 is not limited to a circle, but may be an ellipse, a polygon, etc. Also, different shapes of the holes 42 may be combined.

[0172] As in the modified example of the tenth embodiment, the shape of the hole 42 may be changed. In this case, the same effects as those of the eighth embodiment can be obtained.

[0173] 19 is a top view showing an example of the configuration of the holes 42 according to the 11th embodiment. In the 12th embodiment, the arrangement of the holes 42 is different from that in the 10th embodiment.

[0174] The holes 42 may be arranged in one of the arrangements shown in (a) to (d) of Figure 19, or at least two of them may be combined.

[0175] In the example shown in FIG. 19(a), the holes 42 are arranged at equal pitches.

[0176] In the example shown in FIG. 19B, the holes 42 are arranged at a pitch offset of, for example, half a pitch.

[0177] 19C, holes 42 having different diameters are arranged. Small-diameter holes 421 are arranged around the sides of the semiconductor chip CH. Large-diameter holes 422 are arranged around the corners of the semiconductor chip CH.

[0178] 19D, the holes 42 are arranged at different pitches. Around the corners of the semiconductor chip CH, the holes 42 are arranged at a narrow pitch. Around the sides of the semiconductor chip CH, the holes 42 are arranged at a wide pitch.

[0179] As in the eleventh embodiment, the arrangement of the holes 42 may be changed. In this case, the same effects as in the tenth embodiment can be obtained.

[0180] 20 is a top view showing an example of the configuration of the trench 41 and the hole 42 according to the twelfth embodiment. The twelfth embodiment differs from the eighth and tenth embodiments in that both the trench 41 and the hole 42 are provided.

[0181] The trenches 41 and holes 42 are arranged in accordance with the shape, area, thickness, etc. of the semiconductor chip CH, thereby making it possible to locally relieve distortion, leading to further reduction in distortion.

[0182] 20 , the trench 41 includes a trench 411 on the side closer to the semiconductor chip CH and a trench 412 on the side farther from the semiconductor chip CH. The trench 411 has, for example, a quadrangular ring shape and is provided around the periphery of the semiconductor chip CH. The trench 412 is provided around a corner of the semiconductor chip CH.

[0183] In the example shown in FIG. 20, the holes 42 are provided around the corners of the semiconductor chip CH.

[0184] As in the twelfth embodiment, both the trench 41 and the hole 42 may be provided. In this case, the same effects as those of the eighth and tenth embodiments can be obtained.

[0185] The present technology may have the following configurations: (1) A semiconductor element comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and having the same size as the first semiconductor chip; a third semiconductor chip stacked on the first semiconductor chip or the second semiconductor chip and having a size different from that of the first semiconductor chip and the second semiconductor chip; and a member covering the third semiconductor chip and provided so as to embed a layer of the third semiconductor chip, wherein a surface of the member opposite to the third semiconductor chip has a shape corresponding to the third semiconductor chip. (2) The semiconductor element according to (1), wherein the member is a first insulating film. (3) The semiconductor element according to (1) or (2), wherein a surface of the member opposite to the third semiconductor chip has a convex shape that protrudes toward the opposite side from the third semiconductor chip at a position corresponding to the position of the third semiconductor chip. (4) The semiconductor element according to any one of (1) to (3), further comprising a support substrate facing the member, wherein the surface of the support substrate facing the member has a shape that is the inverse of the shape of the surface of the member opposite the third semiconductor chip. (5) The semiconductor element according to any one of (1) to (4), wherein one of the first semiconductor chip and the second semiconductor chip opposite the third semiconductor chip has a semiconductor substrate, wherein the surface of the semiconductor substrate has a shape that is different from the shape of the surface of the member opposite the third semiconductor chip. (6) The semiconductor element according to (5), wherein the surface of the semiconductor substrate has a substantially flat shape. (7) The semiconductor element according to any one of (1) to (6), comprising one third semiconductor chip. (8) The semiconductor element according to any one of (1) to (6), comprising a plurality of third semiconductor chips stacked in the same layer, wherein the plurality of third semiconductor chips have the same shape, and wherein the surface of the member opposite the third semiconductor chip has a shape that corresponds to the arrangement and shape of the third semiconductor chip.(9) The semiconductor element according to any one of (1) to (6), comprising a plurality of the third semiconductor chips stacked in the same layer, wherein the plurality of third semiconductor chips have different shapes, and the surface of the member opposite the third semiconductor chips has a shape corresponding to the arrangement and shape of the third semiconductor chips. (10) The semiconductor element according to (9), wherein the plurality of third semiconductor chips have different heights, and the surface of the member opposite the third semiconductor chips has a shape corresponding to the height of the third semiconductor chips. (11) The semiconductor element according to (1), wherein the member has: a conductive film that embeds a layer of the third semiconductor chip; and a second insulating film that covers the third semiconductor chip and the conductive film. (12) The semiconductor element according to (11), wherein the member further comprises a third insulating film that covers a side surface of the third semiconductor chip. (13) The semiconductor element according to (11) or (12), wherein the member embeds a layer of the third semiconductor chip together with the conductive film and further includes a fourth insulating film containing a resin, the fourth insulating film being provided closer to the first semiconductor chip and the second semiconductor chip than the conductive film. (14) The semiconductor element according to (11) or (12), comprising a plurality of the third semiconductor chips stacked in the same layer, the conductive film being provided between the plurality of third semiconductor chips and having a first trench penetrating the member in the stacking direction of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip. (15) The semiconductor element according to (11), (12), or (14), wherein the conductive film has a plurality of second trenches extending from the second insulating film side to the interior of the conductive film. (16) The semiconductor element according to any one of (11) to (15), comprising a plurality of the third semiconductor chips stacked on the same layer, the plurality of third semiconductor chips having different heights, and a portion of the conductive film being provided between the third semiconductor chip and the second insulating film depending on the height of the third semiconductor chip. (17) The semiconductor element according to any one of (11) to (16), comprising a plurality of the third semiconductor chips stacked on the same layer, the third semiconductor chip having at least one dummy chip, and the second insulating film covering the dummy chip.(18) A stacked structure comprising: a first wafer; a second wafer stacked on the first wafer; a fourth semiconductor chip stacked on the first wafer or the second wafer; and a member covering the fourth semiconductor chip and providing a layer of the fourth semiconductor chip embedded therein, wherein a surface of the member opposite to the fourth semiconductor chip has a shape corresponding to the fourth semiconductor chip. (19) The stacked structure according to (18), comprising a plurality of the fourth semiconductor chips stacked on the same layer, wherein the plurality of fourth semiconductor chips have the same shape, and a surface of the member opposite to the fourth semiconductor chip has a shape corresponding to the arrangement and shape of the fourth semiconductor chip. (20) The stacked structure according to (18), comprising a plurality of the fourth semiconductor chips stacked on the same layer, wherein the plurality of fourth semiconductor chips have different shapes, and a surface of the member opposite to the fourth semiconductor chip has a shape corresponding to the arrangement and shape of the fourth semiconductor chip.

[0186] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0187] 100 Stacked structure, 101 Semiconductor element, 11 Semiconductor substrate, 40 Insulating film, 50 Support substrate, 60 Member, 61 Conductive film, 611 Trench, 612 Trench, 62 Insulating film, 63 Insulating film, 64 Insulating film, CH Semiconductor chip, CHL Chip layer, CH1 Logic chip, CH2 Memory chip, CH3 Dummy chip, W1 Pixel wafer, W2 Logic wafer

Claims

1. A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and having the same size as the first semiconductor chip; a third semiconductor chip stacked on either the first semiconductor chip or the second semiconductor chip and having a size different from the sizes of the first semiconductor chip and the second semiconductor chip; and a member that covers the third semiconductor chip and is provided so as to embed a layer of the third semiconductor chip, wherein the surface of the member opposite to the third semiconductor chip has a shape corresponding to the third semiconductor chip.

2. The semiconductor element according to claim 1, wherein the member is a first insulating film.

3. The semiconductor element according to claim 1, wherein the surface of the member opposite the third semiconductor chip has a convex shape that protrudes in the opposite direction from the third semiconductor chip at a position corresponding to the position of the third semiconductor chip.

4. The semiconductor element according to claim 1, further comprising a support substrate facing said member, wherein the surface of said support substrate facing said member has a shape that is the inverse of the shape of the surface of said member opposite said third semiconductor chip.

5. The semiconductor element according to claim 1, wherein one of the first semiconductor chip and the second semiconductor chip opposite the third semiconductor chip has a semiconductor substrate, and the surface of the semiconductor substrate has a shape different from the shape of the surface of the member opposite the third semiconductor chip.

6. The semiconductor device according to claim 5, wherein the surface of the semiconductor substrate has a substantially flat shape.

7. The semiconductor device according to claim 1, comprising one said third semiconductor chip.

8. The semiconductor element according to claim 1, comprising a plurality of said third semiconductor chips stacked in the same layer, said plurality of third semiconductor chips having the same shape, and a surface of said member opposite said third semiconductor chips having a shape corresponding to the arrangement and shape of said third semiconductor chips.

9. The semiconductor device according to claim 1, comprising a plurality of said third semiconductor chips stacked in the same layer, said plurality of third semiconductor chips having different shapes, and a surface of said member opposite said third semiconductor chips having a shape corresponding to the arrangement and shape of said third semiconductor chips.

10. The semiconductor element according to claim 9, wherein the third semiconductor chips have different heights, and the surface of the member opposite the third semiconductor chips has a shape corresponding to the height of the third semiconductor chips.

11. The semiconductor element according to claim 1, wherein the member comprises: a conductive film that embeds a layer of the third semiconductor chip; and a second insulating film that covers the third semiconductor chip and the conductive film.

12. The semiconductor element according to claim 11, wherein the member further comprises a third insulating film covering a side surface of the third semiconductor chip.

13. The semiconductor element according to claim 11, wherein the member further has a fourth insulating film containing a resin, in which a layer of the third semiconductor chip is embedded together with the conductive film, and the fourth insulating film is provided closer to the first semiconductor chip and the second semiconductor chip than the conductive film.

14. The semiconductor device according to claim 11, comprising a plurality of the third semiconductor chips stacked in the same layer, the conductive film being provided between the plurality of the third semiconductor chips and having a first trench penetrating the member in the stacking direction of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip.

15. The semiconductor device according to claim 11, wherein the conductive film has a plurality of second trenches extending from the second insulating film side to the interior of the conductive film.

16. The semiconductor device according to claim 11, comprising a plurality of the third semiconductor chips stacked in the same layer, the plurality of third semiconductor chips having different heights, and a portion of the conductive film being provided between the third semiconductor chip and the second insulating film depending on the height of the third semiconductor chip.

17. The semiconductor device according to claim 11, comprising a plurality of the third semiconductor chips stacked in the same layer, the third semiconductor chips having at least one dummy chip, and the second insulating film covering the dummy chip.

18. A stacked structure comprising: a first wafer; a second wafer stacked on the first wafer; a fourth semiconductor chip stacked on the first wafer or the second wafer; and a member that covers the fourth semiconductor chip and is provided so as to embed a layer of the fourth semiconductor chip, wherein the surface of the member opposite to the fourth semiconductor chip has a shape corresponding to the fourth semiconductor chip.

19. The stacked structure according to claim 18, comprising a plurality of the fourth semiconductor chips stacked in the same layer, the plurality of fourth semiconductor chips having the same shape, and the surface of the member opposite to the fourth semiconductor chips having a shape corresponding to the arrangement and shape of the fourth semiconductor chips.

20. The stacked structure according to claim 18, comprising a plurality of the fourth semiconductor chips stacked in the same layer, the plurality of fourth semiconductor chips having different shapes, and the surface of the member opposite to the fourth semiconductor chips having a shape corresponding to the arrangement and shape of the fourth semiconductor chips.

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