Semiconductor element

Abstract

A semiconductor element according to one embodiment of the present disclosure includes a first substrate including a first semiconductor layer and a first wiring layer including at least one first conductive section, a second substrate including a second semiconductor layer and a second wiring layer including at least one second conductive section and a low dielectric section formed adjacent to at least one of the at least one first conductive section or the at least one second conductive section of the bonding structure. The first substrate is joined to the second substrate by the at least one first conductive section of the first wiring layer bonded with the at least one second conductive section of the second wiring layer forming a bonding structure and at least one of the at least one first conductive section and the at least one second conductive section includes a conductive via.

Description

SEMICONDUCTOR ELEMENT

[0001] The present technology relates to a semiconductor element, and more particularly to a semiconductor element capable of reducing parasitic capacitance between a connection conductive section and another connection conductive section.

[0002] <CROSS REFERENCE TO RELATED APPLICATIONS> This application claims the benefit of Japanese Priority Patent Application JP 2024-019604 filed on February 13, 2024, the entire contents of which are incorporated herein by reference.

[0003] There is an imaging device configured by joining a first substrate having a photoelectric conversion section, a second substrate having a readout circuit that outputs a pixel signal based on a charge output from the photoelectric conversion section, and a third substrate having a control circuit (see, for example, PTL 1). In this imaging device, a joint electrode formed on a joint surface of the first substrate with the second substrate is electrically connected to a joint electrode formed on a joint surface of the second substrate with the first substrate.

[0004] JP 2020-88380 A

[0005] However, in the imaging device described above, parasitic capacitance is generated between a connection conductive section, which is a conductive section formed on the joint surface of each of the first substrate and the second substrate such as the joint electrode or the like and connected to each other, and another connection conductive section such as another connection conductive section, wiring, or the like. As a result, crosstalk occurs due to coupling between the connection conductive sections connected to floating diffusion (FD), and conversion efficiency is reduced when a received light amount is converted into a pixel signal. Therefore, there is a demand for providing a method for reducing the parasitic capacitance between the connection conductive section and the another connection conductive section, but such a demand has not been sufficiently met.

[0006] The present technology has been made in view of such a situation and can reduce parasitic capacitance between a connection conductive section and another connection conductive section.

[0007] A semiconductor element of a first aspect of the present technology is a semiconductor element including: a first substrate that includes a first wiring layer and a first semiconductor layer; and a second substrate that includes a second wiring layer and a second semiconductor layer, in which the first substrate and the second substrate are joined such that the first wiring layer and the second wiring layer face each other, each of a plurality of first conductive sections formed on a joint surface of the first wiring layer and each of a plurality of second conductive sections formed on a joint surface of the second wiring layer are connected, and a low dielectric section is formed on at least one of the first conductive sections of the first wiring layer or between the second conductive sections of the second wiring layer.

[0008] In the first aspect of the present technology, a first substrate that includes a first wiring layer and a first semiconductor layer and a second substrate that includes a second wiring layer and a second semiconductor layer are provided, the first substrate and the second substrate are joined such that the first wiring layer and the second wiring layer face each other, each of a plurality of first conductive sections formed on a joint surface of the first wiring layer and each of a plurality of second conductive sections formed on a joint surface of the second wiring layer are connected, and a low dielectric section is formed on at least one of the first conductive sections of the first wiring layer or between the second conductive sections of the second wiring layer.

[0009] A second aspect of the present technology is a semiconductor element including: a first substrate that includes a first wiring layer and a first semiconductor layer; and a second substrate that includes a second wiring layer and a second semiconductor layer, in which the first substrate and the second substrate are joined such that the first wiring layer and the second wiring layer face each other, a first conductive section formed on a joint surface of the first wiring layer and a second conductive section formed on a joint surface of the second wiring layer are connected, and a low dielectric section is formed in the vicinity of at least one of the first conductive section or the second conductive section.

[0010] In the second aspect of the present technology, a first substrate that includes a first wiring layer and a first semiconductor layer and a second substrate that includes a second wiring layer and a second semiconductor layer are provided, the first substrate and the second substrate are joined such that the first wiring layer and the second wiring layer face each other, a first conductive section formed on a joint surface of the first wiring layer and a second conductive section formed on a joint surface of the second wiring layer are connected, and a low dielectric section is formed in the vicinity of at least one of the first conductive section or the second conductive section.

[0011] Fig. 1 is a conceptual diagram depicting an example of a laminated structure of an imaging element as a first embodiment of a semiconductor element to which the present technology is applied.Fig. 2 is a diagram depicting a circuit configuration example of a pixel region and a readout circuit.Fig. 3 is a diagram depicting a configuration example of a logic circuit.Fig. 4 is a cross-sectional view depicting a first structural example of the imaging element in Fig. 1.Fig. 5 is a top view depicting a structural example of a low dielectric section in Fig. 4.Fig. 6 is a view for describing an effect by the low dielectric section.Figs. 7A to 7D are first views for describing a method of manufacturing the low dielectric section including a low dielectric constant material.Figs. 8A to 8D are second views for describing the method of manufacturing the low dielectric section including the low dielectric constant material.Fig. 9 is a third view for describing the method of manufacturing the low dielectric section including the low dielectric constant material.Figs. 10A to 10E are first views for describing a method of manufacturing the low dielectric section including an air layer.Figs. 11A to 11E are second views for describing the method of manufacturing the low dielectric section including the air layer.Fig. 12 is a third view for describing the method of manufacturing the low dielectric section including the air layer.Fig. 13 is a view depicting an example of a width in a plane direction perpendicular to a lamination direction of the low dielectric section.Figs. 14A to 14D are top views depicting other structural examples of the low dielectric section in the first embodiment.Fig. 15 is a cross-sectional view depicting a second structural example of the imaging element in Fig. 1.Fig. 16 is a cross-sectional view depicting a third structural example of the imaging element in Fig. 1.Fig. 17 is a cross-sectional view depicting a fourth structural example of the imaging element in Fig. 1.Fig. 18 is a cross-sectional view depicting a fifth structural example of the imaging element in Fig. 1.Fig. 19 is a cross-sectional view depicting a first structural example of an imaging element as a second embodiment of a semiconductor element to which the present technology is applied.Fig. 20 is a top view depicting a structural example of a low dielectric section in Fig. 19.Figs. 21A to 21D are top views depicting other structural examples of the low dielectric section in the second embodiment.Fig. 22 is a cross-sectional view depicting a second structural example of the imaging element as the second embodiment of the semiconductor element to which the present technology is applied.Fig. 23 is a cross-sectional view depicting a structural example of an imaging element as a third embodiment of a semiconductor element to which the present technology is applied.Fig. 24 is a cross-sectional view depicting a structural example of an imaging element as a fourth embodiment of a semiconductor element to which the present technology is applied.Fig. 25 is a block diagram depicting a configuration example of an imaging device as an electronic device to which the present technology is applied.Fig. 26 is a diagram for describing a use example of the imaging element.Fig. 27 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 28 is an explanatory diagram depicting an example of an installation position of an imaging section.

[0012] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. Incidentally, the description will be made in the following order. 1. First Embodiment (an imaging element in which a low dielectric section is in contact with a conductive pad) 2. Second Embodiment (an imaging element in which a low dielectric section is not in contact with a conductive pad) 3. Third Embodiment (an imaging element in which a connection conductive section includes a conductive pad and a conductive via) 4. Fourth Embodiment (an imaging element in which a connection conductive section includes two conductive vias) 5. Application Example to Electronic Device 6. Use Example of Imaging Element 7. Application Example to Mobile Body

[0013] Incidentally, in the drawings referred to in the following description, the same or similar portions are denoted by the same or similar reference signs. Note that the drawings are schematic, and a relationship between a thickness and a plane dimension, a ratio of a thickness of each layer, and the like are different from the actual ones. In addition, the drawings may include portions having different dimensional relationships and ratios.

[0014] In addition, definitions of directions such as up and down and the like in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present disclosure. For example, when an object is observed by rotating the object by 90°, upper and lower sides are read by converting into left and right sides, and when the object is observed by rotating the object by 180°, the upper and lower sides are read by inverting.

[0015] <1. First embodiment> <Example of Laminated Structure of Imaging Element> Fig. 1 is a conceptual diagram depicting an example of a laminated structure of an imaging element as a first embodiment of a semiconductor element to which the present technology is applied.

[0016] An imaging element 10 in Fig. 1 is a complementary metal oxide semiconductor (CMOS) image sensor configured by laminating substrates 11 to 13, which are semiconductor substrates, so that the substrates 11, 12, and 13 are arranged in this order from the top.

[0017] On the substrate 11, a pixel region 11a in which pixel sections are arranged in a two-dimensional array that perform photoelectric conversion is formed. On the substrate 12, a readout circuit 12a that outputs pixel signals based on charges generated by the respective pixel sections of the substrate 11, and the like is formed. On the substrate 13, a logic circuit 13a that controls each pixel section and the readout circuit 12a and processes the pixel signals output from the readout circuit 12a, and the like is formed.

[0018] <Circuit Configuration Example of Pixel Region and Readout Circuit> Fig. 2 is a diagram depicting a circuit configuration example of the pixel region 11a and the readout circuit 12a in Fig. 1.

[0019] Incidentally, in Fig. 2, in order to simplify the drawing, only configurations of a circuit related to one shared pixel section 20 among the pixel sections arranged in the pixel region 11a and the readout circuit 12a corresponding to the shared pixel section 20 are illustrated.

[0020] The shared pixel section 20 includes a total of four pixel sections 21-1 to 21-4 arranged in pairs in each of a row direction (horizontal direction) and a column direction (vertical direction). Incidentally, the four pixel sections 21-1 to 21-4 will be collectively referred to as the pixel sections 21 hereinafter in a case where it is not necessary to particularly distinguish them.

[0021] As depicted in Fig. 2, in the pixel region 11a, the one shared pixel section 20 and one floating diffusion(FD) 22 are formed as circuits related to the one shared pixel section 20.

[0022] Each of the pixel sections 21 constituting the shared pixel section 20 includes a photodiode 41 and a transfer transistor 42. The photodiode 41 is a photoelectric conversion section that generates a charge corresponding to a received light amount of incident light to accumulate. The photodiode 41 has an anode grounded at a reference potential VSS of the substrate 11 and a cathode connected to a source of the transfer transistor 42.

[0023] A gate 42a of the transfer transistor 42 is connected to the logic circuit 13a of the substrate 13. A drain of the transfer transistor 42 is connected to the FD 22, and a source of a reset transistor 61 of the readout circuit 12a and a gate 62a of an amplification transistor 62 to be described later. When the transfer transistor 42 is turned on, the transfer transistor 42 reads out a charge generated by the photodiode 41 and transfers the charge to the FD 22.

[0024] The FD 22 is a charge holding section that holds a charge transferred from the transfer transistor 42 of each of the pixel sections 21 configuring the shared pixel section 20 in order to read out the charge as a pixel signal. The FD 22 causes a capacitance Cfd to be generated between the reference potential VSS and a wiring 51 connected to the drain of each transfer transistor 42 of the shared pixel section 20, the source of the reset transistor 61, and the gate 62a.

[0025] The readout circuit 12a includes the reset transistor 61, the amplification transistor 62, and a selection transistor 63.

[0026] A drain of the reset transistor 61 is connected to a wiring to which a power supply potential VDD is applied and a drain of the amplification transistor 62, and a gate 61a is connected to the logic circuit 13a. When the reset transistor 61 is turned on, a charge held in the FD 22 is discharged to the wiring to which the power supply potential VDD is applied to reset a potential of the FD 22.

[0027] A source of the amplification transistor 62 is connected to a drain of the selection transistor 63. A source of the selection transistor 63 is connected to the logic circuit 13a via a vertical signal line 71, and the gate 62a is connected to the logic circuit 13a. When the selection transistor 63 is turned on, the amplification transistor 62 outputs a pixel signal, which is an electric signal obtained by amplifying a potential corresponding to a charge held in the FD 22, to the vertical signal line 71 via the selection transistor 63.

[0028] Incidentally, the shared pixel section 20 sharing the FD 22 does not have to include 2 (rows) × 2 (columns) pixel sections 21 as long as it includes one or more pixel sections 21.

[0029] <Configuration Example of Logic Circuit> Fig. 3 is a diagram depicting a configuration example of the logic circuit 13a in Fig. 1.

[0030] The logic circuit 13a in Fig. 3 includes the vertical signal line 71, a pixel drive line 80, a vertical drive circuit 81, a column signal processing circuit 82, a horizontal drive circuit 83, an output terminal 84, and a system control circuit 85.

[0031] The pixel drive line 80 is formed for each row of the shared pixel section 20. The vertical drive circuit 81 is connected to each gate 42a of the shared pixel section 20 in each row, the gate 61a, and a gate 63a via the pixel drive line 80. The vertical drive circuit 81 sequentially selects each row of the shared pixel section 20. Then, the vertical drive circuit 81 sequentially supplies a transfer signal to each gate 42a connected to the pixel drive line 80 of the selected row, supplies a reset signal to the gate 61a, and supplies a selection signal to the gate 63a. With this arrangement, for each row of the shared pixel section 20, pixel signals of the four pixel sections 21 constituting the shared pixel section 20 are sequentially output to the vertical signal line 71. The vertical signal line 71 is formed for each column of the shared pixel section 20.

[0032] The column signal processing circuit 82 includes a signal processing circuit for each column of the shared pixel section 20, and each signal processing circuit is connected to the source of the selection transistor 63 via the vertical signal line 71. Each signal processing circuit of the column signal processing circuit 82 performs signal processing such as correlated double sampling, analog-to-digital (AD) conversion, and the like on a pixel signal input from the shared pixel section 20 of a row selected by the vertical drive circuit 81 via the vertical signal line 71.

[0033] The horizontal drive circuit 83 includes, for example, a shift register. The horizontal drive circuit 83 sequentially outputs horizontal scanning pulses to each signal processing circuit of the column signal processing circuit 82 to select each signal processing circuit and causes the selected signal processing circuit to output a pixel signal subjected to signal processing to the outside via the output terminal 84.

[0034] The system control circuit 85 controls driving of the vertical drive circuit 81, the column signal processing circuit 82, and the horizontal drive circuit 83.

[0035] <First Structural Example of Imaging Element> Fig. 4 is a cross-sectional view depicting a first structural example of the imaging element 10 in Fig. 1.

[0036] Incidentally, in Fig. 4, in order to simplify the drawing, only a cross section of a region around the two shared pixel sections 20 at a right end portion among the pixel sections 21 arranged in the pixel region 11a is illustrated. This applies similarly to Figs. 15 to 19 and 22 to 24 as described later.

[0037] As depicted in Fig. 4, a color filter layer 91 having color filters of predetermined colors is formed in a region corresponding to each pixel section 21 on the uppermost substrate 11 of the imaging element 10. In the example of Fig. 4, an array of the color filters of each pixel section 21 is a Bayer array, and the color filter layer 91 has the color filters of red (R), green (G), red (R), and green (G) in order from a left side of Fig. 4. On the color filter layer 91, an on-chip lens layer 92 having on-chip lenses in the region corresponding to each pixel section 21 is formed.

[0038] The substrate 11 (first substrate) includes a semiconductor layer 101 (first semiconductor layer) and a wiring layer 102 (first wiring layer) in this order from the top.

[0039] In the semiconductor layer 101, portions other than the gate 42a of the transfer transistor 42 in the pixel section 21 are formed. A trench 101a for element isolation is formed between the photodiodes 41 of the respective pixel sections 21. In the semiconductor layer 101, for each shared pixel section 20, the FD 22 is also formed on a side of the wiring layer 102 of the trench 101a at a center of the shared pixel section 20.

[0040] The wiring layer 102 is multilayered, and an interlayer film 102a including an insulating film of silicon dioxide (SiO2) or the like is formed between the respective layers. In the wiring layer 102, the gate 42a and the pixel drive line 80 connected to the gate 42a are formed. In the wiring layer 102, a through-via 102b connected to the FD 22 is also formed for each shared pixel section 20. The through-via 102b is connected to a conductive pad 102c formed on a joint surface of the wiring layer 102 with the substrate 12.

[0041] In a peripheral portion of the pixel region 11a in the wiring layer 102, a pad hole 102d is formed with a lamination direction (up-and-down direction in Fig. 4) of the substrates 11 to 13 in a depth direction. An aluminum pad 102e for electrical connection with an external device is formed on a bottom surface of the pad hole 102d. In the wiring layer 102, a through-via 102f connected to the aluminum pad 102e is also formed. The through-via 102f is connected to a conductive pad 102g formed on the joint surface of the wiring layer 102 with the substrate 12.

[0042] The substrate 12 (second substrate) includes a wiring layer 111 (second wiring layer) and a semiconductor layer 112 (second semiconductor layer) in this order from the top. The substrate 11 and the substrate 12 are joined such that the wiring layer 102 and the wiring layer 111 face each other. The wiring layer 111 is multilayered, and an interlayer film 111a including an insulating film of SiO2 or the like is formed between the respective layers.

[0043] Each conductive pad 111b is formed in a region facing each conductive pad 102c on a joint surface of the wiring layer 111, and the conductive pad 102c and the conductive pad 111b facing each other are electrically connected to form a connection conductive section 103. A low dielectric section 113 is formed around each connection conductive sections 103 so as to be in contact with both of two lamination direction surfaces 103a parallel to a lamination direction of the connection conductive section 103 and two plane direction surfaces 103b perpendicular to the lamination direction surfaces 103a.

[0044] The low dielectric section 113 has a relative dielectric constant lower than a relative dielectric constant of the interlayer film 102a of the wiring layer 102 and the interlayer film 111a of the wiring layer 111 in which the low dielectric section 113 is formed. The low dielectric section 113 desirably includes an air layer having a relative dielectric constant of 1, but may include, for example, a low dielectric constant material (Low-k material) having a relative dielectric constant (k) of equal to or smaller than 3.0. Examples of the low dielectric constant material include organic polymers and the like, such as silicon oxycarbide (SiOC), SiOCH, porous silica, SiOF, inorganic SOG, organic SOG, polyallyl ether, and the like.

[0045] In the wiring layer 111, a via 111c is also formed so as to be connected to the conductive pad 111b. The via 111c is connected to the gate 62a of the amplification transistor 62 formed on a surface of the wiring layer 111 on a side of the semiconductor layer 112 and is connected to the source of the reset transistor 61 formed in the semiconductor layer 112. The wiring 51 is configured by the through-via 102b, the connection conductive section 103, and the via 111c.

[0046] In the wiring layer 111, in addition to the gate 62a, the gate 61a of the reset transistor 61, the gate 63a of the selection transistor 63 (not illustrated), and the like are also formed.

[0047] A conductive pad 111d is formed in a region facing the conductive pad 102g on the joint surface of the wiring layer 111, and the conductive pad 102g and the conductive pad 111d are electrically connected. In the wiring layer 111, a via 111e is also formed so as to penetrate the wiring layer 111 from the conductive pad 111d. The via 111e is connected to a conductive pad 111f formed on a joint surface of the wiring layer 111 with the substrate 13.

[0048] In the semiconductor layer 112, semiconductor regions of the reset transistor 61, the amplification transistor 62, and the selection transistor 63 are formed. Shallow trench isolation (STI) 112a for element isolation is formed at a boundary of each semiconductor region.

[0049] The substrate 13 includes a wiring layer 121 and a semiconductor layer 122 in this order from the top. The substrate 12 and the substrate 13 are joined such that the semiconductor layer 112 and the wiring layer 121 face each other.

[0050] The wiring layer 121 is multilayered, and an interlayer film 121a including an insulating film of SiO2 or the like is formed between the respective layers. In the wiring layer 121, for example, a gate 121b of a PMOS transistor, a gate 121c of an NMOS transistor, and the like constituting the logic circuit 13a are formed. A conductive pad 121d is formed in a region facing the conductive pad 111f on a joint surface of the wiring layer 121, and the conductive pad 111f and the conductive pad 121d are electrically connected.

[0051] In the semiconductor layer 122, semiconductor regions of the PMOS transistor having the gate 121b and the NMOS transistor having the gate 121c are formed, and an STI 122c is formed at a boundary of each semiconductor region.

[0052] Incidentally, the conductive pads 102c (102g, 111b, 111d, 111f, 121d) are pad-like conductive sections including metal such as copper (Cu), tungsten (W), or the like. A low dielectric section may be formed around the conductive pads 102g and 111d similarly to the low dielectric section formed around the connection conductive section 103.

[0053] <Structural Example of Low Dielectric Section> Fig. 5 is a top view depicting a structural example of the low dielectric section 113 in Fig. 4.

[0054] As depicted in Fig. 5, the low dielectric section 113 covers an entire outer periphery of the connection conductive section 103.

[0055] <Description of Effect> Fig. 6 is a view for describing an effect by the low dielectric section 113 in Fig. 4.

[0056] In an imaging element 140 in Fig. 6, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10. The imaging element 140 is different from the imaging element 10 in that the low dielectric section 113 is not formed and is otherwise constituted similarly to the imaging element 10.

[0057] A size of a connection conductive section 103 is relatively large. Therefore, as depicted in Fig. 6, in a case where the low dielectric section 113 is not formed, coupling due to parasitic capacitance 141 occurs between the adjacent connection conductive sections 103. As a result, crosstalk occurs between lines of the wiring 51 connected to the FD 22 of adjacent shared pixel sections 20. In addition, a parasitic capacitance 142 is generated between a conductive pad 102c (111b) and a wiring other than a through-via 102b (via 111c) formed in a wiring layer 102 (111). With this arrangement, the capacitance at the time of converting a received light amount into a pixel signal increases, and conversion efficiency decreases.

[0058] On the other hand, in the imaging element 10, the low dielectric section 113 is formed on the outer periphery of the connection conductive section 103. With this arrangement, it is possible to suppress electrical coupling between each of the connection conductive sections 103 and another conductive section such as the connection conductive section 103 other than the connection conductive section 103, wiring other than the through-via 102b (via 111c) formed in the wiring layer 102 (111), and the like. As a result, it is possible to reduce the occurrence of crosstalk between the adjacent lines of the wiring 51, and to increase the conversion efficiency at the time of converting the received light amount into the pixel signal. As a result, image quality of an image is improved.

[0059] <First Example of Method of Manufacturing Low Dielectric Section> Figs. 7A to 9 are views for describing a method of manufacturing the low dielectric section 113 including the low dielectric constant material.

[0060] In the method of manufacturing in Figs. 7A to 9, after the low dielectric section 113 on a side of the substrate 11 and the low dielectric section 113 on a side of the substrate 12 are separately formed, the substrates 11 and 12 are joined to each other, thereby manufacturing the low dielectric section 113.

[0061] Specifically, as depicted in Fig. 7A, a first step is performed on the conductive pad 102c, a pad connection section which is a portion of the through-via 102b connected to the conductive pad 102c, and the substrate 11 on which the low dielectric section 113 is not formed yet. The first step is a step of dry etching a region 161 of the interlayer film 102a corresponding to the conductive pad 102c.

[0062] In a second step, as depicted in Fig. 7B, the low dielectric constant material is deposited in the region 161 by chemical vapor deposition (CVD) to form a low dielectric section 162, and the low dielectric section 162 is planarized by chemical mechanical polishing (CMP).

[0063] In a third step, as depicted in Fig. 7C, a photoresist is applied to a region of the low dielectric section 162 other than the region corresponding to the conductive pad 102c, a region where the photoresist is not applied is dry etched, and the photoresist is removed. With this arrangement, the low dielectric constant material of a region 163 of the low dielectric section 162 corresponding to the conductive pad 102c is removed. Next, a photoresist is applied to a region of the region 163 other than a region corresponding to the pad connection section of the through-via 102b, a region where the photoresist is not applied is dry etched, and the photoresist is removed. With this arrangement, in the low dielectric section 162 and the interlayer film 102a, the low dielectric constant material and the interlayer film 102a in a region 164 corresponding to the pad connection section of the through-via 102b are removed.

[0064] As described above, in the third step, the regions corresponding to the conductive pad 102c of the low dielectric section 162 and the pad connection section of the through-via 102b are removed, whereby an upper low dielectric section 165, which is the low dielectric section 113 on the side of the substrate 11, is formed.

[0065] In a fourth step, as depicted in Fig. 7D, for example, in a case where the pad connection section of the through-via 102b and the conductive pad 102c include copper, seed layers are formed in the regions 163 and 164. Thereafter, copper is deposited by CVD on the regions 163 and 164 where the seed layers are formed. As a result, the conductive pad 102c is formed, and the through-via 102b is completed. Then, an annealing processing is performed, and planarization by CMP is performed.

[0066] On the other hand, as depicted in Fig. 8A, a first step is performed on the conductive pad 111b, a pad connection section which is a portion of the via 111c connected to the conductive pad 111b, and the substrate 12 on which the low dielectric section 113 is not formed yet. The first step is a step of dry etching a region 181 of the interlayer film 111a corresponding to the conductive pad 111b.

[0067] In a second step, as depicted in Fig. 8B, the low dielectric constant material is deposited in the region 181 by CVD to form a low dielectric section 182, and the low dielectric section 182 is planarized by CMP.

[0068] In a third step, as depicted in Fig. 8C, a photoresist is applied to a region of the low dielectric section 182 other than the region corresponding to the conductive pad 111b, a region where the photoresist is not applied is dry etched, and the photoresist is removed. With this arrangement, the low dielectric constant material of a region 183 of the low dielectric section 182 corresponding to the conductive pad 111b is removed. Next, a photoresist is applied to a region of the region 183 other than a region corresponding to the pad connection section of the via 111c, a region where the photoresist is not applied is dry etched, and the photoresist is removed. With this arrangement, in the low dielectric section 182 and the interlayer film 111a, the low dielectric constant material and the interlayer film 111a in a region 184 corresponding to the pad connection section of the via 111c are removed.

[0069] As described above, in the third step, the regions corresponding to the conductive pad 111b of the low dielectric section 182 and the pad connection section of the via 111c are deleted, whereby a lower low dielectric section 185, which is the low dielectric section 113 on the side of the substrate 12, is formed.

[0070] In a fourth step, as depicted in Fig. 8D, for example, in a case where the pad connection section of the via 111c and the conductive pad 111b include copper, seed layers are formed in the regions 183 and 184. Thereafter, copper is deposited by CVD on the regions 183 and 184 where the seed layers are formed. As a result, the conductive pad 111b is formed, and the via 111c is completed. Then, an annealing processing is performed, and planarization by CMP is performed.

[0071] As depicted in Fig. 9, the substrate 11 in which the upper low dielectric section 165 is formed by the first step to the fourth step in Figs. 7A to 7D and the substrate 12 in which the lower low dielectric section 185 is formed by the first step to the fourth step in Figs. 8A to 8D are joined such that the wiring layer 102 and the wiring layer 111 face each other. With this arrangement, the upper low dielectric section 165 and the lower low dielectric section 185 are joined to form the low dielectric section 113 including the low dielectric constant material, and the conductive pads 102c and 111b are electrically connected to form the connection conductive section 103.

[0072] <Second Example of Method of Manufacturing Low Dielectric Section> Figs. 10A to 12 are views for describing a method of manufacturing the low dielectric section 113 including an air layer.

[0073] Incidentally, portions in Figs. 10A to 12 corresponding to those in Figs. 7A to 9 are denoted by the same reference signs.

[0074] In the method of manufacturing in Figs. 10A to 12, after the low dielectric section 113 on the side of the substrate 11 and the low dielectric section 113 on the side of the substrate 12 are separately formed, the substrates 11 and 12 are joined to each other, thereby manufacturing the low dielectric section 113.

[0075] Since a first step to a third step depicted in Figs. 10A to 10C are similar to the first step to the third step depicted in Figs. 7A to C, description thereof is omitted. Note that, in the third step depicted in Fig. 10C, only the regions corresponding to the conductive pad 102c of the low dielectric section 162 and the pad connection section of the through-via 102b are deleted, and the low dielectric section 113 on the side of the substrate 11 is not formed yet.

[0076] Since a fourth step depicted in Fig. 10D is similar to the fourth step depicted in Fig. 7D, description thereof is omitted. After the fourth step depicted in Fig. 10D, in a fifth step, as depicted in Fig. 10E, the low dielectric constant material deposited on the low dielectric section 162 is wet etched. With this arrangement, an upper low dielectric section 201, which is the low dielectric section 113 on the side of the substrate 11 including the air layer, is formed.

[0077] Since a first step to a third step depicted in Figs. 11A to 11C are similar to the first step to the third step depicted in Figs. 8A to 8C, description thereof is omitted. Note that, in the third step depicted in Fig. 11C, only the regions corresponding to the conductive pad 111b of the low dielectric section 162 and the pad connection section of the via 111c are deleted, and the low dielectric section 113 on the side of the substrate 12 is not formed yet.

[0078] Since a fourth step depicted in Fig. 11D is similar to the fourth step depicted in Fig. 8D, description thereof is omitted. After the fourth step depicted in Fig. 11D, in a fifth step, as depicted in Fig. 11E, the low dielectric constant material deposited on the low dielectric section 182 is wet etched. With this arrangement, a lower low dielectric section 202, which is the low dielectric section 113 on the side of the substrate 12 including the air layer, is formed.

[0079] As depicted in Fig. 12, the substrate 11 in which the upper low dielectric section 201 is formed by the first step to the fifth step in Figs. 10A to 10E and the substrate 12 in which the lower low dielectric section 202 is formed by the first step to the fifth step in Figs. 11A to 11E are joined such that the wiring layer 102 and the wiring layer 111 face each other. With this arrangement, the upper low dielectric section 201 and the lower low dielectric section 202 are joined to form the low dielectric section 113 including the air layer, and the conductive pads 102c and 111b are electrically connected to form the connection conductive section 103.

[0080] Incidentally, in a case where the low dielectric section 113 includes the air layer, the conductive pad 102c (111b) has to be supported by the through-via 102b (via 111c).

[0081] <Example of Width of Low Dielectric Section in Plane Direction> Fig. 13 is a view depicting an example of a width X of a low dielectric section in a plane direction perpendicular to a lamination direction of the low dielectric section 113.

[0082] In the example of Fig. 13, it is assumed that the low dielectric section 113 includes the low dielectric constant material.

[0083] As described with reference to Figs. 7A to 9, after the upper low dielectric section 165 and the lower low dielectric section 185 are separately formed, the substrates 11 and 12 are joined to each other, thereby forming the low dielectric section 113. Therefore, a joint position between the substrates 11 and 12 may be shifted in the plane direction (left-and-right direction in Fig. 13).

[0084] As depicted in Fig. 13, when a maximum value of the shift amount is ΔX, the width X of the low dielectric section 113 in the plane direction is desirably equal to or larger than the maximum value ΔX of the shift amount. More specifically, the width X is a distance between an end portion of the upper low dielectric section 165 (lower low dielectric section 185) in the plane direction and the lamination direction surface 103a in contact with the upper low dielectric section 165 (lower low dielectric section 185).

[0085] In a case where the width X is equal to or larger than the maximum value ΔX of the shift amount, the conductive pads 102c and 111b can be covered with the low dielectric section 113 even in a case where the shift occurs at the joint position between the substrates 11 and 12. Therefore, it is possible to prevent the effect of the low dielectric section 113 described with reference to Fig. 6 from being reduced due to the shift of the joint position between the substrates 11 and 12. Note that, even in a case where the width X is smaller than the maximum value ΔX of the shift amount, the effect of the low dielectric section 113 described with reference to Fig. 6 can be obtained.

[0086] Incidentally, in the example of Fig. 13, the case has been described where the low dielectric section 113 includes the low dielectric constant material, but this similarly applies to the case where the low dielectric section 113 includes the air layer.

[0087] <Another Structural Example of Low Dielectric Section> Figs. 14A to 14D are top views depicting other structural examples of the low dielectric section 113.

[0088] As depicted in Figs. 14A to 14D, the low dielectric section 113 may be formed so as to cover only a part of the outer periphery of the connection conductive section 103. That is, the low dielectric section 113 may be formed so as to be in contact with only a part of the connection conductive section 103. Specifically, the low dielectric section 113 may be formed so as to cover only four corners of the outer periphery of the connection conductive section 103 as depicted in Fig. 14A or may be formed so as to cover only other than the four corners as depicted in Fig. 14B. The low dielectric section 113 may be formed so as to cover only a horizontal direction (row direction) of the outer periphery of the connection conductive section 103 as depicted in Fig. 14C or may be formed so as to cover only a vertical direction (column direction) as depicted in Fig. 14D.

[0089] <Second Structural Example of Imaging Element> Fig. 15 is a cross-sectional view depicting a second structural example of the imaging element 10 in Fig. 1.

[0090] In the imaging element 10 in Fig. 15, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10 in Fig. 4. The imaging element 10 in Fig. 15 is different from the imaging element 10 in Fig. 4 in that a low dielectric section 221 is provided instead of the low dielectric section 113 and is otherwise constituted similarly to the imaging element 10 in Fig. 4.

[0091] The low dielectric section 221 is formed so as to be in contact with both of the two lamination direction surfaces 103a and one of the plane direction surfaces 103b only around the conductive pad 102c of the connection conductive section 103. Similarly to the low dielectric section 113, the low dielectric section 221 is formed so as to have a relative dielectric constant lower than the relative dielectric constant of the interlayer films 102a and 111a.

[0092] Incidentally, in the example of Fig. 15, the low dielectric section 221 is formed only between the conductive pads 102c of the connection conductive section 103 but may be formed only between the conductive pads 111b.

[0093] <Third Structural Example of Imaging Element> Fig. 16 is a cross-sectional view depicting a third structural example of the imaging element 10 in Fig. 1.

[0094] In the imaging element 10 in Fig. 16, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10 in Fig. 4. The imaging element 10 in Fig. 16 is different from the imaging element 10 in Fig. 4 in that a low dielectric section 241 is provided instead of the low dielectric section 113 and is otherwise constituted similarly to the imaging element 10 in Fig. 4.

[0095] The low dielectric section 241 is different from the low dielectric section 113 in that the low dielectric section 241 is formed so as to be in contact with only the two lamination direction surfaces 103a around the connection conductive section 103 and is otherwise constituted similarly to the low dielectric section 113.

[0096] <Fourth Structural Example of Imaging Element> Fig. 17 is a cross-sectional view depicting a fourth structural example of the imaging element 10 in Fig. 1.

[0097] In the imaging element 10 in Fig. 17, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10 in Fig. 4. The imaging element 10 in Fig. 17 is different from the imaging element 10 in Fig. 4 in that a low dielectric section 261 is provided instead of the low dielectric section 113 and is otherwise constituted similarly to the imaging element 10 in Fig. 4.

[0098] The low dielectric section 261 is different from the low dielectric section 113 in that the low dielectric section 261 is formed so as to be in contact with only the two plane direction surfaces 103b around the connection conductive section 103 and is otherwise constituted similarly to the low dielectric section 113.

[0099] <Fifth Structural Example of Imaging Element> Fig. 18 is a cross-sectional view depicting a fifth structural example of the imaging element 10 in Fig. 1.

[0100] In the imaging element 10 in Fig. 18, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10 in Fig. 4. The imaging element 10 in Fig. 18 is different from the imaging element 10 in Fig. 4 in that conductive sections 281 and 282 are newly provided and is otherwise constituted similarly to the imaging element 10 in Fig. 4.

[0101] The conductive section 281 is a shield conductive section formed on the joint surface of the wiring layer 102 between the adjacent conductive pads 102c of the wiring layer 102. The conductive section 282 is a shield conductive section formed on the joint surface of the wiring layer 111 between the adjacent conductive pads 111b of the wiring layer 111. The conductive sections 281 and 282 are connected to a fixed potential such as a ground potential or the like. By providing the conductive sections 281 and 282, it is possible to further suppress occurrence of coupling due to parasitic capacitance between the adjacent connection conductive sections 103.

[0102] Incidentally, in the example of Fig. 18, the imaging element 10 includes both the conductive sections 281 and 282, but may include either one. The low dielectric section 113 in Fig. 18 may be the low dielectric section 221 (241, 261).

[0103] As described above, the imaging element 10 includes the substrates 11 and 12, and the substrates 11 and 12 are joined such that the wiring layers 102 and 111 face each other. Each of the plurality of conductive pads 102c (102g) formed on the joint surface of the wiring layer 102 is connected to each of the plurality of conductive pads 111b (111d) formed on the joint surface of the wiring layer 111. The low dielectric section 113 (221, 241, 261) is formed between the conductive pads 102c (102g) and between the conductive pads 111b (111d), that is, in at least one of the vicinity of the conductive pads 102c (102g) or the vicinity of the conductive pads 111b (111d).

[0104] Therefore, it is possible to reduce parasitic capacitance between each of the connection conductive sections 103 and another conductive section such as the connection conductive section 103 other than the connection conductive section 103, wiring other than the through-via 102b (via 111c) formed in the wiring layer 102 (111), and the like. With this arrangement, it is possible to suppress the occurrence of the crosstalk between the lines of the wiring 51 connected to the FD 22 of the adjacent shared pixel sections 20 and to suppress the decrease in the conversion efficiency (voltage value per electron) at the time of converting the received light amount into the pixel signal. As a result, image quality of an image is improved.

[0105] On the other hand, in a case where the low dielectric section 113 (221, 241, 261) is not provided, the effect of reducing the parasitic capacitance is small even in an imaging element in which a dug is formed around the conductive pad 102c (102g, 111b, 111d) or a conductive section is provided.

[0106] <2. Second Embodiment> <First Structural Example of Imaging Element> Fig. 19 is a cross-sectional view depicting a first structural example of an imaging element as a second embodiment of a semiconductor element to which the present technology is applied.

[0107] In an imaging element 310 in Fig. 19, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10. The imaging element 310 is different from the imaging element 10 in Fig. 4 in that low dielectric sections 311 and 312 that are not in contact with a connection conductive section 103 are provided instead of the low dielectric section 113 and is otherwise constituted similarly to the imaging element 10 in Fig. 4.

[0108] The low dielectric section 311 is formed between adjacent conductive pads 102c (102g) on a joint surface of a wiring layer 102 so as not to be in contact with the conductive pads 102c (102g). The low dielectric section 312 is formed between adjacent conductive pads 111b (111d) on a joint surface of a wiring layer 111 so as not to be in contact with the conductive pads 111b (111d). Positions on the joint surfaces of the low dielectric sections 311 and 312 are the same, and the low dielectric sections 311 and 312 are connected to each other. Similarly to the low dielectric section 113, the low dielectric sections 311 and 312 are formed so as to have a relative dielectric constant lower than a relative dielectric constant of interlayer films 102a and 111a.

[0109] Incidentally, in the example of Fig. 19, both the low dielectric sections 311 and 312 are formed, but only either one of them may be formed.

[0110] <Structural Example of Low Dielectric Section> Fig. 20 is a top view depicting a structural example of the low dielectric section 311 in Fig. 19.

[0111] Incidentally, in Fig. 20, in order to simplify the drawing, only the low dielectric section 311 around a 2 × 2 connection conductive sections 103 is illustrated. This is similar in Figs. 21A to 21D to be described later.

[0112] As depicted in Fig. 20, the low dielectric section 311 formed between the connection conductive sections 103 adjacent in the horizontal direction extends in the vertical direction, and the low dielectric section 311 formed between the connection conductive sections 103 adjacent in the vertical direction extends in the horizontal direction. That is, the low dielectric section 311 is formed in a lattice shape. Incidentally, although not illustrated, the low dielectric section 312 is also formed in a lattice shape similarly to the low dielectric section 311.

[0113] Incidentally, the number of the low dielectric sections 311 and 312 formed between the connection conductive sections 103 adjacent to each other in the horizontal direction and the vertical direction may be plural (for example, three).

[0114] <Another Structural Example of Low Dielectric Section> Figs. 21A to 21D are top views depicting other structural examples of the low dielectric section 311.

[0115] As depicted in Figs. 21A to 21D, it is sufficient that the low dielectric section 311 is formed at least at a part between the connection conductive sections 103 adjacent to each other in at least one of the horizontal direction or the vertical direction, and a shape of the low dielectric section 311 does not have to be a lattice shape.

[0116] Specifically, as depicted in Fig. 21A, the low dielectric section 311 may be formed entirely between the connection conductive sections 103 adjacent to each other in the horizontal direction. In this case, the shape of the low dielectric section 311 is a vertical stripe shape (stripe shape). As depicted in Fig. 21B, the low dielectric section 311 may be formed entirely between the connection conductive sections 103 adjacent to each other in the vertical direction. In this case, the shape of the low dielectric section 311 is a lateral stripe shape (stripe shape).

[0117] As depicted in Fig. 21C, the low dielectric sections 311 may be formed only at four corners between the connection conductive sections 103 adjacent to each other in the horizontal direction and the vertical direction. In this case, the shape of the low dielectric section 311 is a cross shape. As depicted in Fig. 21D, the low dielectric sections 311 may be formed at predetermined intervals between the connection conductive sections 103 adjacent to each other in the horizontal direction and the vertical direction. In this case, the shape of the low dielectric section 311 is a dot shape. Incidentally, although not illustrated, a shape of the low dielectric section 312 can be similar to the shape of the low dielectric section 311.

[0118] <Second Structural Example of Imaging Element> Fig. 22 is a cross-sectional view depicting a second structural example of the imaging element as the second embodiment of the semiconductor element to which the present technology is applied.

[0119] In an imaging element 330 in Fig. 22, portions corresponding to those of the imaging element 310 in Fig. 19 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 310. The imaging element 330 is different from the imaging element 310 in that low dielectric sections 331 and 332 are provided instead of the low dielectric sections 311 and 312 and is otherwise constituted similarly to the imaging element 310.

[0120] The low dielectric sections 331 and 332 are different from the low dielectric sections 311 and 312 in that positions on joint surfaces of the low dielectric sections 331 and 332 are different, that is, the low dielectric section 331 is joined to an interlayer film 111a, and the low dielectric section 332 is joined to the interlayer film 102a. The low dielectric section 331 is different from the low dielectric section 311 in that the number of low dielectric sections 331 formed between adjacent conductive pads 102c (102g) is three. The low dielectric section 332 is different from the low dielectric section 312 in that the number of low dielectric sections 332 formed between adjacent conductive pads 111b (111d) is two. The other points are similar to those of the low dielectric sections 311 and 312.

[0121] Incidentally, in the example of Fig. 22, both the low dielectric sections 331 and 332 are formed, but only either one of them may be formed.

[0122] As described above, the imaging element 310 (330) includes substrates 11 and 12, and the substrates 11 and 12 are joined such that the wiring layer 102 and a wiring layer 111 face each other. Each of the plurality of conductive pads 102c (102g) formed on the joint surface of the wiring layer 102 is connected to each of the plurality of conductive pads 111b (111d) formed on the joint surface of the wiring layer 111. The low dielectric section 311 (331, 312, 332) is formed between the conductive pads 102c (102g) and between the conductive pads 111b (111d), that is, in at least one of the vicinity of the conductive pads 102c (102g) or the vicinity of the conductive pads 111b (111d). Therefore, as in the first embodiment, parasitic capacitance between the connection conductive section 103 and another connection conductive section can be reduced.

[0123] <3. Third Embodiment> <Structural Example of Imaging Element> Fig. 23 is a cross-sectional view depicting a structural example of an imaging element as a third embodiment of a semiconductor element to which the present technology is applied.

[0124] In an imaging element 410 in Fig. 23, portions corresponding to those of the imaging element 10 in Fig. 15 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10. The imaging element 410 is different from the imaging element 10 in Fig. 15 in that a via 411 is provided instead of the conductive pad 111b and is otherwise constituted similarly to the imaging element 10 in Fig. 15.

[0125] The via 411 (conductive via) is a conductive section formed in a region facing each conductive pad 102c on a joint surface of a wiring layer 111 so as to be connected to the conductive pad 102c. The conductive pad 102c and the via 411 facing each other are electrically connected to form a connection conductive section 412. The via 411 is connected to a via 111c. Therefore, wiring 51 is configured by a through-via 102b, the connection conductive section 412, and the via 111c.

[0126] As described above, since the imaging element 410 is configured similarly to the imaging element 10 in Fig. 15 except that the via 411 is provided instead of the conductive pad 111b, it is possible to obtain an effect similar to the effect by the imaging element 10 described above.

[0127] Incidentally, in the example of Fig. 23, a low dielectric section 221 is formed so as to be in contact with only the conductive pad 102c but may be formed in a structure other than the structure in Fig. 15 in the first embodiment or in a manner similar to that in the second embodiment.

[0128] <4. Fourth Embodiment> <Structural Example of Imaging Element> Fig. 24 is a cross-sectional view depicting a structural example of an imaging element as a fourth embodiment of a semiconductor element to which the present technology is applied.

[0129] In an imaging element 510 in Fig. 24, portions corresponding to those of the imaging element 10 in Fig. 4 are denoted by the same reference signs. Therefore, description of the portions will be appropriately omitted, and the following description will be made focusing on portions different from those of the imaging element 10. The imaging element 510 is different from the imaging element 10 in Fig. 4 in that vias 511 and 512 are provided instead of the conductive pads 102c and 111b and is otherwise constituted similarly to the imaging element 10 in Fig. 4.

[0130] The via 511 (conductive via) is a conductive section formed on a joint surface of a wiring layer 102 for each through-via 102b so as to be connected to the through-via 102b. The via 512 (conductive via) is a conductive section formed in a region facing each via 511 on a joint surface of a wiring layer 111 so as to be connected to the via 511. The vias 511 and 512 facing each other are electrically connected to form a connection conductive section 513. The via 512 is connected to a via 111c. In this manner, wiring 51 is configured by the through-via 102b, the connection conductive section 513, and the via 111c.

[0131] As described above, since the imaging element 510 is configured similarly to the imaging element 10 in Fig. 4 except that the vias 511 and 512 are provided instead of the conductive pads 102c and 111b, it is possible to obtain an effect similar to the effect by the imaging element 10 described above. The imaging element 510 is particularly suitable for fine processing because a connection region on the joint surfaces of the wiring layer 102 and the wiring layer 111 is small.

[0132] Incidentally, in the example of Fig. 24, a low dielectric section 113 is formed so as to be in contact with both of the vias 511 and 512 but may be formed in a structure other than the structure in Fig. 4 in the first embodiment or in a manner similar to that in the second embodiment.

[0133] <5. Application Example to Electronic Device> The imaging element 10 (310, 330, 410, 510) described above can be applied to various kinds of electronic devices such as, for example, an imaging device such as a digital still camera, a digital video camera, and the like, a mobile phone with an imaging function, other devices having an imaging function, or the like.

[0134] Fig. 25 is a block diagram depicting a configuration example of the imaging device as the electronic device to which the present technology is applied.

[0135] An imaging device 1001 depicted in Fig. 25 includes an optical system 1002, a shutter device 1003, a solid-state imaging device 1004, a control circuit 1005, a signal processing circuit 1006, a monitor 1007, and a memory 1008, and can image a still image and a moving image.

[0136] The optical system 1002 includes one or a plurality of lenses, guides light (incident light) from a subject to the solid-state imaging device 1004 and forms an image on a light receiving surface of the solid-state imaging device 1004.

[0137] The shutter device 1003 is disposed between the optical system 1002 and the solid-state imaging device 1004 and controls a light radiation period to the solid-state imaging device 1004 and a light-shielding period according to control of the control circuit 1005.

[0138] The solid-state imaging device 1004 includes the imaging element 10 (310, 330, 410, 510) described above. The solid-state imaging device 1004 accumulates a signal charge during a certain period according to the light forming an image on the light receiving surface via the optical system 1002 and the shutter device 1003. The signal charge accumulated in the solid-state imaging device 1004 is transferred according to a driving signal (timing signal) supplied from the control circuit 1005.

[0139] The control circuit 1005 outputs the driving signal for controlling a transfer operation of the solid-state imaging device 1004 and a shutter operation of the shutter device 1003 to drive the solid-state imaging device 1004 and the shutter device 1003.

[0140] The signal processing circuit 1006 performs various kinds of signal processing on the signal charge output from the solid-state imaging device 1004. An image (image data) obtained by signal processing performed by the signal processing circuit 1006 is supplied to the monitor 1007 to be displayed or supplied to the memory 1008 to be stored (recorded).

[0141] Also, in the imaging device 1001 configured as described above, parasitic capacitance between the connection conductive section 103 (412, 513) and another conductive section can be reduced by applying the imaging element 10 (310, 330, 410, 510) as the solid-state imaging device 1004. As a result, image quality of an imaged image can be improved.

[0142] <6. Use Example of Imaging Element> Fig. 26 is a diagram depicting a use example of using the imaging element 10 (310, 330, 410, 510) described above.

[0143] The imaging element 10 (310, 330, 410, 510) described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, X-ray, and the like, as described below, for example.

[0144] - A device for imaging to be used for viewing, such as a digital camera, a mobile device with a camera function, and the like - A device for traffic purpose such as a vehicle-mounted sensor which images front, rear, surroundings, interior and the like of an automobile, a surveillance camera for monitoring driving vehicles and roads, a ranging sensor that measures a distance between vehicles and the like, and the like for safe driving such as automatic stop and the like, recognition of a driver's state, and the like - A device for home appliance such as a television, a refrigerator, an air conditioner, and the like that images a user's gesture and performs device operation according to the gesture - A device to be used for medical and health care such as an endoscope, a device that performs angiography by receiving infrared light, and the like - A device for security use such as a surveillance camera for crime prevention, an individual authentication camera, and the like - A device to be used for beauty care, such as a skin measuring instrument for imaging skin, a microscope for imaging a scalp, and the like - A device to be used for sport, such as an action camera, a wearable camera, and the like for sports applications or the like - A device to be used for agriculture, such as a camera for monitoring a state of a field or crop, and the like

[0145] <7. Application Example to Mobile Body> The technology (the present technology) according to an embodiment of the present disclosure can be applied to various products. For example, the technology according to an embodiment of the present disclosure may be implemented as a device included in a mobile body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, or the like.

[0146] Fig. 27 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0147] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 27, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0148] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0149] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches, can be input to the body system control unit 12020. The body system control unit 12020 receives this input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like, of the vehicle.

[0150] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 instructs the imaging section 12031 to provide an image of the outside of the vehicle and receives the image from the imaging section unit 12031. Based on the received image, the outside-vehicle information detecting unit 12030 processes the received image to detect objects such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processes the received image to detect distances from the objects.

[0151] The imaging section 12031 is an optical sensor that receives light outputs an electrical signal corresponding to a received amount of light. The imaging section 12031 can output the electrical signal as an image or can output the electrical signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light or may be invisible light such as infrared rays, or the like.

[0152] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing off.

[0153] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0154] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, (e.g., operating the vehicle without input from the driver), or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like based on the information about the outside or inside of the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0155] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based the information about the outside of the vehicle, which is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0156] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 27, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0157] Fig. 28 is a diagram depicting an example of an installation position of the imaging section 12031.

[0158] In Fig. 28, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0159] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door, obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0160] Incidentally, Fig. 28 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0161] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements or maybe an imaging element having pixels for phase difference detection.

[0162] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that allows the vehicle to operate in an automated manner of the driver or the like.

[0163] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0164] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0165] An example of the vehicle control system to which the technology, according to an embodiment of the present disclosure can be applied, has been described above. The technology according to an embodiment of the present disclosure can be applied to the imaging section 12031 and the like in the configuration described above. Specifically, the imaging element 10 (310, 330, 410, 510) can be applied to the imaging section 12031. By applying the technology according to an embodiment of the present disclosure to the imaging section 12031, a more easily viewable imaged image can be obtained, by which fatigue of a driver can be reduced.

[0166] The present technology can also be applied to a semiconductor element other than the imaging element.

[0167] An embodiment of the present technology is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present technology.

[0168] For example, it is possible to adopt a mode obtained by combining all or a part of the plurality of embodiments described above.

[0169] The effects described in the present specification are merely examples and are not limited, and other effects may be provided.

[0170] The present technology can have the following configurations. (1) A semiconductor element, comprising: a first substrate including a first semiconductor layer and a first wiring layer including at least one first conductive section; a second substrate including a second semiconductor layer and a second wiring layer including at least one second conductive section, wherein the first substrate is joined to the second substrate by the at least one first conductive section of the first wiring layer bonded with the at least one second conductive section of the second wiring layer forming a bonding structure; and a low dielectric section formed adjacent to at least one of the at least one first conductive section or the at least one second conductive section of the bonding structure, wherein at least one of the at least one first conductive section and the at least one second conductive section includes a conductive via. (2) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by a horizontal surface and vertical surfaces of at least one of the at least one first conductive section and the at least one second conductive section. (3) The semiconductor element according to the above (2), wherein the low dielectric section contacts a periphery defined by the horizontal surface and the vertical surfaces of the at least one first conductive section and the at least one second conductive section. (4) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by at least one corner portion of a plurality of corner portions of the bonding section excluding horizontal and vertical midsections of the bonding section. (5) The semiconductor element according to the above (4), wherein the low dielectric section contacts a periphery defined by each corner portion of the plurality of corner portions of the bonding section excluding the horizontal and the vertical midsections of the bonding section. (6) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by at least one of an upper horizontal section and a lower horizontal section of the bonding section excluding vertical midsections of the bonding section. (7) The semiconductor element according to the above (6), wherein the low dielectric section contacts a periphery defined by each of the upper horizontal section and the lower horizontal section of the bonding section excluding the vertical midsections of the bonding section. (8) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by at least one of an upper horizontal section and a lower horizontal section of the bonding section. (9) The semiconductor element according to the above (8), wherein the low dielectric section contacts a periphery defined by each of the upper horizontal section and the lower horizontal section of the bonding section. (10) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by at least one of a first vertical side section and a second vertical side section of the bonding section excluding horizontal midsections of the bonding section. (11) The semiconductor element according to the above (10), wherein the low dielectric section contacts a periphery defined by each of the first vertical side section and the second vertical side section of the bonding section excluding the horizontal midsections of the bonding section. (12) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by at least one of a first vertical side section and a second vertical side section of the bonding section. (13) The semiconductor element according to the above (12), wherein the low dielectric section contacts a periphery defined by each of the first vertical side section and the second vertical side section of the bonding section. (14) The semiconductor element according to the above (1), wherein the low dielectric section contacts a periphery defined by at least one midsection of a plurality of midsections of the bonding section excluding corner portions of a plurality of corner portions of the bonding section. (15) The semiconductor element according to the above (14), wherein the low dielectric section contacts a periphery defined by each of the midsections of the plurality of midsections of the bonding section excluding the corner portions of the plurality of corner portions of the bonding section. (16) The semiconductor element according to the above (1), wherein the low dielectric section includes a first low dielectric section provided in the first wiring layer and a second low dielectric section provided in the second wiring layer, wherein the first low dielectric section faces and connects to the second low dielectric section forming a low dielectric structure, and wherein the low dielectric structure is provided near either end of the bonding structure. (17) The semiconductor element according to the above (1), wherein the low dielectric section includes a first low dielectric section provided in the first wiring layer and a second low dielectric section provided in the second wiring layer and wherein at least one of the first low dielectric section or the second low dielectric section is provided near either end of the bonding structure. (18) The semiconductor element according to the above (1), wherein the at least one first conductive section is offset with respect to the at least one second conductive section in a horizontal direction. (19) The semiconductor element according to the above (18), wherein the low dielectric section includes a first low dielectric section provided in the first wiring layer and a second low dielectric section provided in the second wiring layer and wherein the first low dielectric section is offset with respect to the second low dielectric section in the horizontal direction. (20) A semiconductor element, comprising: a first substrate including a first semiconductor layer and a first wiring layer including a plurality of first conductive sections; a second substrate including a second semiconductor layer and a second wiring layer including a plurality of second conductive sections, wherein the first substrate is joined to the second substrate by the plurality of first conductive sections of the first wiring layer bonded with the plurality of second conductive sections of the second wiring layer forming bonding structures, wherein the bonding structures are arranged in a two-by-two array in a plan view; and a low dielectric section formed adjacent to the two-by-two array of the bonding structures in the plan view.

[0171] 10 Imaging element 11, 12 Substrate 22 FD 41 Photodiode 62 Amplification transistor 101 Semiconductor layer 102 Wiring layer 102a Interlayer film 102c Conductive pad 103a Lamination direction surface 103b Plane direction surface 111 Wiring layer 111a Interlayer film 111b Conductive pad 112 Semiconductor layer 113, 221, 241, 261 Low dielectric section 281, 282 Conductive section 310 Imaging element 311, 312 Low dielectric section 330 Imaging element 331, 332 Low dielectric section 410 Imaging element 411 Via 510 Imaging element 511, 512 Via

Claims

1. A semiconductor element, comprising: a first substrate including a first semiconductor layer and a first wiring layer including at least one first conductive section; a second substrate including a second semiconductor layer and a second wiring layer including at least one second conductive section, wherein the first substrate is joined to the second substrate by the at least one first conductive section of the first wiring layer bonded with the at least one second conductive section of the second wiring layer forming a bonding structure; and a low dielectric section formed adjacent to at least one of the at least one first conductive section or the at least one second conductive section of the bonding structure, wherein at least one of the at least one first conductive section and the at least one second conductive section includes a conductive via.

2. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by a horizontal surface and vertical surfaces of at least one of the at least one first conductive section and the at least one second conductive section.

3. The semiconductor element according to claim 2, wherein the low dielectric section contacts a periphery defined by the horizontal surface and the vertical surfaces of the at least one first conductive section and the at least one second conductive section.

4. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by at least one corner portion of a plurality of corner portions of the bonding section excluding horizontal and vertical midsections of the bonding section.

5. The semiconductor element according to claim 4, wherein the low dielectric section contacts a periphery defined by each corner portion of the plurality of corner portions of the bonding section excluding the horizontal and the vertical midsections of the bonding section.

6. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by at least one of an upper horizontal section and a lower horizontal section of the bonding section excluding vertical midsections of the bonding section.

7. The semiconductor element according to claim 6, wherein the low dielectric section contacts a periphery defined by each of the upper horizontal section and the lower horizontal section of the bonding section excluding the vertical midsections of the bonding section.

8. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by at least one of an upper horizontal section and a lower horizontal section of the bonding section.

9. The semiconductor element according to claim 8, wherein the low dielectric section contacts a periphery defined by each of the upper horizontal section and the lower horizontal section of the bonding section.

10. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by at least one of a first vertical side section and a second vertical side section of the bonding section excluding horizontal midsections of the bonding section.

11. The semiconductor element according to claim 10, wherein the low dielectric section contacts a periphery defined by each of the first vertical side section and the second vertical side section of the bonding section excluding the horizontal midsections of the bonding section.

12. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by at least one of a first vertical side section and a second vertical side section of the bonding section.

13. The semiconductor element according to claim 12, wherein the low dielectric section contacts a periphery defined by each of the first vertical side section and the second vertical side section of the bonding section.

14. The semiconductor element according to claim 1, wherein the low dielectric section contacts a periphery defined by at least one midsection of a plurality of midsections of the bonding section excluding corner portions of a plurality of corner portions of the bonding section.

15. The semiconductor element according to claim 14, wherein the low dielectric section contacts a periphery defined by each of the midsections of the plurality of midsections of the bonding section excluding the corner portions of the plurality of corner portions of the bonding section.

16. The semiconductor element according to claim 1, wherein the low dielectric section includes a first low dielectric section provided in the first wiring layer and a second low dielectric section provided in the second wiring layer, wherein the first low dielectric section faces and connects to the second low dielectric section forming a low dielectric structure, and wherein the low dielectric structure is provided near either end of the bonding structure.

17. The semiconductor element according to claim 1, wherein the low dielectric section includes a first low dielectric section provided in the first wiring layer and a second low dielectric section provided in the second wiring layer and wherein at least one of the first low dielectric section or the second low dielectric section is provided near either end of the bonding structure.

18. The semiconductor element according to claim 1, wherein the at least one first conductive section is offset with respect to the at least one second conductive section in a horizontal direction.

19. The semiconductor element according to claim 18, wherein the low dielectric section includes a first low dielectric section provided in the first wiring layer and a second low dielectric section provided in the second wiring layer and wherein the first low dielectric section is offset with respect to the second low dielectric section in the horizontal direction.

20. A semiconductor element, comprising: a first substrate including a first semiconductor layer and a first wiring layer including a plurality of first conductive sections; a second substrate including a second semiconductor layer and a second wiring layer including a plurality of second conductive sections, wherein the first substrate is joined to the second substrate by the plurality of first conductive sections of the first wiring layer bonded with the plurality of second conductive sections of the second wiring layer forming bonding structures, wherein the bonding structures are arranged in a two-by-two array in a plan view; and a low dielectric section formed adjacent to the two-by-two array of the bonding structures in the plan view.

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