Crystal film and multilayer crystal film

Abstract

The present invention addresses the problem of providing a crystal film and a multilayer crystal film, which contribute to improvement of the electric characteristics of a semiconductor. Disclosed is a crystal film which contains a crystalline oxide and one or more group 14 elements of the periodic table as a dopant, wherein the trap density at 0.2-0.8 eV from the lower end of a conduction band of a semiconductor layer of the oxide is 1 × 1014 / cm3 or less.

Description

Crystalline and multi-layered crystalline films

[0001] The present disclosure relates to crystalline films and multi-layer crystalline films.

[0002] In Non-Patent Document 1, tin is added at 1×10 １７ / cm ３ , 5 x 10 １７ / cm ３ and 1 x 10 １９ / cm ３ Three types of c-plane α-type gallium oxide were fabricated by HVPE, each doped n-type with a carrier concentration of 1.1 × 10 １７ / cm ３ , 5 x 10 １７ / cm ３ and 4.8 × 10 １９ / cm ３ Furthermore, when the trap level densities at the energy levels Ec-0.23 eV, Ec-0.6 eV, and Ec-0.85 eV were measured by the DLTS method, they were all found to be 5×10 １４ / cm ３ It exceeded the

[0003] A. Y. Polyakov et al. , “Deep trap spectrum of Sn-doped α-Ga2O3 grown by halide vapor phase epitaxy on sapphire”, APL Mater. 7, 051102 (2019)

[0004] An object of the present disclosure is to provide a crystalline film and a multilayer crystalline film that contribute to improving the electrical properties of semiconductors.

[0005] In order to solve the above problems, a crystalline film according to one embodiment of the present disclosure includes a crystalline oxide and one or more Group 14 elements of the periodic table as a dopant, and the oxide has a trap state density of 1×10 or less at an energy level of 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer. １４ / cm ３In order to solve the above problems, a multilayer crystalline film according to one aspect of the present disclosure is a multilayer crystalline film including a first crystalline film and a second crystalline film, wherein the first crystalline film contains a crystalline oxide and one or more Group 14 elements of the periodic table as dopants, and the oxide has a trap state density of 1×10 at an energy level of 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer. １４ / cm ３ or less, and the carrier concentration of the second crystalline film is higher than the carrier concentration of the first crystalline film.

[0006] When used in a semiconductor device, the crystalline film and multilayer crystalline film of the present disclosure can reduce the trap state density at relatively shallow energy levels, which is believed to be likely to affect the electrical characteristics, and as a result, can improve the electrical characteristics of the semiconductor device.

[0007] 1 is a perspective view schematically showing an example of a crystal film 10 according to an embodiment of the present disclosure; FIG. 2 is a flowchart showing an example of a method for manufacturing the crystal film 10 according to an embodiment of the present disclosure; FIG. 3 is a perspective view schematically showing a multilayer crystal film 100 according to an embodiment of the present disclosure; FIG. 4 is a flowchart showing a method for manufacturing the multilayer crystal film 100 according to an embodiment of the present disclosure; FIG. 5 is a perspective view schematically showing an example of a substrate 20 having a groove 21 formed on a main surface according to an embodiment of the present disclosure; FIG. 6 is a cross-sectional view schematically showing an example of a substrate 20 having a buffer layer formed as an intermediate layer 25 according to an embodiment of the present disclosure; FIG. 7 is a cross-sectional view schematically showing an example of a substrate 20 having an ELO mask layer formed as an intermediate layer 26 according to an embodiment of the present disclosure; FIG. 8 is a cross-sectional view schematically showing an example of a multilayer crystal film 100 including a p-type semiconductor film 130 according to an embodiment of the present disclosure; and FIG. 9 is a cross-sectional view schematically showing an example of a substrate 200 including a second crystal film 120 after a first step according to an embodiment of the present disclosure. 1 is a cross-sectional view schematically showing an example of a multilayer crystalline film 100 in which a first crystalline film 110 is formed directly on a second crystalline film 120 after the second step, according to an embodiment of the present disclosure. 2 is a cross-sectional view schematically showing an example of a multilayer crystalline film 100 in which a second crystalline film 120, a first crystalline film 110, and a p-type semiconductor film 130 are formed after the third step, according to an embodiment of the present disclosure. 3 is a cross-sectional view schematically showing an example of a semiconductor device 400 in accordance with an embodiment of the present disclosure. 4 is a cross-sectional view schematically showing an example of a semiconductor device 500 in accordance with an embodiment of the present disclosure. 5 is a cross-sectional view schematically showing an example of a semiconductor device 550 in accordance with an embodiment of the present disclosure. 6 is a cross-sectional view schematically showing an example of a semiconductor device 600 in accordance with an embodiment of the present disclosure. 7 is a cross-sectional view schematically showing an example of a semiconductor device 700 in accordance with an embodiment of the present disclosure. 8 is a cross-sectional view schematically showing an example of a semiconductor device 720 in accordance with an embodiment of the present disclosure. 9 is a cross-sectional view schematically showing an example of a semiconductor device 730 in accordance with an embodiment of the present disclosure. 10 is a cross-sectional view schematically showing an example of a semiconductor device 750 in accordance with an embodiment of the present disclosure. 1 is a cross-sectional view schematically showing an example of a semiconductor device 800 according to one embodiment of the present disclosure; FIG. 2 is a cross-sectional view schematically showing an example of a semiconductor device 850 according to one embodiment of the present disclosure; FIG. 3 is a block diagram showing an example of a power supply system 900; FIG. 4 is a block diagram showing an example of a system device 910; and FIG. 5 is a circuit diagram showing an example of a power supply circuit 920 of a power supply device.1 is a diagram schematically illustrating an example of a film forming apparatus.

[0008]

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the invention according to the claims is not limited to these embodiments. Furthermore, not all of the combinations of configurations described in the embodiments are necessarily required to solve the problems. Furthermore, each configuration of the present disclosure is described to the extent that it does not interfere with the solution of the problems of the present disclosure. Note that the same components are designated by the same reference numerals to avoid redundant description.

[0010] Additionally, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily drawn to scale, even if not otherwise stated herein. It should also be noted that one feature of one embodiment may be used in another embodiment. Descriptions of well-known elements and processing techniques may be omitted so as not to unnecessarily obscure the embodiments of the present disclosure. The examples used herein are merely intended to aid in the understanding of the present disclosure and further enable those skilled in the art to practice the embodiments of the present disclosure. Therefore, the embodiments and examples herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable law.

[0011] Terms such as "first," "second," and the like are used to describe various elements used herein, but the elements are not limited by these terms. Terms such as "first," "second," and the like are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and a second element could be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any or all combinations of one or more of the listed items.

[0012] In this disclosure, the direction toward one side in the thickness direction of the crystal film will be described as "upper" and the direction toward the other side as "lower." Of the two main surfaces of a layer, substrate, or other component, the upper surface will be described as the upper surface, and the lower surface will be described as the lower surface. These "upper" and "lower" directions are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device. In this disclosure, a view from above is referred to as a "planar view." The terms used in this specification are intended to describe only specific embodiments and are not intended to limit this disclosure. As used in this specification, "comprises" and "includes" indicate the presence of the described elements and do not exclude the presence of one or more other elements.

[0013] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning that is consistent with the meaning in the context of the present specification and the related art. Furthermore, unless defined herein, it should be understood that terms used herein should not be interpreted in an idealized or overly formal sense. 1. Crystalline Film

[0014] 1 is a perspective view schematically illustrating an example of a crystal film 10 according to an embodiment of the present disclosure. The crystal film 10 according to an embodiment of the present disclosure includes a crystalline oxide and one or more Group 14 elements of the periodic table as dopants, and has a trap state density of 1×10 in an energy level of 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer of the crystalline oxide. １４ / cm ３ When such a crystal film 10 is used in a semiconductor device, the electrical characteristics of the semiconductor device can be improved.

[0015] The crystalline oxide contains a metal element, such as gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr), and may contain one or more elements selected from these. The crystalline oxide preferably contains at least one metal element selected from gallium, aluminum, and indium, and gallium accounts for at least 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total metal elements contained in the crystalline oxide in terms of atomic ratio. The metal element contained in the crystalline oxide may be gallium alone.

[0016] The crystalline oxide may be a single crystal or a polycrystalline oxide, and is preferably a single crystal. Examples of the crystal structure of the crystalline oxide include a corundum structure, a β-gallium structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), a cubic structure, or a tetragonal structure. The crystalline oxide preferably has a corundum structure. The crystalline oxide may also be a mixed crystal containing two or more of the metal elements.

[0017] Examples of the gallium-containing crystalline oxide having a corundum structure include those having a c-plane, m-plane, a-plane, or r-plane. The m-plane is preferred. The dopant contained in the crystal film 10 according to one embodiment of the present disclosure is not particularly limited, and examples thereof include n-type dopants such as tin (Sn), germanium (Ge), silicon (Si), titanium (Ti), zirconium (Zr), vanadium (V), and niobium (Nb), and p-type dopants such as magnesium (Mg), hydrogen (H), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), francium (Fr), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), radon (Ra), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), copper (Cu), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), mercury (Hg), titanium (Ti), lead (Pb), nickel (N), and phosphorus (P).

[0018] The dopant preferably contains at least one of germanium, tin, and silicon. In this case, the crystal film 10, which is an embodiment of the present disclosure, exhibits the function of an n-type semiconductor film. The dopant is more preferably germanium. Note that the crystal film 10, which is an embodiment of the present disclosure, may be either an n-type semiconductor layer or a p-type semiconductor layer. In this disclosure, the term "n-type semiconductor layer" collectively refers to a semiconductor layer used as an n-type semiconductor layer and a semiconductor layer used as an n+ type semiconductor layer, and the term "p-type semiconductor layer" collectively refers to a semiconductor layer used as a p-type semiconductor layer and a semiconductor layer used as a p+ type semiconductor layer.

[0019] The content of the dopant is not particularly limited, and is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic % in the composition of the crystal film 10. In addition, the concentration of the dopant in the crystal film 10 is usually 1×10 ２２ / cm ３For example, when the obtained crystal film 10 is used as an n-type semiconductor layer in a semiconductor device, it is preferable that the crystal film 10 has a resistance of 1×10 １７ / cm ３ It is preferable that the withstand voltage is 1×10 or less. １６ / cm ３ It is more preferable that the dopant concentration is not more than 1000 ppm. The dopant concentration can be appropriately determined by those skilled in the art depending on the intended use.

[0020] The crystal film 10 according to one embodiment of the present disclosure has a trap state density of 1×10 in an energy level of 0.2 to 0.8 eV from the bottom of the conduction band of the crystalline oxide semiconductor layer. １４ / cm ３ The trap level density at the energy level of 0.2 to 0.8 eV is 1×10 １４ / cm ３ If the crystal film 10 is used as a semiconductor device, the electrical characteristics cannot be improved. １３ / cm ３ Preferably, it is 5×10 or less. １３ / cm ３ It is even more preferable that:

[0021] The trap level density can be measured by the DLTS method. The DLTS method is an abbreviation for Deep Level Transient Spectroscopy, and is a method well known to those skilled in the art. The measuring device for the DLTS method is not particularly limited, and an FT-1230 (manufactured by Phys Tech) can be given as an example. The trap density measurement conditions for the DLTS method used in measuring the crystal film 10 according to one embodiment of the present disclosure can be given as follows. Specifically, the measurement conditions were as follows: (1) measurement method: correlation function method; (2) temperature range: 80 to 673 K; (3) measurement temperature interval: 2 K; (4) pulse voltage / bias voltage: 0 / -5 V; (5) pulse width: 0.1 ms; (6) period widths (TW): 19.2, 192, and 1930 ms; and (7) time constants corresponding to TW: 9.84, 91.94, and 920 ms.

[0022] From the obtained DLTS spectrum, a peak at a relatively shallow energy level of 0.2 to 0.8 eV from the bottom of the conduction band of the crystalline oxide semiconductor layer is analyzed, and the density of trap levels can be obtained. Furthermore, when the crystalline film 10 according to one embodiment of the present disclosure is used as an n-type semiconductor layer, the carrier concentration of the crystalline film 10 is set to 1×10 １７ / cm ３ Preferably, it is 5×10 or less. １６ / cm ３ It is more preferable that the carrier concentration is less than 100%. Here, when the crystal film 10 is an n-type semiconductor layer, it is well known to those skilled in the art that it is preferable to make the carrier concentration as low as possible, particularly in order to improve the withstand voltage performance. However, because trap levels capture carriers, the lower the carrier concentration, the more susceptible it is to the influence of the trap level density.

[0023] The method for measuring the carrier concentration is not particularly limited, and examples thereof include methods well known to those skilled in the art, such as a Hall effect measurement method. Furthermore, the concentration of halogen contained in the crystal film 10 according to one embodiment of the present disclosure is 1×10 １７ / cm ３ Preferably, it is 5×10 or less.１６ / cm ３ More preferably, it is 1×10 or less. １６ / cm ３ It is more preferable that the concentration is less than 0.05. The halogen remaining in the crystal film 10 tends to increase the trap density, which may degrade the electrical characteristics when the resulting crystal film 10 is used as a semiconductor device. The method for measuring the halogen concentration is not particularly limited, and examples thereof include secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy) measurement. The measurement region in the crystal film 10 where the halogen concentration is measured is not particularly limited, and for example, it is any 100 nm range at a depth of 100 nm or more from the outermost surface. The outermost surface is not included in the measurement region because, in SIMS measurement, there are a sputtering unstable region and a sputtering stable region, and the element distribution in the sputtering unstable region is likely to change depending on, for example, the primary ion species, energy, and incident angle, which makes accurate analysis difficult.

[0024] The shape of the crystal film 10 according to an embodiment of the present disclosure is not particularly limited, and examples thereof include a circular or rectangular shape in plan view. Furthermore, the thickness of the crystal film 10 according to an embodiment of the present disclosure is not particularly limited, and is, for example, 100 nm to 100 μm. As shown in FIG. 1 , the crystal film 10 is provided on a substrate 20, and can be incorporated, for example, in part or in whole, into a semiconductor device. Examples of such semiconductor devices include diodes and transistors. (Method for Manufacturing the Crystal Film 10) A method for manufacturing the crystal film 10 according to an embodiment of the present disclosure will now be described. FIG. 2 is a flowchart illustrating an example of a method for manufacturing the crystal film 10 according to an embodiment of the present disclosure. The crystal film 10 is formed, for example, on an underlying substrate 20. The method for manufacturing the crystal film 10 is not particularly limited, and the crystal film 10 can be formed directly on the substrate 20 or via an intermediate layer.

[0025] The substrate 20 can support the crystal film 10, and examples of the substrate include an insulator, a semiconductor, and a conductor. It may be either single crystal or polycrystalline. The substrate 20 may include, for example, a substrate containing a crystalline material having a corundum structure as a main component. Examples of the crystalline material having a corundum structure include sapphire, α-type gallium oxide, and an α-type mixed crystal containing gallium oxide and aluminum oxide. The α-type mixed crystal contains, for example, 0 to 60 mass% aluminum oxide. Examples of the sapphire having a corundum structure include c-plane, m-plane, a-plane, and r-plane. The substrate 20 is preferably c-plane sapphire or α-type gallium oxide. The substrate 20 may have an off-angle, for example, 0.01 degrees or greater. The thickness of the substrate 20 is preferably 10 μm to 20 mm, and more preferably 10 μm to 1000 μm.

[0026] The substrate 20 preferably has a diameter of 2 inches or more, more preferably 4 inches or more. The area of ​​the substrate 20 is approximately 15.9 cm ２ Preferably, it is about 31.9 cm or more. ２ More preferably, the above is the case. It is preferable to form grooves 21 in advance on the main surface of the substrate 20, i.e., the surface on which the intermediate layer 25 or the crystalline film 10 will be formed later. By forming the grooves 21, the film formation temperature (described later) can be increased without damaging the resulting crystalline film 10. The shape of the grooves 21 is not particularly limited, and may be, for example, multiple parallel grooves or intersecting grooves. Examples of the grooves 21 include a U-shape, a V-shape, and an arc shape. The grooves 21 can be formed, for example, by irradiating the surface of the substrate 20 with a laser, with the wavelength, processing speed, number of repetitions, etc. set to specific values. FIG. 5 is a perspective view schematically illustrating an example of a substrate 20 having grooves 21 formed on its main surface, which is one embodiment of the present disclosure. The grooves 21 can be formed, for example, by irradiating the main surface of the substrate 20 with a laser.

[0027] When forming the grooves 21, it is preferable to clean the surface of the substrate 20 on which the grooves 21 are formed. This cleaning can remove factors or inducers that may increase the trap level density in the grooves 21 and the entire surface of the substrate 20. The cleaning is performed, for example, by supplying a liquid to the surface of the substrate 20. The liquid is, for example, a cleaning liquid containing hydrofluoric acid or water. Examples of cleaning liquids containing hydrofluoric acid include hydrofluoric acid, an aqueous hydrofluoric acid solution, and buffered hydrofluoric acid. Buffered hydrofluoric acid is preferable as a cleaning liquid containing hydrofluoric acid because it is easy to handle. The cleaning method is not particularly limited, and examples include a method of spraying the liquid onto the surface of the substrate 20. In this case, for example, a cleaning device is used that includes a nozzle that sprays the liquid onto the substrate 20 and a moving device that moves the nozzle, and that can clean the entire surface of the substrate 20 by spraying the liquid from the nozzle onto the surface of the substrate 20 while moving the nozzle.

[0028] After the cleaning, the substrate 20 is preferably heated at a constant temperature for a predetermined period of time. The heating method is not particularly limited and may be, for example, a hot plate, a heater, or other methods well known to those skilled in the art. The heating temperature is not particularly limited and may be, for example, the temperature used to form the intermediate layer or crystal film 10 described below. The heating time is also not particularly limited and may be set by those skilled in the art. After the heating, the substrate 20 that has cooled after heating can be cleaned again. By cleaning again, it is possible to further remove substances that may be factors or inducers that increase the trap level density in the grooves 21 and the entire surface of the substrate 20. The cleaning method is not particularly limited and may be, for example, the same as the cleaning method described above. The liquid used for cleaning is, for example, water. The liquid is preferably sprayed onto the surface of the substrate 20. In this case, for example, a cleaning device is used that includes a nozzle that sprays the liquid onto the substrate 20 and a moving device that moves the nozzle, and that can clean the entire surface of the substrate 20 by spraying the liquid from the nozzle onto the surface of the substrate 20 while moving the nozzle.

[0029] An intermediate layer 25 is preferably formed on the substrate 20. Examples of the intermediate layer 25 include a buffer layer or a stress relaxation layer. The buffer layer preferably contains a metal oxide, and more preferably contains a metal oxide as a main component. Examples of metal oxides include metal oxides containing one or more metals selected from aluminum (Al), gallium (Ga), indium (In), iron (Fe), chromium (Cr), vanadium (V), titanium (Ti), rhodium (Rh), nickel (Ni), cobalt (Co), and iridium (Ir). The metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and / or gallium, and even more preferably contains at least gallium. Furthermore, from the viewpoint of reducing dislocations within the crystalline film, the buffer layer preferably has the same crystalline structure as the crystalline film 10, which is one embodiment of the present disclosure. Specifically, the crystalline structure of the buffer layer is preferably a corundum structure or a β-gallium structure, and more preferably a corundum structure. The stress relaxation layer may be an ELO mask layer.

[0030] 6 is a cross-sectional view schematically illustrating an example of a substrate 20 on which a buffer layer is formed as the intermediate layer 25, which is one embodiment of the present disclosure, and FIG. 7 is a cross-sectional view schematically illustrating an example of a substrate 20 on which an ELO mask layer is formed as the intermediate layer 26, which is also one embodiment of the present disclosure. The method for manufacturing the crystal film 10 is not particularly limited, and it can be formed, for example, by epitaxial crystal growth. Specifically, examples of the method include CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MOVPE (Metalorganic Vapor-phase Epitaxy), Mist CVD, Mist Epitaxy, MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), and pulse growth. The method for producing the crystal film 10 is preferably the Mist CVD, Mist Epitaxy, or HVPE method. Hereinafter, the methods for manufacturing the crystal film 10 using the mist CVD method, the mist epitaxy method, and the HVPE method will be described in order.

[0031] (Mist CVD Method, Mist Epitaxy Method) The mist CVD method or mist epitaxy method includes, for example, a step of preparing a source solution containing a metal and atomizing the source solution to generate mist or atomized droplets (atomization step), a step of transporting the resulting atomized droplets to the vicinity of the substrate 20 using a carrier gas (transport step), and a step of reacting the atomized droplets to form the crystalline film 10 (film formation step). The source solution used in the atomization step contains the metal element contained in the crystalline film 10. The source solution may also contain an inorganic material or an organic material. The metal element contained in the source solution may be a metal element contained in the crystalline film 10 in the form of a complex or salt dissolved or dispersed in a solvent. Examples of the metal element include the metal elements described in the crystalline oxide of the crystalline film 10, which is one embodiment of the present disclosure. Examples of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex. Examples of the salt form include organic metal salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, metal iodides, etc.). Examples of the solvent include inorganic solvents such as water, organic solvents such as alcohols, and mixed solvents of inorganic solvents and organic solvents. The solvent for the raw material solution preferably contains water.

[0032] The raw material solution used in the atomization step may contain additives such as hydrohalic acid or an oxidizing agent. Examples of hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of oxidizing agents include hydrogen peroxide (H ２ O ２ ), sodium peroxide (Na ２ O ２ ), barium peroxide (BaO ２ ), benzoyl peroxide (C ６ H ５ CO) ２ O ２Examples of suitable peroxides include peroxides such as HClO, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, and organic peroxides such as nitrobenzene. The raw material solution may further contain the dopant described in the section on crystal film 10, which is one embodiment of the present disclosure. In the atomization process, the raw material solution is atomized to form atomized droplets. The means for atomizing the raw material solution is not particularly limited, and examples include means using ultrasonic vibration. The atomized droplets obtained in the atomization process are airborne, and are preferably droplets that float in space with an initial velocity of zero, are not sprayed like a spray, and can be transported by a carrier gas, as described below. The major axis of the atomized droplets is preferably 50 μm or less, and more preferably 1 μm to 10 μm.

[0033] In the transport process, the atomized droplets obtained in the atomization process are transported to the substrate 20 by a carrier gas. Examples of the carrier gas include oxygen, ozone, an inert gas (e.g., nitrogen or argon), or a reducing gas (e.g., hydrogen gas or forming gas). The type of carrier gas used in the transport process may be one or more types. For example, a dilution gas with a different carrier gas concentration (e.g., a 10-fold dilution gas) may be used as a second carrier gas. The number of carrier gas supply locations may be one or more. The flow rates of the carrier gas and the dilution gas are preferably 1.0 L / min or less, and more preferably 0.1 L / min to 1.0 L / min. The timing for starting the flow of the carrier gas is not limited to a specific time, and may be before or after the film formation chamber reaches a set film formation temperature in the film formation process described below. Discharging substances that may increase trap density in the film formation chamber is believed to contribute to reducing trap level density at relatively shallow energy levels, so it is preferable for the flow to begin before the film formation temperature is reached. In the film formation process, the atomized droplets supplied in the transport process undergo a thermal reaction on the substrate 20 placed in the film formation chamber, thereby forming a crystal film 10 on the substrate 20. The conditions for the thermal reaction are not limited, and for example, the film formation process is carried out while maintaining the temperature in the film formation chamber at a predetermined temperature called the film formation temperature by heating using a hot plate or the like, as described below. That is, the film formation temperature is the temperature of the substrate 20 during the thermal reaction, and is typically a temperature above the evaporation temperature of the solvent in the raw material solution used in the atomization process, but is lower than that of conventional CVD. Specifically, 650°C or less is more preferable, and 450°C to 650°C is even more preferable. In particular, if the raw material solution used in the atomization process contains a halogen compound, a temperature below 450°C may slow down the desorption of the halogen, potentially resulting in a high halogen concentration in the resulting crystal film 10. Furthermore, if the temperature is higher than 650° C., the resulting crystal film 10 may undergo a phase transition.

[0034] The thermal reaction may be carried out under any of the following conditions: vacuum, non-oxygen atmosphere, reducing gas atmosphere, and oxygen atmosphere. The thermal reaction may also be carried out under any of atmospheric pressure, pressurized atmosphere, and reduced pressure. The thermal reaction is preferably carried out under atmospheric pressure, since this simplifies the calculation of the evaporation temperature and simplifies the equipment. The thickness of the crystal film 10 formed in the film formation process can be varied by adjusting the time required for the film formation process. These processes can be carried out sequentially or simultaneously, or can be divided into steps, temporarily suspended, and then resumed after other steps have been performed. This can be adjusted as appropriate by those skilled in the art.

[0035] An example of a film formation apparatus used in the manufacturing method of the crystal film 10 will be described below. Figure 25 is a schematic diagram showing an example of a film formation apparatus. The film formation apparatus 30 includes a carrier gas source 32a for supplying a carrier gas, a flow rate control valve 33a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 32a, a carrier gas source 32b for supplying a carrier gas (diluted), i.e., a diluted carrier gas, a flow rate control valve 33b for adjusting the flow rate of the carrier gas (diluted) delivered from the carrier gas source 32b, an atomized droplet generating source 34 containing a raw material solution 34a, a container 35 containing water 35a, an ultrasonic vibrator 36 attached to the bottom of the container 35, a film formation chamber 37, a supply pipe 38 connecting the atomized droplet generating source 34 and the film formation chamber 37, and a hot plate (heater) 39 installed in the film formation chamber 37. The film formation chamber 37 is provided with an exhaust port 37a for discharging the atomized droplets and exhaust gas after the reaction.

[0036] The substrate 20 is placed on the hot plate 39. The raw material solution 34a is contained in the atomized droplet generating source 34. In this state, the hot plate 39 is activated, and the temperature inside the film formation chamber 37 is increased by the hot plate 39. At the same time, the flow control valves 33a and 33b are opened to supply the carrier gas and the carrier gas (diluted) from the carrier gas sources 32a and 32b into the film formation chamber 37. After the atmosphere in the film formation chamber 37 is sufficiently replaced with the carrier gas, the flow rates of the carrier gas and the carrier gas (diluted) are adjusted, respectively. Next, the ultrasonic vibrator 36 begins to vibrate. The vibration of the ultrasonic vibrator 36 propagates to the raw material solution 34a through the water 35a. This causes the raw material solution 34a to atomize, generating atomized droplets 34b. The atomized droplets 34b are introduced into the film formation chamber 37 by the carrier gas and the carrier gas (diluted), and then transported to the vicinity of the substrate 20. Then, the atomized droplets 34 b undergo a thermal reaction in the film-forming chamber 37 under atmospheric pressure, and the crystal film 10 is formed on the substrate 20 .

[0037] FIG. 26 is a schematic diagram showing another example of a film formation apparatus. Similar to the film formation apparatus 30, the film formation apparatus 40 includes a carrier gas source 32a, a flow rate control valve 33a, a carrier gas source 32b, a flow rate control valve 33b, an atomized droplet generating source 34, a container 35, and an ultrasonic vibrator 36. Additionally, the film formation apparatus 40 includes a supply pipe 42 to which atomized droplets are supplied from the atomized droplet generating source 34, a susceptor 41 provided within the supply pipe 42, and a heater 43 installed around the supply pipe 42. The supply pipe 42 essentially forms a film formation chamber. The supply pipe 42 is provided with an exhaust port 42a for discharging atomized droplets and exhaust gas after reaction. The susceptor 41 has a mounting surface on which the substrate 20 is placed. The mounting surface is inclined relative to the horizontal plane. The film formation apparatus 40 can be used in the same manner as the film formation apparatus 30 described above. The crystal film 10 may be produced by performing the atomization step, the transport step, and the film formation step once, or may be produced by performing the atomization step, the transport step, and the film formation step repeatedly a plurality of times.

[0038] (HVPE Method) The HVPE method includes a step of reacting a metal source with a halogenating agent to generate a metal-containing source gas (gasification step), and a step of supplying the metal-containing source gas and the oxygen-containing source gas to a substrate 20 placed in a reaction chamber and epitaxially growing a crystal to form a crystal film 10 on the substrate 20 (film formation step). The metal source used in the gasification step includes a metal element contained in the crystal film 10. Examples of the metal source include an elemental metal of the metal element contained in the crystal film 10 and a metal compound containing the metal element. The form of the metal source is not particularly limited and may be any of a gas, liquid, and solid, but is preferably a liquid.

[0039] The halogenating agent is capable of halogenating the metal source, and examples thereof include halogens and hydrogen halides. Examples of the halogen include fluorine (F), chlorine (Cl), bromine (Br), and iodine (I). Examples of the hydrogen halides include hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For halogenation, hydrogen halides are preferably used, and hydrogen chloride is more preferably used. In the gasification step, the metal source is reacted with the halogenating agent to generate a metal-containing source gas. The reaction method is not particularly limited, and examples include contacting the metal source with the halogenating agent at a gasification reaction temperature equal to or higher than the vaporization temperature of the metal halide to be generated. The gasification reaction temperature is not particularly limited and can be appropriately set by those skilled in the art depending on the type of metal source and the type of halogenating agent.

[0040] Examples of the metal-containing source gas obtained by the gasification process include metal fluorides, chlorides, bromides, and iodides. Here, when the metal source is gallium and the halogenating agent is hydrogen chloride, the metal-containing source gas generated is gallium chloride gas, and from the viewpoint of the vaporization temperature of gallium chloride, the gasification reaction temperature is preferably 900°C or less, more preferably 700°C or less, and more preferably 400°C or more and 700°C or less. Gallium chloride is generated by the gasification process, and a metal-containing source gas containing gallium can be generated. In the film formation process, the metal-containing source gas and oxygen-containing source gas obtained by the gasification process are supplied to a substrate 20 placed in a reaction chamber, and a crystal is epitaxially grown to form a crystal film 10 on the substrate 20. The oxygen-containing source gas is, for example, oxygen (O ２ ) gas, carbon dioxide (CO ２ ) gas, nitric oxide (NO) gas, nitrogen dioxide (NO ２ ) gas, nitrous oxide (N ２ O) gas, water vapor (H ２ O) or ozone (O ３ The oxygen-containing source gas is preferably one or more gases selected from the group consisting of oxygen, water vapor, nitric oxide, and nitrous oxide, and more preferably contains oxygen gas. Furthermore, the oxygen-containing source gas preferably further contains nitrogen dioxide.

[0041] In the film formation process, a reactive gas can be used in addition to the metal-containing source gas and oxygen-containing source gas. The reactive gas is a gas with a different reactivity from the metal-containing source gas and oxygen-containing source gas, and does not include an inert gas. Examples of the reactive gas include an etching gas. Specific examples of the reactive gas include the halogen gas and hydrogen halide gas described as halogenating agents in the gasification process, as well as hydrogen gas or a mixed gas containing two or more of these. Hydrogen halide gas is preferred, and hydrogen chloride is even more preferred. The partial pressure of the metal-containing source gas in the film formation process is preferably 0.5 Pa to 1 kPa, more preferably 5 Pa to 0.5 kPa. The partial pressure of the oxygen-containing source gas is preferably 0.5 to 100 times, more preferably 1 to 20 times, the partial pressure of the metal-containing source gas. The partial pressure of the reactive gas is also preferably 0.1 to 5 times, more preferably 0.2 to 3 times, the partial pressure of the metal-containing source gas.

[0042] The film formation process may further include a carrier gas. Examples of the carrier gas include inert gases such as nitrogen and argon. In addition to the metal-containing source gas, oxygen-containing source gas, and optionally the reactive gas and carrier gas, a dopant-containing gas may be used in the film formation process. The dopant-containing gas may include a gas containing the dopant contained in the crystal film 10. The dopant-containing gas is not particularly limited, and may include a gas containing the dopant in the form of a halide or oxide. The partial pressure of the dopant-containing source gas in the film formation process is 1×10 of the partial pressure of the metal-containing source gas. －７ Times to 1 x 10 －１ Preferably, it is 2.5×10 －６ Times ~ 7.5 x 10 －２ It is more preferable that it is twice as large.

[0043] In the film formation process, a crystalline film 10 is formed on a substrate 20 placed in a film formation chamber by thermal reaction of the metal-containing source gas, oxygen-containing source gas, and optionally the reactive gas and dopant-containing gas generated in the gasification process, supplied by convection or, if necessary, the carrier gas. The thermal reaction is not particularly limited, and, similar to the mist CVD and mist epitaxy methods described above, is carried out by heating using a hot plate or the like, while maintaining the temperature in the film formation chamber at a predetermined temperature known as the film formation temperature. The film formation temperature is not particularly limited, and is preferably 650°C or less, with 450°C to 650°C being even more preferred. In particular, if the metal-containing source gas, reactive gas, and dopant-containing gas contain halogen compounds, temperatures below 450°C may slow the desorption of halogen, potentially resulting in a high halogen concentration in the resulting crystalline film 10. Furthermore, temperatures above 650°C may result in a phase transition in the resulting crystalline film 10.

[0044] Specific examples of the thickness of the crystalline film 10 formed in the thermal reaction and film-forming processes include those described above in the mist CVD and mist epitaxy processes. The crystalline film 10 may be produced by performing the gasification and film-forming processes once or multiple times. The crystalline film 10 according to one aspect of the present disclosure may further include a p-type semiconductor film. The p-type semiconductor film may contain a crystalline oxide and a dopant capable of forming a p-type semiconductor. Examples of the crystalline oxide and p-type semiconductor film include those described above. The carrier concentration of the p-type semiconductor film is not particularly limited, and the concentration of the p-type dopant can be appropriately adjusted so that the p-type semiconductor film exhibits p-type properties. Furthermore, the p-type semiconductor film may contain, rather than a dopant, an element constituting the crystalline oxide that can exhibit p-type semiconductor function. A specific example of such an element is iridium. The method for forming the p-type semiconductor film is not particularly limited, but is preferably the mist CVD method, mist epitaxy method, or HVPE method described above.

[0045] 3 is a perspective view schematically illustrating a multilayer crystalline film 100 according to one embodiment of the present disclosure. The multilayer crystalline film 100 according to one embodiment of the present disclosure includes a first crystalline film 110 and a second crystalline film 120, wherein the first crystalline film 110 contains a crystalline oxide and one or more Group 14 elements of the periodic table as dopants, and the trap state density in the energy level 0.2 to 0.8 eV from the bottom of the conduction band of the semiconductor layer of the crystalline oxide is 1×10 １４ / cm ３ or less, and the carrier concentration of the second crystalline film 120 is higher than the carrier concentration of the first crystalline film 110. When such a multilayer crystalline film 100 is used in a semiconductor device, the electrical characteristics of the semiconductor device can be improved. The first crystalline film 110 contains a crystalline oxide and a dopant. Specific examples of the crystalline oxide and dopant include the crystalline oxide and dopant described above in the section on the crystalline film 10, which is an embodiment of the present disclosure. Furthermore, examples of the trap level density at the energy level of 0.2 to 0.8 eV include those described above in the section on the crystalline film 10, which is an embodiment of the present disclosure. Furthermore, the halogen concentration of the first crystalline film 110 is 5×10 １６ / cm ３ Preferably, it is 1×10 or less. １６ / cm ３ It is more preferable that the concentration of halogen is less than 100%. The halogen remaining in the first crystalline film 110 tends to increase the trap density, which may deteriorate the electrical characteristics when the obtained first crystalline film 110 is used as a semiconductor device. The method for measuring the concentration of halogen is not particularly limited, and the SIMS measurement described above for the crystalline film 10 can be used.

[0046] In the multilayer crystalline film 100 according to one aspect of the present disclosure, the carrier concentration of the second crystalline film 120 is higher than the carrier concentration of the first crystalline film 110. Specifically, the carrier concentration of the first crystalline film 110 is 1×10 １７ / cm ３ Preferably, it is 5×10 or less. １６ / cm ３On the other hand, the carrier concentration of the second crystalline film 120 is preferably 1 to 10 １７ / cm ３ It is preferable that the ratio is 1×10 or more. １８ / cm ３ It is more preferable that the carrier concentration of the second crystal film 120 is higher than the carrier concentration of the first crystal film 110. The carrier concentration can be adjusted by adjusting the content of the dopant concentration. In short, the multilayer crystal film 100 according to one aspect of the present disclosure includes the second crystal film 120 as an n+ semiconductor layer and the first crystal film 110 as an n- semiconductor layer, and preferably includes the first crystal film 110 directly on the second crystal film 120.

[0047] From the viewpoint of electrical characteristics when the multilayer crystalline film 100 according to an embodiment of the present disclosure is used as a semiconductor device, the second crystalline film 120 may contain, for example, a crystalline oxide and a dopant, similar to the first crystalline film 110. In particular, when the first crystalline film 110 is provided directly on the second crystalline film 120, from the viewpoint of crystal alignment and the final electrical characteristics, the second crystalline film 120 preferably has a lattice structure and interatomic distances similar to or similar to those of the first crystalline film 110. Therefore, the crystalline oxide and dopant contained in the second crystalline film 120 are similar to the crystalline oxide and dopant in the first crystalline film 110, and specifically, may be those described above for the crystalline film 10 according to an embodiment of the present disclosure. The multilayer crystalline film 100 according to an embodiment of the present disclosure may include other films in addition to the first crystalline film 110 and the second crystalline film 120, and may be composed of three or more layers.

[0048] FIG. 8 is a cross-sectional view schematically illustrating an example of a multilayer crystalline film 100 including a p-type semiconductor film 130 as the other film. The p-type semiconductor film 130 may contain a crystalline oxide and a dopant capable of forming a p-type semiconductor. Examples of the crystalline oxide include those described in the section on the crystalline film 10, which is an embodiment of the present disclosure. Examples of the dopant capable of forming a p-type semiconductor include the p-type dopants described in the section on the crystalline film 10, which is an embodiment of the present disclosure. The carrier concentration of the p-type semiconductor film 130 is not particularly limited, and the concentration of the p-type dopant can be appropriately adjusted so that the p-type semiconductor film 130 exhibits p-type properties. Furthermore, the p-type semiconductor film 130 may contain, rather than a dopant, an element constituting the crystalline oxide that can impart p-type semiconductor functionality. A specific example of such an element is iridium.

[0049] The thickness of the p-type semiconductor film 130 is not particularly limited and is, for example, 10 nm to 10 μm. The multilayer crystalline film 100 according to one embodiment of the present disclosure may include another crystalline film in addition to the second crystalline film 120, the first crystalline film 110, and, if necessary, the p-type semiconductor film 130. The other crystalline film is not particularly limited and may again include, for example, an n-type semiconductor film or a p-type semiconductor film. Examples of the n-type semiconductor film and the p-type semiconductor film include the first crystalline film, the second crystalline film, and a p-type semiconductor film. The shape of the multilayer crystalline film 100 according to one embodiment of the present disclosure is not particularly limited and may, for example, be a circle or a square in plan view. The total thickness of the multilayer crystalline film 100 according to one embodiment of the present disclosure is also not particularly limited and is, for example, 100 nm to 100 μm.

[0050] The multilayer crystalline film 100 according to one embodiment of the present disclosure can be incorporated, in part or in whole, into a semiconductor device, similar to the crystalline film 10 described above. Such a semiconductor device may be, for example, a diode or a transistor. (Method for Manufacturing the Multilayer Crystal Film 100) A method for manufacturing the multilayer crystalline film 100 according to one embodiment of the present disclosure will now be described. FIG. 4 is a flowchart illustrating an example of a method for manufacturing the multilayer crystalline film 100. The multilayer crystalline film 100 is formed, for example, on an underlying substrate 200. The method for manufacturing the substrate 200 is not particularly limited, and may involve forming a second crystalline film 120 on the substrate 200 directly or via an intermediate layer, followed by forming the first crystalline film 110. The substrate 200 can support the multilayer crystalline film 100, and specifically includes the substrate 20 described in the method for manufacturing the crystalline film 10 according to one embodiment of the present disclosure. The method for manufacturing the multilayer crystalline film 10 according to one embodiment of the present disclosure is not particularly limited, and specifically includes the method described in the method for manufacturing the crystalline film 10 according to one embodiment of the present disclosure. The multilayer crystal film 100 is preferably manufactured by mist CVD, mist epitaxy, or HVPE.

[0051] The mist CVD method, mist epitaxy method, and HVPE method are not particularly limited, and specifically include those described in the above-mentioned method for producing the crystalline film 10, which is one embodiment of the present disclosure. For example, the mist CVD method and mist epitaxy method include the same atomization process, transport process, and film formation process as the above-mentioned method for producing the crystalline film 10, which is one embodiment of the present disclosure, while the HVPE method includes the same gasification process and film formation process. When using the mist CVD method or mist epitaxy method, the method for producing the multilayer crystalline film 10, which is one embodiment of the present disclosure, includes, as a first step, forming a second crystalline film 120 on the substrate 200 through the atomization process, transport process, and film formation process described in the above-mentioned method for producing the crystalline film 10, which is one embodiment of the present disclosure. Figure 9 is a cross-sectional view schematically showing an example of a substrate 200 with a second crystalline film 120 after the first step. Next, in the second step, the first crystal film 110 is formed on the substrate 200 provided with the obtained second crystal film 120 through the atomization step, the transport step, and the film formation step.

[0052] In the second step, the first crystalline film 110 may be formed directly on the second crystalline film 120 formed on the substrate 200, or another film may be formed directly on the second crystalline film 120 by performing a different film formation method between the first and second steps, and then the first crystalline film 110 may be formed directly on the other film in the second step. Figure 10 is a cross-sectional view schematically showing an example of a multilayer crystalline film 100 after the second step, in which the first crystalline film 110 is formed directly on the second crystalline film 120. Here, the raw material solution used in the atomization process in each of the above steps contains a predetermined amount of a metal element and a dopant based on a crystalline oxide as described above in connection with the multilayer crystalline film 100, which is one aspect of the present disclosure.

[0053] The transport steps in the first and second steps may be the same as those described in the method for producing the crystal film 10, which is one aspect of the present disclosure. In the film formation step of step 2, if the raw material solution used in the atomization step contains a halogen compound, the concentration of halogen contained in the resulting first crystal film 110 is 5×10, similar to the crystal film 10 described above. １６ / cm ３ Preferably, it is 1×10 or less. １６ / cm ３ The halogen remaining in the first crystalline film 110 tends to increase the trap density, which may deteriorate the electrical characteristics when the resulting multilayer crystalline film 100 is used as a semiconductor device.

[0054] The method for manufacturing the multilayer crystalline film 100 may include, in addition to the first and second steps, a third step of forming the p-type semiconductor film 130. The method for forming the p-type semiconductor film 130 in the third step is not particularly limited, and is preferably a mist CVD method, a mist epitaxy method, or an HVPE method. Specific examples of the mist CVD method, the mist epitaxy method, or the HVPE method include the method for manufacturing the crystalline film 10, which is one aspect of the present disclosure.

[0055] FIG. 11 is a cross-sectional view schematically illustrating an example of a multilayer crystalline film 100 having a second crystalline film 120, a first crystalline film 110, and a p-type semiconductor film 130 formed thereon after the above three steps. The source solution used in the atomization step of the third step contains metal elements and dopants based on the crystalline oxide described above in connection with the crystalline film 10, which is one embodiment of the present disclosure, so as to exhibit the function of a p-type semiconductor. An additional film may be formed between the first crystalline film 110 and the p-type semiconductor film 130 or on the p-type semiconductor film 130. The method for forming such a film is not particularly limited, and examples thereof include the mist CVD method, mist epitaxy method, and HVPE method, which are described in connection with the crystalline film 10, which is one embodiment of the present disclosure.

[0056] The crystalline film 10 and the multilayer crystalline film 100 are useful for semiconductor devices, particularly power devices. Semiconductor devices including the crystalline film 10 and the multilayer crystalline film 100 include, for example, vertical devices and horizontal devices. A horizontal device is a semiconductor device in which electrodes are arranged on only one side of the crystalline film 10 and the multilayer crystalline film 100 in the thickness direction. A vertical device is a semiconductor device in which electrodes are arranged on both sides of the crystalline film 10 and the multilayer crystalline film 100 in the thickness direction. Examples of semiconductor devices formed using the crystalline film 10 and the multilayer crystalline film 100 include transistors and TFTs such as MESFETs (metal semiconductor field effect transistors), MOSFETs (metal oxide semiconductor field effect transistors), metal insulator semiconductor field effect transistors (MISFETs), IGBTs (insulated gate bipolar transistors), HEMTs (high electron mobility transistors), JFETs (junction field effect transistors), and SITs (static induction transistors), as well as SBDs (Schottky barrier diodes) and JBSs (junction barrier Schottky diodes) that utilize semiconductor-metal junctions, PN or PIN diodes combined with other p-layers, LEDs (light emitting diodes), and light emitting / receiving elements. The crystalline film 10 and the multilayer crystalline film 100 can be used as semiconductor layers in semiconductor devices after being peeled off from the substrate 20 or 200, for example. The crystalline film 10 and the multilayer crystalline film 100 can also be used by being disposed on another substrate having a higher thermal conductivity than the substrate 20 or 200, for example.

[0057] Below, preferred examples of semiconductor devices incorporating the crystalline film 10 and the multilayer crystalline film 100 as semiconductor layers will be described. In the semiconductor devices described below, the crystalline film 10 and the multilayer crystalline film 100 may be incorporated into the semiconductor device as an n-type semiconductor layer, a p-type semiconductor layer, or a composite film of an n-type semiconductor and a p-type semiconductor. When a semiconductor device includes multiple semiconductor layers, all or part of the multiple semiconductor layers may be the crystalline film 10 and the multilayer crystalline film 100. When a semiconductor device includes an n-type semiconductor layer and a p-type semiconductor layer, each of the n-type semiconductor layer and the p-type semiconductor layer may be the crystalline film 10 or the multilayer crystalline film 100, or only the n-type semiconductor layer or only the p-type semiconductor layer may be the crystalline film 10 or the multilayer crystalline film 100. When the semiconductor layer of a semiconductor device is formed from multiple layers, the entire semiconductor layer may be the crystalline film 10 or the multilayer crystalline film 100, or only part of the semiconductor layer may be the crystalline film 10 or the multilayer crystalline film 100.

[0058] FIG. 12 is a cross-sectional view schematically illustrating an example of a semiconductor device 400. The semiconductor device 400 is an SBD (Schottky barrier diode). The semiconductor device 400 includes a semiconductor layer 401, a first electrode 404, and a second electrode 405. The semiconductor layer 401 includes an n+ type semiconductor layer 402 and an n- type semiconductor layer 403. The n+ type semiconductor layer 402 and the n- type semiconductor layer 403 are aligned in the thickness direction of the semiconductor layer 401. The surface of the n- type semiconductor layer 403 opposite to the n+ type semiconductor layer 402 forms a first surface 401a, which is one surface of the semiconductor layer 401 in the thickness direction. The surface of the n+ type semiconductor layer 402 opposite to the n- type semiconductor layer 403 forms a second surface 401b, which is the surface of the semiconductor layer 401 opposite to the first surface 401a. The first electrode 404 is disposed on the first surface 401a. The first electrode 404 is a Schottky electrode. The second electrode 405 is disposed on the second surface 401b. The second electrode 405 is an ohmic electrode.

[0059] The materials for the first electrode 404 and the second electrode 405 may be known electrode materials. Examples of electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; or mixtures and laminates thereof. The methods for forming the first electrode 404 and the second electrode 405 are not particularly limited. The method for forming the first electrode 404 and the second electrode 405 can be appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration their compatibility with the above-mentioned materials. The first electrode 404 and the second electrode 405 may each be formed using two types of metal, a first metal and a second metal. In this case, the first electrode 404 or the second electrode 405 may be formed by stacking a layer made of the first metal and a layer made of the second metal and patterning the layer made of the first metal and the layer made of the second metal using a photolithography technique. When a reverse bias is applied to the semiconductor device 400, a depletion layer expands into the n-type semiconductor layer 403, resulting in a high-voltage SBD. When a forward bias is applied, electrons flow from the second electrode 405 to the first electrode 404.

[0060] FIG. 13 is a cross-sectional view schematically illustrating another example of a semiconductor device 500. The semiconductor device 500 is a JBS (junction barrier Schottky diode). The semiconductor device 500 includes a semiconductor layer 501, a barrier height adjusting region 502, a first electrode 503, and a second electrode 504. The semiconductor layer 501 may be a single layer or may include multiple semiconductor layers. The semiconductor layer 501 has a first surface 501a, which is one surface of the semiconductor layer 501 in the thickness direction, and a second surface 501b, which is the surface opposite to the first surface 501a. The barrier height adjusting region 502 is formed on the first surface 501a. The first electrode 503 is formed on the first surface 501a so as to be in contact with both the semiconductor layer 501 and the barrier height adjusting region 502. The first electrode 503 is a barrier electrode that forms a Schottky barrier between the semiconductor layer 501 and the first electrode 503. The second electrode 504 is formed on the second surface 501b. The second electrode 504 is an ohmic electrode. The barrier height adjusting region 502 is formed between the semiconductor layer 501 and the first electrode 503. The barrier height adjusting region 502 forms a Schottky barrier between the semiconductor layer 501 and the first electrode 503, with a barrier height greater than that of the Schottky barrier of the first electrode 503. In this example, a plurality of trenches 501c are formed in the first surface 501a of the semiconductor layer 501. The barrier height adjusting region 502 is embedded in each trench 501c. The barrier height adjusting region 502 is preferably provided at least between both ends of the first electrode 503 and the semiconductor layer 501. The barrier height adjusting region 502 is preferably provided at regular intervals.

[0061] The material of each of the first electrode 503 and the second electrode 504 may be a known electrode material. The electrode material may be the same as the material of each of the first electrode 404 and the second electrode 405 of the semiconductor device 400. Each of the first electrode 503 and the second electrode 504 may be formed by a known method, such as a vacuum deposition method or a sputtering method. Each of the first electrode 503 and the second electrode 504 may be formed in the same manner as each of the first electrode 404 and the second electrode 405 of the semiconductor device 400. The same applies to the material and formation of each electrode of the semiconductor devices 550, 600, 700, and 800 described below.

[0062] FIG. 14 is a cross-sectional view schematically illustrating another example of a semiconductor device 550. The semiconductor device 550 is a JBS (junction barrier Schottky diode). Like the semiconductor device 500, the semiconductor device 550 includes a semiconductor layer 551, a barrier height adjusting region 552, a first electrode 553, and a second electrode 554. In addition, the semiconductor device 550 further includes a guard ring 555 formed on the semiconductor layer 551. In this example, the semiconductor device 550 includes a plurality of guard rings 555. The guard rings 555 are positioned around the first electrode 553. At least a portion of the guard rings 555 is embedded in the semiconductor layer 551. By providing the guard rings 555, it is possible to improve the breakdown voltage and the like, thereby improving the semiconductor characteristics of the semiconductor device 550.

[0063] The guard ring 555 is typically made of a material with a high barrier height. Examples of materials used for the guard ring 555 include conductive materials with a barrier height of 1 eV or more. The material for the guard ring 555 may be the same material as the electrode material. The material for the guard ring 555 may be any of the metals exemplified as the materials for the first electrode 404 and the second electrode 405 of the semiconductor device 400. In this case, the design freedom for the voltage-resistant structure is high, and many guard rings 555 can be provided, thereby flexibly improving the voltage resistance. The shape of the guard ring 555 is not particularly limited. Examples of the shape of the guard ring 555 include a square shape, a circular shape, a U-shape, an L-shape, and a strip shape. The number of guard rings 555 included in the semiconductor device 550 is also not particularly limited. The semiconductor device 550 preferably includes three or more guard rings 555, and more preferably six or more guard rings 555.

[0064] FIG. 15 is a cross-sectional view schematically illustrating another example of a semiconductor device 600. The semiconductor device 600 is an LED. The semiconductor device 600 includes an n-type semiconductor layer 601, a light-emitting layer 602, a p-type semiconductor layer 603, a transparent electrode 604, a first electrode 605, and a second electrode 606. The light-emitting layer 602 is formed on the n-type semiconductor layer 601. The light-emitting layer 602 emits light. The p-type semiconductor layer 603 is formed on the light-emitting layer 602. The transparent electrode 604 is formed on the p-type semiconductor layer 603. The transparent electrode 604 is transparent. Therefore, light generated in the light-emitting layer 602 passes through the transparent electrode 604. The first electrode 605 is formed on the transparent electrode 604. The first electrode 605 is an anode electrode. The second electrode 606 is formed on the surface of the n-type semiconductor layer 601 opposite to the light emitting layer 602. The second electrode 606 is a cathode electrode. The semiconductor device 600 may be covered with a protective layer except for the electrode portion.

[0065] FIG. 16 is a cross-sectional view schematically illustrating another example of a semiconductor device 700. The semiconductor device 700 is a MOSFET, specifically, a vertical device called a trench MOSFET. The semiconductor device 700 includes a first n+ type semiconductor layer 701, an n- type semiconductor layer 702, a p-type semiconductor layer 703, a second n+ type semiconductor layer 704, an insulating film 705, a first electrode 706, a second electrode 707, and a third electrode 708. The n- type semiconductor layer 702 is formed on the first n+ type semiconductor layer 701. The p-type semiconductor layer 703 is formed on the n- type semiconductor layer 702. The second n+ type semiconductor layer 704 is formed on the p-type semiconductor layer 703. The first electrode 706 is formed on the second n+ type semiconductor layer 704. The first electrode 706 is a source electrode. The second electrode 707 is formed on the surface of the first n+ type semiconductor layer 701 opposite to the n- type semiconductor layer 702. The second electrode 707 is a drain electrode. A plurality of trenches 709 are formed on the surface of the semiconductor layer formed from the n- type semiconductor layer 702, the p-type semiconductor layer 703, and the second n+ type semiconductor layer 704, on the first electrode 706 side. Each of the plurality of trenches 709 penetrates the second n+ type semiconductor layer 704 and the p-type semiconductor layer 703 to reach the n- type semiconductor layer 702. A third electrode 708 is buried in each trench 709 via an insulating film 705. The third electrode 708 is a gate electrode.

[0066] FIG. 17 is a cross-sectional view schematically illustrating another example of a semiconductor device 720. The semiconductor device 720 is a MOSFET, specifically, a vertical device called a planar MOSFET. The semiconductor device 720 includes a first n+ type semiconductor layer 721, an n- type semiconductor layer 722, a p-type semiconductor layer 723, a second n+ type semiconductor layer 724, an insulating film 725, a first electrode 727, a second electrode 728, and a third electrode 726. The n- type semiconductor layer 722 is formed on the first n+ type semiconductor layer 721. The p-type semiconductor layer 723 is formed on the n- type semiconductor layer 722. The second n+ type semiconductor layer 724 is formed so as to be embedded in the p-type semiconductor layer 723. The first electrode 727 is formed so as to straddle the p-type semiconductor layer 723 and the second n+ type semiconductor layer 724. The first electrode 727 is a source electrode. The second electrode 728 is formed on the surface of the first n+ type semiconductor layer 721 opposite to the n- type semiconductor layer 722. The second electrode 728 is a drain electrode. A third electrode 726 is formed via an insulating film 725 formed so as to straddle the n- type semiconductor layer, the p-type semiconductor layer 724, and a portion of the second n+ type semiconductor layer 724. The third electrode 726 is a gate electrode.

[0067] FIG. 18 is a cross-sectional view schematically illustrating another example of a semiconductor device 730. The semiconductor device 730 is a MOSFET, specifically, a lateral device MOSFET. The semiconductor device 730 includes an n-type semiconductor layer 731a, a first n+ type semiconductor layer 731b, a second n+ type semiconductor layer 731c, an insulating film 734, a first electrode 735a, a second electrode 735b, and a third electrode 735c on a substrate 739 via a buffer layer. The n-type semiconductor layer 731a is formed on a buffer layer 738. The first n+ type semiconductor layer 731b and the second n+ type semiconductor layer 731c are formed so as to be embedded in the n- type semiconductor layer 731a. The first electrode 735a is formed on the n-type semiconductor layer 731a via an insulating film 734 formed so as to straddle a portion of the first n+ type semiconductor layer 731b and the second n+ type semiconductor layer 731c. The first electrode 735a is a gate electrode. A second electrode 735b is formed on the first n+ type semiconductor layer 731b. The second electrode 735b is a source electrode. Furthermore, a third electrode 735c is formed on the second n+ type semiconductor layer 731c. The third electrode is a drain electrode.

[0068] FIG. 19 is a cross-sectional view schematically illustrating another example of a semiconductor device 750. The semiconductor device 750 is an IGBT. The semiconductor device 750 includes a p-type semiconductor layer 751, an n-type semiconductor layer 752, an n-type semiconductor layer 753, a p-type semiconductor region 754, an n+ type semiconductor region 755, an insulating film 756, a plurality of first electrodes 757, a second electrode 758, and a third electrode 759. The n-type semiconductor layer 752 is formed on the p-type semiconductor layer 751. The n-type semiconductor layer 753 is formed on the n-type semiconductor layer 752. A plurality of trenches 752a are formed on the surface of the n-type semiconductor layer 753 opposite to the n-type semiconductor layer 752. A p-type semiconductor region 754 is formed inside each of the plurality of trenches 752a. An n+ type semiconductor region 755 is formed inside each of the p-type semiconductor regions 754. The insulating film 756 is formed on the n- type semiconductor layer 753 so as to be in contact with the n- type semiconductor layer 753, the p-type semiconductor region 754, and the n+ type semiconductor region 755. Each of the plurality of first electrodes 757 is formed on the p-type semiconductor region 754 so as to be in contact with the p-type semiconductor region 754 and the n+ type semiconductor region 755. The first electrode 757 is an emitter electrode. The second electrode 758 is formed on the surface of the p-type semiconductor layer 751 opposite to the n-type semiconductor layer 752. The second electrode 758 is a collector electrode. The third electrode 759 is formed on the insulating film 756. The third electrode 759 is a gate electrode.

[0069] FIG. 20 is a cross-sectional view schematically illustrating another example of a semiconductor device 800. The semiconductor device 800 is a HEMT. The semiconductor device 800 includes a semi-insulating layer 801, a buffer layer 802, a first n-type semiconductor layer 803, a second n-type semiconductor layer 804, a plurality of n+ type semiconductor layers 805, a first electrode 806, a second electrode 807, and a third electrode 808. The buffer layer 802 is formed on the semi-insulating layer 801. The first n-type semiconductor layer 803 is formed on the buffer layer 802. The second n-type semiconductor layer 804 is formed on the first n-type semiconductor layer 803. The band gap of the second n-type semiconductor layer 804 is wider than the band gap of the first n-type semiconductor layer 803. The plurality of n+ type semiconductor layers 805 are embedded in the first n-type semiconductor layer 803 and the second n-type semiconductor layer 804. The n+ type semiconductor layer 805 is in contact with the first n-type semiconductor layer 803 and the second n-type semiconductor layer 804. A first electrode 806 and a second electrode 807 are formed on each of the n+ type semiconductor layers 805. The first electrode 806 is a source electrode. The second electrode 807 is a drain electrode. A third electrode 808 is formed on the second n-type semiconductor layer 804. The third electrode 808 is a gate electrode.

[0070] 21 is a cross-sectional view schematically showing another example of a semiconductor device 850. The semiconductor device 850 is a JFET. The semiconductor device 850 includes a first n+ type semiconductor layer 851, an n- type semiconductor layer 852, a second n+ type semiconductor layer 853, a first electrode 854, a second electrode 855, and a third electrode 856. The n- type semiconductor layer 852 is formed on the first n+ type semiconductor layer 851. The second n+ type semiconductor layer 853 is formed on the n- type semiconductor layer 852. The first electrode 854 is formed on the second n+ type semiconductor layer 853. The first electrode 854 is a source electrode. A layer formed by the n-type semiconductor layer 852, the second n+ type semiconductor layer 853, and the first electrode 854 has a plurality of trenches 857 formed therein, the trenches 857 extending from the surface of the first electrode 854 opposite the n+ type semiconductor layer 853, through the first electrode 854 and the second n+ type semiconductor layer 853, and reaching the n-type semiconductor layer 852. The second electrode 855 is formed on the surface of the n-type semiconductor layer 852 opposite the first n+ type semiconductor layer 851. The second electrode 855 is a drain electrode. The third electrode 856 is formed at the bottom of each trench 857. The third electrode 856 is in contact with the n-type semiconductor layer 852. The third electrode 856 is a gate electrode. In addition to the above features, the semiconductor devices 400, 500, 550, 600, 700, 730, 750, 800, and 850 can be suitably used as power modules, inverters, or converters using known methods, and can also be suitably used in, for example, semiconductor systems using power supply devices. A power supply device can be fabricated using known methods by connecting the semiconductor devices 400, 500, 550, 600, 700, 730, 750, 800, and 850 to a wiring pattern, etc.

[0071] FIG. 22 is a block diagram showing an example of a power supply system 900. The power supply system 900 includes multiple power supply devices 901 and 902 and a control circuit 903. FIG. 23 is a block diagram showing an example of a system device 910. The system device 910 includes the power supply system 900 and an electronic circuit 911. FIG. 24 is a circuit diagram showing an example of a power supply circuit 920 for a power supply device. This power supply circuit 920 includes a power circuit and a control circuit. This power supply circuit 920 uses an inverter 921 (comprising MOSFETs A to D) to switch DC voltage at high frequency to convert it to AC, then uses a transformer 922 to perform insulation and transformation, rectifies the voltage using a rectifier MOSFET 923, and smooths it using a DCL 924 (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, a voltage comparator 925 compares the output voltage with a reference voltage, and a PWM control circuit 926 controls the inverter 921 and rectifier MOSFET 923 to achieve the desired output voltage.

[0072] Example 1 Examples of the present disclosure will be described below, but the present disclosure is not limited thereto. An m-plane sapphire substrate with a diameter of 2 inches and a thickness of 300 μm was used as the substrate 20. A long-wavelength laser (SHG laser, laser wavelength 655 nm, processing speed 200 mm / s, repetition number 4) was irradiated onto a portion of the upper surface of the substrate 20 to form grooves on the upper surface of the substrate 20, and then the upper surface of the substrate 20 with the grooves formed thereon was cleaned with a cleaning solution containing hydrofluoric acid. Next, a film formation apparatus 40 shown in FIG. 26 was prepared. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used. The supply pipe 42 and the susceptor 41 were both made of quartz in order to prevent impurities from the apparatus from being mixed into the crystal film.

[0073] (Method for forming crystal film 1) (1) Preparation of raw material solution Gallium bromide was prepared at 0.1 mol / L and １６ / cm ３Tin bromide was mixed with ultrapure water to prepare a solution containing 10% by volume of hydrobromic acid, which was used as a crystal film raw material solution 34a. The resulting crystal film raw material solution 34a was placed in the atomized droplet generating source 34. (2) Transport Step: The previously cleaned substrate 20 was placed on the susceptor 41, and the temperature of the heater 43 was raised to 550°C. Next, oxygen gas was used as a carrier gas, and the flow control valves 33a and 33b were opened to supply the carrier gas from the carrier gas sources 32a and 32b into the supply pipe 42. Thereafter, the flow rates of the carrier gas from the carrier gas source 32a and the carrier gas (diluted) from the carrier gas source 32b were adjusted to 0.5 L / min and 0.5 L / min, respectively, and the temperature of the heater 43 was maintained at 550°C. (3) Atomization Process and Film Formation Process Next, the ultrasonic vibrator 36 was vibrated, and the vibration was propagated to the raw material solution 34a through the water 35a, thereby atomizing the raw material solution 34a and generating atomized droplets. The generated atomized droplets were transported to the film formation chamber in the transport process, and a crystalline film 1 having a corundum structure with little transition to the β-type was obtained on the substrate 20 placed on the susceptor 41 and heated and maintained at 550°C.

[0074] Example 2: A substrate 20 was used after grooves were formed on its upper surface in the same manner as in Example 1 and then cleaned with a cleaning solution containing hydrofluoric acid. A buffer layer was formed on the grooved upper surface of the substrate 20 according to the following procedure. To fabricate the buffer layer, a film-forming apparatus 40 shown in FIG. 26 was prepared, as in Example 1. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used. (Formation of Buffer Layer) (1) Preparation of Source Solution: Gallium bromide and tin bromide were mixed with ultrapure water to prepare an aqueous solution such that the atomic ratio of tin to gallium was 1:0.08 and the gallium concentration was 0.1 mol / L. Hydrobromic acid was further added at a volume ratio of 20%. This was used as a buffer layer source solution 34a. The resulting buffer layer source solution 34a was placed in the atomized droplet generator 34. (2) Transfer Step Next, the cleaned substrate 20 was placed on the susceptor 41, and the flow rate control valve 33b was opened to supply a carrier gas (diluted) from the carrier gas source 32b into the supply pipe 42. Next, the heater 43 was started to heat up, and the temperature of the heater 43 was raised to 600°C. Furthermore, oxygen gas was used as the carrier gas, and the flow rate control valve 33a was opened to supply the carrier gas from the carrier gas source 32a into the supply pipe 42. After the heater 43 was heated, the flow rates of the carrier gas from the carrier gas source 32a and the carrier gas (diluted) from the carrier gas source 32b were adjusted to 1.0 L / min, respectively, and the temperature of the heater 43 was maintained at 600°C. (3) Atomization Step and Film Formation Step Next, the ultrasonic vibrator 36 was vibrated, and the vibrations were propagated to the raw material solution 34a through the water 35a, thereby atomizing the raw material solution 34a and generating atomized droplets. The atomized droplets were transported to the supply pipe 42 by the carrier gas, and the atomized droplets were subjected to a thermal reaction near the surface of the substrate 20 under atmospheric pressure, forming a buffer layer having a corundum structure on the substrate 20 .

[0075] (Method of Forming Crystalline Film 2) Subsequently, the crystal film 2 was formed on the substrate 20 on which the buffer layer was formed by the following method. (1) Preparation of Raw Material Solution Gallium bromide was added to a solution containing 0.1 mol / L of gallium bromide and a carrier concentration of 2.0×10 １６ / cm ３Bis[2-carboxyethylgermanium(IV)]sesquioxide (C ６ H １０ Ge ２ O ７ ) was mixed with ultrapure water to prepare a solution containing 10% by volume of hydrobromic acid. This solution was used as a raw material solution 34a for the crystal film. The resulting raw material solution 34a for the crystal film was placed in the atomized droplet generating source 34. (2) Transport Step: The substrate 20 on which the buffer layer was formed was placed on the susceptor 41, and the temperature of the heater 43 was maintained at 600°C. Next, oxygen was used as the carrier gas, and the flow control valves 33a and 33b were opened to supply the carrier gas from the carrier gas sources 32a and 32b into the supply pipe 42. Thereafter, the flow rates of the carrier gas from the carrier gas source 32a and the carrier gas (diluted) from the carrier gas source 32b were adjusted to 0.5 L / min and 0.5 L / min, respectively, and the temperature of the heater 43 was maintained at 600°C. Note that oxygen was used as the carrier gas.

[0076] (3) Atomization Process and Film Formation Process Next, the ultrasonic vibrator 36 was vibrated, and the vibration was propagated to the raw material solution 34a through the water 35a, thereby atomizing the raw material solution 34a and generating atomized droplets. The generated atomized droplets were transported to the film formation chamber in the transport process, and a buffer layer having a corundum structure was formed on the substrate 20, which was placed on the susceptor 41 and heated and maintained at 600°C.

[0077] (Example 3) In the transport process for forming the buffer layer, the flow control valves 33a and 33b were opened simultaneously with the start of heating by the heater 43, and the carrier gas and the carrier gas (diluted) were supplied into the supply pipe 42 from the carrier gas sources 32a and 32b. In the same manner as in Example 2, a crystal film 3 was obtained on the substrate 20 on which the buffer layer was formed.

[0078] Example 4: An m-plane sapphire substrate with a diameter of 2 inches and a thickness of 300 μm was used as the substrate 20. A long-wavelength laser (SHG laser, laser wavelength 655 nm, processing speed 200 mm / s, repetition rate 4 times) was irradiated onto a portion of the upper surface of the substrate 20 to form grooves on the upper surface of the substrate 20, and the upper surface of the substrate 20 with the grooves formed thereon was then cleaned by spraying water. Next, a film-forming apparatus 40 shown in FIG. 26 was prepared, and the substrate 20, which had been grooved and then cleaned with water, was placed on a susceptor 41. Next, oxygen was used as the carrier gas, and the flow rate control valve 33b was opened to supply a diluted carrier gas from the carrier gas source 32b into the supply pipe 42. Then, heating by the heater 43 was started, and the temperature of the heater 43 was raised to 600° C. Next, without vibrating the ultrasonic vibrator or performing the atomization process, the flow rate control valve 33a was opened to supply a carrier gas from the carrier gas source 32a into the supply pipe 42. After the temperature of the heater 43 was raised, the flow rates of the carrier gas from the carrier gas source 32a and the carrier gas (diluted) from the carrier gas source 32b were adjusted to 1.0 L / min and 1.0 L / min, respectively, to maintain the temperature of the heater 43 at 600°C. Oxygen was used as the carrier gas. Thereafter, heating by the heater 43 was stopped, and the substrate 20 was cooled to room temperature. The cooled substrate 20 was then placed on the susceptor 41 of the film-forming apparatus 40, and a buffer layer and a crystalline film were formed in sequence in the same manner as in Example 3. A crystalline film 4 having a corundum structure with very little transition to the β-type was obtained on the substrate 20 on which the buffer layer was formed.

[0079] Example 5 An m-plane sapphire substrate with a diameter of 2 inches and a thickness of 300 μm was used as the substrate 200. A long-wavelength laser (SHG laser, laser wavelength 655 nm, processing speed 200 mm / s, repeated 4 times) was irradiated onto a portion of the upper surface of the substrate 200 to form grooves on the upper surface of the substrate 200, and then the upper surface of the substrate 200 with the grooves formed thereon was cleaned with a cleaning solution containing hydrofluoric acid. Next, a film formation apparatus 40 shown in FIG. 26 was prepared. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used. The supply pipe 42 and the susceptor 41 were both made of quartz in order to prevent impurities from the apparatus from being mixed into the crystal film.

[0080] (Formation of buffer layer) A buffer layer was formed on the substrate 200 in the same manner as in Example 4, except that the substrate 200 was used instead of the substrate 20. (Method of forming second crystal film 1-2) The substrate 200 on which a buffer layer was formed was used instead of the substrate 20 on which a buffer layer was formed, and the carrier concentration was 2.5×10 １６ A second crystalline film 1-2 was obtained on a substrate 200 having a buffer layer formed thereon in the same manner as in Example 4, except that the concentration of bis[2-carboxyethylgermanium(IV)]sesquioxide in the raw material solution was adjusted so that the second crystalline film 1-2 was 0.05g / cm 2 (Method of Forming First Crystalline Film 1-1) The obtained second crystalline film 1-2 was placed on a susceptor 41, and the temperature of a heater 43 was maintained at 600°C. Then, a first crystalline film 1-1 was formed on the second crystalline film 1-2 in the same manner as in Example 4. As a result, a multilayer crystalline film 1 was obtained, which was made up of the second crystalline film 1-2 and the first crystalline film 1-1, and which had a corundum structure with very little transition to the β-type, and in which the second crystalline film 1-2 and the first crystalline film 1-1 were laminated in this order on a substrate 200 having a buffer layer.

[0081] (Comparative Example 1) An m-plane sapphire substrate having a diameter of 2 inches and a thickness of 300 μm was used as the substrate 20, and without forming a groove or a buffer layer, it was placed on the susceptor 41 of the film-forming device 40. In the same manner as in the method for forming the crystal film 2 of Example 2, a crystal film 5 having a corundum structure but in which a phase transition to the β type had occurred in part of the substrate was obtained on the substrate 20.

[0082] Comparative Example 2: A crystalline film 6 having a corundum structure with very little phase transition to the β type was formed on a substrate 20 that had been cleaned after grooves were formed in the same manner as in Example 1, except that the temperature of the heater 43 was changed from 550°C to 400°C.

[0083] (Evaluation Measurement) (1) Measurement of trap level density (only for crystalline film and first crystalline film) For the crystalline films 1 to 6 obtained in Examples 1 to 4, Comparative Examples 1 and 2, and the first crystalline film 1-1 of the multilayer crystalline film 1 obtained in Example 5, DLTS measurements were performed using an FT-1239 (manufactured by PhysTech) under the following measurement conditions: temperature range 80 to 673 K, measurement temperature interval 2 K, pulse voltage 0 V, bias voltage -5 V, pulse width 0.1 ms, period width (Tw) 19.2 ms, 192 ms, 1920 ms, time constants corresponding to Tw 9.84 ms, 91.94 ms, 920 ms, and analysis method was the correlation function method. The measurement results are shown in Table 1 and Table 2. (2) Measurement of Carrier Concentration (for All Crystalline Films) Carrier concentrations were measured by Hall effect measurement for the crystal films 1 to 6 obtained in Examples 1 to 4 and Comparative Examples 1 and 2, and for the first crystal film 1-1 and second crystal film 1-2 of the multilayer crystal film 1 obtained in Example 5. The measurement results are shown in Tables 1 and 2. (3) Measurement of Halogen Concentration Halogen concentrations were measured by SIMS for the crystal films 1 to 6 obtained in Examples 1 to 4 and Comparative Examples 1 and 2, and for the first crystal film 1-1 of the multilayer crystal film 1 obtained in Example 5. The measurement results are shown in Tables 1 and 2.

[0084] A plurality of semiconductor devices were fabricated using, in part or in whole, the crystalline films 1 to 6 obtained in Examples 1 to 4 and Comparative Examples 1 and 2, and the multilayer crystalline film 1 obtained in Example 5. Each of the plurality of semiconductor devices was the semiconductor device shown in Figures 12 to 21, and all of them exhibited excellent electrical characteristics.

[0085] The following additional notes are provided for the above-described embodiments of the present disclosure: (Additional Note 1) A semiconductor device comprising a crystalline oxide and one or more Group 14 elements of the periodic table as dopants, wherein the trap level density in a region 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer of the oxide is 1×10 １４ / cm ３(Appendix 2) The crystalline film according to Appendix 1, wherein the trap level density is a value obtained by a DLTS method. (Appendix 3) The crystalline film according to Appendix 1 or Appendix 2, wherein the crystalline oxide contains one or more metal elements selected from gallium, aluminum, and indium. (Appendix 4) The crystalline film according to any one of Appendix 1 to Appendix 3, wherein the dopant contains at least one of germanium, tin, and silicon. (Appendix 5) A carrier concentration of 1×10 １７ / cm3 or less. (Supplementary Note 6) A multilayer crystalline film comprising a first crystalline film and a second crystalline film, wherein the first crystalline film contains a crystalline oxide and one or more Group 14 elements of the periodic table as dopants, and the trap level density at 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer of the oxide is 1×10 １４ / cm ３ A multilayer crystalline film in which the carrier concentration of the second crystalline film is 1.0×10 or less, and the carrier concentration of the second crystalline film is higher than the carrier concentration of the first crystalline film. １８ / cm ３ The multilayer crystalline film according to Appendix 6, wherein the multilayer crystalline film is formed directly on the first crystalline film. (Appendix 8) The multilayer crystalline film according to Appendix 6 or Appendix 7, wherein the second crystalline film is provided directly on the first crystalline film. (Appendix 9) The multilayer crystalline film according to any one of Appendix 6 to Appendix 8, further comprising a p-type semiconductor film. (Appendix 10) A semiconductor device including the crystalline film according to any one of Appendix 1 to Appendix 5. (Appendix 11) A semiconductor device including the multilayer crystalline film according to any one of Appendix 6 to Appendix 9.

[0086] REFERENCE SIGNS LIST 10 Crystal film 20 Substrate 21 Groove 25 Buffer layer 26 ELO mask 30 Film formation apparatus 32a Carrier gas source (dilution) 32b Carrier gas source 33a Flow rate adjustment valve 33b Flow rate adjustment valve 34 Atomized droplet generation source 34a Raw material solution 35 Container 35a Water 36 Ultrasonic vibrator 37 Film formation chamber 37a Exhaust port 38 Supply pipe 39 Hot plate 40 Film formation apparatus 41 Susceptor 42 Supply pipe 42a Exhaust port 43 Heater 100 Multilayer crystal film 110 First crystal film 120 Second crystal film 130 P-type semiconductor layer 200 Substrate 400 Semiconductor device 401 Semiconductor layer 401a First surface 401b Second surface 402 N+-type semiconductor layer 403 n-type semiconductor layer 404 First electrode 405 Second electrode 500 Semiconductor device 501 Semiconductor layer 501a First surface 501b Second surface 501c Trench 502 Barrier height adjusting region 503 First electrode 504 Second electrode 550 Semiconductor device 551 Semiconductor layer 551a First surface 551b Second surface 551c Trench 552 Barrier height adjusting region 553 First electrode 554 Second electrode 555 Guard ring 600 Semiconductor device 601 n-type semiconductor layer 602 Light-emitting layer 603 p-type semiconductor layer 604 Transparent electrode 605 First electrode 606 Second electrode 700 Semiconductor device 701 First n+ type semiconductor layer 702 n- type semiconductor layer 703 p-type semiconductor layer 704 second n+ type semiconductor layer 705 insulating film 706 first electrode 707 second electrode 708 third electrode 709 trench 720 semiconductor device 721 first n+ type semiconductor layer 722 n- type semiconductor layer 723 p-type semiconductor layer 724 second n+ type semiconductor layer 725 gate insulating film 726 first electrode 727 second electrode 728 third electrode 730 semiconductor device 731a n- type semiconductor layer 731b first n+ type semiconductor layer 731c second n+ type semiconductor layer 734 insulating film 735a first electrode 735b second electrode 735c third electrode 738 buffer layer 739 substrate 750 semiconductor device 751 p-type semiconductor layer 752 n- type semiconductor layer 752a trench 753 n-type semiconductor layer 754 p-type semiconductor layer 755 n+ type semiconductor layer 756 insulating film757 First electrode 758 Second electrode 759 Third electrode 800 Semiconductor device 801 Semi-insulating layer 802 Buffer layer 803 First n+ type semiconductor layer 804 Second n+ type semiconductor layer 805 n+ type semiconductor layer 806 First electrode 807 Second electrode 808 Third electrode 850 Semiconductor device 851 First n+ type semiconductor layer 852 n- type semiconductor layer 853 Second n+ type semiconductor layer 854 First electrode 855 Second electrode 856 Third electrode 857 Trench

Claims

1. A crystalline oxide containing one or more Group 14 elements of the periodic table as a dopant, wherein the trap level density at 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer of the oxide is 1×10 １４ / cm ３ Below is a crystalline film.

2. The crystal film according to claim 1, wherein the trap level density is a value obtained by the DLTS method.

3. The crystalline film according to claim 1, wherein the crystalline oxide contains one or more metal elements selected from the group consisting of gallium, aluminum, and indium.

4. The crystalline film according to claim 1, wherein the dopant includes at least one of germanium, tin, and silicon.

5. Carrier concentration is 1×10 １７ / cm ３ The crystal film according to claim 1, wherein:

6. A multilayer crystalline film comprising a first crystalline film and a second crystalline film, wherein the first crystalline film and the second crystalline film each contain a crystalline oxide and one or more Group 14 elements of the periodic table as dopants, and the trap level density at 0.2 to 0.8 eV from the bottom of the conduction band of a semiconductor layer of the oxide is 1×10 １４ / cm ３ a carrier concentration of the second crystal film higher than a carrier concentration of the first crystal film; 7. The carrier concentration of the second crystalline film is 1.0×10 １８ / cm ３ 7. The multilayer crystal film according to claim 6, wherein the multilayer crystal film is a multilayer crystal film having the above structure.

8. The multilayer crystalline film according to claim 6, wherein the second crystalline film is provided directly on the first crystalline film.

9. The multilayer crystalline film according to claim 6, further comprising a p-type semiconductor film.

10. A semiconductor device comprising the crystalline film according to claim 1.

11. A semiconductor device comprising the multilayer crystalline film according to claim 6.

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