Semiconductor device and design method therefor, and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device and a design method therefor, and an electronic device, which are used for alleviating problems such as the relatively low yield and reliability of chips. The semiconductor device comprises: a first die, a second die and a plurality of interconnection ports, wherein the first die comprises a plurality of shift transmission circuits, the second die comprises a plurality of shift reception circuits, and an ith signal output end of each shift transmission circuit is connected to an ith signal input end of each shift reception circuit by means of an ith interconnection port, so as to form a shift transfer circuit; and any two adjacent interconnection ports of the semiconductor device are connected to different shift transfer circuits, and when a bridging fault occurs in any two adjacent interconnection ports, shift repair can be respectively performed on the interconnection ports by means of different shift transfer circuits.

Description

Semiconductor device, design method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 21, 2024, with application number 202410195023.6 and application name “A semiconductor device, its design method, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a design method thereof, and an electronic device. Background Art

[0003] Three-dimensional integrated circuits (3D ICs) use interconnections such as through-silicon vias (TSVs) to vertically interconnect multiple stacked dies, offering advantages such as high performance, high bandwidth, low power consumption, and support for heterogeneous integration.

[0004] 3D chips are prone to defects during the manufacturing process. For example, interconnect defects may be caused by factors such as misalignment stress or external force, resulting in interconnect short circuits, short circuits or bridging faults. Interconnect faults can be repaired by signal shifting or signal switching, affecting the yield and reliability of 3D chips.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a semiconductor device and a design method thereof, as well as an electronic device, to improve problems such as low chip yield and reliability.

[0007] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a first die, a second die, and a plurality of interconnection ports; the first die comprises a plurality of signal sending nodes and a plurality of shift sending circuits; the shift sending circuit comprises a plurality of signal input terminals and a plurality of signal output terminals, the signal inputted by the i-th signal input terminal is configured to be outputted through the i-th signal output terminal or the i+1-th signal output terminal, where i is a positive integer; the plurality of signal input terminals of the shift sending circuit are respectively connected to a signal sending node; the second die comprises a plurality of signal receiving nodes and a plurality of shift receiving circuits, the shift receiving circuit comprises a plurality of signal input terminals and a plurality of signal output terminals, the i-th signal output terminal is configured to output the signal inputted by the i-th signal input terminal or the i+1-th signal input terminal, and the plurality of signal output terminals of the shift receiving circuit are respectively connected to a signal receiving node; the i-th signal output terminal of the shift sending circuit is connected to the i-th signal input terminal of the shift receiving circuit through the i-th interconnection port; the shift sending circuits connected to any two adjacent interconnection ports of the semiconductor device are different, and the shift receiving circuits connected to any two adjacent interconnection ports are different.

[0008] The semiconductor device provided in the embodiment of the present application includes multiple interconnect ports, and any two adjacent interconnect ports are located in different shift transmission circuits. When a bridging fault occurs in the adjacent interconnect ports, the bridging fault of the two interconnect ports can be converted into a fault of a single interconnect port in the two shift transmission circuits. Shift repair of the single interconnect port can be implemented in the two shift transmission circuits respectively, thereby implementing bridge fault repair of the two interconnect ports.

[0009] In a possible implementation, different shift and transmit circuits have the same or different numbers of signal input terminals.

[0010] In one possible implementation, the shift transmission circuit includes n signal input terminals, n+1 signal output terminals, and n-1 multiplexers, the multiplexers including a first input terminal, a second input terminal, and an output terminal; in the shift transmission circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift transmission circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift transmission circuit, and the output terminal of the mth multiplexer is connected to the m+1th signal output terminal of the shift transmission circuit, where m and n are positive integers, and m≤n-1.

[0011] In a possible implementation, the first signal input terminal of the shift transmission circuit is also connected to the first signal output terminal of the shift transmission circuit; the nth signal input terminal of the shift transmission circuit is also connected to the n+1th signal output terminal of the shift transmission circuit.

[0012] In a possible implementation, different shift receiving circuits have the same or different numbers of signal input terminals.

[0013] In one possible implementation, the shift receiving circuit includes n+1 signal input terminals, n signal output terminals, and n multiplexers, each multiplexer including a first input terminal, a second input terminal, and an output terminal. In the shift receiving circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift receiving circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift receiving circuit, and the output terminal of the mth multiplexer is connected to the mth signal output terminal of the shift receiving circuit, where m and n are positive integers and m≤n-1.

[0014] In a possible implementation, the plurality of interconnection ports are arranged in rows and columns, and any two adjacent interconnection ports in the same row or column are connected to different shifted transmitting circuits and different shifted receiving circuits.

[0015] In one possible implementation, the interconnection port includes a micro bump, a hybrid bonding port, and a through silicon via.

[0016] In one possible implementation, the multiple interconnect ports include a first interconnect port, a second interconnect port, and a third interconnect port, the first interconnect port is adjacent to the second interconnect port, the distance between the first interconnect port and the second interconnect port is less than or equal to the distance between the first interconnect port and the third interconnect port, and the distance between the first interconnect port and the second interconnect port is less than or equal to the distance between the second interconnect port and the third interconnect port.

[0017] In the second aspect, an embodiment of the present application provides a bare chip, comprising multiple signal sending nodes, multiple shift sending circuits and multiple interconnection ports; the shift sending circuit comprises multiple signal input terminals and multiple signal output terminals, the signal input at the i-th signal input terminal is configured to be output through the i-th signal output terminal or the i+1-th signal output terminal, where i is a positive integer; the multiple signal input terminals of the shift sending circuit are respectively connected to a signal sending node, and the multiple signal output terminals of the shift sending circuit are respectively connected to an interconnection port; any two adjacent interconnection ports of the bare chip are connected to different shift sending circuits.

[0018] In a possible implementation, different shift and transmit circuits have the same or different numbers of input terminals.

[0019] In one possible implementation, the shift transmission circuit includes n signal input terminals, n+1 signal output terminals, and n-1 multiplexers, the multiplexers including a first input terminal, a second input terminal, and an output terminal; in the shift transmission circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift transmission circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift transmission circuit, and the output terminal of the mth multiplexer is connected to the m+1th signal output terminal of the shift transmission circuit, where m and n are positive integers, and m≤n-1.

[0020] In a possible implementation, the first signal input terminal of the shift transmission circuit is also connected to the first signal output terminal of the shift transmission circuit; the nth signal input terminal of the shift transmission circuit is also connected to the n+1th signal output terminal of the shift transmission circuit.

[0021] On the third aspect, an embodiment of the present application also provides a bare chip, comprising multiple signal receiving nodes, multiple shift receiving circuits and multiple interconnection ports, the shift receiving circuit comprising multiple signal input terminals and multiple signal output terminals, the i-th signal output terminal is configured to output the signal input by the i-th signal input terminal or the i+1-th signal input terminal, where i is a positive integer; the multiple signal input terminals of the shift receiving circuit are respectively connected to an interconnection port, and the multiple signal output terminals of the shift receiving circuit are respectively connected to a signal receiving node; any two adjacent interconnection ports of the bare chip are connected to different shift receiving circuits.

[0022] In a possible implementation, different shift receiving circuits have the same or different numbers of signal input terminals.

[0023] In one possible implementation, the shift receiving circuit includes n+1 signal input terminals, n signal output terminals, and n multiplexers, each multiplexer including a first input terminal, a second input terminal, and an output terminal. In the shift receiving circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift receiving circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift receiving circuit, and the output terminal of the mth multiplexer is connected to the mth signal output terminal of the shift receiving circuit, where m and n are positive integers and m≤n-1.

[0024] An embodiment of the present application also provides a design method for a semiconductor device, the method comprising: obtaining a target number of shift transmission circuits to be arranged, the target number being greater than or equal to 2; connecting multiple interconnection ports between a first die and a second die with a shift sending circuit of the first die and a shift receiving circuit of the second die to form a target number of shift transmission circuits, wherein any two adjacent interconnection ports are located in different shift transmission circuits, wherein the shift sending circuit comprises multiple signal input terminals and multiple signal output terminals, a signal inputted by the i-th signal input terminal of the shift sending circuit is configured to be outputted through the i-th signal output terminal or the i+1-th signal output terminal of the shift receiving circuit, the shift receiving circuit comprises multiple signal input terminals and multiple signal output terminals, the i-th signal output terminal of the shift receiving circuit is configured to output a signal inputted by the i-th signal input terminal or the i+1-th signal input terminal of the shift receiving circuit, the i-th signal output terminal of the shift sending circuit is connected to the i-th signal input terminal of the shift receiving circuit through the i-th interconnection port, and i is a positive integer.

[0025] In one possible implementation, multiple interconnect ports between a first die and a second die are arranged in multiple rows and columns to form an interconnect port array. The multiple interconnect ports between the first die and the second die are connected to a shifted transmitting circuit of the first die and a shifted receiving circuit of the second die to form a target number of shifted transmission circuits, and any two adjacent interconnect ports are located in different shifted transmission circuits. The method includes: dividing the interconnect port array into multiple interconnect port groups along a diagonal direction of the interconnect port array, wherein the interconnect ports in each interconnect port group are connected in parallel; and connecting the multiple interconnect port groups spaced apart by j groups to the same shift transmission circuit, where j = k-1, and k is the target number of shifted transmission circuits to be arranged.

[0026] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions, and when the computer instructions are executed, implements the steps of the method provided in the third aspect and any implementation thereof.

[0027] In a fifth aspect, an embodiment of the present application further provides a computer program product, which, when running on a processor, enables the processor to execute the steps of the method provided in the third aspect and any implementation thereof.

[0028] In a sixth aspect, an embodiment of the present application further provides a chip, the chip comprising a substrate and a semiconductor device as provided in the first aspect and any implementation method, wherein the semiconductor device is disposed on the substrate.

[0029] In the seventh aspect, an embodiment of the present application further provides an electronic device, which includes a circuit board and a chip provided in the sixth aspect and any implementation thereof, wherein the chip is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a 3D chip provided in an embodiment of the present application;

[0031] FIG2 is a schematic diagram of the interconnection port distribution provided in an embodiment of the present application;

[0032] FIG3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0033] FIG4 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0034] FIG5 is a schematic diagram of interconnection port repair based on signal selection according to an embodiment of the present application;

[0035] FIG6 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0036] FIG7 is a schematic diagram of interconnection port repair based on signal shifting according to an embodiment of the present application;

[0037] FIG8 is a schematic diagram of a signal shift repair solution provided in an embodiment of the present application;

[0038] FIG9 is a schematic diagram of another signal shift repair solution provided in an embodiment of the present application;

[0039] FIG10 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0040] FIG11 is a schematic diagram of another interconnection port repair method based on signal shifting according to an embodiment of the present application;

[0041] FIG12 is a schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0042] FIG13 is a schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0043] FIG14 is a schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0044] FIG15 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0045] FIG16 is a schematic diagram of an interconnection port distribution provided in an embodiment of the present application;

[0046] FIG17 is a schematic diagram of the layout of a shift transmission circuit provided in an embodiment of the present application;

[0047] FIG18 is a partial schematic diagram of the shift transmission circuit layout shown in FIG17;

[0048] FIG19 is a schematic diagram of the layout of another shift transmission circuit provided in an embodiment of the present application;

[0049] FIG20 is a schematic flow chart of a method for designing a semiconductor device according to an embodiment of the present application;

[0050] FIG21 is a schematic diagram of grouping interconnection ports provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to implement and use the present description and technology and do not limit the scope of this application. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art.

[0052] Various circuits or other components may be described or referred to as being "configured to" or "configured to" perform one or more tasks. In this case, "configured to" or "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the term "configured to" include hardware, such as circuitry that performs an operation, etc.

[0053] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" may refer to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B may represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c may represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c may be single or multiple.

[0054] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0055] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0056] The integrated circuit industry has been experiencing rapid growth, driven by Moore's Law, which states that the number of transistors that can be accommodated on an integrated circuit doubles approximately every 18 to 24 months. However, as Moore's Law continues to grow, the number of devices and transistors increases, while their sizes shrink. This leads to increasing leakage currents caused by the electron tunneling effect. From this perspective, transistor size cannot be further reduced after reaching a certain size. Therefore, Moore's Law has its limits and will not continue indefinitely.

[0057] More than Moore is a new development theory. When the size of transistors or chips is reduced to a certain extent, more functions can be integrated into the same chip or the same package through integrated stacking packaging technology, including packaging storage and computing together, as well as integrating antennas, sensors, etc.

[0058] In recent years, 2.5D or three-dimensional (3D) chips have become a key technology route for the industry to achieve "more than Moore". This type of chip interconnects multiple bare chips (dies) through passive interconnect devices, or stacks multiple active chips vertically in 3D. People generally refer to them as core particles (chiplets). For example, in conjunction with Figure 1, taking a 3D chip as an example, a 3D chip can stack multiple homogeneous or heterogeneous wafers or circuit modules in the vertical direction, and use interconnect ports (or interconnect media) such as micro bumps, hybrid bonding, and through silicon vias (TSVs) to achieve signal interconnection between bare chips. In conjunction with Figure 2, Figure 2 shows a schematic diagram of the distribution of multiple interconnect ports. Multiple interconnect ports between bare chips can be arranged in a matrix with multiple rows and columns. These interconnect ports are characterized by high density and small spacing to meet the needs of increasing the number of interconnects and bandwidth.

[0059] As a simplified example, please refer to Figure 3, which shows a structural schematic diagram of a semiconductor device, including a first bare chip die1 and a second bare chip die2. The first bare chip die1 and the second bare chip die2 are coupled through multiple interconnection ports (for example, interconnection ports S1 to interconnection ports S4). The first bare chip and the second bare chip can transmit signals through the interconnection ports, for example, signal I1 is transmitted through interconnection port S1, signal I2 is transmitted through interconnection port S2, signal I3 is transmitted through interconnection port S3, and signal I4 is transmitted through interconnection port S4.

[0060] Current 3D stacked chips typically have a large number of interconnects, ranging from hundreds to thousands or even tens of thousands. Testing and repairing these interfaces are crucial for quality, yield, and cost. As interconnect density increases and spacing decreases, the probability of short circuits and bridges between interconnects increases. Interconnect failures can affect signal transmission between die, impacting product quality.

[0061] To resolve interconnect failures, such as short circuits and bridge faults, different manufacturers or standards have proposed different solutions, such as interconnect repair solutions based on signal switching or signal shifting.

[0062] Interconnect port repair solutions based on signal switching can use redundant interconnect ports. For example, if a group of interconnect ports has a redundant port, the redundant port can replace the failed port in transmitting signals. In practical applications, a multiplexer can be used to switch the signal selection of the failed port to the redundant port for transmission, thus completing the fault repair.

[0063] In combination with Figure 4, Figure 4 shows a structural schematic diagram of another semiconductor device provided by an embodiment of the present application, the semiconductor device includes a first bare die die1 and a second bare die die2, the first bare die die1 includes multiple signal sending nodes, such as signal sending node tx1, signal sending node tx2, signal sending node tx3 and signal sending node tx4, the second bare die die2 includes multiple signal receiving nodes, such as signal receiving node rx1, signal receiving node rx2, signal receiving node rx3 and signal receiving node rx4, the multiple signal sending nodes of the first bare die die1 correspond one-to-one to the multiple signal receiving nodes of the second bare die die2, for example, the signal sending node tx1 is used to send signal I1 to the corresponding signal receiving node rx1, the signal sending node tx2 is used to send signal I2 to the corresponding signal receiving node rx2, the signal sending node tx3 is used to send signal I3 to the corresponding signal receiving node rx3, and the signal sending node tx4 is used to send signal I4 to the corresponding signal receiving node rx4. The node here may be an actual node in the first die 1 or the second die 2 , or may be a junction point of related electrical connections in the first die 1 or the second die 2 .

[0064] The first die 1 and the second die 2 can be stacked and coupled to each other via a plurality of interconnects, such as interconnect S1, interconnect S2, interconnect S3, interconnect S4, and interconnect S5. Interconnect S1 can be used to transmit signal I1, interconnect S2 can be used to transmit signal I2, interconnect S3 can be used to transmit signal I3, and interconnect S4 can be used to transmit signal I4. Interconnect S5 is a redundant interconnect and can be used to replace a failed interconnect in the event of a fault.

[0065] Continuing with FIG4 , the semiconductor device further includes a plurality of output-side multiplexers: MUX1 to MUX4, and an input-side multiplexer: MUX5. To implement interconnection port S5 for repairing a faulty interconnection port among interconnection ports S1 to S4, the output end of MUX5 is connected to the input end of interconnection port S5, and the four input ends of MUX5 are connected one-to-one with the four signal sending nodes (signal sending node tx1, signal sending node tx2, signal sending node tx3, and signal sending node tx4) of the first bare die die1. Therefore, MUX5 can select any one of signals I1 to I4 to be transmitted through interconnection port S5 according to a control signal.

[0066] Each signal receiving node of the second bare chip di2 is correspondingly provided with an output-side multiplexer. The output-side multiplexer is a 2-to-1 multiplexer, which can be used to select a signal transmitted from the interconnection port corresponding to the signal receiving node or a signal transmitted from a redundant interconnection port.

[0067] For example, the signal receiving node rx1 is connected to the output end of MUX1, the first input end of MUX1 is connected to the output end of interconnection port S1, and the second input end of MUX1 is connected to the output end of interconnection port S5; the signal receiving node rx2 is connected to the output end of MUX2, the first input end of MUX2 is connected to the output end of interconnection port S2, and the second input end of MUX2 is connected to the output end of interconnection port S5; and so on, the signal receiving node rx3 is connected to interconnection port S3 and interconnection port S5 through MUX3, and the signal receiving node rx4 is connected to interconnection port S4 and interconnection port S5 through MUX4.

[0068] The redundant interconnection port S5 and MUX1 to MUX5 can be used to implement interface repair based on signal switching. When any of the interconnection ports S1 to S4 fails and cannot transmit signals normally, MUX5 can select interconnection port S5 to transmit the signal corresponding to the failed interconnection port, and the multiplexer on the output side corresponding to the failed interconnection port selects to output the signal transmitted by interconnection port S5 to the signal receiving node corresponding to the failed interconnection port, completing the interface repair.

[0069] For example, in conjunction with Figure 5, when the interconnection port S2 fails, based on the signal switching method, MUX5 chooses to connect the signal sending node tx2 corresponding to the interconnection port S2 to the input end of the interconnection port S5, and MUX2 chooses to connect the output end of the interconnection port S5 to the signal receiving node rx2. In this way, the signal I2 output by the signal sending node tx2 can be transmitted to the signal receiving node rx2 through the interconnection port S5.

[0070] This shows that when a faulty interconnection port occurs, MUX1-MUX5 need to adjust the selection state or selection position so that interconnection port S5 can be used to transmit signals instead of the faulty interconnection port. The location of the faulty interconnection port in this group of interconnections can be recorded by a set of binary counting registers, which can be encoded in binary and are relatively few in number. However, since the input-side multiplexer needs to be able to connect the signal sending node corresponding to any faulty interface to the interconnection port, a multiple-to-one multiplexer is required. The number of input terminals of the multiplexer matches the number of signal sending nodes. This results in a more complex structure of the multiplexer, a larger number of logic gates, a larger occupied area, and a larger signal delay.

[0071] In addition, for some interconnection ports that are far away from the interconnection port S5, for example, if the interconnection port S1 fails and the signal I1 is switched to be transmitted through the interconnection port S5, the distance between the signal sending node tx1 and the interconnection port S5 is relatively long, and the transmission of the signal I1 through the interconnection port S5 will cause a large signal delay, thereby affecting the signal transmission rate.

[0072] The interconnect repair solution based on signal shifting can avoid problems such as signal delay. The interconnect repair solution based on signal shifting can set up redundant interconnects on the left or right side of a group of interconnects. When any interconnect fails, the entire signal can be shifted to the side where the redundant interconnect is located to complete the repair.

[0073] As shown in Figure 6, Figure 6 shows a schematic diagram of a semiconductor device, which includes a first bare die die1 and a second bare die die2. The first bare die die1 includes multiple signal sending nodes, such as signal sending node tx1, signal sending node tx2, signal sending node tx3 and signal sending node tx4, and the second bare die die2 includes multiple signal receiving nodes, such as signal receiving node rx1, signal receiving node rx2, signal receiving node rx3 and signal receiving node rx4. The multiple signal sending nodes of the first bare die die1 correspond one-to-one to the multiple signal receiving nodes of the second bare die die2. For example, the signal sending node tx1 is used to send a signal I1 to the corresponding signal receiving node rx1, the signal sending node tx2 is used to send a signal I2 to the corresponding signal receiving node rx2, the signal sending node tx3 is used to send a signal I3 to the corresponding signal receiving node rx3, and the signal sending node tx4 is used to send a signal I4 to the corresponding signal receiving node rx4. The first die die1 and the second die die2 are coupled via a plurality of interconnection ports, namely, interconnection port S1, interconnection port S2, interconnection port S3, interconnection port S4, and interconnection port S5. Interconnection port S1 can be used to transmit signal I1, interconnection port S2 can be used to transmit signal I2, interconnection port S3 can be used to transmit signal I3, interconnection port S4 can be used to transmit signal I4, and interconnection port S5 is a redundant interconnection port.

[0074] An interconnect repair solution based on signal shifting means that the signal output by any signal-sending node can be transmitted through the interconnect corresponding to that node, or it can be shifted and transmitted through another adjacent interconnect. For example, signal I1 can be transmitted through interconnect S1, or it can be shifted right and transmitted through interconnect S2, which is adjacent to interconnect S1. Signal I2 can be transmitted through interconnect S2, or it can be shifted right and transmitted through interconnect S3. Signal I3 can be transmitted through interconnect S3, or it can be shifted right and transmitted through interconnect S4. Signal I4 can be transmitted through interconnect S4, or it can be shifted right and transmitted through redundant interconnect S5. In this case, the structure formed by connecting interconnects S1 to S4 and the redundant interconnect S5 is called a shift repair chain or a shift transmission circuit.

[0075] FIG6 shows four interconnect ports (interconnect ports S1 to S4) and one redundant interconnect port (interconnect port S5) for transmitting four signals. Interconnect ports S1 to S5 are connected through multiple multiplexers on the input side and multiple multiplexers on the output side to form a shift repair chain. In the embodiment of the present application, a unidirectional shift repair chain is used as an example. The multiplexer on the input side is a 2-to-1 multiplexer, and the number of multiplexers on the input side is two less than the number of interconnection ports. Alternatively, it can be considered that when one redundant interconnection port exists among the interconnection ports, the number of multiplexers on the input side is one less than the number of signals to be transmitted (i.e., the number of signal sending nodes or signal receiving nodes). For example, corresponding to four signal sending nodes, three multiplexers: MUX1 to MUX3 are provided on the input side. The multiplexer on the output side is also a 2-to-1 multiplexer, and the number of multiplexers on the output side is one less than the number of interconnection ports. Alternatively, it can be considered that the number of multiplexers on the output side is the same as the number of signals to be transmitted (i.e., the number of signal sending nodes or signal receiving nodes). For example, corresponding to four signal receiving nodes (or signal sending nodes), four multiplexers: MUX4 to MUX7 are provided on the output side.

[0076] The signal sending node tx1 is connected to the input end of the interconnection port S1, and the signal sending node tx1 is also connected to the first input end of MUX1, and the output end of MUX1 is connected to the input end of the interconnection port S2; the signal sending node tx2 is connected to the second input end of MUX1, and the signal sending node tx2 is also connected to the first input end of MUX2, and the output end of MUX2 is connected to the input end of the interconnection port S3; the signal sending node tx3 is connected to the second input end of MUX2, and the signal sending node tx3 is also connected to the first input end of MUX3, and the output end of MUX3 is connected to the input end of the interconnection port S4; the signal sending node tx4 is connected to the second input end of MUX3, and the signal sending node tx4 is also connected to the input end of the interconnection port S5.

[0077] A first input terminal of MUX4 is connected to the output terminal of the interconnection port S1, a second input terminal of MUX4 is connected to the output terminal of the interconnection port S1, and the output terminal of MUX4 is connected to the signal receiving node rx1; a first input terminal of MUX5 is connected to the output terminal of the interconnection port S2, a second input terminal of MUX5 is connected to the output terminal of the interconnection port S2, and the output terminal of MUX5 is connected to the signal receiving node rx2; a first input terminal of MUX6 is connected to the output terminal of the interconnection port S3, a second input terminal of MUX6 is connected to the output terminal of the interconnection port S3, and the output terminal of MUX6 is connected to the signal receiving node rx3; a first input terminal of MUX7 is connected to the output terminal of the interconnection port S4, a second input terminal of MUX7 is connected to the output terminal of the interconnection port S5, and the output terminal of MUX7 is connected to the signal receiving node rx4.

[0078] The multiplexers on the input and output sides can be used to select which interconnection port is used to transmit the signal sent by the signal sending node to the signal receiving node. For example, when MUX1 selects to connect the first input terminal and the output terminal according to the control signal, the signal I1 is transmitted through the interconnection port S1. At this time, MUX4 needs to connect the interconnection port S1 to the signal receiving node rx1; when MUX1 selects to connect the second input terminal and the output terminal according to the control signal, the signal I1 is shifted to the right and transmitted through the interconnection port S2. At this time, MUX4 needs to connect the interconnection port S2 to the signal receiving node rx1.

[0079] In the embodiment of the present application, the redundant interconnection port is located at the right end of the shift repair chain. When any interconnection port fails, the signals of the failed interconnection port and the interconnection port to its right can be shifted right by one position to ensure normal signal transmission and complete the repair.

[0080] For example, referring to FIG. 7 , when interconnection port S3 fails, the transmission mode of interconnection ports S1 and S2 to the left of interconnection port S3 can be maintained unchanged, that is, signal I1 is transmitted by interconnection port S1, and signal I2 is transmitted by interconnection port S2; the signals of interconnection ports S3 and S4 are shifted right by one position as a whole, so that signal I4 is shifted right and transmitted by interconnection port S5, and signal I3 is shifted right and transmitted by interconnection port S4, thereby repairing the interconnection ports.

[0081] For signal shift repair solutions, each signal can be assigned a register that records the interconnect port from which the signal is transmitted. This makes it more suitable for processing shift selection logic, so the number of combinational logic gates in this structure is relatively small. In addition, because each signal can be shifted and transmitted through adjacent interconnect ports in the shift repair solution, the spacing between adjacent interconnect ports is smaller (compared to the distance between redundant interconnect ports in Figure 4), and the signal delay before and after the shift is also smaller, making the shift-based signal repair solution more widely applicable.

[0082] In the above example, only one redundant interconnection port is provided, so the signal can only be shifted in one direction to repair a faulty interconnection port. When stronger repair capabilities are required, multiple shift repair chains or shift transmission circuits can be provided. FIG8 shows another repair solution, in which all interconnection ports are divided into two groups to form a shift repair chain structure. Each group of interconnection ports includes a redundant interconnection port. If there is any faulty interconnection port in each group, it can be repaired by shifting it.

[0083] As shown in FIG8 , FIG8 is a schematic diagram of a signal repair. FIG8 shows multiple interconnects, two of which are redundant interconnects, and the remaining interconnects are working interconnects. The redundant interconnects and the working interconnects have the same structure. The difference between the redundant interconnects and the working interconnects is that when the working interconnect is not faulty, the redundant interconnect will not be used to transmit data; when the working interconnect fails, the redundant interconnect will be used to transmit data. The multiple interconnects are divided into two groups. As shown in FIG8 , the multiple interconnects in each group form a shift repair chain. Each shift repair chain includes a redundant interconnect. The connection method of the shift repair chain has been described in detail in the previous example and will not be repeated here.

[0084] In the repair scheme shown in Figure 8, if any interconnect port within each group experiences a fault, it can be repaired by shifting it. This scheme has the advantage of a simple structure, requiring only a single 2-to-1 MUX multiplexer to be added to both the input and output ends of the interconnect port, resulting in relatively low latency and minimal impact on signal transmission rates. However, this structure also has a disadvantage: if a bridging fault occurs within any group, it cannot be repaired. A bridging fault occurs when two interconnect ports are connected together. Bridging faults often occur between adjacent interconnect ports that are relatively close to each other. For example, in a matrix of multiple interconnect ports arranged in rows and columns, adjacent interconnect ports in the same row or column are more likely to experience a bridging fault. However, interconnect ports located diagonally are farther apart than adjacent interconnect ports in the same row or column, making them less likely to experience a bridging fault.

[0085] In the repair scheme shown in Figure 8, a bridging fault within any group would render both interconnects inoperable. Since there is only one redundant interconnect within the group, only the faulty interconnect can be repaired, not both bridged interconnects. However, as interconnect density in 3D ICs continues to increase and the spacing between interconnects continues to decrease, the probability of bridging faults between interconnects increases, significantly reducing the effectiveness of this repair scheme.

[0086] An embodiment of the present application also provides another shift repair solution, in which two redundant interconnection ports are set in the shift repair chain, as shown in Figure 9. Multiple working interconnection ports and redundant interconnection ports form a bidirectional shift repair chain or shift transmission circuit, and signals can be shifted bidirectionally. For example, in addition to being transmitted through the interconnection port corresponding to the signal, a certain signal can also be shifted to the left or right. This bidirectional shift solution can be used to repair bridging faults.

[0087] Refer to Figure 10, which shows a structural schematic diagram of a semiconductor device. The semiconductor device includes a first bare die die1 and a second bare die die2. The first bare die die1 includes multiple signal sending nodes, such as signal sending node tx1, signal sending node tx2, signal sending node tx3, signal sending node tx4 and signal sending node tx5. The second bare die die2 includes multiple signal receiving nodes, such as signal receiving node rx1, signal receiving node rx2, signal receiving node rx3, signal receiving node rx4 and signal receiving node rx5. The multiple signal sending nodes of the first bare die die1 correspond one-to-one to the multiple signal receiving nodes of the second bare die die2. For example, the signal sending node tx1 is used to send a signal I1 to the corresponding signal receiving node rx1, the signal sending node tx2 is used to send a signal I2 to the corresponding signal receiving node rx2... and the signal sending node tx5 is used to send a signal I5 to the corresponding signal receiving node rx5.

[0088] The first bare chip die1 and the second bare chip die2 are coupled through multiple interconnection ports, such as interconnection port S1, interconnection port S2, interconnection port S3, interconnection port S4, interconnection port S5, interconnection port S6, and interconnection port S7. Among them, interconnection port S1 can be used to transmit signal I1, interconnection port S2 can be used to transmit signal I2, interconnection port S3 can be used to transmit signal I3, interconnection port S4 can be used to transmit signal I4, and interconnection port S5 can be used to transmit signal I5. Interconnection ports S1 to S5 can be called working interconnection ports; interconnection port S6 and interconnection port S7 are redundant interconnection ports, among which interconnection port S6 is set on the right side of the working interconnection port, and interconnection port S7 is set on the left side of the working interconnection port.

[0089] Interconnection ports S1 to S7 are connected through multiple multiplexers on the input and output sides to form a shift repair chain. A redundant interconnection port is provided at each end of the shift repair chain. The signal sent by each signal sending node can be sent by the interconnection port corresponding to the signal sending node, or can be sent by the interconnection port to the left of the interconnection port, or can be sent by the interconnection port to the right of the interconnection port.

[0090] The input side is provided with multiple multiplexers, such as MUX1 to MUX5, where MUX1 and MUX5 are multiplexers at both ends of the shift repair chain, and both are 2-to-1 multiplexers, and MUX2 to MUX4 are 3-to-1 multiplexers. The signal sending node tx1 is connected to the input end of the interconnection port S7, and the signal sending node tx1 is also connected to the first input end of MUX1, and the signal sending node tx1 is also connected to the first input end of MUX2; the signal sending node tx2 is connected to the second input end of MUX1, and the signal sending node tx2 is also connected to the second input end of MUX2, and the signal sending node tx2 is also connected to the first input end of MUX3; the signal sending node tx3 is connected to the third selection end of MUX2, and the signal sending node tx3 is also connected to the second input end of MUX3, and the signal sending node tx3 is also connected to the first input end of MUX4; the signal sending node tx4 is connected to the third selection end of MUX3, The signal sending node tx4 is also connected to the second input terminal of MUX4, and the signal sending node tx4 is also connected to the first input terminal of MUX5; the signal sending node tx5 is connected to the third selection terminal of MUX4, and the signal sending node tx5 is also connected to the second input terminal of MUX5, and the signal sending node tx5 is also connected to the input terminal of the redundant interconnection port S6; the output terminal of MUX1 is connected to the input terminal of the interconnection port S1, the output terminal of MUX2 is connected to the input terminal of the interconnection port S2, the output terminal of MUX3 is connected to the input terminal of the interconnection port S3, the output terminal of MUX4 is connected to the input terminal of the interconnection port S4, and the output terminal of MUX5 is connected to the input terminal of the interconnection port S5.

[0091] The output side is also provided with a plurality of multiplexers, such as MUX6 to MUX10, each of which is a 3-to-1 multiplexer. The first input end of MUX6 is connected to the output end of the redundant interconnection port S7, the second input end of MUX6 is connected to the output end of the interconnection port S1, the third selection end of MUX6 is connected to the output end of the interconnection port S2, and the output end of MUX6 is connected to the signal receiving node rx1; the first input end of MUX7 is connected to the output end of the interconnection port S1, the second input end of MUX7 is connected to the output end of the interconnection port S2, and the third selection end of MUX7 is connected to the output end of the interconnection port S3. The output end of MUX7 is connected to the signal receiving node rx1; the first input end of MUX8 is connected to the output end of the interconnection port S2, the second input end of MUX8 is connected to the output end of the interconnection port S3, the third selection end of MUX8 is connected to the output end of the interconnection port S4, and the output end of MUX8 is connected to the signal receiving node rx2... The first input end of MUX10 is connected to the output end of the interconnection port S4, the second input end of MUX10 is connected to the output end of the interconnection port S5, the third selection end of MUX10 is connected to the output end of the redundant interconnection port S6, and the output end of MUX10 is connected to the signal receiving node rx5.

[0092] The multiplexers on the input and output sides can be used to select which interconnection port to transmit the signal sent by the signal sending node to the signal receiving node. For example, when MUX1 selects to connect the first input terminal and the output terminal according to the control signal, the signal I1 is transmitted through the interconnection port S1. At this time, MUX6 needs to connect the interconnection port S1 to the signal receiving node rx1; when MUX1 selects to connect the second input terminal and the output terminal according to the control signal, the signal I1 is shifted to the right and transmitted through the interconnection port S2. At this time, MUX6 needs to connect the interconnection port S2 to the signal receiving node rx1.

[0093] When a bridging fault occurs between any two interconnection ports, for example, referring to FIG11 , when interconnection ports S3 and S4 fail, signal I3 corresponding to interconnection port S3 is shifted to the left and transmitted by interconnection port S2, signal I2 corresponding to interconnection port S2 is shifted to the left and transmitted by interconnection port S1, and signal I1 corresponding to interconnection port S1 is shifted to the left and transmitted by redundant interconnection port S7; signal I4 corresponding to interconnection port S4 is shifted to the right and transmitted by interconnection port S5, and signal I5 corresponding to interconnection port S5 is transmitted by redundant interconnection port S6. By providing two redundant interconnection ports S6 and S7, bidirectional shifting is possible when a bridging fault occurs, with one portion of the signal shifted to the left and the other portion of the signal shifted to the right, thereby completing the repair of the bridging fault.

[0094] The above solution can repair bridging faults between interconnects, but it requires multiple 3-to-1 multiplexers on the input side of the interconnect to select one of the three signal-transmitting nodes to conduct and transmit the signal output by that signal-transmitting node. Each interconnect output is equipped with a 3-to-1 multiplexer to select one of the three signals transmitted from the interconnect to be output to the signal-receiving node. The 3-to-1 multiplexer has a greater delay, so this solution has a relatively greater impact on signal transmission latency. For high-speed cross-die transmission applications, this can affect the signal transmission rate.

[0095] As can be seen from the foregoing, constructing a shift transmission circuit based on a 3-to-1 multiplexer can repair interconnection port bridging faults, but the 3-to-1 multiplexer has a large delay, which affects the signal transmission rate. The shift transmission circuit constructed based on a 2-to-1 multiplexer shown in Figure 6 has a small delay, but cannot be repaired when a bridging fault occurs. To improve the above problems, the embodiments of the present application provide an interconnection port repair solution that can meet the requirements of implementing a repair solution using a 2-to-1 multiplexer, avoiding increased signal delay and affecting the transmission rate, and can also meet the requirements of repairing conventional open circuit, broken circuit, delay faults, and bridging faults.

[0096] An embodiment of the present application provides a semiconductor device including a first die, a second die, and a plurality of interconnects, wherein the plurality of interconnects couple the first die to the second die. The first die includes a plurality of signal transmitting nodes, and the second die includes a plurality of signal receiving nodes. The signal transmitting nodes of the first die can transmit signals to the signal receiving nodes of the second die via the interconnects.

[0097] The interconnection ports in semiconductor devices may have faults such as open circuit and bridge. In order to repair the faults of the interconnection ports, the first die includes multiple shift transmission circuits, and the second die includes multiple shift receiving circuits. The multiple shift transmission circuits, the multiple shift receiving circuits and the multiple interconnection ports between the first die and the second die constitute multiple shift transmission circuits, or can also be called multiple shift repair chains. In consideration of signal delay, the shift transmission circuit can be a unidirectional shift transmission circuit. For example, n signal transmission nodes are coupled to n signal receiving nodes through the shift transmission circuit. The shift transmission circuit includes n +1 interconnection port, for example, the signal of the i-th signal sending node can be transmitted through the i-th interconnection port or shifted to the i+1-th interconnection port. For example, under normal circumstances, the signal of the i-th signal sending node is sent through the i-th interconnection port. If the i-th interconnection port fails, it can be shifted to be sent through the i+1-th interconnection port, and the signal of the i+1-th signal sending node is transmitted through the i+2-th interconnection port. Similarly, the signal of the n-th signal sending node is transmitted through the n+1-th interconnection port. In this way, when any interconnection port fails, it can be repaired by signal shifting. The i-th signal sending node, i-th signal receiving node, i-th interconnection port, etc. here are logical concepts and are not limitations on the positions of signal sending nodes, signal receiving nodes, or interconnection ports.

[0098] A semiconductor device includes multiple interconnects, and any two adjacent interconnects are located in different shift transmission circuits. For example, in conjunction with FIG12 , FIG12 shows a schematic diagram of the arrangement of some interconnects (interconnects S1 to S24) of a semiconductor device. Interconnects S1 to S24 can be arranged in a matrix of multiple rows and columns. Interconnects S1 to S24 can be located in two shift transmission circuits, so that any two adjacent interconnects are located in different shift transmission circuits. The arrows in the figure indicate the direction of signal shifting. In this way, when a bridging fault occurs in adjacent interconnects, the bridging fault of the two interconnects can be converted into a fault of a single interconnect in the two shift transmission circuits. Shift repair of the single interconnect can be implemented in the two shift transmission circuits, thereby achieving bridging fault repair of the two interconnects.

[0099] The first die and the second die may each reserve multiple interconnection ports. For example, the first die may be provided with multiple first interconnection ports, and the second die may be provided with multiple second interconnection ports. The number and position of the multiple first interconnection ports match the number and position of the multiple second interconnection ports. Moreover, the first interconnection ports and the second interconnection ports may be connected one-to-one through the interconnection ports to form a shift transmission circuit.

[0100] For example, referring to FIG13 , FIG13 shows a schematic diagram of another semiconductor device, which includes a plurality of shift transmission circuits. For ease of explanation, FIG13 shows only a schematic diagram of one of the shift transmission circuits.

[0101] The first die 110 includes a plurality of signal transmission nodes (e.g., signal transmission nodes tx1 through txn), a shift transmission circuit 111, and a plurality of first interconnect ports (e.g., first interconnect ports PA1 through PAn+1). The shift transmission circuit 111 includes a plurality of signal input terminals (e.g., signal input terminals inA1 through inAn) and a plurality of signal output terminals (e.g., signal output terminals outA1 through outAn+1). A signal input to the i-th signal input terminal is configured to be output through the i-th signal output terminal or the i+1-th signal output terminal, where i is a positive integer. For example, a signal input to the signal output terminal outA1 can be output through the signal output terminal outA1 or the signal output terminal outA2. The multiple signal input terminals of the shifted transmission circuit 111 are each connected to a signal transmission node, and the multiple signal output terminals of the shifted transmission circuit 111 are each connected to a first interconnect port. For example, the signal input terminal inA1 is connected to the signal transmission node tx1, the signal input terminal inAn is connected to the signal transmission node txn, the signal output terminal outA1 is connected to the first interconnect port PA1, the signal output terminal outAn is connected to the first interconnect port PAn, and the signal output terminal outAn+1 is connected to the first interconnect port PAn+1. Figure 13 shows only one shifted transmission circuit of the first die 110. The first die 110 includes multiple shifted transmission circuits. Any two adjacent first interconnect ports of the first die 110 are connected to different shifted transmission circuits.

[0102] The second bare die 120 includes multiple signal receiving nodes (e.g., signal receiving nodes rx1 to rxn), a shift receiving circuit 121, and multiple second interconnection ports (e.g., second interconnection port PB1 to second interconnection port PBn+1). The shift receiving circuit 121 includes multiple signal input terminals (e.g., signal input terminal inB1 to signal input terminal inBn+1) and multiple signal output terminals (e.g., signal output terminal outB1 to signal output terminal outBn). The i-th signal output terminal of the shift receiving circuit 121 is configured to output the signal input by the i-th signal input terminal or the i+1-th signal input terminal. For example, the signal output terminal outB1 of the shift receiving circuit 121 can output the signal of the signal input terminal inB1 or the signal input terminal inB2 of the shift receiving circuit 121, and the signal output terminal outB2 of the shift receiving circuit 121 can output the signal of the signal input terminal inB2 or the signal input terminal inB3 of the shift receiving circuit 121. The multiple signal input terminals of shifted receiving circuit 121 are each connected to a second interconnect port, and the multiple signal output terminals of shifted receiving circuit 121 are each connected to a signal receiving node. For example, signal input terminal inB1 of shifted receiving circuit 121 is connected to second interconnect port PB1 of second die 120, signal input terminal inBn is connected to second interconnect port PBn, and signal input terminal inBn+1 is connected to second interconnect port PBn+1. Figure 13 shows only one shifted receiving circuit of second die 120. Second die 120 includes multiple shifted receiving circuits. Any two adjacent second interconnect ports of second die 120 are connected to different shifted receiving circuits.

[0103] The shifted transmitting circuit 111 of the first bare die 110 includes multiple signal output terminals, each of which is connected to a first interconnection port; the shifted receiving circuit 121 of the second bare die 120 includes multiple signal input terminals, each of which is connected to a second interconnection port. Each first interconnection port can be connected to a second interconnection port in a one-to-one correspondence through an interconnection port. In this way, the shifted transmitting circuit, the interconnection port, and the shifted receiving circuit can constitute a shifted transmission circuit.

[0104] For example, the i-th signal output terminal of the shifted transmitting circuit is connected to the i-th signal input terminal of the shifted receiving circuit through the i-th interconnection port. Specifically, the first interconnection port to which the i-th signal output terminal of the shifted transmitting circuit is connected is connected to the second interconnection port to which the i-th signal input terminal of the shifted receiving circuit is connected through the i-th interconnection port.

[0105] During the production process, the first die and the second die can be prepared first, and then the first die and the second die are stacked, and the first die and the second die are coupled using an interconnection port; or the first die and the second die can be prepared at the same time, and multiple interconnections are formed while preparing the first die and the second die to couple the first die and the second die.

[0106] In the above example, a shift transmission circuit of a semiconductor device is taken as an example to introduce a method in which a first bare chip and a second bare chip are coupled through multiple interconnection ports to form a shift transmission circuit. The shift transmission circuit provided in the embodiment of the present application can realize the repair of a single faulty interconnection port through signal shift transmission. In actual applications, the semiconductor device includes multiple shift transmission circuits, and any two adjacent interconnection ports of the semiconductor device are located in different shift transmission circuits, that is, the shift sending circuits connected to any two adjacent interconnection ports of the semiconductor device are different, and the shift receiving circuits connected to the two adjacent interconnection ports are different. When a bridging fault occurs between two adjacent interconnection ports, the bridging fault can be converted into a fault of a single interconnection port in two different shift transmission circuits, and repair is achieved through signal shift transmission.

[0107] Two adjacent interconnecting ports refer to two interconnecting ports (for example, a first interconnecting port and a second interconnecting port) whose distance is less than or equal to the distance between one of the interconnecting ports and any other interconnecting port. For example, the distance between the adjacent first interconnecting port and the second interconnecting port is less than or equal to the distance between the first interconnecting port and any third interconnecting port, or the distance between the first interconnecting port and the second interconnecting port is less than or equal to the distance between the second interconnecting port and any third interconnecting port.

[0108] The probability of a bridging fault occurring between two interconnection ports that are close to each other is higher. Therefore, it is only necessary to ensure that any two adjacent interconnection ports are located in different shift transmission circuits. When a bridging fault occurs between these two adjacent interconnection ports, the shift transmission circuit where the faulty interconnection port is located can be used to shift and repair the faulty interconnection port.

[0109] The shift sending circuit and the corresponding shift receiving circuit are connected through an interconnection port to form a shift transmission circuit, which can transmit the signal of the signal sending node to the signal receiving node. The principles of the shift sending circuit of the first bare chip and the shift receiving circuit of the second bare chip are similar. The embodiment of the present application is first introduced by taking the shift sending circuit of the first bare chip as an example.

[0110] Exemplarily, in conjunction with FIG14 , the shift transmission circuit 111 includes n signal input terminals (e.g., signal input terminal inA1 to signal input terminal inAn), n+1 signal output terminals (e.g., signal output terminal outA1 to signal output terminal outAn+1), and n-1 multiplexers (e.g., IMUX1 to IMUXn-1). The multiplexer is a two-select-one multiplexer. The multiplexer includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the m-th multiplexer among the n-1 multiplexers is connected to the m-th signal input terminal of the shift transmission circuit, the second input terminal of the m-th multiplexer among the n-1 multiplexers is connected to the m+1-th signal input terminal of the shift transmission circuit, and the n-1 multiplexers are connected to the m-th multiplexer among the n-1 multiplexers. The output terminals of the m multiplexers are connected to the m+1th signal output terminal of the shift sending circuit, where m and n are positive integers, m≤n-1, and the first signal input terminal of the shift sending circuit is also connected to the first signal output terminal of the shift sending circuit (for example, the signal input terminal inA1 is connected to the signal output terminal outA1); the nth signal input terminal of the shift sending circuit is also connected to the n+1th signal output terminal of the shift sending circuit (for example, the signal input terminal inAn is connected to the signal output terminal outAn+1). In addition, as introduced in the above example, each signal output terminal of the shift sending circuit 111 is connected to a first interconnection port, that is, each signal output terminal can correspond to an interconnection port, and the n signal input terminals of the shift sending circuit correspond to n+1 interconnection ports.

[0111] The semiconductor device includes multiple shift transmission circuits. Accordingly, the first die includes multiple signal sending nodes and multiple shift sending circuits, and the number of signal input terminals of different shift sending circuits is the same or different. The second die includes multiple signal receiving nodes and multiple shift receiving circuits. The multiple shift receiving circuits of the second die correspond one-to-one to the shift sending circuits of the first die.

[0112] For example, if the shifted transmitting circuit 111 of the first die 110 includes n signal input terminals and n+1 signal output terminals, then the shifted receiving circuit 121 of the second die 120 includes n+1 signal input terminals and n signal output terminals. The n+1 signal input terminals of the shifted receiving circuit 121 correspond one-to-one with the n+1 signal output terminals of the shifted transmitting circuit 111 of the first die 110. In the shifted receiving circuit 121, the i-th signal output terminal is configured to output the signal input by the i-th signal input terminal or the i+1-th signal input terminal, where i is a positive integer. The multiple signal input terminals of the shifted receiving circuit 121 are each connected to a second interconnect port, and the multiple signal output terminals of the shifted receiving circuit 121 are each connected to a signal receiving node. Any two adjacent second interconnect ports of the second die are connected to different shifted receiving circuits.

[0113] The shift receiving circuit 121 also includes n multiplexers (for example, OMUX1 to OMUXn), each multiplexer including a first input terminal, a second input terminal, and an output terminal. In the shift receiving circuit 121, the first input terminal of the mth multiplexer among the n multiplexers of the shift receiving circuit 121 is connected to the mth signal input terminal of the shift receiving circuit 121, the second input terminal of the mth multiplexer among the n multiplexers of the shift receiving circuit 121 is connected to the m+1th signal input terminal of the shift receiving circuit 121, and the output terminal of the mth multiplexer among the n multiplexers of the shift receiving circuit 121 is connected to the mth signal output terminal of the shift receiving circuit 121, where m and n are positive integers and m≤n-1. In addition, as described in the previous example, each signal input terminal of shifted receiving circuit 121 is connected to a second interconnect port. This means that each signal input terminal corresponds to one interconnect port, and the n+1 signal input terminals of shifted receiving circuit 121 correspond to n+1 interconnect ports. Any two adjacent second interconnect ports of the second die are connected to different shifted transmitting circuits. This means that any two adjacent interconnect ports of the semiconductor device are connected to different shifted receiving circuits 121.

[0114] In other words, any two adjacent interconnect ports of the semiconductor device are connected to different shift transmission circuits. Thus, when a bridging fault occurs between any two adjacent interconnect ports, since the two adjacent interconnect ports are connected to different shift transmission circuits, the faulty interconnect ports can be repaired separately through the shift transmission circuits to which they are connected. Moreover, since the shift transmission circuit is a unidirectional repair chain, repair can be achieved by only setting up multiple 2-to-1 multiplexers. Compared with setting up a bidirectional repair chain using a 3-to-1 multiplexer, signal delay can be reduced, thereby minimizing the impact on the signal transmission rate.

[0115] Referring to FIG. 15 , FIG. 15 shows a schematic diagram of a semiconductor device according to an embodiment of the present application. The semiconductor device includes multiple shift transmission circuits, and FIG. 15 illustrates two shift transmission circuits of the semiconductor device. The semiconductor device includes a first die and a second die, which are coupled via multiple interconnects (e.g., interconnects S1 through S24 ). The first die includes multiple signal transmitting nodes (e.g., signal transmitting nodes tx1 through tx22 ), and the second die includes multiple signal receiving nodes (e.g., signal receiving nodes rx1 through rx22 ).

[0116] Exemplarily, interconnection ports S1 to S24 are arranged in sequence, for example, interconnection port S1 is adjacent to interconnection port S2, interconnection port S2 is adjacent to interconnection port S3, ..., interconnection port S23 is adjacent to interconnection port S24.

[0117] Interconnection ports S1, S3, S5...S21, and S23 are connected to the first shift sending circuit of the first die and the first shift receiving circuit of the second die to form a first shift transmission circuit; interconnection ports S2, S4, S6...S22, and S24 are connected to the second shift sending circuit of the first die and the second shift receiving circuit of the second die to form a second shift transmission circuit.

[0118] The method for forming the shift transmission circuit has been described in detail in the previous example and will not be repeated here. The following describes the principle of repairing a bridging fault in a semiconductor device according to an embodiment of the present application, in conjunction with FIG15 . Since a bridging fault is more likely to occur between two adjacent interconnects, the example of a bridging fault occurring between interconnects S18 and S19 is used for this description.

[0119] For the interconnection port S18, the signal sending node tx18 cannot transmit signals to the signal receiving node rx18 through the interconnection port S18. The multiplexer in the second shift transmission circuit connects the signal sending node tx18, the signal receiving node rx18, and the interconnection port S20 in the second shift transmission circuit, which is shifted right by one position of the interconnection port S18, and connects the signal sending node tx20, the signal receiving node rx20, and the interconnection port S22 in the second shift transmission circuit, which is shifted right by one position of the interconnection port S20, and connects the signal sending node tx22, the signal receiving node rx22, and the interconnection port S24 in the second shift transmission circuit, which is shifted right by one position of the interconnection port S22.

[0120] For the interconnection port S19, the signal sending node tx19 cannot transmit signals to the signal receiving node rx19 through the interconnection port S19. The multiplexer in the first shift transmission circuit connects the signal sending node tx19, the signal receiving node rx19, and the interconnection port S21 in the first shift transmission circuit, which is shifted right by one position from the interconnection port S19; connects the signal sending node tx21, the signal receiving node rx21, and the interconnection port S23 in the first shift transmission circuit, which is shifted right by one position from the interconnection port S21; and connects the signal sending node tx23, the signal receiving node rx23, and the interconnection port S25 in the first shift transmission circuit, which is shifted right by one position from the interconnection port S23.

[0121] In the above example, the case where multiple interconnection ports are located in two shift transmission circuits is taken as an example. In this case, the multiple interconnection ports can be arranged in rows and columns, and any two adjacent interconnection ports in the same row or column are located in different shift transmission circuits. For example, the multiple interconnection ports can be arranged in a serpentine arrangement, with odd-numbered interconnection ports set in a unidirectional shift transmission circuit, and even-numbered interconnection ports set in a unidirectional shift transmission circuit. In this way, any two adjacent interconnection ports are located in different shift transmission circuits, and when a bridging fault occurs in the adjacent interconnection ports, they can be repaired separately by different shift transmission circuits.

[0122] An embodiment of the present application also provides another layout method for a shift transmission circuit, for example, multiple interconnection ports are arranged in multiple rows and columns. Since bridging failures usually occur between two adjacent interconnection ports in the same row or two adjacent interconnection ports in a column, two interconnection ports located on the same diagonal line are less likely to have bridging failures. An embodiment of the present application provides a layout method for a shift transmission circuit, in which the interconnection ports located on the same diagonal line are set in the same shift transmission circuit, and the interconnection ports on adjacent diagonals are located in different shift transmission circuits. This can also satisfy the requirement that any two adjacent interconnection ports are located in different shift transmission circuits.

[0123] Alternatively, it can be considered that the semiconductor device includes a first shift transmission circuit and a second shift transmission circuit; there is at least one interconnection port located in the second shift transmission circuit between any two interconnection ports located in the same row or column in the first shift transmission circuit, and the second shift transmission circuit is different from the first shift transmission circuit.

[0124] As shown in FIG16 , FIG16 is a schematic diagram of multiple interconnects of a semiconductor device, labeled 1 to 40. These 40 interconnects are arranged in five rows and eight columns along the X and Y directions. The following describes the layout of the shift transmission circuit provided in an embodiment of the present application based on the multiple interconnects shown in FIG16 .

[0125] In one possible implementation, referring to FIG. 17 , the five rows and eight columns of interconnect ports can be connected in series, with each port separated by a diagonal line, to form a shift transmission circuit. For example, along a fixed direction, interconnect ports distributed along odd-numbered diagonals can be connected in series to form a shift transmission circuit, while interconnect ports distributed along even-numbered diagonals can be connected in series to form a shift transmission circuit. For example, interconnects 1, 3, 10, 17, 33, 26, 19, 12, 5, 7, 14, 21, 28, 35, 37, 30, 23, 16, 32, and 39 are located in shift transmission circuit C1, and interconnects 9, 2, 4, 11, 18, 25, 34, 27, 20, 13, 6, 8, 15, 22, 29, 36, 38, 31, 24, and 40 are located in shift transmission circuit C2. These 40 interconnects constitute two shift transmission circuits, each with a redundant interconnect, for a total of two redundant interconnects. By capturing multiple interconnects in any region of Figure 17, it can be seen, for example, in conjunction with Figure 18, that any two adjacent interconnects are located in different shift transmission circuits, and a bridging fault between them can be repaired, such as between interconnects 1 and 2, or between interconnects 9 and 10. The interconnection ports located on the same diagonal line may be located in the same shift transmission circuit, for example, the interconnection port 1, the interconnection port 10, and the interconnection port 19 are located in the same shift transmission circuit.

[0126] Alternatively, in another possible implementation, referring to FIG. 19 , interconnection ports spaced two diagonally apart may be arranged in the same shift transmission circuit. For example, the 40 interconnection ports include 12 diagonals along the same direction. The interconnection ports distributed along the 1st, 4th, 7th, and 10th diagonals may be arranged in the same shift transmission circuit. The interconnection ports distributed along the 2nd, 5th, 8th, and 11th diagonals may be arranged in the same shift transmission circuit. The interconnection ports distributed along the 3rd, 6th, 9th, and 12th diagonals may be arranged in the same shift transmission circuit. As shown in Figure 19, interconnection ports 1, 4, 11, 18, 25, 35, 28, 21, 14, 7, 24, 31, and 38 are located in shift transmission circuit C1, interconnection ports 9, 2, 5, 12, 19, 26, 33, 36, 29, 22, 15, 8, 32, and 39 are located in shift transmission circuit C2, and interconnection ports 17, 10, 3, 6, 13, 20, 27, 34, 37, 30, 23, 16, and 40 are located in shift transmission circuit C3. In this way, the 40 interconnection ports can be set in three shift transmission circuits, and any two adjacent interconnection ports are located in different shift transmission circuits.

[0127] Alternatively, interconnection ports spaced three or more diagonally apart may be arranged in the same shift transmission circuit, so that 40 interconnection ports may be arranged in 4 or more shift transmission circuits.

[0128] For example, with reference to FIG17 , between any two interconnection ports in the same row or column of shift transmission circuit C1, there is at least one interconnection port located in shift transmission circuit C2. For example, interconnection ports 1 and 3 are located in shift transmission circuit C1, and interconnection port 2 located in shift transmission circuit C2 exists between interconnection ports 1 and 3. For another example, interconnection ports 10 and 26 are located in shift transmission circuit C1, and interconnection port 18 located in shift transmission circuit C2 exists between interconnection ports 10 and 26.

[0129] Alternatively, in conjunction with Figure 19, between any two interconnection ports in the same row or column of the shift transmission circuit C1, there is at least one interconnection port located in the shift transmission circuit C2 and at least one interconnection port located in the shift transmission circuit C3, for example, interconnection port 1 and interconnection port 4 are located in the shift transmission circuit C1, and interconnection port 2 and interconnection port 3 exist between interconnection port 1 and interconnection port 4, where interconnection port 2 is located in the shift transmission circuit C2, and interconnection port 3 is located in the shift transmission circuit C3.

[0130] In order to be able to use electronic design automation (EDA) tools to automatically connect multiple interconnect ports in series into a shift transmission circuit (shift repair chain) during the integrated circuit design process, thereby improving the automation level of integrated circuit design, an embodiment of the present application also provides a design method for a semiconductor device, which can automatically calculate and complete the layout of the shift transmission circuit based on the arrangement and number of interconnect ports between two bare chips, the number of redundant interconnect ports, etc.

[0131] For ease of explanation, the present invention uses the method provided in the present invention as an example of an interconnection port array arranged in multiple rows and columns between two dies as shown in FIG. 16 . Referring to FIG. 20 , the method includes:

[0132] S201: Obtain a target number of shift transmission circuits to be arranged, where the target number is greater than or equal to 2.

[0133] Taking into account the signal transmission delay and layout cost, the embodiment of the present application provides a shift transmission circuit that is a unidirectional shift transmission circuit. Each shift transmission circuit can be set with a redundant interconnection port. In other words, the number of shift transmission circuits is the same as the number of redundant interconnection ports. The target number of shift transmission circuits to be laid out can be a number pre-set by the user. For example, in order to ensure that the failure of any two interconnection ports can be repaired, the target number is greater than or equal to 2.

[0134] S202: Connecting a plurality of interconnection ports between the first die and the second die to the shift transmission circuit of the first die and the shift receiving circuit of the second die to form a target number of shift transmission circuits, wherein any two adjacent interconnection ports are located in different shift transmission circuits.

[0135] The design method provided in the embodiment of the present application can set the interconnection ports in the semiconductor device in a target number of shift transmission circuits according to the target number of shift transmission circuits to be arranged, and make any two adjacent interconnection ports located in different shift transmission circuits, for example, connecting the interconnection ports to the shift sending circuit of the first bare chip and the shift receiving circuit of the second bare chip, wherein the shift sending circuit includes multiple signal input terminals and multiple signal output terminals, and the signal inputted by the i-th signal input terminal of the shift sending circuit is configured to be outputted through the i-th signal output terminal or the i+1-th signal output terminal of the shift receiving circuit, and the shift receiving circuit includes multiple signal input terminals and multiple signal output terminals, and the i-th signal output terminal of the shift receiving circuit is configured to output the signal inputted by the i-th signal input terminal or the i+1-th signal input terminal of the shift receiving circuit, and the i-th signal output terminal of the shift sending circuit is connected to the i-th signal input terminal of the shift receiving circuit through the i-th interconnection port, where i is a positive integer.

[0136] In one possible implementation, the plurality of interconnects between the first die and the second die are arranged in multiple rows and columns to form an interconnect array. For example, referring to FIG. 21 , the plurality of interconnects may be divided into multiple groups along a diagonal line of the interconnect array. The lines connecting the interconnects in each group are parallel to the diagonal line of the interconnect array, such as lines L1 to L12 shown in FIG. 21 . The lines connecting the interconnects in each group are parallel to each other. S202 may include:

[0137] S2021: Divide the interconnection port array into a plurality of interconnection port groups according to the diagonal direction of the interconnection port array, wherein the connection lines of the interconnection ports in each interconnection port group are parallel to each other.

[0138] S2022: Connect multiple interconnection port groups of interval j to the same shift transmission circuit, where j=k-1, and k is the target number of shift transmission circuits to be laid out.

[0139] Here, in the embodiment of the present application, a plurality of interconnection ports are arranged in a matrix form with multiple rows and columns. In some cases, the interconnection ports may be arranged in other forms, but according to the distance relationship between the interconnection ports, they can be equivalently arranged in a matrix form.

[0140] For example, a semiconductor device may require two shift transmission circuits, i.e., k = 2. When two shift transmission circuits are deployed, interconnection port groups separated by one group can be placed in one shift transmission circuit. For example, if interconnection port lines are used to identify interconnection port groups, in conjunction with FIG21 and FIG17 , interconnection port groups corresponding to L1, L3, L5, L7, L9, and L11, which are separated by one interconnection port group, can be placed in the same shift transmission circuit, and interconnection port groups corresponding to L2, L4, L6, L8, L10, and L12, which are separated by one interconnection port group, can be placed in the same shift transmission circuit. This arrangement forms two shift transmission circuits, and any two adjacent interconnection ports are located in different shift transmission circuits.

[0141] If the semiconductor device needs to be provided with three shift transmission circuits, that is, k=3, when three shift transmission circuits are arranged, interconnection port groups that are separated by two groups can be arranged in one shift transmission circuit. For example, if the interconnection port connection is used as the identifier of the interconnection port group, in combination with FIG21 and FIG19 , the interconnection port groups corresponding to L1, L4, L7, and L10 that are separated by two interconnection port groups can be arranged in the same shift transmission circuit, the interconnection port groups corresponding to L2, L5, L8, and L11 that are separated by two interconnection port groups can be arranged in the same shift transmission circuit, and the interconnection port groups corresponding to L3, L6, L9, and L12 that are separated by two interconnection port groups can be arranged in the same shift transmission circuit. In this way, three shift transmission circuits are formed, and any two adjacent interconnection ports are located in different shift transmission circuits.

[0142] In the embodiment of the present application, considering the impact of signal transmission rate and cost, each shift transmission circuit can be a unidirectional shift transmission circuit as shown in Figure 6. In addition, the above is only an exemplary description of automatically chaining the shift transmission circuits. During the chaining, if an interconnection port corresponding to a power signal, clock signal, redundant signal, or other signal that does not need to be chained in the shift transmission circuit is encountered, it can be simply skipped.

[0143] An embodiment of the present application further provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the semiconductor device design method in the above-mentioned embodiment.

[0144] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the semiconductor device design method in the above-mentioned embodiment.

[0145] An embodiment of the present application further provides a chip, which includes a substrate and the semiconductor device provided by the aforementioned embodiment, wherein the semiconductor device is disposed on the substrate.

[0146] An embodiment of the present application further provides an electronic device, which includes a circuit board and the above-mentioned chip, wherein the chip is electrically connected to the circuit board.

[0147] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0148] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0151] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0152] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: a first die, a second die, and a plurality of interconnect ports; The first die includes a plurality of signal transmission nodes and a plurality of shift transmission circuits; the shift transmission circuit includes a plurality of signal input terminals and a plurality of signal output terminals, a signal inputted by the i-th signal input terminal is configured to be outputted through the i-th signal output terminal or the i+1-th signal output terminal, where i is a positive integer; the plurality of signal input terminals of the shift transmission circuit are respectively connected to one of the signal transmission nodes; The second die includes a plurality of signal receiving nodes and a plurality of shift receiving circuits, wherein the shift receiving circuit includes a plurality of signal input terminals and a plurality of signal output terminals, wherein the i-th signal output terminal is configured to output a signal input by the i-th signal input terminal or the (i+1)-th signal input terminal, and each of the plurality of signal output terminals of the shift receiving circuit is connected to one of the signal receiving nodes; The i-th signal output terminal of the shift sending circuit is connected to the i-th signal input terminal of the shift receiving circuit through the i-th interconnection port; The shifted transmitting circuits connected to any two adjacent interconnection ports of the semiconductor device are different, and the shifted receiving circuits connected to any two adjacent interconnection ports are different.

2. The semiconductor device according to claim 1, wherein Different shift and transmit circuits may have the same or different numbers of signal input terminals.

3. The semiconductor device according to claim 2, wherein The shift transmission circuit includes n signal input terminals, n+1 signal output terminals, and n-1 multiplexers, wherein the multiplexers include a first input terminal, a second input terminal, and an output terminal; In the shift and transmit circuit, a first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift and transmit circuit, a second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift and transmit circuit, and an output terminal of the mth multiplexer is connected to the m+1th signal output terminal of the shift and transmit circuit, where m and n are positive integers and m≤n-1.

4. The semiconductor device according to claim 3, wherein The first signal input terminal of the shift transmission circuit is also connected to the first signal output terminal of the shift transmission circuit; the nth signal input terminal of the shift transmission circuit is also connected to the n+1th signal output terminal of the shift transmission circuit.

5. The semiconductor device according to any one of claims 1 to 4, wherein: Different shift receiving circuits may have the same or different numbers of signal input terminals.

6. The semiconductor device according to claim 5, wherein The shift receiving circuit includes n+1 signal input terminals, n signal output terminals and n multiplexers, wherein the multiplexer includes a first input terminal, a second input terminal and an output terminal; In the shift receiving circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift receiving circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift receiving circuit, and the output terminal of the mth multiplexer is connected to the mth signal output terminal of the shift receiving circuit, where m and n are positive integers and m≤n-1.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The plurality of interconnection ports are arranged in rows and columns, and any two adjacent interconnection ports in the same row or column are connected to different shifted sending circuits and different shifted receiving circuits.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The interconnection ports include microbumps, hybrid bonding ports and through silicon vias.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The plurality of interconnection ports include a first interconnection port, a second interconnection port, and a third interconnection port. The first interconnection port is adjacent to the second interconnection port. A distance between the first interconnection port and the second interconnection port is less than or equal to a distance between the first interconnection port and the third interconnection port. A distance between the first interconnection port and the second interconnection port is less than or equal to a distance between the second interconnection port and the third interconnection port.

10. A bare chip, characterized in that: including a plurality of signal sending nodes, a plurality of shift sending circuits, and a plurality of interconnection ports; The shift transmission circuit includes a plurality of signal input terminals and a plurality of signal output terminals, wherein a signal inputted by the i-th signal input terminal is configured to be outputted through the i-th signal output terminal or the i+1-th signal output terminal, where i is a positive integer; The plurality of signal input terminals of the shift sending circuit are respectively connected to one of the signal sending nodes, and the plurality of signal output terminals of the shift sending circuit are respectively connected to one of the interconnection ports; Any two adjacent interconnection ports of the die are connected to different shift and transmit circuits.

11. The die according to claim 10, wherein: Different shift and transmit circuits may have the same or different numbers of input terminals.

12. The die according to claim 11, wherein: The shift transmission circuit includes n signal input terminals, n+1 signal output terminals, and n-1 multiplexers, wherein the multiplexers include a first input terminal, a second input terminal, and an output terminal; In the shift transmission circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift transmission circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift transmission circuit, and the output terminal of the mth multiplexer is connected to the m+1th signal output terminal of the shift transmission circuit, where m and n are positive integers and m≤n-1.

13. The die according to claim 12, wherein: The first signal input terminal of the shift transmission circuit is also connected to the first signal output terminal of the shift transmission circuit; The nth signal input terminal of the shift sending circuit is also connected to the (n+1)th signal output terminal of the shift sending circuit.

14. A bare chip, characterized in that: The device comprises a plurality of signal receiving nodes, a plurality of shift receiving circuits, and a plurality of interconnection ports, wherein the shift receiving circuit comprises a plurality of signal input terminals and a plurality of signal output terminals, wherein the i-th signal output terminal is configured to output a signal inputted by the i-th signal input terminal or the i+1-th signal input terminal, where i is a positive integer; The plurality of signal input terminals of the shift receiving circuit are respectively connected to one of the interconnection ports, and the plurality of signal output terminals of the shift receiving circuit are respectively connected to one of the signal receiving nodes; Any two adjacent interconnection ports of the die are connected to different shift receiving circuits.

15. The die according to claim 14, wherein: The numbers of signal input terminals of different shift receiving circuits are the same or different.

16. The die according to claim 15, wherein: The shift receiving circuit includes n+1 signal input terminals, n signal output terminals and n multiplexers, wherein the multiplexer includes a first input terminal, a second input terminal and an output terminal; In the shift receiving circuit, the first input terminal of the mth multiplexer is connected to the mth signal input terminal of the shift receiving circuit, the second input terminal of the mth multiplexer is connected to the m+1th signal input terminal of the shift receiving circuit, and the output terminal of the mth multiplexer is connected to the mth signal output terminal of the shift receiving circuit, where m and n are positive integers and m≤n-1.

17. A method for designing a semiconductor device, characterized in that: The method comprises: Obtaining a target number of shift transmission circuits to be arranged, where the target number is greater than or equal to 2; Connecting multiple interconnection ports between the first die and the second die with the shifted transmitting circuit of the first die and the shifted receiving circuit of the second die to form the target number of shifted transmission circuits, where any two adjacent interconnection ports are located in different shifted transmission circuits, wherein the shifted transmitting circuit includes multiple signal input terminals and multiple signal output terminals, and a signal inputted by the i-th signal input terminal of the shifted transmitting circuit is configured to be outputted through the i-th signal output terminal or the i+1-th signal output terminal of the shifted transmitting circuit; the shifted receiving circuit includes multiple signal input terminals and multiple signal output terminals, and the i-th signal output terminal of the shifted receiving circuit is configured to output a signal inputted by the i-th signal input terminal or the i+1-th signal input terminal of the shifted receiving circuit; and the i-th signal output terminal of the shifted transmitting circuit is connected to the i-th signal input terminal of the shifted receiving circuit through the i-th interconnection port, where i is a positive integer.

18. The method according to claim 17, characterized in that The plurality of interconnection ports between the first die and the second die are arranged in multiple rows and columns to form an interconnection port array, the plurality of interconnection ports between the first die and the second die are connected to the shift transmission circuit of the first die and the shift receiving circuit of the second die to form the target number of shift transmission circuits, and any two adjacent interconnection ports are located in different shift transmission circuits, including: Dividing the interconnection port array into a plurality of interconnection port groups according to the diagonal direction of the interconnection port array, wherein the lines connecting the interconnection ports in each interconnection port group are parallel to each other; Connect multiple interconnection port groups of interval j to the same shift transmission circuit, where j=k-1, and k is the target number of shift transmission circuits to be laid out.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, which implement the steps of the method according to claim 17 or 18 when the computer instructions are executed.

20. A computer program product, characterized in that When the computer program product is run on a processor, the processor is caused to perform the steps of the method according to claim 17 or 18.

21. A chip, characterized in that: The chip includes a substrate and the semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is provided on the substrate.

22. An electronic device, characterized in that: The electronic device includes a circuit board and the chip according to claim 21, wherein the chip is electrically connected to the circuit board.

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