Bidirectional ESD protection device and manufacturing method therefor

Abstract

The present invention relates to a bidirectional ESD protection device and a manufacturing method therefor. The device comprises a P-substrate; an N-bury layer, which is located on part of the P-substrate; a first P-well region, which is located on the N-bury layer; a P-bury layer, which is located on part of the P-substrate; a second P-well region, which is located on the P-bury layer; a first insulating structure, which is located between the first P-well region and the second P-well region, and between the N-bury layer and the P-bury layer. The present invention optimizes the current discharge path of the bidirectional ESD protection device from the transversal direction into the longitudinal direction, such that the device area can be saved, thereby improving the current discharge capability per unit area of the device.

Description

Bidirectional ESD protection device and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 202410206435.5, filed on February 23, 2024, entitled “BI-directional ESD protection device and manufacturing method thereof,” and incorporates herein in its entirety. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to a bidirectional ESD protection device and a manufacturing method of the bidirectional ESD protection device. Background Art

[0004] ESD (Electro-Static Discharge) protection is an important part of IC (Integrated Circuit) design. ESD protection devices play a role in protecting internal circuits from damage by static electricity.

[0005] Bidirectional ESD devices are essential components of ESD protection circuits in circuit applications. They must withstand both positive and negative voltages. In related technologies, a lateral PNP transistor with a floating base is used to achieve this. The positive voltage withstands the CB (collector-base) junction, while the negative voltage withstands the EB (emitter-base) junction.

[0006] ESD protection is limited by the current discharge capability of the ESD protection device per unit area. It is generally believed that the greater the current a device can discharge per unit area, the stronger its ESD protection capability. Lateral PNP transistors, as bidirectional ESD devices, have a relatively weak current discharge capability per unit area. Summary of the Invention

[0007] Based on this, it is necessary to provide a bidirectional ESD protection device with a strong current discharge capability per unit area and a manufacturing method thereof.

[0008] A bidirectional ESD protection device includes: a P-type substrate; an N-type buried layer located on a portion of the P-type substrate; a first P-type well region located on the N-type buried layer; a P-type buried layer located on a portion of the P-type substrate; a second P-type well region located on the P-type buried layer; and a first insulating structure located between the first P-type well region and the second P-type well region, and between the N-type buried layer and the P-type buried layer.

[0009] The above-mentioned bidirectional ESD protection device optimizes the current discharge path of the bidirectional ESD protection device from horizontal to vertical, which can save device area and thus improve the device's discharge current capability per unit area.

[0010] In one embodiment, the top of the first P-type well region is used to connect to an ESD port, and the top of the second P-type well region is used to be grounded.

[0011] In one embodiment, a bottom depth of the first insulating structure is deeper than a bottom depth of the N-type buried layer and a bottom depth of the P-type buried layer.

[0012] In one embodiment, the bidirectional ESD protection device further includes a first P-type doping region located at the bottom of the first insulating structure, and the doping concentration of the first P-type doping region is greater than the doping concentration of the P-type substrate.

[0013] In one embodiment, a second insulating structure is further included on a side of the first P-type well region opposite to the first insulating structure.

[0014] In one embodiment, a bottom depth of the second insulating structure is deeper than a bottom depth of the N-type buried layer and a bottom depth of the P-type buried layer.

[0015] In one embodiment, the bidirectional ESD protection device further includes a second P-type doping region located at the bottom of the second insulating structure, and the doping concentration of the second P-type doping region is greater than the doping concentration of the P-type substrate.

[0016] In one embodiment, the first insulating structure is a closed surrounding structure in the laterally direction, and the P-type buried layer and the second P-type well region are laterally surrounded by the first insulating structure.

[0017] In one embodiment, the second insulating structure is a closed surrounding structure in the laterally direction, and the N-type buried layer and the first P-type well region are laterally surrounded by the second insulating structure and are located between the second insulating structure and the first insulating structure.

[0018] In one embodiment, the bidirectional ESD protection device further includes: a third P-type doped region located on top of the first P-type well region, the doping concentration of the third P-type doped region is greater than the doping concentration of the first P-type well region, and the first P-type well region is connected to the ESD port through the third P-type doped region.

[0019] In one embodiment, the bidirectional ESD protection device further includes: a fourth P-type doping region located on top of the second P-type well region, the doping concentration of the fourth P-type doping region is greater than the doping concentration of the second P-type well region, and the second P-type well region is grounded through the fourth P-type doping region.

[0020] A method for manufacturing a bidirectional ESD protection device comprises: providing a wafer having a P-type substrate, an N-type buried layer, a P-type buried layer, and a P-type well region; the P-type well region is located on the N-type buried layer and the P-type buried layer, and the N-type buried layer and the P-type buried layer are located on at least a portion of the P-type substrate; forming a trench penetrating the P-type well region; a portion of the trench structure is located between the N-type buried layer and the P-type buried layer, and a portion of the P-type well region located above the N-type buried layer and a portion located above the P-type buried layer are separated by the trench; and forming a first insulating structure in the trench.

[0021] In one embodiment, the step of providing a wafer having a P-type substrate, an N-type buried layer, a P-type buried layer and a P-type well region includes: forming the N-type buried layer and the P-type buried layer in the P-type substrate; forming an epitaxial layer on the P-type substrate; and forming the P-type well region in the epitaxial layer.

[0022] In one embodiment, the step of forming a trench passing through the P-type well region includes: forming a shallow trench isolation structure; the bottom of the shallow trench isolation structure extends into the P-type well region, and the shallow trench isolation structure is not formed on the top of at least a portion of the P-type well region directly above the N-type buried layer, and the shallow trench isolation structure is not formed on the top of at least a portion of the P-type well region directly above the P-type buried layer; forming a patterned hard mask layer on the P-type well region; using the hard mask layer as a barrier layer, etching the shallow trench isolation structure, and continuing to etch downward the P-type well region, as well as the N-type buried layer and / or the P-type buried layer to form the trench.

[0023] In one embodiment, the step of forming the first insulating structure in the trench includes: depositing an oxide layer in the trench; etching the oxide layer at the bottom of the trench to expose the P-type substrate at the bottom of the trench; filling the oxide layer into the trench to form the first insulating structure; wherein, after the step of etching the oxide layer at the bottom of the trench and before the step of filling the oxide layer into the trench, the manufacturing method further includes: forming a first P-type doped region in the P-type substrate below the bottom of the trench by ion implantation, the doping concentration of the first P-type doped region being greater than the doping concentration of the P-type substrate.

[0024] The manufacturing method of the bidirectional ESD protection device optimizes the current discharge path of the bidirectional ESD protection device from a horizontal direction to a vertical direction, which can save device area and thus improve the current discharge capacity per unit area of ​​the device.

[0025] In one embodiment, the step of forming a trench passing through the P-type well region includes forming a first trench separating the N-type buried layer from the P-type buried layer, and forming a second trench located on a side of the N-type buried layer opposite to the first trench, and the N-type buried layer is located between the first trench and the second trench; the step of forming a first insulating structure and a second insulating structure in the trench includes: forming the first insulating structure in the first trench and forming the second insulating structure in the second trench.

[0026] In one embodiment, the step of forming a first P-type doping region and a second P-type doping region in the P-type substrate below the bottom of the trench by ion implantation includes: forming a first P-type doping region in the P-type substrate below the bottom of the first trench, and forming a second P-type doping region in the P-type substrate below the bottom of the second trench; the doping concentration of the second P-type doping region is greater than the doping concentration of the P-type substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0028] FIG1 is a schematic structural diagram of a bidirectional ESD protection device according to an embodiment of the present application;

[0029] FIG2 is a diagram showing the flow path of electrons in the bidirectional ESD protection device shown in FIG1 during reverse withstand voltage;

[0030] FIG3 is a top view of the first insulating structure 142 and the second insulating structure 144 in one embodiment of the present application;

[0031] 4 is a flow chart of a method for manufacturing a bidirectional ESD protection device according to an embodiment of the present application;

[0032] FIG5 is a flowchart of sub-steps of step S410 in one embodiment of the present application;

[0033] 6a to 6h are schematic cross-sectional views of a device during the process of manufacturing a bidirectional ESD protection device using the method shown in FIG4 ;

[0034] FIG7 is a flowchart of sub-steps of step S420 in one embodiment of the present application;

[0035] FIG8 is a flowchart of sub-steps of step S520 in an embodiment of the present application. DETAILED DESCRIPTION

[0036] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate alternative embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the first element, first component, first region, first layer, or portion discussed below may be represented as a second element, second component, second region, second layer, or portion without departing from the teachings of the present invention.

[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0042] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0043] This application proposes a new bidirectional ESD protection device, which adjusts the current discharge path to the longitudinal direction while meeting the positive and negative withstand voltage requirements, which can effectively reduce the device area and improve the current discharge capability of the ESD device.

[0044] FIG1 is a schematic diagram of the structure of a bidirectional ESD protection device in one embodiment of the present application. The bidirectional ESD protection device shown in FIG1 is bilaterally symmetrical, so some structures are numbered only on one side. In the embodiment shown in FIG1 , the bidirectional ESD protection device includes a P-type substrate 110, an N-type buried layer (N-Bury) 122, a P-type buried layer (P-Bury) 124, a first P-type well region 132, a second P-type well region 133, and a first insulating structure 142. The N-type buried layer 122 is located on a portion of the P-type substrate 110, and the P-type buried layer 124 is located on a portion of the P-type substrate 110. The first P-type well region 132 is located on the N-type buried layer 122. The second P-type well region 133 is located on the P-type buried layer 124. The first insulating structure 142 is located between the first P-type well region 132 and the second P-type well region 133, and between the N-type buried layer 122 and the P-type buried layer 124.

[0045] In the embodiment shown in FIG1 , the top of the first P-type well region 132 is used to connect to the ESD port, that is, to connect to the anode electrode; the top of the second P-type well region 133 is used for grounding (GND), that is, to connect to the cathode electrode.

[0046] The forward withstand voltage of the bidirectional ESD protection device shown in Figure 1 is the turn-on voltage of the vertical PMOS, where the first P-type well region 132 is the source region of the PMOS, the P-type substrate 110 below the N-type buried layer 122 is the drain region of the PMOS, and the P-type buried layer 124 is the gate of the PMOS. The gate is connected to the ground through the second P-type well region 133, and the first insulating structure 142 serves as the gate dielectric layer. When an electrostatic surge arrives at the ESD port, the voltage of the first P-type well region 132 reaches the turn-on voltage of the PMOS, the PMOS turns on, and the device discharges current through the path indicated by the arrow in Figure 1. The first insulating structure 142 acts to block the lateral movement of the current. The negative direction of the bidirectional ESD protection device shown in Figure 1 is withstand voltage through the EB junction of the PNP transistor (the collector includes the second P-type well region 133, the P-type buried layer 124, the P-type substrate 110 below the P-type buried layer 124, and the base is the N-type buried layer 122). Referring to Figure 2 , when an electrostatic surge occurs at the GND port, the voltage of the second P-type well region 133 reaches the turn-on voltage of the PNP transistor, turning on the PNP transistor. The direction of electron movement in the device is indicated by the arrows in Figure 2 (the current flows in the opposite direction of the electron movement). Because the current path is longitudinal, device area can be saved, thereby improving the device's current discharge capacity per unit area.

[0047] In the embodiment shown in FIG1 , the bottom depth of the first insulating structure 142 is deeper than the bottom depth of the N-type buried layer 122 and the bottom depth of the P-type buried layer 124 , that is, the depth of the first insulating structure 142 extending into the P-type substrate 110 is deeper than the depth of the N-type buried layer 122 / P-type buried layer 124 extending into the P-type substrate 110 .

[0048] In the embodiment shown in FIG1 , the bidirectional ESD protection device further includes a first P-type doped region 136 located at the bottom of the first insulating structure 142. The doping concentration of the first P-type doped region 136 is greater than the doping concentration of the P-type substrate 110. The provision of the first P-type doped region 136 can reduce the resistance of the conduction path during ESD current discharge, thereby improving the current discharge capability.

[0049] In the embodiment shown in FIG. 1 , the bidirectional ESD protection device further includes a second insulating structure 144 located on a side of the first P-type well region 132 opposite to the first insulating structure 142 .

[0050] In one embodiment of the present application, the first insulating structure 142 is a closed surrounding structure in the laterally direction, and the P-type buried layer 124 and the second P-type well region 133 are laterally surrounded by the first insulating structure 142 .

[0051] In one embodiment of the present application, the second insulating structure 144 is a closed, enclosing structure in the laterally direction. The N-type buried layer 122 and the first P-type well region 132 are laterally enclosed by the second insulating structure 144 and located between the second insulating structure 144 and the first insulating structure 142. The second insulating structure 144 serves to electrically isolate the N-type buried layer 122 and the first P-type well region 132 from external device structures (outside the second insulating structure 144).

[0052] Figure 3 is a top view of the first insulating structure 142 and the second insulating structure 144 in one embodiment of the present application. In this embodiment, the first insulating structure 142 and the second insulating structure 144 are in the shape of a square frame; in other embodiments, the first insulating structure 142 and the second insulating structure 144 can also be closed structures of other shapes, such as a circular ring, an elliptical ring, a racetrack, etc.

[0053] In the embodiment shown in Figure 1, the bottom depth of the second insulating structure 144 is deeper than the bottom depth of the N-type buried layer 122 and the bottom depth of the P-type buried layer 124, that is, the depth of the second insulating structure 144 extending into the P-type substrate 110 is deeper than the depth of the N-type buried layer 122 / P-type buried layer 124 extending into the P-type substrate 110.

[0054] In the embodiment shown in FIG1 , the bidirectional ESD protection device further includes a second P-type doped region 138 located at the bottom of the second insulating structure 144. The doping concentration of the second P-type doped region 138 is greater than the doping concentration of the P-type substrate 110. The second P-type doped region 138 serves as an electrical isolation layer, preventing the N-type buried layer 122 from penetrating into external device structures (e.g., other N-type regions).

[0055] In the embodiment shown in FIG1 , the bidirectional ESD protection device further includes a third P-type doped region 134 located on top of the first P-type well region 132. The doping concentration of the third P-type doped region 134 is greater than that of the first P-type well region 132, thereby reducing contact resistance. The first P-type well region 132 is connected to the ESD port via the third P-type doped region 134.

[0056] In the embodiment shown in FIG1 , the bidirectional ESD protection device further includes a fourth P-type doped region 135 located on top of the second P-type well region 133. The doping concentration of the fourth P-type doped region 135 is greater than that of the second P-type well region 133, thereby reducing contact resistance. The second P-type well region 133 is grounded via the fourth P-type doped region 135.

[0057] In one embodiment of the present application, the first insulating structure 142 is made of silicon oxide, such as silicon dioxide. In one embodiment of the present application, the second insulating structure 144 is made of silicon oxide, such as silicon dioxide.

[0058] The present application accordingly provides a method for manufacturing a bidirectional ESD protection device, which is used to manufacture the ESD protection device described in any of the above embodiments. FIG4 is a flow chart of the method for manufacturing a bidirectional ESD protection device in an embodiment of the present application, comprising the following steps:

[0059] S410 , providing a wafer having a P-type substrate, an N-type buried layer, a P-type buried layer, and a P-type well region.

[0060] The P-type well region 130 is located on the N-type buried layer 122 and the P-type buried layer 124 . The N-type buried layer 122 and the P-type buried layer 124 are located on at least a portion of the P-type substrate 110 .

[0061] Referring to FIG. 5 , in one embodiment of the present application, step S410 includes:

[0062] S412 , forming an N-type buried layer and a P-type buried layer in the P-type substrate.

[0063] Referring to Figure 6a, in one embodiment of the present application, a pad oxide layer (PAD Oxide) 141 can be first formed on the surface of the P-type substrate 110 of the wafer by thermal oxidation, and then an N-type buried layer 122 and a P-type buried layer 124 can be formed in the P-type substrate 110 by patterning (such as photolithography) and ion implantation.

[0064] S414, forming an epitaxial layer on the P-type substrate.

[0065] In one embodiment of the present application, after the pad oxide layer 141 is removed, an epitaxial layer is grown on the P-type substrate 110 , the N-type buried layer 122 , and the P-type buried layer 124 .

[0066] S416 , forming a P-type well region in the epitaxial layer.

[0067] 6 b , a P-type well region 130 is formed in the epitaxial layer on the N-type buried layer 122 and the P-type buried layer 124 by patterning (eg, photolithography) and ion implantation (implanting P-type ions).

[0068] At this point, step S410 is completed and the process proceeds to step S420.

[0069] S420 , forming a trench penetrating the P-type well region.

[0070] In one embodiment of the present application, the bottom of the trench is deeper than the bottoms of the N-type buried layer 122 and the P-type buried layer 124 .

[0071] Referring to FIG. 7 , in one embodiment of the present application, step S420 includes:

[0072] S422, forming a shallow trench isolation structure.

[0073] Patterning (e.g., photolithography and etching) is performed on the front side of the wafer to form shallow trenches, and then an oxide layer is deposited to form shallow trench isolation structures 146. Referring to FIG. 6c , the bottom of shallow trench isolation structures 146 extends into P-type well region 130. Shallow trench isolation structures 146 are not formed on top of at least a portion of P-type well region 130 directly above N-type buried layer 122, and are not formed on top of at least a portion of P-type well region 130 directly above P-type buried layer 124. This exposes P-type well region 130 on the front side of the wafer. In one embodiment of the present application, at least a portion of shallow trench isolation structures 146 is required to form deep trench isolation (DTI) structures in the subsequent step S430.

[0074] S424 , forming a patterned hard mask layer on the P-type well region.

[0075] In one embodiment of the present application, silicon nitride is deposited on the front side of the wafer, and then patterned (photolithography and etching) to form a hard mask layer 152, as shown in FIG6d. The window exposed by the hard mask layer 152 is located on the shallow trench isolation structure 146. In one embodiment of the present application, before depositing silicon nitride, a step of forming a PAD oxide (not shown in FIG6d) ​​on the front side of the wafer is also included, and the silicon nitride is deposited on the PAD oxide.

[0076] S426 , using the hard mask layer as a barrier layer, etching to form a trench.

[0077] After etching through the shallow trench isolation structure 146, the P-type well region 130, as well as the N-type buried layer 122 and / or the P-type buried layer 124, is further etched downward to form a trench 131, as shown in FIG6e. In the embodiment shown in FIG6e, the trench 131 includes a first trench 131a that separates the N-type buried layer 122 from the P-type buried layer 124, and a second trench 131b located outside the N-type buried layer 122 (i.e., on the side of the N-type buried layer 122 opposite the first trench 131a). The first trench 131a separates the P-type well region 130 into a first P-type well region 132 on the N-type buried layer 122 and a second P-type well region 133 on the P-type buried layer 124.

[0078] In one embodiment of the present application, the bottom depth of the trench 131 is deeper than the bottom depth of the N-type buried layer 122 and the bottom depth of the P-type buried layer 124 .

[0079] At this point, step S420 is completed and the process proceeds to step S430.

[0080] S430 , forming a first insulating structure in the trench.

[0081] Referring to FIG. 8 , in one embodiment of the present application, step S430 includes:

[0082] S432, depositing an oxide layer into the trench.

[0083] In one embodiment of the present application, an oxide layer 143 is deposited into the first trench 131 a and the second trench 131 b , as shown in FIG. 6 f .

[0084] S434, etching the oxide layer at the bottom of the trench to expose the P-type substrate at the bottom of the trench.

[0085] In one embodiment of the present application, the oxide layer 143 at the bottom of the first trench 131 a and the second trench 131 b is removed by etching, so that the P-type substrate 110 at the bottom is exposed.

[0086] In one embodiment of the present application, after the P-type substrate 110 at the bottom of the trench 131 is exposed, ion implantation (implanting P-type ions) is performed to form a first P-type doped region 136 in the P-type substrate 110 below the bottom of the first trench 131a, and a second P-type doped region 138 in the P-type substrate 110 below the bottom of the second trench 131b (see FIG. 6 g ). The doping concentrations of the first P-type doped region 136 and the second P-type doped region 138 are greater than the doping concentration of the P-type substrate 110.

[0087] S436 , filling the trench with an oxide layer to form a first insulating structure.

[0088] In one embodiment of the present application, the trench is filled with an oxide layer and then etched back. Furthermore, after the etch back, the upper surface of the oxide layer can be slightly higher than the upper surface of the shallow trench isolation structure 146.

[0089] In the embodiment shown in FIG6h , the first trench 131a is filled with an oxide layer to form a first insulating structure 142, and the second trench 131b is filled with an oxide layer to form a second insulating structure 144. The first insulating structure 142 separates the first P-type well region 132 from the second P-type well region 133, and separates the N-type buried layer 122 from the P-type buried layer 124.

[0090] The manufacturing method of the bidirectional ESD protection device optimizes the current discharge path of the bidirectional ESD protection device from a horizontal direction to a vertical direction, which can save device area and thus improve the current discharge capacity per unit area of ​​the device.

[0091] In one embodiment of the present application, after step S436, a step of removing the hard mask layer 152 is further included. Specifically, it can be removed by etching. In one embodiment of the present application, after the step of removing the hard mask layer 152, a third P-type doping region 134 is formed on top of the first P-type well region 132, and a fourth P-type doping region 135 is formed on top of the second P-type well region 133 by patterning (such as photolithography) and ion implantation (implanting P-type ions). The device structure after this step is completed can be seen in Figure 1. The doping concentration of the third P-type doping region 134 is greater than the doping concentration of the first P-type well region 132, and the doping concentration of the fourth P-type doping region 135 is greater than the doping concentration of the second P-type well region 133.

[0092] The manufacturing method of the bidirectional ESD protection device of the present application and the bidirectional ESD protection device are based on the same inventive concept. For matters not specifically described in the manufacturing method of the bidirectional ESD protection device, please refer to the previous introduction to the bidirectional ESD protection device.

[0093] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0094] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0095] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A bidirectional ESD protection device, characterized in that: include: P-type substrate; An N-type buried layer is located on a portion of the P-type substrate; a first P-type well region, located on the N-type buried layer; A P-type buried layer, located on a portion of the P-type substrate; a second P-type well region, located on the P-type buried layer; The first insulating structure is located between the first P-type well region and the second P-type well region, and between the N-type buried layer and the P-type buried layer.

2. The bidirectional ESD protection device according to claim 1, characterized in that: The top of the first P-type well region is used to connect to the ESD port, and the top of the second P-type well region is used to be grounded.

3. The bidirectional ESD protection device according to claim 1, wherein: A bottom depth of the first insulating structure is deeper than a bottom depth of the N-type buried layer and a bottom depth of the P-type buried layer.

4. The bidirectional ESD protection device according to claim 1 or 3, characterized in that: The bidirectional ESD protection device further includes a first P-type doping region located at the bottom of the first insulating structure, and the doping concentration of the first P-type doping region is greater than the doping concentration of the P-type substrate.

5. The bidirectional ESD protection device according to claim 1, wherein: The invention also includes a second insulating structure located on a side of the first P-type well region opposite to the first insulating structure.

6. The bidirectional ESD protection device according to claim 5, characterized in that: A bottom depth of the second insulating structure is deeper than a bottom depth of the N-type buried layer and a bottom depth of the P-type buried layer.

7. The bidirectional ESD protection device according to claim 5 or 6, characterized in that: The bidirectional ESD protection device further includes a second P-type doping region located at the bottom of the second insulating structure, and the doping concentration of the second P-type doping region is greater than the doping concentration of the P-type substrate.

8. The bidirectional ESD protection device according to claim 1, wherein: The first insulating structure is a closed surrounding structure in the lateral direction, and the P-type buried layer and the second P-type well region are surrounded by the first insulating structure in the lateral direction.

9. The bidirectional ESD protection device according to claim 5, wherein: The second insulating structure is a closed surrounding structure in the laterally direction. The N-type buried layer and the first P-type well region are laterally surrounded by the second insulating structure and are located between the second insulating structure and the first insulating structure.

10. The bidirectional ESD protection device according to claim 1, wherein: Also includes: A third P-type doping region is located on top of the first P-type well region. The doping concentration of the third P-type doping region is greater than the doping concentration of the first P-type well region. The first P-type well region is connected to the ESD port through the third P-type doping region.

11. The bidirectional ESD protection device according to claim 1 or 10, characterized in that: Also includes: A fourth P-type doping region is located on top of the second P-type well region. The doping concentration of the fourth P-type doping region is greater than the doping concentration of the second P-type well region. The second P-type well region is grounded through the fourth P-type doping region.

12. A method for manufacturing a bidirectional ESD protection device, characterized in that: include: Providing a wafer having a P-type substrate, an N-type buried layer, a P-type buried layer and a P-type well region; The P-type well region is located on the N-type buried layer and the P-type buried layer, and the N-type buried layer and the P-type buried layer are located on at least a portion of the P-type substrate; forming a trench penetrating the P-type well region; wherein a portion of the trench is located between the N-type buried layer and the P-type buried layer, and a portion of the P-type well region located above the N-type buried layer is separated from a portion located above the P-type buried layer by the trench; A first insulating structure is formed in the trench.

13. The method for manufacturing a bidirectional ESD protection device according to claim 12, wherein: The step of providing a wafer having a P-type substrate, an N-type buried layer, a P-type buried layer and a P-type well region comprises: forming the N-type buried layer and the P-type buried layer in the P-type substrate; forming an epitaxial layer on the P-type substrate; The P-type well region is formed in the epitaxial layer.

14. The method for manufacturing a bidirectional ESD protection device according to claim 12, wherein: The step of forming a trench penetrating the P-type well region comprises: forming a shallow trench isolation structure; the bottom of the shallow trench isolation structure extends into the P-type well region, the shallow trench isolation structure is not formed on the top of at least a portion of the P-type well region directly above the N-type buried layer, and the shallow trench isolation structure is not formed on the top of at least a portion of the P-type well region directly above the P-type buried layer; forming a patterned hard mask layer on the P-type well region; The shallow trench isolation structure is etched using the hard mask layer as a barrier layer, and the P-type well region is further etched downward, as well as the N-type buried layer and / or the P-type buried layer to form the trench.

15. The method for manufacturing a bidirectional ESD protection device according to claim 14, wherein: The step of forming a first insulating structure in the trench comprises: depositing an oxide layer into the trench; Etching the oxide layer at the bottom of the trench to expose the P-type substrate at the bottom of the trench; filling an oxide layer into the trench to form the first insulating structure; Among them, after the step of etching the oxide layer at the bottom of the trench and before the step of filling the oxide layer into the trench, the manufacturing method further includes: forming a first P-type doping region in the P-type substrate below the bottom of the trench by ion implantation, and the doping concentration of the first P-type doping region is greater than the doping concentration of the P-type substrate.

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