Three-dimensional flash memory device and forming method therefor

Abstract

Provided in the present invention is a method for forming a three-dimensional flash memory device. The method comprises: sequentially and alternately forming on a substrate several gate isolation oxide layers and several control gate layers; forming several spaced and alternately arranged first shallow trench isolation structures and second shallow trench isolation structures in the several control gate layers and the several gate isolation oxide layers; forming several first through holes in the first shallow trench isolation structures; sequentially forming an ONO layer, a polycrystalline silicon layer and an insulating layer in each first through hole in the direction from the edge of the first through hole to the interior of the first through hole; forming a source conductive pillar and a drain conductive pillar in each of the first shallow trench isolation structures on two sides of each first through hole; etching the edges of the several control gate layers and the several gate isolation oxide layers to form a stepped shape; connecting the drain conductive pillars in the same row to form a first bit line, and connecting the source conductive pillars in the same row to form a second bit line; and connecting the control gate layers in the same layer to form a word line.

Description

Three-dimensional flash memory device and method for forming the same Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional flash memory device and a method for forming the same. Background Art

[0002] Flash memory, a special structure of electrically erasable and programmable read-only memory, has now occupied most of the market share of non-volatile semiconductor memory and has become the fastest-growing non-volatile semiconductor memory.

[0003] In the prior art, the structure of NOR Flash memory is generally planar, and the planar structure is limited by the process node, resulting in a limited density of flash memory cells in the flash memory device, thereby making the flash memory device less integrated and larger in size. Summary of the Invention

[0004] An object of the present invention is to provide a method for forming a three-dimensional flash memory device, so as to improve the integration of the flash memory device.

[0005] In order to achieve the above object, the present invention provides a method for forming a three-dimensional flash memory device, comprising:

[0006] Providing a substrate, setting a direction perpendicular to a substrate surface and starting from the substrate surface and away from the substrate surface as a Z direction, and setting an X direction and a Y direction perpendicular to each other and parallel to the substrate surface;

[0007] forming a plurality of gate isolation oxide layers and a plurality of control gate layers in sequence and alternately on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers;

[0008] forming a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced apart and alternately arranged in the plurality of control gate layers and the plurality of gate isolation oxide layers, wherein each of the first shallow trench isolation structures and the second shallow trench isolation structures vertically penetrates the plurality of control gate layers and the plurality of gate isolation oxide layers, and each of the first shallow trench isolation structures and the second shallow trench isolation structures extends along the Y direction;

[0009] forming a plurality of first through holes in the first shallow trench isolation structure, wherein a sidewall of the control gate layer is exposed in each of the first through holes;

[0010] forming an ONO layer, a polysilicon layer, and an insulating layer in sequence in each of the first through holes along a direction from an edge of the first through hole to an interior of the first through hole, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate;

[0011] forming a source conductive column and a drain conductive column in the first shallow trench isolation structure on both sides of each first through hole, respectively, wherein the source conductive column and the drain conductive column in the same first through hole are both connected to the polysilicon layer in the same first through hole;

[0012] Etching edges of the plurality of control gate layers and the plurality of gate isolation oxide layers in the Y direction so that the lengths of the plurality of gate isolation oxide layers and the plurality of control gate layers in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape;

[0013] Connecting drain conductive pillars in the same row in the X direction to form a first bit line, and connecting source conductive pillars in the same row in the X direction to form a second bit line;

[0014] The control gate layers of the same layer are connected in the X direction to form word lines.

[0015] Optionally, in the method for forming a three-dimensional flash memory device, the cross-section of the first through hole is elliptical, the major axis of the ellipse is arranged along the X direction, and the minor axis of the ellipse is arranged along the Y direction.

[0016] Optionally, in the method for forming the three-dimensional flash memory device, a method for forming a plurality of first shallow trench isolation structures and second shallow trench isolation structures that are spaced and alternately arranged in a plurality of control gate layers and a plurality of gate isolation oxide layers includes:

[0017] forming a nitride layer on the surface of the top gate isolation oxide layer;

[0018] Etching a plurality of gate isolation oxide layers and a plurality of control gate layers from the surface of the nitride layer downward in sequence to form a plurality of first shallow trenches and second shallow trenches spaced apart and alternately arranged in the plurality of gate isolation oxide layers and the plurality of control gate layers;

[0019] Filling the first shallow trench and the second shallow trench with oxide and grinding the oxide to form a plurality of first shallow trench isolation structures and second shallow trench isolation structures that are spaced apart and alternately arranged;

[0020] The nitride layer is removed.

[0021] Optionally, in the method for forming a three-dimensional flash memory device, the length of the first shallow trench isolation structure in the X direction is greater than or equal to the width of the second shallow trench isolation structure in the X direction.

[0022] Optionally, in the method for forming a three-dimensional flash memory device, the cross-sections of the first shallow trench isolation structure and the second shallow trench isolation structure are both rectangular, with the length of the rectangle being arranged along the Y direction and the width being arranged along the X direction.

[0023] Optionally, in the method for forming the three-dimensional flash memory device, the method of respectively forming a source conductive pillar and a drain conductive pillar in the first shallow trench isolation structure on both sides of each first through hole includes:

[0024] Etching the first shallow trench isolation structure and the ONO layer on the first side of the first through hole to form a second through hole, wherein the second through hole exposes the sidewall of the polysilicon gate layer;

[0025] The first shallow trench isolation structure and the ONO layer on the second side of the first through hole are etched to form a third through hole, wherein the third through hole exposes the sidewall of the polysilicon gate layer, and the first side and the second side are located on both sides of the first through hole in the Y direction.

[0026] Optionally, in the method for forming the three-dimensional flash memory device, the method for connecting control gate layers of the same layer in the X direction to form word lines includes: connecting all control gate layers of the same layer as one word line.

[0027] Optionally, in the method for forming the three-dimensional flash memory device, the method for connecting the control gate layers of the same layer in the X direction to form word lines includes: dividing all control gate layers in the X direction into first control gate layers and second control gate layers that are alternately arranged, connecting all first control gate layers as first word lines, and connecting all second control gate layers as second word lines.

[0028] Optionally, in the method for forming the three-dimensional flash memory device, the method of connecting drain conductive pillars in the same row in the X direction to form a first bit line and connecting source conductive pillars in the same row in the X direction to form a second bit line includes:

[0029] forming plugs on all drain conductive pillars;

[0030] A metal layer is formed on the plug and etched to form a plurality of metal lines. One metal line connects drain conductive pillars in the same row to form a first bit line. Another metal line connects source conductive pillars in the same row in the X direction to form a second bit line.

[0031] Optionally, in the method for forming a three-dimensional flash memory device, a metal line connects control gate layers of the same layer in the X direction to form a word line.

[0032] Accordingly, the present invention further provides a three-dimensional flash memory device formed using the above-mentioned method for forming a three-dimensional flash memory device, comprising:

[0033] A substrate, wherein a direction perpendicular to a substrate surface and starting from the substrate surface and moving away from the substrate surface is set as a Z direction, and an X direction and a Y direction perpendicular to each other are set parallel to the substrate surface;

[0034] A plurality of gate isolation oxide layers and a plurality of control gate layers are sequentially and alternately formed on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers, and the lengths of the plurality of gate isolation oxide layers and the plurality of control gate layers in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape;

[0035] a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced and alternately arranged within the plurality of control gate layers and the plurality of gate isolation oxide layers, wherein each of the first shallow trench isolation structure and the second shallow trench isolation structure vertically penetrates the plurality of control gate layers and the plurality of gate isolation oxide layers, and each of the first shallow trench isolation structure and the second shallow trench isolation structure extends along the Y direction;

[0036] a plurality of first through holes located in the first shallow trench isolation structure, an ONO layer, a polysilicon layer, and an insulating layer located in the first through holes and sequentially formed along the edge of the first through holes to the interior of the first through holes, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate;

[0037] a source conductive pillar and a drain conductive pillar respectively located in the first shallow trench isolation structure on both sides of each first through hole, wherein the source conductive pillar and the drain conductive pillar in the same first through hole are both connected to the polysilicon layer in the same first through hole;

[0038] A first bit line connects drain conductive pillars located in the same row in the X direction;

[0039] A second bit line connects the source conductive pillars in the same row in the X direction;

[0040] The word line connects the control gate layers of the same layer in the X direction.

[0041] In the three-dimensional flash memory device and the formation method thereof provided by the present invention, the formation method includes: providing a substrate, setting a direction perpendicular to the substrate surface and starting from the substrate surface and away from the substrate surface as the Z direction, and setting mutually perpendicular X and Y directions parallel to the substrate surface; sequentially and alternately forming a plurality of gate isolation oxide layers and a plurality of control gate layers on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers; forming a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced and alternately arranged in the plurality of control gate layers and the plurality of gate isolation oxide layers, wherein each of the first shallow trench isolation structures and the second shallow trench isolation structures vertically penetrates the plurality of control gate layers and the plurality of gate isolation oxide layers, and each of the first shallow trench isolation structures and the second shallow trench isolation structures extends along the Y direction; forming a plurality of first through holes in the first shallow trench isolation structure, wherein each first through hole exposes a plurality of first through holes. The method includes: forming a sidewall of the control gate layer; sequentially forming an ONO layer, a polysilicon layer, and an insulating layer in each first through hole along the direction from the edge of the first through hole to the interior of the first through hole, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; forming a source conductive pillar and a drain conductive pillar in the first shallow trench isolation structure on both sides of each first through hole, wherein the source conductive pillar and the drain conductive pillar in the same first through hole are both connected to the polysilicon layer in the same first through hole; etching the edges of the control gate layer and the gate isolation oxide layer in the Y direction so that the lengths of the gate isolation oxide layer and the control gate layer in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; connecting the drain conductive pillars in the same row in the X direction to form a first bit line, connecting the source conductive pillars in the same row in the X direction to form a second bit line; and connecting the control gate layers in the same layer in the X direction to form a word line.The three-dimensional flash memory device includes: a substrate, a direction perpendicular to the substrate surface and starting from the substrate surface and moving away from the substrate surface is defined as a Z direction, and mutually perpendicular X and Y directions are provided parallel to the substrate surface; a plurality of gate isolation oxide layers and a plurality of control gate layers are sequentially and alternately formed on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers, and the lengths of the plurality of gate isolation oxide layers and the plurality of control gate layers in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; a plurality of first shallow trench isolation structures and second shallow trench isolation structures are spaced and alternately provided within the plurality of control gate layers and the plurality of gate isolation oxide layers, wherein each of the first shallow trench isolation structures and the second shallow trench isolation structure vertically penetrates the plurality of control gate layers and the plurality of gate isolation oxide layers. Each first shallow trench isolation structure and second shallow trench isolation structure extends along the Y direction; a plurality of first through holes are located within the first shallow trench isolation structure; an ONO layer, a polysilicon layer, and an insulating layer are sequentially formed within the first through holes and along the edge of the first through holes to the interior of the first through holes, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; source conductive pillars and drain conductive pillars are located within the first shallow trench isolation structure on both sides of each first through hole, and the source conductive pillars and drain conductive pillars within the same first through hole are both connected to the polysilicon layer within the same first through hole; a first bit line connects drain conductive pillars in the same row in the X direction; a second bit line connects source conductive pillars in the same row in the X direction; and a word line connects control gate layers in the same layer in the X direction. The present invention makes the flash memory device three-dimensional, thereby improving the integration of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] 1 is a flow chart of a method for forming a three-dimensional flash memory device according to an embodiment of the present invention;

[0043] 2 is a schematic longitudinal cross-sectional view of a three-dimensional flash memory device after forming a fourth gate isolation oxide layer according to an embodiment of the present invention;

[0044] 3 is a schematic longitudinal cross-sectional view of a three-dimensional flash memory device after forming a first shallow trench isolation structure and a second shallow trench isolation structure according to an embodiment of the present invention;

[0045] 4 is a top view of a three-dimensional flash memory device after forming a first shallow trench isolation structure and a second shallow trench isolation structure according to an embodiment of the present invention;

[0046] 5 is a top view of a three-dimensional flash memory device after forming a source conductive pillar and a drain conductive pillar according to an embodiment of the present invention;

[0047] 6 is a schematic longitudinal cross-sectional view of a three-dimensional flash memory device after etching the control gate and the end of the gate isolation oxide layer according to an embodiment of the present invention;

[0048] 7 is a top view of a three-dimensional flash memory device after forming a plug according to an embodiment of the present invention;

[0049] 8 is a schematic longitudinal cross-sectional view of a three-dimensional flash memory device after forming a plug according to an embodiment of the present invention;

[0050] In the figure: 110-substrate, 121-first gate isolation oxide layer, 122-second gate isolation oxide layer, 123-third gate isolation oxide layer, 124-fourth gate isolation oxide layer, 131-first control gate layer, 132-second control gate layer, 133-third control gate layer, 140-nitride layer, 151-first shallow trench isolation structure, 152-second shallow trench isolation structure, 161-ONO layer, 162-polysilicon channel layer, 163-fifth oxide layer, 171-source conductive column, 172-drain conductive column, 180-plug. DETAILED DESCRIPTION

[0051] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0052] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0053] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0054] Referring to FIG. 1 , the present invention provides a method for forming a three-dimensional flash memory device, comprising:

[0055] S11: providing a substrate, setting a direction perpendicular to a substrate surface and starting from the substrate surface and away from the substrate surface as a Z direction, and setting an X direction and a Y direction perpendicular to each other and parallel to the substrate surface;

[0056] S12: sequentially and alternately forming a plurality of gate isolation oxide layers and a plurality of control gate layers on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers;

[0057] S13: forming a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced apart and alternately arranged in the plurality of control gate layers and the plurality of gate isolation oxide layers, wherein each of the first shallow trench isolation structures and the second shallow trench isolation structure vertically penetrates the plurality of control gate layers and the plurality of gate isolation oxide layers, and each of the first shallow trench isolation structures and the second shallow trench isolation structure extends along the Y direction;

[0058] S14: forming a plurality of first through holes in the first shallow trench isolation structure, wherein a sidewall of the control gate layer is exposed in each of the first through holes;

[0059] S15: forming an ONO layer, a polysilicon layer, and an insulating layer in sequence in each first through hole along a direction from an edge of the first through hole to an interior of the first through hole, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact a surface of the substrate;

[0060] S16: forming a source conductive pillar and a drain conductive pillar in the first shallow trench isolation structure on both sides of each first through hole, respectively, wherein the source conductive pillar and the drain conductive pillar in the same first through hole are both connected to the polysilicon layer in the same first through hole;

[0061] S17: etching edges of the plurality of control gate layers and the plurality of gate isolation oxide layers in the Y direction, so that the lengths of the plurality of gate isolation oxide layers and the plurality of control gate layers in the Y direction decrease sequentially along the Z direction, thereby forming a stepped shape;

[0062] S18: Connecting drain conductive pillars in the same row in the X direction to form a first bit line, and connecting source conductive pillars in the same row in the X direction to form a second bit line;

[0063] S19: Connecting control gate layers of the same layer in the X direction to form word lines.

[0064] Referring to Figure 2, first, a substrate 110 is provided. The substrate 110 can be a wafer. A direction perpendicular to the surface of the substrate 110 and extending away from the surface of the substrate 110 is defined as the Z direction. Mutually perpendicular X and Y directions are defined parallel to the surface of the substrate 110. Next, a plurality of gate isolation oxide layers and a plurality of control gate layers are sequentially and alternately formed on the substrate 110. The first and top layers are both gate isolation oxide layers. Specifically, the embodiment of the present invention uses four gate isolation oxide layers and three control gate layers as an example. In other embodiments of the present invention, other numbers of gate isolation oxide layers and control gate layers may also be used. Therefore, after providing the substrate 110, the steps are to sequentially form a first gate isolation oxide layer 121, a first control gate layer 131, a second gate isolation oxide layer 122, a second control gate layer 132, a third gate isolation oxide layer 123, a third control gate layer 133, and a fourth gate isolation oxide layer 124 on the substrate 110. The first gate isolation oxide layer 121, the second gate isolation oxide layer 122, the third gate isolation oxide layer 123, and the fourth gate isolation oxide layer 124 may all be silicon dioxide. The first control gate layer 131, the second control gate layer 132, and the third control gate layer 133 may all be polysilicon. Next, a nitride layer 140 is formed on the surface of the fourth gate isolation oxide layer 124. The nitride layer 140 may be silicon nitride.

[0065] Next, referring to Figures 3 and 4, starting from the surface of the nitride layer 140, the nitride layer 140, the fourth gate isolation oxide layer 124, the third control gate layer 133, the third gate isolation oxide layer 123, the second control gate layer 132, the second gate isolation oxide layer 122, the first control gate layer 131, and the first gate isolation oxide layer 121 are sequentially etched downward to expose the surface of the substrate 110, thereby forming a plurality of shallow trenches spaced apart in the first gate isolation oxide layer 121, the first control gate layer 131, the second gate isolation oxide layer 122, the second control gate layer 132, the third gate isolation oxide layer 123, the third control gate layer 133, the fourth gate isolation oxide layer 124, and the nitride layer 140. In this embodiment of the present invention, the plurality of shallow trenches are divided into first shallow trenches and second shallow trenches, and the first shallow trenches and the second shallow trenches are alternately arranged. The first shallow trenches and the second shallow trenches both extend along the Y direction, and the cross-sections of the first shallow trenches and the second shallow trenches are both rectangular, with the length along the Y direction and the width along the X direction. In the X-direction, the width of the first shallow trench is greater than or equal to the width of the second shallow trench. Next, the first and second shallow trenches are filled with an oxide, such as silicon dioxide, and the silicon dioxide is polished to form a first shallow trench isolation structure 151 and a second shallow trench isolation structure 152. In this formation step, the nitride layer 140 serves as a barrier layer for polishing the silicon dioxide. After forming the first and second shallow trench isolation structures 151, 152, the nitride layer 140 is removed. In the X-direction, the width of the first shallow trench isolation structure 151 is greater than or equal to the width of the second shallow trench isolation structure 152. In this embodiment of the present invention, three first shallow trench isolation structures 151 and two second shallow trench isolation structures 152 are formed, and the three first shallow trench isolation structures 151 and the two second shallow trench isolation structures 152 are arranged alternately. In other embodiments of the present invention, other numbers of first shallow trench isolation structures 151 and second shallow trench isolation structures 152 may be used.

[0066] Next, referring to FIG. 5 , the first shallow trench isolation structure 151 is etched downward from its surface. This forms a first through-hole in the first shallow trench isolation structure 151, exposing the surface of the substrate 110 and the sidewalls of the first control gate layer 131, the second control gate layer 132, and the third control gate layer 133. The first through-hole has an elliptical cross-section, with its major axis extending along the X-direction and its minor axis extending along the Y-direction. Therefore, the first through-hole can partially etch the first gate isolation oxide layer 121, the first control gate layer 131, the second gate isolation oxide layer 122, the second control gate layer 132, the third gate isolation oxide layer 123, the third control gate layer 133, and the fourth gate isolation oxide layer 124 in the X-direction. Since there are several first shallow trench isolation structures 151, the embodiment of the present invention selects multiple first shallow trench isolation structures 151 as an example, and selects three first through holes on each first shallow trench isolation structure 151 as an example, so there will be many first through holes, so multiple first through holes can be arranged in the form of an array.

[0067] Next, referring to Figure 5, an ONO layer 161, a polysilicon channel layer 162, and a fifth oxide layer 163 are sequentially formed in the first through hole. The ONO layer 161 is a stack of silicon oxide, silicon nitride, and silicon oxide, so a layer of oxide can be first formed to cover the inner wall of the first through hole, and then a layer of silicon nitride can be formed to cover the sidewalls formed by the silicon oxide. Finally, another layer of silicon oxide can be formed to cover the sidewalls formed by the silicon nitride. The ONO layer at the bottom of the first through hole is removed by etching to expose the surface of the substrate 110, and finally the ONO layer 161 is formed. Next, a polysilicon channel layer 162 is formed to cover the sidewalls formed by the ONO layer 161, and finally, silicon dioxide is filled into the through hole formed by the polysilicon channel layer 162 to form the fifth oxide layer 163. The material of the polysilicon channel layer 162 can be polysilicon.

[0068] Next, referring to Figure 5 , a portion of the thickness of the first shallow trench isolation structure 151 is etched downward on the surface of the first shallow trench isolation structure 151 on both sides of the first through-hole. At the same time, a portion of the ONO layer 161 in the first through-hole can be etched, so that the sidewalls of the polysilicon channel layer 162 are exposed in both the second through-hole and the third through-hole. The depth of the second through-hole and the third through-hole is not limited and is determined based on actual production conditions. Next, doped polysilicon is filled into both the second through-hole and the third through-hole to form a source conductive pillar 171 and a drain conductive pillar 172. The source conductive pillar 171 and the drain conductive pillar 172 are respectively connected to the polysilicon channel layer 162.

[0069] Since the first shallow trench isolation structure 151 and the second shallow trench isolation structure 152 separate the first gate isolation oxide layer 121, the first control gate layer 131, the second gate isolation oxide layer 122, the second control gate layer 132, the third gate isolation oxide layer 123, the third control gate layer 133 and the fourth gate isolation oxide layer 124, the first gate isolation oxide layer 121, the first control gate layer 131, the second gate isolation oxide layer 122, the second control gate layer 132, the third gate isolation oxide layer 123, the third control gate layer 133 and the fourth gate isolation oxide layer 124 are also divided into multiple strips, and the strips extend along the Y direction. Next, referring to FIG6 , the present invention etches the ends of the plurality of strip-shaped first gate isolation oxide layer 121, first control gate layer 131, second gate isolation oxide layer 122, second control gate layer 132, third gate isolation oxide layer 123, third control gate layer 133, and fourth gate isolation oxide layer 124, exposing the ends of the first control gate layer 131, second control gate layer 132, and third control gate layer 133, thereby forming a stepped shape in the Z and Y directions. Specifically, the steps may include first etching a portion (length in the Y direction) of the fourth gate isolation oxide layer 124 to expose the surface of the end of the third control gate layer 133. Next, etching a portion of the third control gate layer 133 and the third gate isolation oxide layer 123 to expose the surface of the end of the second control gate layer 132. Next, etching a portion of the second control gate layer 132 and the second gate isolation oxide layer 122 to expose the surface of the end of the first control gate layer 131. This exposes the ends of the first control gate layer 131, the second control gate layer 132, and the third control gate layer 133 for subsequent plug formation. The specific length of the exposure is determined by the size and number of the plugs to be formed.

[0070] Next, referring to Figures 7 and 8, plugs 180 are formed on all source conductive pillars 171 and drain conductive pillars 172, as well as the exposed multiple strips of the first control gate layer 131, the second control gate layer 132, and the third control gate layer 133. The method for forming the plugs 180 can be to deposit a dielectric layer, then etch the interlayer dielectric layer to form a through hole, then fill the through hole with metal to form the plug 180, and finally remove the dielectric layer. Next, a metal layer is formed and etched to form multiple metal lines. More specific steps are not described here. One of the metal lines connects the plugs 180 of the source conductive pillars 171 in the same row as the first bit line, and one of the metal lines connects the plugs 180 of the drain conductive pillars 172 in the same row as the second bit line. Therefore, according to this method, multiple first and second bit lines are formed. The first and second bit lines extend in the X direction.

[0071] Next, word lines are formed. Two embodiments are possible. In the first embodiment, a metal line is used to connect all plugs 180 in the first control gate layer 131 to form a word line, all plugs 180 in the second control gate layer 132 to form a word line, and all plugs 180 in the third control gate layer 133 to form a word line. In the second embodiment, a metal line is used to connect every other plug 180 in the first control gate layer 131 to form a word line, and a metal line is used to connect the remaining plugs 180 in the first control gate layer 131 to form a word line. A metal line is used to connect every other plug 180 in the second control gate layer 132 to form a word line, and a metal line is used to connect the remaining plugs 180 in the second control gate layer 132 to form a word line. A metal line is used to connect every other plug 180 in the third control gate layer 133 to form a word line, and a metal line is used to connect the remaining plugs 180 in the third control gate layer 133 to form a word line. That is, if the first shallow trench isolation structure 151 and the second shallow trench isolation structure 152 divide the first control gate layer 131, the second control gate layer 132, and the third control gate layer 133 into multiple strips, then in the second embodiment, a metal line can connect the plugs 180 on the first strip, the third strip, and the fifth strip of the first control gate layer 131 together as a word line. A metal line can connect the plugs 180 on the second strip, the fourth strip, and the sixth strip of the first control gate layer 131 together as a word line. A metal line can connect the plugs 180 on the first strip, the third strip, and the fifth strip of the second control gate layer 132 together as a word line. A metal line can connect the plugs 180 on the second strip, the fourth strip, and the sixth strip of the second control gate layer 132 together as a word line. A metal line can connect the plugs 180 on the first strip, the third strip, and the fifth strip of the third control gate layer 133 together as a word line. A metal line can connect the plugs 180 on the second, fourth, and sixth strips of the third control gate layer 133 to form a word line. Therefore, the plug 180 on the first strip of the first control gate layer 131 and the plug 180 on the adjacent second strip of the first control gate layer 131 are not aligned. Similarly, the plugs 180 on the remaining adjacent strips of the first control gate layer 131 are not aligned. The same applies to the second control gate layer 132 and the third control gate layer 133.

[0072] Accordingly, the present invention also provides a three-dimensional flash memory device formed by the above-mentioned method for forming a three-dimensional flash memory device, comprising: a substrate, wherein a direction perpendicular to the substrate surface and starting from the substrate surface and away from the substrate surface is set as a Z direction, and an X direction and a Y direction perpendicular to each other are set in parallel to the substrate surface; a plurality of gate isolation oxide layers and a plurality of control gate layers formed sequentially and alternately on the substrate, the first layer and the top layer are both gate isolation oxide layers, and the lengths of the plurality of gate isolation oxide layers and the plurality of control gate layers in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced and alternately arranged within the plurality of control gate layers and the plurality of gate isolation oxide layers, each of the first shallow trench isolation structures and the second shallow trench isolation structure vertically penetrating the plurality of layers. A control gate layer and several gate isolation oxide layers, each of the first shallow trench isolation structure and the second shallow trench isolation structure extending along the Y direction; several first through holes located within the first shallow trench isolation structure; an ONO layer, a polysilicon layer, and an insulating layer located within the first through holes and sequentially formed from the edge of the first through hole to the interior of the first through hole, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; source conductive pillars and drain conductive pillars located within the first shallow trench isolation structure on both sides of each first through hole, respectively; the source conductive pillars and drain conductive pillars within the same first through hole are both connected to the polysilicon layer within the same first through hole; a first bit line connecting drain conductive pillars located in the same row in the X direction; a second bit line connecting source conductive pillars located in the same row in the X direction; and a word line connecting control gate layers of the same layer in the X direction.

[0073] There are multiple first shallow trench isolation structures and multiple second shallow trench isolation structures, and the width of the first shallow trench isolation structure in the X direction is greater than or equal to the width of the second shallow trench isolation structure in the X direction. There are multiple first through holes, source conductive pillars, and drain conductive pillars in the first shallow trench isolation structure.

[0074] In summary, in the method for forming a three-dimensional flash memory device provided in an embodiment of the present invention, the formation method includes: providing a substrate, setting a direction perpendicular to the substrate surface and starting from the substrate surface along the direction away from the substrate surface as the Z direction, and setting mutually perpendicular X and Y directions parallel to the substrate surface; sequentially and alternately forming a plurality of gate isolation oxide layers and a plurality of control gate layers on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers; forming a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced and alternately arranged in the plurality of control gate layers and the plurality of gate isolation oxide layers, each of the first shallow trench isolation structures and the second shallow trench isolation structures vertically penetrating the plurality of control gate layers and the plurality of gate isolation oxide layers, and each of the first shallow trench isolation structures and the second shallow trench isolation structures extends along the Y direction; forming a plurality of first through holes in the first shallow trench isolation structure, each of the first through holes The method comprises: exposing a sidewall of the control gate layer; sequentially forming an ONO layer, a polysilicon layer, and an insulating layer in each first through hole along the direction from the edge of the first through hole to the interior of the first through hole, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; forming a source conductive pillar and a drain conductive pillar in the first shallow trench isolation structure on both sides of each first through hole, wherein the source conductive pillar and the drain conductive pillar in the same first through hole are both connected to the polysilicon layer in the same first through hole; etching edges of the control gate layer and the gate isolation oxide layer in the Y direction so that the lengths of the gate isolation oxide layer and the control gate layer in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; connecting the drain conductive pillars in the same row in the X direction to form a first bit line, connecting the source conductive pillars in the same row in the X direction to form a second bit line; and connecting the control gate layers in the same layer in the X direction to form a word line.The three-dimensional flash memory device includes: a substrate, a direction perpendicular to the substrate surface and starting from the substrate surface and moving away from the substrate surface is defined as a Z direction, and mutually perpendicular X and Y directions are provided parallel to the substrate surface; a plurality of gate isolation oxide layers and a plurality of control gate layers are sequentially and alternately formed on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers, and the lengths of the plurality of gate isolation oxide layers and the plurality of control gate layers in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; a plurality of first shallow trench isolation structures and second shallow trench isolation structures are spaced and alternately provided within the plurality of control gate layers and the plurality of gate isolation oxide layers, wherein each of the first shallow trench isolation structures and the second shallow trench isolation structure vertically penetrates the plurality of control gate layers and the plurality of gate isolation oxide layers. Each first shallow trench isolation structure and second shallow trench isolation structure extends along the Y direction; a plurality of first through holes are located within the first shallow trench isolation structure; an ONO layer, a polysilicon layer, and an insulating layer are sequentially formed within the first through holes and along the edge of the first through holes to the interior of the first through holes, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; source conductive pillars and drain conductive pillars are located within the first shallow trench isolation structure on both sides of each first through hole, and the source conductive pillars and drain conductive pillars within the same first through hole are both connected to the polysilicon layer within the same first through hole; a first bit line connects drain conductive pillars in the same row in the X direction; a second bit line connects source conductive pillars in the same row in the X direction; and a word line connects control gate layers in the same layer in the X direction. The present invention makes the flash memory device three-dimensional, thereby improving the integration of the flash memory device.

[0075] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for forming a three-dimensional flash memory device, characterized in that: include: Providing a substrate, defining a direction perpendicular to a surface of the substrate and starting from the surface of the substrate and moving away from the surface of the substrate as a Z direction, and defining directions parallel to the surface of the substrate and perpendicular to each other as an X direction and a Y direction; forming a plurality of gate isolation oxide layers and a plurality of control gate layers in sequence and alternately on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers; Forming a plurality of first shallow trench isolation structures and a plurality of second shallow trench isolation structures spaced apart and alternately arranged in the multiple control gate layers and the multiple gate isolation oxide layers, each of the first shallow trench isolation structures and the second shallow trench isolation structures vertically penetrating the multiple control gate layers and the multiple gate isolation oxide layers, and each of the first shallow trench isolation structures and the second shallow trench isolation structures extending along the Y direction; forming a plurality of first through holes in the first shallow trench isolation structure, wherein a sidewall of the control gate layer is exposed in each of the first through holes; forming an ONO layer, a polysilicon layer, and an insulating layer in sequence in each of the first through holes along a direction from an edge of the first through hole to an interior of the first through hole, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; forming a source conductive column and a drain conductive column in the first shallow trench isolation structure on both sides of each first through hole, respectively, wherein the source conductive column and the drain conductive column in the same first through hole are both connected to the polysilicon layer in the same first through hole; Etching the edges of the multi-layer control gate layer and the multi-layer gate isolation oxide layer in the Y direction so that the lengths of the multi-layer gate isolation oxide layer and the multi-layer control gate layer in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; Connecting drain conductive pillars in the same row in the X direction to form a first bit line, and connecting source conductive pillars in the same row in the X direction to form a second bit line; The control gate layers of the same layer are connected in the X direction to form word lines.

2. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The cross section of the first through hole is elliptical, the major axis of the ellipse is arranged along the X direction, and the minor axis of the ellipse is arranged along the Y direction.

3. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The method of forming a plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced apart and alternately arranged in a multi-layer control gate layer and a multi-layer gate isolation oxide layer comprises: forming a nitride layer on the surface of the top gate isolation oxide layer; Etching the multiple gate isolation oxide layers and the multiple control gate layers in sequence downward from the surface of the nitride layer to form a plurality of first shallow trenches and second shallow trenches spaced apart and alternately arranged in the multiple gate isolation oxide layers and the multiple control gate layers; Filling the first shallow trench and the second shallow trench with oxide and grinding the oxide to form a plurality of first shallow trench isolation structures and second shallow trench isolation structures that are spaced apart and alternately arranged; The nitride layer is removed.

4. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The length of the first shallow trench isolation structure in the X direction is greater than the width of the second shallow trench isolation structure in the X direction.

5. [Corrected 09.12.2024 according to Rule 26] The method for forming a three-dimensional flash memory device according to claim 1, characterized in that: The length of the first shallow trench isolation structure in the X direction is equal to the width of the second shallow trench isolation structure in the X direction.

6. [Corrected 09.12.2024 according to Rule 26] The method for forming a three-dimensional flash memory device according to claim 1, characterized in that: The cross-sections of the first shallow trench isolation structure and the second shallow trench isolation structure are both rectangular, with the length of the rectangle being arranged along the Y direction and the width being arranged along the X direction.

7. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The method of forming a source conductive pillar and a drain conductive pillar in the first shallow trench isolation structure on both sides of each first through hole includes: Etching the first shallow trench isolation structure and the ONO layer on the first side of the first through hole to form a second through hole, wherein the second through hole exposes the sidewall of the polysilicon gate layer; The first shallow trench isolation structure and the ONO layer on the second side of the first through hole are etched to form a third through hole, wherein the third through hole exposes the sidewall of the polysilicon gate layer, and the first side and the second side are located on both sides of the first through hole in the Y direction.

8. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The method of connecting the control gate layers of the same layer in the X direction to form a word line includes: connecting all the control gate layers of the same layer to form a word line.

9. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The method for connecting the control gate layers of the same layer in the X direction to form word lines includes: dividing all the control gate layers in the X direction into first control gate layers and second control gate layers that are alternately arranged, connecting all the first control gate layers to form a first word line, and connecting all the second control gate layers to form a second word line.

10. The method for forming a three-dimensional flash memory device according to claim 1, wherein: The method of connecting drain conductive pillars in the same row in the X direction to form a first bit line and connecting source conductive pillars in the same row in the X direction to form a second bit line includes: forming plugs on all drain conductive pillars; A metal layer is formed on the plug, and the metal layer is etched to form a plurality of metal lines. One of the plurality of metal lines connects the drain conductive pillars in the same row to form a first bit line, and another one of the plurality of metal lines connects the source conductive pillars in the same row in the X direction to form a second bit line.

11. The method for forming a three-dimensional flash memory device according to claim 10, wherein: Another one of the plurality of metal lines connects the control gate layer of the same layer in the X direction to form a word line.

12. A three-dimensional flash memory device formed using the method for forming a three-dimensional flash memory device according to claim 1, characterized in that: include: a substrate, a direction perpendicular to a surface of the substrate and starting from the surface of the substrate and moving away from the surface of the substrate is defined as a Z direction, and directions parallel to the surface of the substrate and perpendicular to each other are defined as an X direction and a Y direction; Multiple gate isolation oxide layers and multiple control gate layers are sequentially and alternately formed on the substrate, wherein the first layer and the top layer are both gate isolation oxide layers, and the lengths of the multiple gate isolation oxide layers and the multiple control gate layers in the Y direction decrease sequentially along the Z direction, thereby presenting a stepped shape; A plurality of first shallow trench isolation structures and second shallow trench isolation structures spaced and alternately arranged within the multi-layer control gate layer and the multi-layer gate isolation oxide layer, each of the first shallow trench isolation structure and the second shallow trench isolation structure vertically penetrating the multi-layer control gate layer and the multi-layer gate isolation oxide layer, and each of the first shallow trench isolation structure and the second shallow trench isolation structure extending along the Y direction; a plurality of first through holes located in the first shallow trench isolation structure, an ONO layer, a polysilicon layer, and an insulating layer located in the first through holes and sequentially formed along the edge of the first through holes to the interior of the first through holes, wherein the ONO layer, the polysilicon layer, and the insulating layer all contact the surface of the substrate; a source conductive pillar and a drain conductive pillar respectively located in the first shallow trench isolation structure on both sides of each first through hole, wherein the source conductive pillar and the drain conductive pillar in the same first through hole are both connected to the polysilicon layer in the same first through hole; a first bit line connecting drain conductive pillars in the same row in the X direction; a second bit line connecting the source conductive pillars in the same row in the X direction; The word line connects the control gate layers of the same layer in the X direction.

13. The three-dimensional flash memory device according to claim 12, wherein: The cross section of the first through hole is elliptical, the major axis of the ellipse is arranged along the X direction, and the minor axis of the ellipse is arranged along the Y direction.

14. The three-dimensional flash memory device according to claim 12, wherein: The length of the first shallow trench isolation structure in the X direction is greater than the width of the second shallow trench isolation structure in the X direction.

15. The three-dimensional flash memory device according to claim 12, wherein: The length of the first shallow trench isolation structure in the X direction is equal to the width of the second shallow trench isolation structure in the X direction.

16. The three-dimensional flash memory device according to claim 12, wherein: The cross-sections of the first shallow trench isolation structure and the second shallow trench isolation structure are both rectangular, with the length of the rectangle being arranged along the Y direction and the width being arranged along the X direction.

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