Reading method, writing method and erasing method for memory

Abstract

A reading method, a writing method and an erasing method for a memory. The reading method comprises: performing a first reading operation to acquire a first reading result, the first reading operation comprising: applying a first voltage to a second word line connected to a first selection transistor and a second selection transistor in a memory cell for reading, applying a second voltage to a first word line and a third word line connected to a first storage transistor and a second storage transistor, and acquiring the first reading result; when the first reading result represents stored data in the first storage transistor and the second storage transistor, ending the reading operation; and, when the first reading result does not represent the stored data in the first storage transistor and the second storage transistor, performing a second reading operation to acquire a second reading result. The present application acquires at a bit line end a first reading current on the bit line end, so as to read stored data on the first storage transistor and the second storage transistor at the same time, thereby reducing reading disturbances of storage transistors.

Description

Memory read, write, and erase methods

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 19, 2024, with application number 202410186079.5 and invention name “Method for reading, writing and erasing memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for reading, writing and erasing a memory. Background Art

[0003] SONOS (Silicon Oxide Nitride Oxide Silicon) technology is structurally categorized into single-gate, split-gate, and dual-gate technologies. With the advancement of mainstream process technologies and the increasing demand for Flash devices, split-gate Flash memory based on a split-gate structure has attracted widespread attention. Compared to traditional Flash, split-gate flash memory, as a type of flash memory, has attracted increasing attention in both single-cell and embedded products due to its efficient programming speed and ability to completely avoid over-erasure.

[0004] However, the storage performance of current split-gate memories needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for reading, writing and erasing a memory, so as to improve the storage performance of a split-gate memory.

[0006] To solve the above technical problem, an embodiment of the present invention provides a method for reading a memory, wherein the memory includes: a plurality of memory cells arranged in an array, the memory cells including a first word line, a second word line, a third word line, and a bit line; a first storage tube, wherein the gate of the first storage tube is connected to the first word line, and one of the source or drain of the first storage tube is connected to the bit line; a first selection tube, wherein the gate of the first selection tube is connected to the second word line, and one of the source or drain of the first selection tube is connected to the other source or drain of the first storage tube; a second selection tube, wherein the gate of the second selection tube is connected to the second word line, and one of the source or drain of the second selection tube is connected to the other source or drain of the first selection tube; a second storage tube, wherein the gate of the second storage tube is connected to the third word line, and one of the source or drain of the second storage tube is connected to the other source or drain of the second selection tube, and the other source or drain of the second storage tube is connected to the bit line, comprising: performing a first read operation , obtaining a first read result, the first read operation including: applying a first voltage to a second word line connected to the first selection tube and the second selection tube in the memory cell to be read, so that the first selection tube and the second selection tube are in a conductive state, applying a second voltage to a first word line and a third word line connected to the first storage tube and the second storage tube, so that a read current is generated in the first storage tube and the second storage tube, obtaining a first read current on a bit line end, and obtaining a first read result based on the first read current; when the first read result is characterized as the stored data on the first storage tube and the second storage tube, ending the read operation; when the first read result is not characterized as the stored data on the first storage tube and the second storage tube, performing a second read operation to obtain a second read result, the second read operation including: continuing to obtain a second read current on the bit line end, obtaining a second read result based on the second read current, and the second read result is characterized as the stored data on the first storage tube and the second storage tube.

[0007] In one possible design, in another implementation of another aspect of the embodiment of the present application, the first read result includes a first current, a second current and a third current, the first current is greater than the second current, and the third current is between the first current and the second current. According to the first read current, obtaining the first read result includes: in response to the first current at the bit line end, the storage data on the first storage tube and the second storage tube are both "0"; in response to the second current at the bit line end, the storage data on the first storage tube and the second storage tube are both "1"; in response to the third current at the bit line end, continuing to obtain the second read result.

[0008] In one possible design, in another implementation of another aspect of the embodiment of the present application, a method for obtaining a second read result based on the second read current includes: applying a third voltage to the third word line end, obtaining a second read current on the bit line end, when the second read current is less than the third current, the storage data on the first storage tube is "1", and the storage data on the second storage tube is "0"; when the second read current is equal to the third current, the storage data on the first storage tube is "0", and the storage data on the second storage tube is "1".

[0009] In one possible design, in another implementation of another aspect of the embodiment of the present application, the reading method further includes: applying a second voltage to the first word line, the second word line, and the third word line connected to the memory cell not to be read, and applying a floating voltage to the bit line connected to the memory cell not to be read.

[0010] The technical solution of the present invention also provides a method for writing to a memory, wherein the memory comprises: a plurality of memory cells arranged in an array, wherein the memory cells comprise a first word line, a second word line, a third word line, and a bit line; a first storage tube, wherein the gate of the first storage tube is connected to the first word line, and one of the source or drain of the first storage tube is connected to the bit line; a first selection tube, wherein the gate of the first selection tube is connected to the second word line, and one of the source or drain of the first selection tube is connected to the other source or drain of the first storage tube; a second selection tube, wherein the gate of the second selection tube is connected to the second word line, and one of the source or drain of the second selection tube is connected to the other source or drain of the first selection tube; a second storage tube, wherein the gate of the second storage tube is connected to the third word line, and one of the source or drain of the second storage tube is connected to the other source or drain of the second selection tube, and the second storage tube Another source or drain of the transistor is connected to the bit line, including: performing a first write operation, the first write operation method including: applying a first write negative voltage to the second word line connected to the memory cell to be written, applying a write positive voltage to the first word line or the third word line connected to the memory cell to be written, applying a first write negative voltage to the bit line connected to the memory cell to be written, so that a write current is generated in the memory cell to be written, so as to perform the first write operation on any row of memory cells in the memory, obtain a write start voltage on the memory cell to be written, and compare the write start voltage with a preset write start voltage; when the write start voltage is within the preset write start voltage, it is determined that the write operation is completed; when the write start voltage is not within the preset write start voltage, a second write operation is performed, the second write operation including: repeating the first write operation until the write start voltage is within the preset write start voltage.

[0011] In one possible design, in another implementation of another aspect of the embodiment of the present application, the write-start voltage includes a first write-start voltage, the preset write-start voltage includes a first preset write-start voltage, and the method of obtaining the write-start voltage on the storage unit to be written and comparing the write-start voltage with the preset write-start voltage includes: after writing data "1", obtaining the first write-start voltage on the storage unit to be written, comparing the first write-start voltage with the first preset write-start voltage, when the first write-start voltage is greater than the first preset write-start voltage, the operation of writing data "1" is completed, and when the first write-start voltage is less than or equal to the first preset write-start voltage, repeating the first write operation until the first write-start voltage is greater than the first preset write-start voltage.

[0012] In one possible design, in another implementation of another aspect of the embodiment of the present application, the write-start voltage includes a second write-start voltage, the preset write-start voltage includes a second preset write-start voltage, and the method of obtaining the write-start voltage on the storage unit to be written and comparing the write-start voltage with the preset write-start voltage also includes: after writing data "0", obtaining the second write-start voltage on the storage unit to be written, comparing the second write-start voltage with the second preset write-start voltage, when the second write-start voltage is less than the second preset write-start voltage, the operation of writing data "0" is completed, and when the second write-start voltage is greater than or equal to the second preset write-start voltage, repeating the first write operation until the second write-start voltage is less than the second preset write-start voltage.

[0013] In one possible design, in another implementation of another aspect of the embodiment of the present application, the write method further includes: applying a first write negative voltage to the second word line connected to the memory cell not to be written, applying a second write negative voltage to the first word line and the third word line connected to the memory cell not to be written, and applying the first write negative voltage to the bit line connected to the memory cell not to be written.

[0014] The technical solution of the present invention also provides a method for erasing a memory, wherein the memory includes: a plurality of memory cells arranged in an array, the memory cells including a first word line, a second word line, a third word line, and a bit line; a first storage tube, wherein the gate of the first storage tube is connected to the first word line, and one of the source or drain of the first storage tube is connected to the bit line; a first selection tube, wherein the gate of the first selection tube is connected to the second word line, and one of the source or drain of the first selection tube is connected to the other source or drain of the first storage tube; a second selection tube, wherein the gate of the second selection tube is connected to the second word line, and one of the source or drain of the second selection tube is connected to the other source or drain of the first selection tube; and a second storage tube, wherein the gate of the second storage tube is connected to the third word line, and one of the source or drain of the second storage tube is connected to the other source or drain of the second selection tube. , the other source or drain of the second storage tube is connected to the bit line, and the erasing method includes: performing a first erasing operation, the first erasing operation including: applying an erase positive voltage to the second word line connected to the memory cell to be erased, applying an erase negative voltage to the first word line or the third word line connected to the memory cell to be erased, applying an erase positive voltage to the bit line BL connected to the memory cell to be erased, performing the first erasing operation on any row of memory cells in the memory, obtaining an erase start voltage on the memory cell to be erased, and comparing the erase start voltage with a preset erase start voltage range; when the erase start voltage is within the preset erase start voltage range, it is determined that the erase operation is completed; when the erase start voltage is not within the preset erase start voltage range, entering a second erasing operation, the second erasing operation including: repeating the first erasing operation until the erase start voltage is within the preset erase start voltage range.

[0015] In one possible design, in another implementation of another aspect of the embodiment of the present application, a method for obtaining an erase start voltage on a memory cell to be erased and comparing the erase start voltage with a preset erase start voltage range includes: if the erase start voltage is greater than the preset erase start voltage range, repeating the first erase operation until the erase start voltage is within the preset erase start voltage range; if the erase start voltage is less than the preset erase start voltage range, applying a positive compaction pressure to the first word line or the third word line connected to the memory cell to be erased until the erase start voltage is within the preset erase start voltage range.

[0016] In one possible design, in another implementation of another aspect of the embodiment of the present application, the erasing method further includes: applying an erasing positive voltage to the second word line, the first word line, the third word line and the bit line connected to the non-erased storage unit.

[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0018] The memory reading method provided by the technical solution of the present invention realizes simultaneous reading of the storage data on the first storage tube and the second storage tube by obtaining a first reading current on the bit line end, thereby improving the reading efficiency of the storage unit and reducing the read interference of the storage tube. In addition, it is determined whether the storage data on the first storage tube and the second storage tube are both read out based on the first reading result. If the storage data on the first storage tube and the second storage tube are not read, the second reading current on the bit line end is continuously obtained. According to the second reading current, the storage data on the first storage tube and the second storage tube are continuously read, thereby ensuring the accuracy of the reading.

[0019] Furthermore, by obtaining different values ​​of the read current at the bit line end, the storage data on the first storage tube and the second storage tube are read, and when the read current cannot clearly determine the storage data on the first storage tube and the second storage tube, the voltage of the bit line end is made to show an obvious change trend by half-off the voltage of the second storage tube, that is, the third voltage, and according to the change trend of the voltage at the bit line end, different storage data on the first storage tube and the second storage tube are obtained, thereby achieving simultaneous acquisition of the storage data on the first storage tube and the second storage tube, improving the reading efficiency of the storage unit, reducing the read interference of the storage tube, and ensuring the accuracy of reading different storage tubes.

[0020] The memory writing method provided by the technical solution of the present invention continuously obtains the write-on voltage on the memory cell to be written after writing different data, so that the write-on voltage on the memory cell to be written is within the preset write-on voltage, thereby reducing the discreteness of the write-on voltage and improving the storage performance of the memory.

[0021] The memory erasing method provided by the technical solution of the present invention continuously obtains the erase start voltage on the storage unit to be erased and compares the erase start voltage with a preset erase start voltage range. When the erase start voltage is within the preset erase start voltage range, it is determined that the erase operation is completed, thereby reducing the discreteness of the erase start voltage and improving the storage performance of the memory.

[0022] Furthermore, when the erase start voltage is not within the preset erase start voltage range, there is an over-erase situation, that is, erasure causes excessive loss of electrons on the floating gate, and the erase start voltage decreases, resulting in an erroneous reading of 1 in a subsequent read operation. At this time, a positive compaction pressure is applied to the first word line or the third word line connected to the memory cell to be erased until the erase start voltage is within the preset erase start voltage range, that is, a part of electrons are added to the floating gate, so that the erase start voltage increases to a normal value, thereby reducing the discreteness of the erase start voltage and improving the storage performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic flow chart of a reading method in the technical solution of the present invention;

[0024] FIG2 is a schematic flow chart of a writing method in the technical solution of the present invention;

[0025] FIG3 is a schematic flow chart of an erasing method in the technical solution of the present invention;

[0026] FIG4 is a schematic diagram of the structure of the memory in the technical solution of the present invention;

[0027] 5 is a schematic diagram of the structure of the memory after entering the first read operation in the technical solution of the present invention;

[0028] 6 is a schematic diagram of the structure of the memory after entering the second read operation in the technical solution of the present invention;

[0029] 7 is a schematic diagram of the structure of the memory after entering the write operation in the technical solution of the present invention;

[0030] 8 is a schematic diagram of the structure of the memory after entering the erase operation in the technical solution of the present invention;

[0031] FIG9 is a schematic diagram of the semiconductor structure of the memory in the technical solution of the present invention. DETAILED DESCRIPTION

[0032] As mentioned in the background art, the storage performance of current split-gate memories needs to be further improved.

[0033] To reduce the area of ​​memory cells, two-bit split-gate flash memory has been widely researched and applied. Currently, two-bit split-gate flash memory uses a single select gate to store two bits of data, enabling higher integration. However, this type of two-bit split-gate flash memory requires turning off or on another unselected memory transistor when reading data from one of the memory transistors. This causes severe read interference on the unselected memory transistors, reducing the performance of the memory cell.

[0034] To address the above-mentioned problems, the present invention provides a method for reading, writing, and erasing a memory. By acquiring a first read current at the bit line BL end, the method simultaneously reads the stored data on the first storage transistor A1 and the second storage transistor B1. This improves the read efficiency of the memory cell and reduces the read interference of the storage transistors. Furthermore, the method determines whether the stored data on the first storage transistor A1 and the second storage transistor B1 have both been read out based on the first read result. If the stored data on the first storage transistor A1 and the second storage transistor B1 have not been read out, the method continues to acquire a second read current at the bit line BL end. Based on the second read current, the method continues to read the stored data on the first storage transistor A1 and the second storage transistor B1, thereby ensuring reading accuracy.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] FIG1 is a flow chart of a reading method in the technical solution of the present invention.

[0037] FIG4 is a schematic diagram of the structure of the memory in the technical solution of the present invention.

[0038] 1 and 4 , the technical solution of the present invention provides a method for reading a memory, wherein the memory includes: a plurality of memory cells 4 arranged in an array, wherein the memory cells 4 include a first word line WL1, a second word line WL2, a third word line WL3, and a bit line BL; a first storage transistor A1, wherein the gate of the first storage transistor A1 is connected to the first word line WL1, and one of the source or drain of the first storage transistor A1 is connected to the bit line BL; a first selection transistor M1, wherein the gate of the first selection transistor M1 is connected to the second word line WL2, and one of the source or drain of the first selection transistor M1 is connected to the bit line BL; a second selection transistor M2, wherein the gate of the second selection transistor M2 is connected to the second word line WL2, and one of the source or drain of the second selection transistor M2 is connected to the other source or drain of the first selection transistor M1; a second storage transistor B1, wherein the gate of the second storage transistor B1 is connected to the third word line WL3, one of the source or drain of the second storage transistor B1 is connected to the other source or drain of the second selection transistor M2, and the other source or drain of the second storage transistor B1 is connected to the bit line BL, and the reading method includes:

[0039] S101: Perform a first read operation to obtain a first read result. The first read operation includes: applying a first voltage to the second word line WL2 connected to the first selection tube M1 and the second selection tube M2 in the memory cell to be read, so that the first selection tube M1 and the second selection tube M2 are in a conductive state; applying a second voltage to the first word line WL1 and the third word line WL3 connected to the first storage tube A1 and the second storage tube B1, so that a read current is generated in the first storage tube A1 and the second storage tube B1; obtaining a first read current on the bit line BL end; and obtaining a first read result based on the first read current.

[0040] S102: When the first reading result indicates the storage data on the first storage transistor A1 and the second storage transistor B1, the reading operation ends.

[0041] S103: When the first read result is not represented by the storage data on the first storage transistor A1 and the second storage transistor B1, a second read operation is performed to obtain a second read result. The second read operation includes: continuing to obtain a second read current on the bit line BL end, and obtaining a second read result based on the second read current. The second read result is represented by the storage data on the first storage transistor A1 and the second storage transistor B1.

[0042] The first reading result includes a first current, a second current, and a third current. The first current is greater than the second current, and the third current is between the first current and the second current.

[0043] In this embodiment, the first selection transistor M1 and the second selection transistor M2 share a source, and the source of the first selection transistor M1, the gate of the first selection transistor M1, the source of the second selection transistor M2, and the gate of the second selection transistor M2 are all connected to the second word line WL2. The gate and source of the first selection transistor M1 and the gate and source of the second selection transistor M2 are connected together using polysilicon to reduce the size of the memory.

[0044] Obtaining a first read result based on the first read current in step S101 includes: in response to the first current at the bit line BL end, the storage data on the first storage tube A1 and the second storage tube B1 are both "0"; in response to the second current at the bit line BL end, the storage data on the first storage tube A1 and the second storage tube B1 are both "1"; and in response to the third current at the bit line BL end, continuing to obtain a second read result.

[0045] In this embodiment, the first current is a large current, which is 40 microamperes; the second current is a small current, which is 40 nanoamperes; and the third current is a medium current, which is 20 microamperes.

[0046] The method for obtaining a second read result based on the second read current in step S103 includes: applying a third voltage to the third word line WL3 end to obtain a second read current on the bit line BL end, when the second read current is less than the third current, the storage data on the first storage tube A1 is "1", and the storage data on the second storage tube B1 is "0"; when the second read current is equal to the third current, the storage data on the first storage tube A1 is "0", and the storage data on the second storage tube B1 is "1".

[0047] In this embodiment, the third voltage is a voltage value that causes the second storage transistor B1 to be half-off.

[0048] The reading method further comprises:

[0049] Step S104 : applying a second voltage to the first word line WL1 , the second word line WL2 , and the third word line WL3 connected to the non-to-be-read memory cells, and applying a floating voltage to the bit line BL connected to the non-to-be-read memory cells.

[0050] In this embodiment, the storage units to be read are A1 and A2, and the other storage units in the memory are non-storage units to be read. Of course, the technical solution of the present invention is not limited to this, and the selection of other storage units to be read is within the protection scope of the technical solution of the present invention.

[0051] In this embodiment, the voltages of the first word line WL1, the second word line WL2, the third word line WL3 and the bit line BL of the memory after the first read operation and the second read operation are as shown in Table 1:

[0052] Table 1

[0053] Wherein, Vpwr is the first voltage, Vgnd is the second voltage, Vnegr is the third voltage, and Floating is the floating voltage.

[0054] In this embodiment, the first voltage ranges from 1.5V to 2.5V, and the third voltage ranges from -0.8V to -2V.

[0055] In this embodiment, the memories share a common well region, and during a read operation, the well voltage has a value of a second voltage Vgnd.

[0056] The well region includes a P-type well region or an N-type well region.

[0057] In this embodiment, the well region is a P-type well region.

[0058] FIG5 is a schematic diagram of the structure of the memory after entering the first read operation in the technical solution of the present invention.

[0059] FIG6 is a schematic diagram of the structure of the memory after entering the second read operation in the technical solution of the present invention.

[0060] The following describes the memory reading method in conjunction with Table 1, FIG5 and FIG6:

[0061] In this embodiment, the storage units 5 to be read are A1 and B1, and the storage units not to be read are C1, D1, A2, B2, C2, and D2.

[0062] For the memory cell 5 to be read, a first voltage (2V) is applied to the second word line WL2 connected to the first selection tube M1 and the second selection tube M2 in the memory cell 5 to be read, so that the first selection tube M1 and the second selection tube M2 are in the on state, and a second voltage (0V) is applied to the first word line WL1 and the third word line WL3 connected to the first storage tube A1 and the second storage tube B1, so that a read current is generated in the first storage tube A1 and the second storage tube B1; a second voltage (0V) is applied to the bit line BL end to obtain a first read current on the bit line BL end, and a first read result is obtained based on the first read current.

[0063] When the first reading result represents the storage data on the first storage tube A1 and the second storage tube B1, the reading operation is terminated. Specifically: in response to the first current at the bit line BL end, the storage data on the first storage tube A1 and the second storage tube B1 are both "0"; in response to the second current at the bit line BL end, the storage data on the first storage tube A1 and the second storage tube B1 are both "1"; in response to the third current at the bit line BL end, the second reading result is continued to be obtained.

[0064] When the first read result does not represent the storage data on the first storage tube A1 and the second storage tube B1, a second read operation is performed. Specifically, a third voltage (-0.8V) is applied to the third word line WL3 end to obtain a second read current on the bit line BL end. When the second read current is less than the third current, the storage data on the first storage tube A1 is "1" and the storage data on the second storage tube B1 is "0". When the second read current is equal to the third current, the storage data on the first storage tube A1 is "0" and the storage data on the second storage tube B1 is "1".

[0065] For non-read memory cells, a second voltage (0V) is applied to the first word line WL1, the second word line WL2 and the third word line WL3 connected to the non-read memory cells, and a floating voltage (Floating) is applied to the bit line BL connected to the non-read memory cells.

[0066] In the above scheme, by obtaining a first read current on the bit line BL end, the stored data on the first storage tube A1 and the second storage tube B1 are simultaneously read, thereby improving the read efficiency of the storage unit and reducing the read interference of the storage tubes. In addition, it is determined based on the first read result whether the stored data on the first storage tube A1 and the second storage tube B1 have been read out. If the stored data on the first storage tube A1 and the second storage tube B1 have not been read out, a second read current on the bit line BL end is continuously obtained. Based on the second read current, the stored data on the first storage tube A1 and the second storage tube B1 are continuously read, thereby ensuring the accuracy of the reading.

[0067] In addition, by obtaining a first read current on the bit line BL end, the storage data on the first storage tube A1 and the second storage tube B1 are simultaneously read, thereby improving the read efficiency of the storage unit and reducing the read interference of the storage tubes. Moreover, it is determined by the first read result whether the storage data on the first storage tube A1 and the second storage tube B1 have been read out. If the storage data on the first storage tube A1 and the second storage tube B1 have not been read out, the second read current on the bit line BL end is continuously obtained. According to the second read current, the storage data on the first storage tube A1 and the second storage tube B1 are continuously read, thereby ensuring the accuracy of the reading.

[0068] 2 and 4 , the technical solution of the present invention provides a method for writing to a memory, wherein the memory includes: a plurality of memory cells arranged in an array, wherein the memory cells include a first word line WL1, a second word line WL2, a third word line WL3, and a bit line BL; a first storage transistor A1, wherein the gate of the first storage transistor A1 is connected to the first word line WL1, and one of the source or drain of the first storage transistor A1 is connected to the bit line BL; a first selection transistor M1, wherein the gate of the first selection transistor M1 is connected to the second word line WL2, and one of the source or drain of the first selection transistor M1 is connected to the bit line BL; a second selection transistor M2, wherein the gate of the second selection transistor M2 is connected to the second word line WL2, and one of the source or drain of the second selection transistor M2 is connected to the other source or drain of the first selection transistor M1; a second storage transistor B1, wherein the gate of the second storage transistor B1 is connected to the third word line WL3, one of the source or drain of the second storage transistor B1 is connected to the other source or drain of the second selection transistor M2, and the other source or drain of the second storage transistor B1 is connected to the bit line BL; the writing method includes:

[0069] Step S201: Perform a first write operation, the first write operation method including: applying a first write negative voltage to the second word line WL2 connected to the memory cell to be written, applying a write positive voltage to the first word line WL1 or the third word line WL3 connected to the memory cell to be written, applying a first write negative voltage to the bit line BL connected to the memory cell to be written, so that a write current is generated in the memory cell to be written, so as to perform a first write operation on any row of memory cells in the memory, obtain a write start voltage on the memory cell to be written, and compare the write start voltage with a preset write start voltage.

[0070] Step S202 : When the write-on voltage is within the preset write-on voltage, it is determined that the write operation is completed.

[0071] Step S203: When the write-on voltage is not within the preset write-on voltage, a second write operation is performed, wherein the second write operation includes repeating the first write operation until the write-on voltage is within the preset write-on voltage.

[0072] In this embodiment, the write-on voltage includes a first write-on voltage, and the preset write-on voltage includes a first preset write-on voltage.

[0073] The method of obtaining the write-on voltage on the storage cell to be written and comparing the write-on voltage with the preset write-on voltage in step S201 includes: after writing data "1", obtaining the first write-on voltage on the storage cell to be written, comparing the first write-on voltage with the first preset write-on voltage, when the first write-on voltage is greater than the first preset write-on voltage, the operation of writing data "1" is completed, when the first write-on voltage is less than or equal to the first preset write-on voltage, repeating the first write operation until the first write-on voltage is greater than the first preset write-on voltage.

[0074] In this embodiment, the write-on voltage includes a second write-on voltage, and the preset write-on voltage includes a second preset write-on voltage.

[0075] The method of obtaining the write-on voltage on the storage unit to be written and comparing the write-on voltage with the preset write-on voltage in step S203 also includes: after writing the data "0", obtaining a second write-on voltage on the storage unit to be written, comparing the second write-on voltage with the second preset write-on voltage, when the second write-on voltage is less than the second preset write-on voltage, the operation of writing the data "0" is completed, and when the second write-on voltage is greater than or equal to the second preset write-on voltage, repeating the first write operation until the second write-on voltage is less than the second preset write-on voltage.

[0076] The writing method further includes:

[0077] Step S204: Apply a first write negative voltage to the second word line WL2 connected to the memory cell not to be written, apply a second write negative voltage to the first word line WL1 and the third word line WL3 connected to the memory cell not to be written, and apply a first write negative voltage to the bit line BL connected to the memory cell not to be written.

[0078] In this embodiment, the voltages of the first word line WL1, the second word line WL2, the third word line WL3 and the bit line BL of the memory after entering the write operation are shown in Table 2:

[0079] Table 2

[0080] Wherein, VnegP is the first negative write voltage, VposP is the positive write voltage, and VnegU is the second negative write voltage.

[0081] In this embodiment, the voltage range of the first negative write voltage is -3V to -5V, the voltage range of the positive write voltage is 4V to 7V, and the voltage range of the second negative write voltage is -2V to -3V.

[0082] In this embodiment, the memories share a common well region, and during a write operation, the well voltage has a value equal to a first negative write voltage VnegP.

[0083] The well region includes a P-type well region or an N-type well region.

[0084] In this embodiment, the well region is a P-type well region.

[0085] FIG7 is a schematic diagram of the structure of the memory after entering the write operation in the technical solution of the present invention.

[0086] The following describes the memory writing method in conjunction with Table 2 and FIG7 :

[0087] In this embodiment, the storage units 6 to be written are A1 and A2, and the storage units not to be written are B1, B2, C1, C2, D1, and D2.

[0088] For the memory cell 6 to be written, a first negative write voltage (-3.6V) is applied to the second word line WL2 connected to the memory cell 6 to be written, a positive write voltage (4.9V) is applied to the first word line WL1 connected to the memory cell 6 to be written, and a first negative write voltage (-3.6V) is applied to the bit line BL connected to the memory cell 6 to be written, so that a write current is generated in the memory cell 6 to be written, so as to perform a first write operation on any row of memory cells in the memory, obtain a write start voltage on the memory cell 6 to be written, and compare the write start voltage with the preset write start voltage.

[0089] In this embodiment, when the data to be written into the memory cell 6 to be written is 1, a -3.6V voltage is applied to the bit line BL connected to the memory cell 6 to be written; when the data to be written into the memory cell 6 to be written is 0, a 1.2V voltage is applied to the bit line BL connected to the memory cell 6 to be written.

[0090] When the write-start voltage Vtp is within the preset write-start voltage, the write operation is determined to be completed; when the write-start voltage Vtp is not within the preset write-start voltage, a second write operation is performed, and the second write operation includes: repeating the first write operation until the write-start voltage Vtp is within the preset write-start voltage.

[0091] Specifically: after writing the data "1", obtain the first write-on voltage on the storage unit 6 to be written, compare the first write-on voltage with the first preset write-on voltage Vtp1, when the first write-on voltage is greater than the first preset write-on voltage Vtp1, the operation of writing the data "1" is completed, when the first write-on voltage is less than or equal to the first preset write-on voltage Vtp1, repeat the first write operation until the first write-on voltage is greater than the first preset write-on voltage Vtp1.

[0092] After writing the data "0", obtain the second write-on voltage Vtp2 on the storage unit 6 to be written, compare the second write-on voltage with the second preset write-on voltage Vtp2, and when the second write-on voltage is less than the second preset write-on voltage Vtp2, the operation of writing the data "0" is completed. When the second write-on voltage is greater than or equal to the second preset write-on voltage Vtp2, repeat the first write operation until the second write-on voltage is less than the second preset write-on voltage Vtp2.

[0093] After entering the write operation, the channel in the storage transistor is turned off. Since the write-on voltage Vtp is greater than the preset write-on voltage, the operating current is less than Idsp1 (small current).

[0094] After entering the write operation, the write-on voltage Vtp is greater than 1.6V, and the corresponding operating current Ids is less than 20nA.

[0095] For the memory cells not to be written, a first negative write voltage (-3.6V) is applied to the second word line WL2 connected to the memory cells not to be written, a second negative write voltage (-2.7V) is applied to the third word line WL3 connected to the memory cells not to be written, and a first negative write voltage is applied to the bit line BL connected to the memory cells not to be written.

[0096] In the above scheme, after writing different data, the write-on voltage on the storage unit to be written is continuously obtained, so that the write-on voltage on the storage unit to be written is within the preset write-on voltage, thereby reducing the discreteness of the write-on voltage and improving the storage performance of the memory.

[0097] FIG9 is a schematic diagram of the semiconductor structure of the memory in the technical solution of the present invention.

[0098] 9 , the memory includes: a substrate 800 ; a well region 801 within the substrate; a select gate 804 at least partially within the substrate; an insulating dielectric layer 803 located on the surface of the substrate 800 and on the sidewalls of the select gate 804 ; and a storage gate 802 located on the surface of the insulating dielectric layer 803 .

[0099] The insulating dielectric layer 803 includes two silicon oxide layers and a silicon nitride layer located between the two silicon oxide layers.

[0100] The well region 801 includes a P-type well region or an N-type well region.

[0101] In this embodiment, the well region 801 is a P-type well region.

[0102] The writing process of the memory is as follows: first, the state of the memory cell after the erase operation is defined as the 0 state, and the writing operation is divided into writing data "1" or writing data "0".

[0103] During a write operation, a first negative write voltage VnegP is applied to the well region 801 in the substrate 800, and a positive write voltage VposP is applied to the gate of the storage transistor in the selected row. At this time, the channel of the storage gate 802 is open to receive the voltage at the bit line BL end.

[0104] Therefore, when writing data "1", a first write negative voltage VnegP is applied to the bit line BL end, and the voltage difference between the selected storage gate and the channel is (write positive voltage VposP-first write negative voltage VnegP) to tunnel electrons into the insulating dielectric layer 803 and be stored.

[0105] When writing data "0", a second write voltage Vp0 is applied to the bit line BL end, and the voltage difference between the selected storage gate and the channel is (write positive voltage VposP-second write voltage Vp0), which is not enough to tunnel electrons into the insulating dielectric layer 803, so the storage cell remains in the 0 state.

[0106] The second write voltage Vp0 is the voltage applied to the bit line BL when writing data “0”.

[0107] In the above scheme, the technical solution of the present invention determines the data writing status according to the current value on the storage tube, specifically:

[0108] For the storage tube with data written as "0", holes are stored in the insulating dielectric layer 803. Therefore, when 0V is applied to the gate of the storage tube in the selected row, electrons will be induced in the channel, causing the storage tube to have current (about 20 microamperes for a single tube).

[0109] For the storage tube with the written data "1", electrons are stored in the insulating dielectric layer 803. Therefore, when 0V is applied to the gate of the storage tube in the selected row, holes will be induced in the channel. At this time, the storage tube is turned off and there is no current (less than 20 nanoamperes for a single tube). Therefore, it can be judged that the written data is "1" or "0".

[0110] 3 and 4 , the technical solution of the present invention provides a method for erasing a memory, wherein the memory includes: a plurality of memory cells arranged in an array, wherein the memory cells include a first word line WL1, a second word line WL2, a third word line WL3, and a bit line BL; a first storage transistor A1, wherein the gate of the first storage transistor A1 is connected to the first word line WL1, and one of the source or drain of the first storage transistor A1 is connected to the bit line BL; a first selection transistor M1, wherein the gate of the first selection transistor M1 is connected to the second word line WL2, and one of the source or drain of the first selection transistor M1 is connected to the bit line BL; a second selection tube M2, wherein the gate of the second selection tube M2 is connected to the second word line WL2, and one of the source or drain of the second selection tube M2 is connected to the other source or drain of the first selection tube M1; a second storage tube B1, wherein the gate of the second storage tube B1 is connected to the third word line WL3, one of the source or drain of the second storage tube B1 is connected to the other source or drain of the second selection tube M2, and the other source or drain of the second storage tube B1 is connected to the bit line BL, and the erasing method includes:

[0111] Step S301: Perform a first erase operation, which includes: applying an erase positive voltage to the second word line WL2 connected to the memory cell to be erased, applying an erase negative voltage to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased, applying an erase positive voltage to the bit line BL connected to the memory cell to be erased, performing a first erase operation on any row of memory cells in the memory, obtaining an erase start voltage on the memory cell to be erased, and comparing the erase start voltage with a preset erase start voltage range.

[0112] Step S302: When the erase start voltage is within the preset erase start voltage range, it is determined that the erase operation is completed.

[0113] Step S303: When the erase start voltage is not within the preset erase start voltage range, a second erase operation is performed. The second erase operation includes repeating the first erase operation until the erase start voltage is within the preset erase start voltage range.

[0114] In this embodiment, the method of obtaining the erase start voltage on the memory cell to be erased and comparing the erase start voltage with the preset erase start voltage range in step S301 includes: if the erase start voltage is greater than the preset erase start voltage range, repeating the first erase operation until the erase start voltage is within the preset erase start voltage range; if the erase start voltage is less than the preset erase start voltage range, applying a positive compaction voltage to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased until the erase start voltage is within the preset erase start voltage range.

[0115] The erasing method further includes:

[0116] Step S304 : applying a positive erase voltage to the second word line WL2 , the first word line WL1 , the third word line WL3 and the bit line BL connected to the non-to-be-erased memory cells.

[0117] In this embodiment, the voltages of the first word line WL1, the second word line WL2, the third word line WL3 and the bit line BL of the memory after entering the erase operation are shown in Table 3:

[0118] Table 3

[0119] Among them, VposE is the erase positive voltage, and VnegE is the erase negative voltage.

[0120] In this embodiment, the voltage range of the erase positive voltage is 4V to 6V, and the voltage range of the erase negative voltage is -3V to -5V.

[0121] In this embodiment, the memories share a common well region. When performing an erase operation, the value of the well voltage is an erase positive voltage VposE.

[0122] The well region includes a P-type well region or an N-type well region.

[0123] In this embodiment, the well region is a P-type well region.

[0124] FIG8 is a schematic diagram of the structure of the memory after entering the erase operation in the technical solution of the present invention.

[0125] The method for erasing the memory is described below in conjunction with Table 3 and FIG8 :

[0126] In this embodiment, the storage cells 7 to be erased are A1 and A2, and the storage cells not to be erased are B1, B2, C1, C2, D1, and D2.

[0127] For the memory cell 7 to be erased, a positive erase voltage (4.2V) is applied to the second word line WL2 connected to the memory cell 7 to be erased, a negative erase voltage (-3.6V) is applied to the first word line WL1 or the third word line WL3 connected to the memory cell 7 to be erased, and a positive erase voltage (4.2V) is applied to the bit line BL connected to the memory cell 7 to be erased. A first erase operation is performed on any row of memory cells in the memory, and an erase start voltage on the memory cell 7 to be erased is obtained, and the erase start voltage Vte is compared with the preset erase start voltage range Vte1 to Vte2.

[0128] When the erase start voltage Vte is within the preset erase start voltage range Vte1 to Vte2, the erase operation is judged to be completed; when the erase start voltage Vte is not within the preset erase start voltage range Vte1 to Vte2, the second erase operation is entered, and the second erase operation includes: repeating the first erase operation until the erase start voltage Vte is within the preset erase start voltage range Vte1 to Vte2.

[0129] Specifically, if the erase start voltage Vte is greater than the absolute value of Vte2 ​​in the preset erase start voltage range Vte1 to Vte2, the first erase operation is repeated until the erase start voltage Vte is within the preset erase start voltage range Vte1 to Vte2; if the erase start voltage Vte is less than the absolute value of Vte1 in the preset erase start voltage range Vte1 to Vte2, a positive compaction voltage is applied to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased until the erase start voltage Vte is within the preset erase start voltage range Vte1 to Vte2.

[0130] In this embodiment, the preset erase enable voltage range Vte1 to Vte2 ​​is -1.4V to -1.5V.

[0131] After entering the erase operation, the channel in the storage transistor is turned on, and the corresponding operating current Ids is also concentrated between the standard Idse1 and Idse2.

[0132] In this embodiment, after the erase operation is completed, the erase start voltage Vte is concentrated between -1.4V and -1.5V, and the corresponding operating current Ids is concentrated between 18uA and 22uA.

[0133] For non-erased memory cells, a positive erase voltage (4.2V) is applied to the second word line WL2 , the first word line WL1 , the third word line WL3 and the bit line BL connected to the non-erased memory cells.

[0134] In this embodiment, the write operation and the erase operation both adopt page mode (ie, row operation). Specifically, the write operation or the erase operation is performed on A1, A2 . . . An in any row of the memory at the same time.

[0135] Please continue to refer to Figure 9, the memory erasing process is as follows:

[0136] During an erase operation, a positive erase voltage VposE is applied to the well region 801 in the substrate 800, and a negative erase voltage VnegE is applied to the memory gate 802 of the selected row. At this time, the voltage difference between the memory gate 802 and the channel (negative erase voltage VnegE minus positive erase voltage VposE) causes holes to tunnel into the insulating dielectric layer 803, resulting in a zero state. In the above scheme, by continuously obtaining the erase start voltage on the memory cell to be erased and comparing the erase start voltage with a preset erase start voltage range, the erase operation is determined to be complete when the erase start voltage is within the preset erase start voltage range. This reduces the dispersion of the erase start voltage and improves the storage performance of the memory.

[0137] In addition, when the erase start voltage is not within the preset erase start voltage range, there is an over-erasure situation, that is, erasure causes excessive loss of electrons on the floating gate, and the erase start voltage decreases, resulting in an erroneous reading of 1 in a subsequent read operation. At this time, a positive compaction voltage is applied to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased until the erase start voltage is within the preset erase start voltage range, that is, a part of electrons are added to the floating gate, so that the erase start voltage increases to a normal value, thereby reducing the discreteness of the erase start voltage and improving the storage performance of the memory.

[0138] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for reading a memory, the memory comprising: A plurality of memory cells arranged in an array, wherein the memory cells include a first word line, a second word line, a third word line, and a bit line; a first storage transistor, wherein a gate of the first storage transistor is connected to the first word line, and one of a source or a drain of the first storage transistor is connected to the bit line; a first selection tube, wherein a gate of the first selection tube is connected to the second word line, and one of a source or a drain of the first selection tube is connected to the other source or drain of the first storage tube; a second selection tube, wherein the gate of the second selection tube is connected to the second word line, and one of the source or drain of the second selection tube is connected to the other source or drain of the first selection tube; and a second storage tube, wherein the gate of the second storage tube is connected to the third word line, one of the source or drain of the second storage tube is connected to the other source or drain of the second selection tube, and the other source or drain of the second storage tube is connected to the bit line, characterized in that it comprises: Performing a first read operation to obtain a first read result, the first read operation comprising: applying a first voltage to a second word line connected to the first selection transistor and the second selection transistor in the memory cell to be read, so that the first selection transistor and the second selection transistor are in a conductive state, applying a second voltage to a first word line and a third word line connected to the first storage transistor and the second storage transistor, so that a read current is generated in the first storage transistor and the second storage transistor, obtaining a first read current at a bit line terminal, and obtaining a first read result based on the first read current; When the first reading result indicates the storage data on the first storage tube and the second storage tube, the reading operation is terminated; When the first reading result is not characterized as the storage data on the first storage tube and the second storage tube, a second reading operation is performed to obtain a second reading result. The second reading operation includes: continuing to obtain a second reading current on the bit line end, and obtaining a second reading result based on the second reading current. The second reading result is characterized as the storage data on the first storage tube and the second storage tube.

2. The memory reading method according to claim 1, wherein: The first reading result includes a first current, a second current and a third current, the first current is greater than the second current, and the third current is between the first current and the second current. According to the first reading current, obtaining the first reading result includes: in response to the first current at the bit line end, the storage data on the first storage tube and the second storage tube are both "0"; in response to the second current at the bit line end, the storage data on the first storage tube and the second storage tube are both "1"; in response to the third current at the bit line end, continuing to obtain the second reading result.

3. The memory reading method according to claim 2, wherein: According to the second read current, the method for obtaining a second read result includes: applying a third voltage to the third word line terminal to obtain a second read current on the bit line terminal; when the second read current is less than the third current, the stored data on the first storage tube is "1" and the stored data on the second storage tube is "0"; when the second read current is equal to the third current, the stored data on the first storage tube is "0" and the stored data on the second storage tube is "1".

4. The memory reading method according to claim 1, wherein: Also includes: A second voltage is applied to the first word line, the second word line and the third word line connected to the non-to-be-read memory cells, and a floating voltage is applied to the bit lines connected to the non-to-be-read memory cells.

5. A method for writing to a memory, the memory comprising: A plurality of memory cells arranged in an array, wherein the memory cells include a first word line, a second word line, a third word line, and a bit line; a first storage transistor, wherein a gate of the first storage transistor is connected to the first word line, and one of a source or a drain of the first storage transistor is connected to the bit line; a first selection tube, wherein a gate of the first selection tube is connected to the second word line, and one of a source or a drain of the first selection tube is connected to the other source or drain of the first storage tube; a second selection tube, wherein the gate of the second selection tube is connected to the second word line, and one of the source or drain of the second selection tube is connected to the other source or drain of the first selection tube; and a second storage tube, wherein the gate of the second storage tube is connected to the third word line, one of the source or drain of the second storage tube is connected to the other source or drain of the second selection tube, and the other source or drain of the second storage tube is connected to the bit line, characterized in that it comprises: Performing a first write operation, the first write operation method comprising: applying a first negative write voltage to a second word line connected to a memory cell to be written, applying a positive write voltage to a first word line or a third word line connected to the memory cell to be written, applying a first negative write voltage to a bit line connected to the memory cell to be written, so that a write current is generated in the memory cell to be written, performing the first write operation on any row of memory cells in the memory, obtaining a write-on voltage on the memory cell to be written, and comparing the write-on voltage with a preset write-on voltage; When the write-on voltage is within the preset write-on voltage, it is determined that the write operation is completed; When the write-on voltage is not within the preset write-on voltage, a second write operation is performed, and the second write operation includes: repeating the first write operation until the write-on voltage is within the preset write-on voltage.

6. The memory writing method according to claim 5, wherein: The write-on voltage includes a first write-on voltage, the preset write-on voltage includes a first preset write-on voltage, and the method of obtaining the write-on voltage on the storage unit to be written and comparing the write-on voltage with the preset write-on voltage includes: after writing data "1", obtaining the first write-on voltage on the storage unit to be written, comparing the first write-on voltage with the first preset write-on voltage, when the first write-on voltage is greater than the first preset write-on voltage, the operation of writing data "1" is completed, and when the first write-on voltage is less than or equal to the first preset write-on voltage, repeating the first write operation until the first write-on voltage is greater than the first preset write-on voltage.

7. The memory writing method according to claim 5, wherein: The write-on voltage includes a second write-on voltage, the preset write-on voltage includes a second preset write-on voltage, and the method of obtaining the write-on voltage on the storage unit to be written and comparing the write-on voltage with the preset write-on voltage also includes: after writing data "0", obtaining the second write-on voltage on the storage unit to be written, comparing the second write-on voltage with the second preset write-on voltage, when the second write-on voltage is less than the second preset write-on voltage, the operation of writing data "0" is completed, and when the second write-on voltage is greater than or equal to the second preset write-on voltage, repeating the first write operation until the second write-on voltage is less than the second preset write-on voltage.

8. The memory writing method according to claim 5, wherein: Also includes: A first negative write voltage is applied to the second word line connected to the non-to-be-written memory cell, a second negative write voltage is applied to the first and third word lines connected to the non-to-be-written memory cell, and a first negative write voltage is applied to the bit line connected to the non-to-be-written memory cell.

9. A method for erasing a memory, the memory comprising: A plurality of memory cells arranged in an array, wherein the memory cells include a first word line, a second word line, a third word line, and a bit line; a first storage transistor, wherein a gate of the first storage transistor is connected to the first word line, and one of a source or a drain of the first storage transistor is connected to the bit line; a first selection tube, wherein a gate of the first selection tube is connected to the second word line, and one of a source or a drain of the first selection tube is connected to the other source or drain of the first storage tube; a second selection tube, wherein the gate of the second selection tube is connected to the second word line, and one of the source or drain of the second selection tube is connected to the other source or drain of the first selection tube; and a second storage tube, wherein the gate of the second storage tube is connected to the third word line, one of the source or drain of the second storage tube is connected to the other source or drain of the second selection tube, and the other source or drain of the second storage tube is connected to the bit line. The erasing method includes: Performing a first erase operation, the first erase operation comprising: applying a positive erase voltage to a second word line connected to a memory cell to be erased, applying a negative erase voltage to a first word line or a third word line connected to the memory cell to be erased, applying a positive erase voltage to a bit line BL connected to the memory cell to be erased, performing the first erase operation on any row of memory cells in the memory, obtaining an erase start voltage on the memory cell to be erased, and comparing the erase start voltage with a preset erase start voltage range; When the erase start voltage is within the preset erase start voltage range, it is determined that the erase operation is completed; When the erase start voltage is not within the preset erase start voltage range, a second erase operation is performed. The second erase operation includes repeating the first erase operation until the erase start voltage is within the preset erase start voltage range.

10. The memory erasing method according to claim 9, wherein: The method for obtaining an erase start voltage on a memory cell to be erased and comparing the erase start voltage with a preset erase start voltage range includes: if the erase start voltage is greater than the preset erase start voltage range, repeating the first erase operation until the erase start voltage is within the preset erase start voltage range; if the erase start voltage is less than the preset erase start voltage range, applying a positive compaction voltage to a first word line or a third word line connected to the memory cell to be erased until the erase start voltage is within the preset erase start voltage range.

11. The memory erasing method according to claim 9, wherein: Also includes: A positive erase voltage is applied to the second word line, the first word line, the third word line, and the bit line connected to the non-to-be-erased memory cells.

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