MIS gate structure device, chip, and related device

Abstract

Provided in the embodiments of the present application are an MIS gate structure device, a chip, and a related device. The MIS gate structure device comprises: a substrate, and a gate dielectric layer, a source electrode, a drain electrode and gate electrodes, which are arranged on the substrate, wherein the gate dielectric layer, the source electrode and the drain electrode are all arranged on the surface of the substrate, and the gate dielectric layer is arranged between the source electrode and the drain electrode; the gate electrodes are stacked on the side of the gate dielectric layer that is away from the substrate; and the gate dielectric layer comprises a first dielectric layer and a superlattice dielectric layer, which are stacked, the superlattice dielectric layer at least comprises a second dielectric layer and a third dielectric layer, which are stacked, and the first dielectric layer is arranged between the substrate and the superlattice dielectric layer, a material forming the second dielectric layer being different from a material forming the third dielectric layer, and the dielectric constants of the materials forming the second dielectric layer and third dielectric layer being both greater than 10. The MIS gate structure device provided in the embodiments of the present application can reduce defects of an MIS gate structure, thereby improving the stability of the device.

Description

MIS gate structure device, chip and related equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 22, 2024, with application number 202410196580.X, and priority to the Chinese patent application entitled "A MIS gate structure device, chip and related equipment", all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a MIS gate structure device, chip and related equipment. Background Art

[0003] Wide bandgap semiconductor materials (such as gallium nitride, silicon carbide, etc.) have the characteristics of high breakdown electric field, high electron mobility and high electron saturation drift velocity, and have broad application prospects in the fields of power electronics and radio frequency microwaves.

[0004] However, in devices based on the traditional Schottky gate structure, the gate is in direct contact with the semiconductor. When the gate voltage swing increases, the device gate leakage current increases rapidly, resulting in increased device losses and reduced stability. The MIS (Metal-Insulator-Semiconductor) gate structure adds an insulating layer between the gate and the semiconductor, also known as a gate dielectric layer, which can effectively reduce gate leakage current. However, during the growth of the insulating layer material, defects will be generated at the interface between the insulating layer and the semiconductor, as well as in the insulating layer material, causing current collapse and threshold voltage instability in the device.

[0005] Therefore, how to reduce the defects of the MIS gate structure and improve the stability of the device is an urgent problem to be solved. Summary of the Invention

[0006] The embodiments of the present application provide a MIS gate structure device, chip and related equipment to reduce the defects of the MIS gate structure, improve the stability of the device, and avoid current collapse and threshold voltage instability in the device.

[0007] In a first aspect, an embodiment of the present application provides a MIS gate structure device, comprising: a substrate, a gate dielectric layer on the substrate, a source, a drain and a gate; wherein the gate dielectric layer, the source and the drain are all arranged on the surface of the substrate, and the gate dielectric layer is arranged between the source and the drain; the gate is stacked on the side of the gate dielectric layer away from the substrate; the gate dielectric layer includes a first dielectric layer and a superlattice dielectric layer arranged in a stacked manner, and the superlattice dielectric layer includes at least a second dielectric layer and a third dielectric layer arranged in a stacked manner, and the first dielectric layer is arranged between the substrate and the superlattice dielectric layer; wherein the material forming the second dielectric layer is different from the material forming the third dielectric layer, and the dielectric constants of the materials forming the second dielectric layer and the third dielectric layer are both greater than 10.

[0008] To reduce defects in MIS gate structures and improve device stability, embodiments of the present application provide a MIS gate structure device. A gate dielectric layer is disposed between the gate and the substrate of the MIS gate structure device. The gate dielectric layer includes a first dielectric layer that easily forms a good contact interface with the substrate, and a second dielectric layer and a third dielectric layer stacked on the first dielectric layer. The interface state density between the first dielectric layer and the substrate is low, making it easy to form a good contact interface with the semiconductor substrate, significantly reducing current collapse and threshold voltage instability in the semiconductor device. Furthermore, the material forming the second dielectric layer and the material forming the third dielectric layer are both high-dielectric constant materials, but the material forming the second dielectric layer is different from the material forming the third dielectric layer, and the second and third dielectric layers can be combined to form a superlattice structure. Compared to a gate dielectric layer formed of a single high-dielectric constant material, the composite gate dielectric layer formed of multiple different materials in the embodiments of the present application can simultaneously achieve a high dielectric constant and good thermal stability. The high dielectric constant helps reduce the gate dielectric thickness, enhance the gate's ability to control the channel, and increase the device's transconductance. The composite structure gate dielectric layer with good thermal stability is not easy to crystallize in a high temperature environment (e.g., 500°C), thus preventing the gate leakage current from increasing. In addition, the superlattice dielectric layer may also include dielectric layers formed of other high dielectric constant materials in addition to the second dielectric layer and the third dielectric layer, and the gate dielectric layer may also include dielectric layers formed of other materials. The embodiments of the present application do not specifically limit this. Therefore, the MIS gate structure device provided in the embodiments of the present application can reduce the defects of the MIS gate structure and improve the stability of the device.

[0009] In a possible implementation, the gate dielectric layer includes multiple layers of the superlattice dielectric layer; the multiple layers of the superlattice dielectric layer are arranged on a side of the first dielectric layer away from the substrate.

[0010] In the embodiment of the present application, compared with the MIS gate structure device with only one superlattice dielectric layer, the composite structure formed by multiple superlattice dielectric layers can further improve the thermal stability of the device, avoid crystallization at higher temperatures, and avoid the increase of gate leakage current, which affects the device performance.

[0011] In a possible implementation, in a direction perpendicular to the substrate, the thickness of the gate dielectric layer is between 0.3 nm and 50 nm.

[0012] In the embodiments of the present application, based on the requirements of different devices, in order to ensure the gate's ability to control the channel and to avoid a rapid increase in the device gate leakage current when the gate voltage swing increases, resulting in increased device loss and reduced stability, the overall thickness of the gate dielectric layer can be between 0.3nm and 50nm.

[0013] In a possible implementation, in a direction perpendicular to the substrate, the thickness of the first dielectric layer, the thickness of the second dielectric layer, and the thickness of the third dielectric layer are all between 0.1 nm and 5 nm.

[0014] In the embodiment of the present application, in order to control the thickness of the gate dielectric layer, the thickness of each dielectric layer is between 0.1 nm and 5 nm, and the thickness of each dielectric layer can be the same or different within the process error range.

[0015] In one possible implementation, the material forming the second dielectric layer and the third dielectric layer includes at least one of the following materials: hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, tantalum pentoxide Ta2O5, lanthanum oxide La2O3, lutetium dioxide LuO2, yttrium oxide Y2O3, and scandium oxide Sc2O3.

[0016] In the embodiment of the present application, the materials of the second dielectric layer and the third dielectric layer are oxides with high dielectric constants, which can enhance the control ability of the gate over the channel and increase the transconductance of the device.

[0017] In a possible implementation, the material forming the first dielectric layer includes at least one of the following materials: aluminum oxide Al2O3, silicon nitride SiN x , silicon dioxide SiO2.

[0018] In an embodiment of the present application, the material of the first dielectric layer is a material that can form a good contact surface with the semiconductor, that is, a material with a low interface state density, which can reduce gate defects and reduce gate leakage current when the gate voltage swing increases, thereby ensuring good device performance.

[0019] In one possible implementation, the material forming the first dielectric layer is the same as the material forming the second dielectric layer, and the materials forming the first dielectric layer and the second dielectric layer include at least one of the following materials: aluminum oxide Al2O3, silicon nitride SiN x , silicon dioxide SiO2; the material forming the third dielectric layer includes at least one of the following materials: hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, tantalum pentoxide Ta2O5, lanthanum oxide La2O3, lutetium dioxide LuO2, yttrium oxide Y2O3, scandium oxide Sc2O3.

[0020] In the embodiment of the present application, the material forming the first dielectric layer and the material forming the second dielectric layer can be the same material that forms a good contact surface with the substrate, so as to reduce gate defects and improve device stability.

[0021] In one possible implementation, the gate dielectric layer further includes a fourth dielectric layer; the fourth dielectric layer is arranged between multiple layers of the superlattice dielectric layer; or is arranged between the first dielectric layer and multiple layers of the superlattice dielectric layer; or is arranged on a side of the multiple layers of the superlattice dielectric layer away from the first dielectric layer.

[0022] In an embodiment of the present application, the gate dielectric layer in the MIS gate structure device can also be provided with a fourth dielectric layer between any two superlattice dielectric layers of the multi-layer superlattice dielectric layer, or between the first dielectric layer and the multi-layer superlattice dielectric layer, or above the multi-layer superlattice dielectric layer, depending on the requirements of the device. The embodiment of the present application does not impose any specific restrictions on the thickness and material of the fourth dielectric layer.

[0023] In a second aspect, an embodiment of the present application provides a chip, comprising a circuit and the MIS gate structure device provided in the first aspect above applied to the circuit.

[0024] In a third aspect, an embodiment of the present application provides an electronic device, comprising a circuit board and the MIS gate structure device provided in the first aspect above, wherein the circuit board is electrically connected to the MIS gate structure device.

[0025] It should be understood that the chip provided in the second aspect and the electronic device provided in the third aspect of this application are consistent with the technical solution of the first aspect of this application. Their specific contents and beneficial effects can be referred to the MIS gate structure device provided in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0027] FIG1 is a schematic structural diagram of a group of conventional gate structure devices provided in an embodiment of the present application.

[0028] FIG2 is a MIS gate structure device provided in an embodiment of the present application.

[0029] FIG3 is a schematic structural diagram of a gate dielectric layer provided in an embodiment of the present application.

[0030] FIG4 is a schematic structural diagram of another gate dielectric layer provided in an embodiment of the present application.

[0031] FIG5 is a schematic structural diagram of another gate dielectric layer provided in an embodiment of the present application.

[0032] FIG6 is a flow chart of a method for fabricating a MIS gate structure device according to an embodiment of the present application.

[0033] FIG7 is a schematic diagram of the fabrication of a MIS gate structure device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0035] The terms "first," "second," and the like in the specification, claims, and accompanying drawings of this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0036] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0037] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0039] First, in order to facilitate understanding of the embodiments of the present application, the technical problems that need to be solved and the applicable application scenarios of the embodiments of the present application are analyzed in detail below.

[0040] Wide bandgap semiconductor materials (such as gallium nitride, silicon carbide, etc.) have the characteristics of high breakdown electric field, high electron mobility and high electron saturation drift velocity, and have broad application prospects in the fields of power electronics and radio frequency microwaves.

[0041] Please refer to FIG1 , which is a schematic diagram of the structure of a group of conventional gate structure devices provided in an embodiment of the present application. As shown in FIG1 (1), in a device based on a conventional Schottky gate structure, the gate is in direct contact with the substrate. When the gate voltage swing increases, the gate leakage current of the device increases rapidly, resulting in increased device loss and reduced stability. In order to reduce device loss, as shown in FIG1 (2), a device based on an MIS (Metal-Insulator-Semiconductor) gate structure adds an insulating layer between the gate and the substrate, which can effectively reduce the gate leakage current.

[0042] Among them, the insulating layer can also be called the gate dielectric layer, which is an insulating material. The commonly used gate dielectric layer materials are generally composed of a single material. During the growth process of the gate dielectric layer material, defects will occur at the interface between the gate dielectric layer and the semiconductor, as well as in the gate dielectric layer material, resulting in current collapse and threshold voltage instability in the device. Therefore, the gate dielectric layer can be selected from materials that can easily form a good contact interface with the semiconductor material, such as Al2O3, SiN x , SiO2, etc., but these materials have relatively low dielectric constants, resulting in thicker gate dielectric layers and poor device performance. Therefore, high-dielectric-constant materials, such as HfO2 and ZrO2, can also be used for the gate dielectric layer. However, these materials exhibit poor interface quality with the semiconductor material (substrate) and high interface state density. Furthermore, they tend to crystallize at relatively high temperatures, increasing leakage current and poor thermal stability.

[0043] To this end, the present invention provides a MIS gate structure device, chip, and related equipment to improve device stability, reduce defects in the MIS gate structure, and avoid current collapse and threshold voltage instability in the device. The specific structure of the MIS gate structure device can be referred to the relevant description of the following embodiments, and the present invention will not be repeated here.

[0044] Secondly, based on the technical issues raised above and to facilitate understanding of the embodiments of the present application, several MIS gate structure devices on which the embodiments of the present application are based are described below.

[0045] An embodiment of the present application provides an MIS gate structure device, comprising: a substrate, a gate dielectric layer on the substrate, a source, a drain, and a gate; wherein the gate dielectric layer, the source, and the drain are all arranged on the surface of the substrate, and the gate dielectric layer is arranged between the source and the drain; the gate is stacked on a side of the gate dielectric layer away from the substrate; the gate dielectric layer comprises a first dielectric layer and a superlattice dielectric layer arranged in a stacked manner, the superlattice dielectric layer comprises at least a second dielectric layer and a third dielectric layer arranged in a stacked manner, and the first dielectric layer is arranged between the substrate and the superlattice dielectric layer; wherein the material forming the second dielectric layer is different from the material forming the third dielectric layer, and the dielectric constants of the materials forming the second dielectric layer and the third dielectric layer are both greater than 10.

[0046] Please refer to Figure 2, which shows a MIS gate structure device provided in an embodiment of the present application. As shown in Figure 2, the MIS gate structure device 10 includes: a substrate 100, a gate dielectric layer 101 on the substrate 100, a source 102, a drain 103 and a gate 104.

[0047] As shown in (1) of FIG2 , the gate dielectric layer 101, the source electrode 102, and the drain electrode 103 are all disposed on the surface of the substrate, and the gate dielectric layer 101 is disposed between the source electrode 102 and the drain electrode 103; the gate electrode 104 is stacked on the side of the gate dielectric layer 101 away from the substrate 100. As shown in (2) of FIG2 , the gate dielectric layer 101 includes a first dielectric layer 201 and a superlattice dielectric layer 202, which are stacked. The superlattice dielectric layer 202 includes at least a second dielectric layer 2021 and a third dielectric layer 2022, which are stacked. The first dielectric layer 201 is disposed between the substrate 100 and the superlattice dielectric layer 202.

[0048] It is understood that a gate dielectric layer 101 is provided between the gate 104 and the substrate 100 of the MIS gate structure device 10. The gate dielectric layer 101 includes a first dielectric layer 201 having a wide bandgap and easily forming a good contact interface with the substrate, and a superlattice dielectric layer 202 stacked on the first dielectric layer 201. The superlattice dielectric layer 202 includes a second dielectric layer 2021 and a third dielectric layer 2022 formed of different high-k dielectric constant materials.

[0049] The material forming the first dielectric layer 201 is a wide bandgap material with a low interface state density with the substrate 100 , which can easily form a good contact interface with the semiconductor substrate 100 , thereby greatly reducing the current collapse and threshold voltage instability of the semiconductor device.

[0050] In some embodiments, the material forming the first dielectric layer includes at least one of the following materials: aluminum oxide Al2O3, silicon nitride SiN x The material forming the first dielectric layer can form a good contact surface with the semiconductor, reduce gate defects, and reduce gate leakage current when the gate voltage swing increases, thereby ensuring good device performance.

[0051] In addition, the material forming the second dielectric layer 2021 and the material forming the third dielectric layer 2022 are both high dielectric constant materials, but the material forming the second dielectric layer 2021 is different from the material forming the third dielectric layer 2022, and the second dielectric layer 2021 and the third dielectric layer 2022 can be combined to form a superlattice structure. Compared with a gate dielectric layer formed of a single high dielectric constant material, a composite structure gate dielectric layer formed using a variety of different materials has better thermal stability and low interface state density. Among them, a high dielectric constant is conducive to reducing the thickness of the gate dielectric, enhancing the gate's control ability over the channel, and increasing the transconductance of the device. A composite structure gate dielectric layer with good thermal stability is not easy to crystallize in a high temperature environment (e.g., 500°C).

[0052] In some embodiments, the material forming the second and third dielectric layers includes at least one of the following materials: hafnium dioxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), lutetium dioxide (LuO2), yttrium oxide (Y2O3), and scandium oxide (Sc2O3). The second and third dielectric layers are made of high-k oxides, which can enhance the gate's ability to control the channel and increase the device's transconductance.

[0053] In other embodiments, the MIS gate structure device 10 may further be stacked with a buffer layer, a channel layer, an insertion layer, a barrier layer, a cap layer, etc. on the substrate 100. The material forming the substrate 100 may include silicon, silicon carbide, aluminum oxide, gallium nitride, diamond, etc., or at least one of composite materials formed based on the above materials. The material forming the buffer layer may include AlN, AlGaN material, or at least one of composite materials formed based on the above materials. The material forming the channel layer may include GaN material, etc. The material forming the insertion layer may include AlN material, etc. The material forming the barrier layer may include AlGaN material, etc. The material forming the cap layer may include GaN material, etc. This is not specifically limited in the embodiments of the present application.

[0054] In some embodiments, the gate dielectric layer includes multiple layers of the superlattice dielectric layer; the multiple layers of the superlattice dielectric layer are arranged on a side of the first dielectric layer away from the substrate.

[0055] It can be understood that, please refer to Figure 3, which is a structural schematic diagram of a gate dielectric layer provided in an embodiment of the present application. As shown in (1) in Figure 3, compared with the gate dielectric layer 101 having only one superlattice dielectric layer 202, the multi-layer superlattice dielectric layer 202 is periodically stacked on the side of the first dielectric layer 201 away from the substrate 100. The composite structure formed by the multi-layer superlattice dielectric layer 202 can improve the thermal stability of the device and prevent the gate dielectric layer from crystallizing at a higher temperature and affecting the device performance.

[0056] In other embodiments, each superlattice dielectric layer may include multiple dielectric layers formed of high dielectric constant materials. For example, as shown in FIG3 (2), the superlattice dielectric layer may include a second dielectric layer 2021, a third dielectric layer 2022, and a fifth dielectric layer 2023. The material forming the fifth dielectric layer is different from the material of the adjacent third dielectric layer 2022, and may be the same as or different from the material of the second dielectric layer 2021. In this regard, the embodiment of the present application does not specifically limit the number of dielectric layers formed of high dielectric constant materials included in each superlattice dielectric layer.

[0057] In some embodiments, the gate dielectric layer has a thickness in a direction perpendicular to the substrate of between 0.3 nm and 50 nm. Controlling the thickness of the gate dielectric layer 101 to between 0.3 nm and 50 nm, i.e., setting the total thickness of the first dielectric layer 201 and the superlattice dielectric layer 202 to between 0.3 nm and 50 nm, can ensure the gate's ability to control the channel and prevent a rapid increase in device gate leakage current when the gate voltage swing increases, leading to increased device losses and reduced stability.

[0058] It should be noted that the thickness of each superlattice dielectric layer in the multi-layer superlattice dielectric layer in the direction perpendicular to the substrate can be the same or different within the process error range, and this embodiment of the application does not impose any specific limitation on this.

[0059] In other embodiments, the material forming the first dielectric layer and the material forming the second dielectric layer can be the same, that is, aluminum oxide Al2O3, silicon nitride SiN3, etc., which form a good contact surface with the semiconductor substrate. x , silicon dioxide SiO2 and other materials. The material forming the third dielectric layer is a high dielectric constant material, such as: hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, tantalum pentoxide Ta2O5, lanthanum oxide La2O3, lutetium dioxide LuO2, yttrium oxide Y2O3 or scandium oxide Sc2O3, etc. For example: Please refer to Figure 5, Figure 5 is another schematic diagram of the gate dielectric layer structure provided by the embodiment of the present application. As shown in Figure 5, the gate dielectric layer is a gate dielectric layer composed of a composite structure composed of Al2O3 and ZrO2 alternating. The gate dielectric layer can combine the material properties of Al2O3 and ZrO2. Al2O3 has very excellent chemical and thermal stability, a wide band gap, and a large band gap offset with different semiconductor substrates, and is easy to form a good contact interface. In addition, ZrO2 has a high dielectric constant (about 25), which can improve the dielectric constant of the gate dielectric layer composed of the composite structure, reduce the thickness of the gate dielectric layer, and enhance the gate's control over the channel.

[0060] It should be noted that the material forming the first dielectric layer can be the same as the material forming the second dielectric layer. For example, the first dielectric layer and the second dielectric layer are formed using a wide-bandgap insulating material, and the third dielectric layer is formed using a different high dielectric constant. This can simultaneously achieve a good contact interface, low interface state density, and a high dielectric constant gate dielectric. The low interface state density is beneficial for suppressing the current collapse effect, and the high dielectric constant is beneficial for reducing the gate dielectric thickness, enhancing the gate's control ability over the channel, and improving the stability of the device.

[0061] In some embodiments, in a direction perpendicular to the substrate, the thickness of the first dielectric layer, the thickness of the second dielectric layer, and the thickness of the third dielectric layer are all between 0.1 nm and 5 nm. It will be appreciated that, to control the thickness of the gate dielectric layer, the thickness of each dielectric layer is between 0.1 nm and 5 nm, and the thickness of each dielectric layer can be the same or different within a process tolerance.

[0062] In other embodiments, the gate dielectric layer further includes a fourth dielectric layer; the fourth dielectric layer is arranged between multiple layers of the superlattice dielectric layer; or is arranged between the first dielectric layer and multiple layers of the superlattice dielectric layer; or is arranged on the side of the multiple layers of the superlattice dielectric layer away from the first dielectric layer.

[0063] Please refer to FIG4, which is a schematic structural diagram of another gate dielectric layer provided in an embodiment of the present application. The gate dielectric layer 101 may also include a fourth dielectric layer 203. As shown in FIG4 (1), the fourth dielectric layer 203 may be arranged on the side of the superlattice dielectric layer 202 away from the first dielectric layer 201; as shown in FIG4 (2), the fourth dielectric layer 203 may be arranged on the side of the superlattice dielectric layer 202 close to the first dielectric layer 201, that is, between the first dielectric layer 201 and the superlattice dielectric layer 202; as shown in FIG4 (3), the fourth dielectric layer 203 may have multiple layers, which are respectively arranged on both sides of the superlattice dielectric layer 202. Therefore, the gate dielectric layer in the MIS gate structure device can also be provided with the fourth dielectric layer 203 at any position according to the requirements of the device. In addition, the embodiment of the present application does not impose any specific restrictions on the thickness and material of the fourth dielectric layer. For example, it can be an insulating material with a high dielectric constant, an insulating material with a wide bandgap, etc.

[0064] To reduce defects in MIS gate structures and improve device stability, embodiments of the present application provide a MIS gate structure device. A gate dielectric layer is disposed between the gate and the substrate of the MIS gate structure device. The gate dielectric layer includes a first dielectric layer that easily forms a good contact interface with the substrate, and a second dielectric layer and a third dielectric layer stacked on the first dielectric layer. The interface state density between the first dielectric layer and the substrate is low, making it easy to form a good contact interface with the semiconductor substrate, significantly reducing current collapse and threshold voltage instability in the semiconductor device. Furthermore, the material forming the second dielectric layer and the material forming the third dielectric layer are both high-dielectric constant materials, but the material forming the second dielectric layer is different from the material forming the third dielectric layer, and the second and third dielectric layers can be combined to form a superlattice structure. Compared to a gate dielectric layer formed of a single high-dielectric constant material, the composite gate dielectric layer formed of multiple different materials in the embodiments of the present application can simultaneously achieve a high dielectric constant and good thermal stability. The high dielectric constant helps reduce the gate dielectric thickness, enhance the gate's ability to control the channel, and increase the device's transconductance. The composite structure gate dielectric layer with good thermal stability is not easy to crystallize in a high temperature environment (e.g., 500°C), thus preventing the gate leakage current from increasing. In addition, the superlattice dielectric layer may also include dielectric layers formed of other high dielectric constant materials in addition to the second dielectric layer and the third dielectric layer, and the gate dielectric layer may also include dielectric layers formed of other materials. The embodiments of the present application do not specifically limit this. Therefore, the MIS gate structure device provided in the embodiments of the present application can reduce the defects of the MIS gate structure and improve the stability of the device.

[0065] Secondly, the embodiment of the present application exemplarily provides a method for manufacturing a MIS gate structure device based on the structure of the MIS gate structure device shown in FIG. 2 .

[0066] Please refer to Figures 6 and 7. Figure 6 is a schematic flow chart of a method for fabricating a MIS gate structure device according to an embodiment of the present application, and Figure 7 is a schematic diagram of fabricating a MIS gate structure device according to an embodiment of the present application. As shown in Figure 6, the method includes:

[0067] Step S1, forming a substrate.

[0068] Specifically, as shown in FIG7 , a substrate 100 is prepared. The substrate may be any type of semiconductor material. For example, the material forming the substrate 100 may include at least one of silicon, silicon carbide, aluminum oxide, gallium nitride, diamond, or a composite material based on the above materials. The substrate 100 may also include a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer, which are not specifically limited in this embodiment of the present application.

[0069] Step S2: preparing a metal layer on the surface of the substrate, and etching or stripping the metal layer to obtain a source electrode and a drain electrode.

[0070] Specifically, as shown in FIG7 , a metal layer is deposited on the surface of substrate 100, and the metal layer is etched or stripped to obtain source 102 and drain 103. It is understood that depositing source and drain metal on a semiconductor substrate requires that the source and drain metal form good ohmic contact with the semiconductor substrate. In the embodiments of the present application, the source and drain ohmic contact can be achieved by a high-temperature annealing method, an ion implantation method, or a secondary epitaxial growth method.

[0071] For example, for high-temperature annealing, the source and drain metals can be made of at least one of Ti, Al, Ni, or Au. High-temperature annealing is performed at 800-900°C in a nitrogen atmosphere to form ohmic contacts between the source and drain.

[0072] Another example is ion implantation. For example, when the substrate is gallium nitride, Si ions can be implanted into the source and drain regions before depositing the source and drain metals. High-temperature annealing is then performed to activate the implanted ions, turning the source and drain regions into highly doped semiconductors. Source and drain metals are then deposited to form good ohmic contacts.

[0073] For another example, in a secondary epitaxial growth scheme, before depositing the source and drain metals, the source and drain regions can be etched, a highly doped semiconductor material can be epitaxially grown in the etched regions, and then the source and drain metals can be deposited to form a good ohmic contact. The specific scheme for achieving source and drain ohmic contact in the embodiments of this application is not limited.

[0074] Step S3: preparing a gate dielectric layer on the surface of the substrate.

[0075] Specifically, as shown in FIG7 , a gate dielectric layer is formed between the source and drain electrodes on the substrate surface, wherein the gate dielectric layer formation may include: interface treatment, gate dielectric layer growth, and gate dielectric layer annealing.

[0076] In some embodiments, regarding interface treatment: after completing the source-drain ohmic contact process and before growing the gate dielectric layer, the substrate surface needs to be treated to remove contamination or defects on the substrate surface and reduce the interface state density.

[0077] Among them, the interface treatment method may include at least one of the following methods: wet treatment, dry treatment, and a treatment method combining wet and dry treatment. The embodiments of the present application do not impose specific restrictions on this. For example: wet treatment mainly involves treating the substrate surface under appropriate conditions through a solution, wherein the solution may include: at least one of TMAH, BOE or HCL; wet treatment conditions may include: at least one of solution concentration, treatment time and solution temperature. Exemplarily, dry treatment mainly involves treating the semiconductor interface under appropriate conditions through plasma, wherein the plasma may include: at least one of N ions and O ions; dry treatment conditions may include: at least one of gas flow rate, power and treatment time.

[0078] In some embodiments, for the growth of the gate dielectric layer, the gate dielectric layer may be deposited by at least one of the following methods: atomic layer deposition (ALD), magnetron sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), etc. It is understood that since the gate dielectric layer includes at least a first dielectric layer and a superlattice dielectric layer, a variety of different growth methods may be used for the growth of the gate dielectric. For example, different growth methods may be used depending on the material of the dielectric layer, or the same growth method may be used to prepare the dielectric layer. This is not specifically limited in the embodiments of the present application.

[0079] In some embodiments, gate dielectric layer annealing can effectively repair defects generated at the interface and in the gate dielectric material during gate dielectric deposition. Therefore, the gate dielectric layer annealing atmosphere can be N2 or O2, and the annealing temperature can be 500-1000°C.

[0080] Step S4: preparing a gate on the surface of the gate dielectric layer.

[0081] Specifically, as shown in FIG7 above, a gate metal is deposited on the surface of the gate dielectric layer and etched to obtain a gate. The gate metal can be deposited by one or more methods such as electron beam evaporation and magnetron sputtering. The gate metal can be a stacked structure, wherein the metal on the side close to the gate dielectric layer can be one or more of Ni or W, and the metal on the side away from the gate dielectric layer can be Au, etc., and the embodiment of the present application does not impose specific restrictions on this. In addition, in the direction parallel to the substrate, in order to ensure the normal function of the MIS gate structure device and prevent the gate from directly contacting the source or drain, the length of the gate is less than the spacing between the source and the drain.

[0082] In some embodiments, after the gate metal is formed, an annealing process at 100-600° C. may be performed to improve gate adhesion.

[0083] It should be noted that the above is only an exemplary method for preparing MIS gate structure devices provided in the embodiment of the present application. The embodiment of the present application does not specifically limit the specific preparation process flow, process usage method and process conditions.

[0084] In addition, an embodiment of the present application also provides a chip, including a circuit and the MIS gate structure device provided in the embodiments shown in Figures 2 to 7 above and applied to the circuit.

[0085] An embodiment of the present application further provides an electronic device, comprising a circuit board and the MIS gate structure device provided in the embodiments shown in FIG. 2 to FIG. 7 above, wherein the circuit board is electrically connected to the MIS gate structure device.

[0086] It should be understood that the chip and electronic device provided in this application are consistent with the MIS gate structure device technical solution provided in this application. Their specific content and beneficial effects can be referred to the MIS gate structure device provided in the embodiments shown in Figures 2 to 7 above, and will not be repeated here.

[0087] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0089] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0091] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0092] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A MIS gate structure device, characterized in that: include: A substrate, a gate dielectric layer, a source electrode, a drain electrode, and a gate electrode on the substrate; wherein the gate dielectric layer, the source electrode, and the drain electrode are all arranged on the surface of the substrate, and the gate dielectric layer is arranged between the source electrode and the drain electrode; and the gate electrode is stacked on a side of the gate dielectric layer away from the substrate; The gate dielectric layer includes a first dielectric layer and a superlattice dielectric layer that are stacked, the superlattice dielectric layer includes at least a second dielectric layer and a third dielectric layer that are stacked, and the first dielectric layer is arranged between the substrate and the superlattice dielectric layer; The material forming the second dielectric layer is different from the material forming the third dielectric layer, and the dielectric constants of the materials forming the second dielectric layer and the third dielectric layer are both greater than 10.

2. The MIS gate structure device according to claim 1, characterized in that: The gate dielectric layer includes multiple layers of the superlattice dielectric layer; the multiple layers of the superlattice dielectric layer are arranged on a side of the first dielectric layer away from the substrate.

3. The MIS gate structure device according to claim 1 or 2, characterized in that: In a direction perpendicular to the substrate, the thickness of the gate dielectric layer is between 0.3 nm and 50 nm.

4. The MIS gate structure device according to any one of claims 1 to 3, characterized in that: In a direction perpendicular to the substrate, the thickness of the first dielectric layer, the thickness of the second dielectric layer, and the thickness of the third dielectric layer are all between 0.1 nm and 5 nm.

5. The MIS gate structure device according to any one of claims 1 to 4, characterized in that: The material forming the second dielectric layer and the third dielectric layer includes at least one of the following materials: hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, tantalum pentoxide Ta2O5, lanthanum oxide La2O3, lutetium dioxide LuO2, yttrium oxide Y2O3, and scandium oxide Sc2O3.

6. The MIS gate structure device according to any one of claims 1 to 5, characterized in that: The material forming the first dielectric layer includes at least one of the following materials: aluminum oxide Al2O3, silicon nitride SiN x , silicon dioxide SiO2.

7. The MIS gate structure device according to any one of claims 1 to 4, characterized in that: The material forming the first dielectric layer is the same as the material forming the second dielectric layer; The materials forming the first dielectric layer and the second dielectric layer include at least one of the following materials: aluminum oxide Al2O3, silicon nitride SiN x , silicon dioxide SiO2; The material forming the third dielectric layer includes at least one of the following materials: hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, tantalum pentoxide Ta2O5, lanthanum oxide La2O3, lutetium dioxide LuO2, yttrium oxide Y2O3, and scandium oxide Sc2O3.

8. The MIS gate structure device according to any one of claims 1 to 7, characterized in that: The gate dielectric layer further includes a fourth dielectric layer; The fourth dielectric layer is disposed between multiple layers of the superlattice dielectric layer; or provided between the first dielectric layer and the plurality of superlattice dielectric layers; or It is arranged on a side of the multi-layer superlattice dielectric layer away from the first dielectric layer.

9. A chip, characterized in that: The invention comprises a circuit and a MIS gate structure device according to any one of claims 1 to 8 applied to the circuit.

10. An electronic device, characterized in that: The invention comprises a circuit board and a MIS gate structure device according to any one of claims 1 to 8, wherein the circuit board is electrically connected to the MIS gate structure device.

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