Layered structures

Abstract

The present disclosure relates to a layered structure comprising: a substrate; a first semiconductor layer over the substrate; an epitaxial metal layer over the first semiconductor layer; and a second semiconductor layer over the epitaxial metal layer. The epitaxial metal layer is configured to modify carrier movement in the second semiconductor layer.

Description

LAYERED STRUCTURESTechnical fieldThe present application relates to a layered structure. The present application also relates to a semiconductor device, an electronic device and a method of manufacturing a layered structure.A layered semiconductor structure may be formed of multiple layers which are epitaxially grown in a stack. The layered structure may be grown using a number of methods, such as chemical vapour deposition (CVD), metal organic CVD (MOCVD), metalorganic vapour-phase epitaxy (MOVPE) and molecular beam epitaxy (MBE). Typically, multiple layers are deposited layer-by-layer on a substrate. The substrate, and the layers, typically comprise semiconductor material.The layers are grown on the substrate to form a semiconductor structure, which may be referred to as a wafer. The wafer may subsequently be fabricated into a semiconductor device, such as a transistor, a filter, a light emitting diode (LED), a micro LED (pLED); a vertical cavity surface emitting laser (VCSEL), an edge emitting laser and a photodetector.The materials used to form the layered structure dictate the properties of the resulting semiconductor device. Semiconductor materials have been developed, which can provide a wide array of properties. However, incorporating other materials into a layered semiconductor structure could lead to additional functionality.It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques.According to a first aspect there is provided a layered structure comprising: a substrate; a first semiconductor layer over the substrate; an epitaxial metal layer over the first semiconductor layer; and a second semiconductor layer over the epitaxial metal layer.The epitaxial metal layer is configured to modify carrier movement in the second semiconductor layer.According to a second aspect there is provided a layered structure comprising: a substrate; a plurality of layers over the substrate comprising: a first lll-N semiconductor layer; an epitaxial metal layer over the first lll-N semiconductor layer; a second lll-N semiconductor layer over the epitaxial metal layer; and an interlayer comprising lll-N material contacting the epitaxial metal layer. The interlayer is between the first lll-N semiconductor layer and the epitaxial metal layer or between the second lll-N semiconductor layer and the epitaxial metal layer.According to a third aspect there is provided a semiconductor device comprising the layered structure according to the first aspect or the second aspect.According to a fourth aspect there is provided an electronic device comprising the semiconductor device according to the third aspect.According to a fifth aspect there is provided a method of forming a layered structure comprising: forming a first semiconductor layer over a substrate; forming an epitaxial metal layer over the first semiconductor layer; and forming a second semiconductor layer over the epitaxial metal layer; wherein the epitaxial metal layer is configured to modify carrier movement in the second semiconductor layer.Brief of theFor a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which:Figure 1 is a example of a semiconductor device;Figure 2 is a example of a layered structure;Figures 3a-d are examples of semiconductor devices;Figure 4 is another example of a layered structure;Figure 5 is another example of a layered structure;Figure 6 is another example of a layered structure;Figure 7 is an example of a HEMT ;Figure 8 is an example of a HEMT ;Figure 9 is an example of a Schottky diode;Figure 10 is another example of a layered structure;Figure 11 is another example of a layered structure.Detailed DescriptionEpitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Epitaxy can also be performed in a metal-organic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition.Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer.A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1 :1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to theproportion of that element within that group. Thus Alo.2sGaAs means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As.Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out- of-plane is used to mean perpendicular to the surface of the substrate.Throughout this disclosure, as will be understood by the skilled reader, crystal orientation <100 means the face of a cubic crystal structure and encompasses

[0100] ,

[0010] and

[0001] orientations using the Miller indices. Similarly <0001> encompasses

[0001] and [000-1] except if the material polarity is critical. Integer multiples of any one or more of the indices are equivalent to the unitary version of the index. For example, (222) is equivalent to, the same as, (111).Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), germanium (Ge), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb).A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100 crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction.Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type.Lattice matched means that two crystalline layers have the same, or similar, lattice spacing and so the second layer will tend to grow isomorphically on the first layer. Lattice constant is the unstrained lattice spacing of the crystalline unit cell. Lattice coincident means that a crystalline layer has a lattice constant which is, or is close to, an integer multiple of the previous layer so that the atoms can be in registry with the previous layer. Lattice mismatch is where the lattice constants of two adjacent layers are neither lattice matched nor lattice coincident. Such mismatch introduces elastic strain into the structure, particularly the second layer, as the second layer adopts the in-plane lattice spacing of the first layer. The strain is compressive where the second layer has a larger lattice constant and tensile where the second layer has a smaller lattice constant.Where the strain is too great the structure relaxes to minimise energy through defect generation, typically dislocations, known as slip, or additional interstitial bonds, each of which allows the layer to revert towards its lattice constant. The strain may be too great due to a large lattice mismatch or due to an accumulation of small mismatches over many layers. A relaxed layer is known as metamorphic, incoherent, incommensurate or relaxed, which terms are also commonly interchangeable.A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function.A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to thevolume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers.A crystalline bixbyite oxide layer may be a rare earth oxide layer. The rare earth elements are scandium (Sc), yttrium (Y) and all of the lanthanoid series which is lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu). The bixbyite oxides are bixbyite in crystal structure. Other bixbyite oxides include indium oxide (ln2O3), vanadium oxide (V2O5), iron oxide (Fe2O3), manganese oxide (Mn2O3) and ternary compounds of a rare earth, a metal and oxygen (RE-M-O).Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer.Examples according to the present disclosure relate to a layered structure comprising a first semiconductor layer, a second semiconductor layer and an epitaxial metal layer situated between the two semiconductor layers. Examples according to the present disclosure thus provide a layered structure, where a metal layer can be epitaxially formed in a layered semiconductor stack for forming a semiconductor device. It is common to form metallic contacts on an exterior of a layered structure in order to apply a current to a semiconductor device. However, examples according to the present disclosure can insert a metal layer into a layered structure in order to utilise the properties of the metal layer in a variety of semiconductor devices. In particular, in examples according to the present disclosure, the metal layer is configured to modify carrier movement in the second semiconductor layer.In one example, the metal layer can act as a current spreading layer to evenly spread carriers or a current across a semiconductor device. In many semiconductor devices current “hotspots” can be observed where the current across a device is not conducted evenly. Such current hotspots are undesirable as they can lead to inconsistent deviceperformance. The buried metal layer can act to spread the current across a semiconductor device to thereby improve device performance.In another example, the metal layer can be epitaxially formed in a layered semiconductor stack for forming a high electron mobility transistor (HEMT). For example, the metal layer may be inserted between the buffer layer and channel layer of the HEMT. In such an example, the metal layer can act as a back gate, where carrier movement and thus the conductive properties of the HEMT can be modified by the application of a voltage to the buried back gate. In one example, the buried back gate can be used to turn a typical depletion mode (D-mode) HEMT into an enhancement mode (E-mode) HEMT.In another example, the metal layer can comprise resistive properties. For example, the metal layer can be formed thin such that the metal layer exhibits resistive properties. In such examples, the metal layer may again be epitaxially grown between a buffer layer and a channel layer of a HEMT. In such examples, the resistive properties of the metal layer may act as an electric field terminator, which can prevent carriers migrating from the channel layer to the buffer layer. The resistive metal layer can thus reduce drain lag, which is a common problem in conventional HEMTs.In another example, the epitaxial metal layer may be used to form one or more Schottky diodes. The metal layer may be epitaxially grown in a semiconductor stack, where a Schottky barrier may be formed with the semiconductor layers either side of the metal layer to modify carrier movement. The metal and semiconductor layer stack may be fabricated into a three terminal Schottky diode semiconductor device for a wide variety of applications, such as power regulating applications. The ability to epitaxially form the metal and semiconductor layers reduces fabrication processing time, compared to conventional methods, which typically involve bonding the metal and semiconductor layers.Figure 1 illustrates a schematic example of a semiconductor device 100 formed from a layered structure. Semiconductor device 100 comprises a substrate 110. In some examples, the substrate 110 may comprise a n-type substrate. In some examples, the substrate may comprise any suitable material as described above.Semiconductor device 100 further comprises a buffer layer 120 over the substrate. In some examples the buffer layer 120 may comprise 11 l-V semiconductor material, such as lll-As semiconductor material or lll-N semiconductor material.Semiconductor device 100 further comprises a device region 130 over the buffer layer 120. The device region 130 may comprise one or more device layers, which individually or in combination provide some function in a semiconductor device. For example, the device region may comprise device layers for an opto-electronic semiconductor device. In such examples, the device layers may comprise a photonic active layer for generating or absorbing light. For example, the active layer may comprise one or more quantum wells, one or more quantum dots or a combination thereof. In such examples, the device region may further comprise one or more cladding layers located either side of the active layer. In some examples, the device region may comprise one or more mirrors either side of the active layer. For example, the device region may comprise a pair of distributed Bragg reflectors (DBRs) comprising semiconductor material either side of the active region. In other examples, the device region may comprise a device layers for an electronic semiconductor device such as a high electron mobility transistor (HEMT). In such examples, the device region may comprise a channel layer and a barrier layer for a HEMT. In some examples, the device layer(s) of the device region 130 may comprise lll-V semiconductor material, such as lll-As semiconductor material or lll-N semiconductor material.Semiconductor device 100 further comprises a contact layer 140 over the device region 130. In some examples the contact layer 140 may comprise lll-V semiconductor material, such as lll-As semiconductor material or lll-N semiconductor material. In some examples, the contact layer 140 may be doped p-type.In some examples, the buffer layer 120, device region 130 and contact layer 140 may be epitaxially grown on the substrate 110.Semiconductor device 100 further comprises a first contact node 150 connected to the substrate 110 and a second contact node 160 connected to the contact layer 140. First contact node 150 and second contact node 160 may further be connected to a current source 170. The connection of first contact node 150, second contact node 160 and current source 170 may thus apply a current 180 to semiconductor device 100. In some examples, the contact nodes 150, 160 may comprise a metal for applying the current tothe semiconductor device 100. In other examples, the contact layer 140 may be omitted from semiconductor device 100, and first contact node 150 may be contacted to a layer of device region 130.As described above, in some examples, current hotspots may occur within the semiconductor device 100. For example, defects may be present within the buffer layer 120, which may lead to the current hotspots. Such current hotspots can result in inconsistent current conduction across the semiconductor device 100, which can lead to inconsistent and undesirable device performance.To improve the current conduction of the semiconductor device 100, dopants may be introduced into layers of the semiconductor device 100. For example, substrate 110 and buffer layer 120 may be doped n-type and contact layer 140 may be doped p-type. This result in a device with a p-on-n junction configuration either side of the device region 130. Furthermore, device layers of the device region 130 may be doped to assist in the current conduction of the semiconductor device 100. In other examples, semiconductor device 100 may comprise a n-on-p junction with contact layer 140 doped n-type and buffer layer 120 and substrate 110 doped p-type.In some material systems, however, the doping concentrations of layers of the semiconductor device 100 may be limited. For example, it can be challenging to introduce dopants into lll-N semiconductor materials, such as GaN, whilst still maintaining high quality crystallinity, low strain and without affecting other layers of the layered structure. For example, dopants may migrate to layers where they are not desired. In another example, the growth conditions used for the addition of dopants may be sub-optimal for the formation of a layer with high crystallinity and low strain. Thus, poor current conduction efficiency and the presence of current hotspots may not be reliably overcome by increasing doping concentrations in some semiconductor materials, such as, lll-N semiconductor materials.Examples according to the present disclosure provide a layered structure including a “buried” metal electrode for spreading current in a device. The metal electrode may be included between two semiconductor layers to more evenly distribute carriers or a current across the device to reduce the presence of current hotspots. The presence of a metal layer within the device, as opposed to at the exterior of the device, may improve the current spreading capabilities of the metal. For example, the reduced distancebetween the metal layer and the device region may result in a more evenly distributed current being applied to the device layers to thereby improve the performance of the device.Figure 2 illustrates a layered structure 200 comprising a “buried” metal electrode layer 220. Layered structure 200 may thus comprise a first semiconductor layer 210 and a second semiconductor layer 230 with metal layer 220 located between the first semiconductor layer 210 and a second semiconductor layer 230. The first semiconductor layer 210, the metal layer 220 and the second semiconductor layer 230 may be epitaxially formed on the substrate 110. In some examples, the first semiconductor layer 210 and the second semiconductor layer 230 may comprise lll-N semiconductor material such as GaN. However, in other examples, the first semiconductor layer 210 and the second semiconductor layer 230 may comprise other lll-V semiconductor materials, such as lll-As semiconductor materials e.g. GaAs.In some examples, the metal layer 220 may comprise a metal for conducting a current. In some examples, the metal layer 220 may comprise Mo, Al, or Pt.In some examples, the first semiconductor layer 210 and the second semiconductor layer 230 may comprise the same doping type. For example, the first semiconductor layer 210 and the second semiconductor layer 230 may comprise n-type dopants. In some examples, an n-type dopant for a lll-N semiconductor material may comprise Si. In some examples, the first semiconductor layer 210 and the second semiconductor layer 230 may comprise p-type dopants. In some examples, a p-type dopant for a lll-N semiconductor material may comprise Mg.Metal layer 220 may thus act to conduct a current and more evenly distribute the current across a device. Furthermore, whilst the dopant concentration the first semiconductor layer 210 and the second semiconductor layer 230 may be limited, the dopants present within these layers may still promote current conduction of a device. In some examples, first semiconductor layer 210, metal layer 220 and second semiconductor layer 230 may thus be referred to as a contact buffer region 201. Contact buffer region 201 may thus be located over substrate 110 and may thereby be incorporated within a layered structure for device fabrication, as opposed to a conventional contact layer, which may be formed on an exterior surface of the substrate 110.For example, buffer layer 120 described above with respect to the device 100 of Figure 1 may be replaced with contact buffer region 201. As such, contact buffer region 201 may thus act to apply a more evenly distributed current to the device region 130 and may further reduce the presence of current hotspots and improve device performance.As will be described in more detail below, a contact node may be applied to the contact buffer region 201 to provide an electrical connection for a device formed from a layered structure including the contact buffer region 201.The first semiconductor layer 210 and the second semiconductor layer 230 may be formed of materials to provide an appropriate buffer between the substrate 110 and the device region 130, or for any intermediary layers between the substrate 110 and the device region 130. The presence of the metal layer 220 may thus not detrimentally impact the crystallinity and strain properties of the contact buffer region 201 as a whole, such that, contact buffer region 201 is able to provide an appropriate platform for the epitaxial growth of semiconductor layers on the contact buffer region 201. Thus, in some examples, first semiconductor layer 210 and the second semiconductor layer 230 may comprise the same lll-N semiconductor material. For example, first semiconductor layer 210 and the second semiconductor layer 230 may comprise lll-N material, such as GaN, AIN or ScAIN. Forming first semiconductor layer 210 and second semiconductor layer 230 from the same lll-N material may improve the crystallinity and strain properties of the contact buffer region 201 as they will be lattice matched either side of the metal layer 220.In some examples, metal layer 220 may comprise a thickness from about 10 nm to about 40 nm. A thickness within this range may result in the metal layer 220 providing improved current spreading properties, whilst enabling the contact buffer region 201 to be formed with high crystallinity and low strain properties.As illustrated in Figure 2, in some examples, the second semiconductor layer 230 may be thinner than the first semiconductor layer 210. This configuration of the second semiconductor layer 230 and the first semiconductor layer 210 results in the first metal layer 220 being located closer to the device region 130 than if the second semiconductor layer 230 and the first semiconductor layer 210 were of equal thicknesses. As such, this configuration of the second semiconductor layer 230 and the first semiconductor layer 210 may improve the current spreading capabilities of the first metal layer 220.Furthermore, the thicker first semiconductor layer 210 may result in enhanced crystal quality and therefore a high-quality surface for the growth of the metal layer 220 thereon.Figures 3a-d illustrate semiconductor devices 300a-d comprising the contact buffer region 201 described above with respect to Figure 2. The contact buffer region 201 may thus operate in substantially the same way to that described above with respect to Figure 2. Semiconductor devices 300a-d further comprise elements in common with semiconductor device 100 described above with respect to Figure 1. Said common elements are labelled with corresponding reference numerals and may operate in substantially the same way to that described above.Figure 3a illustrates a semiconductor device 300a comprising the contact buffer region 201 over substrate 110. Semiconductor device 300a further comprises semiconductor device region 130 over the contact buffer region 201. Substrate 110 may comprise a conductive substrate, such as a n-type Si. Thus, an application of a current from current source 170 will be conducted by the substrate 110 and be conducted by the metal layer 220 comprised in contact buffer region 201. Metal layer 220 may thus evenly distribute the current across the semiconductor device 300a.Figure 3b illustrates a semiconductor device 300b comprising contact buffer region 201 over a transition buffer layer 310. Transition buffer 310 may improve the strain of the semiconductor device 300b. However, transition buffer 310 may comprise relatively poor electrical conductivity properties. The electrode 220 of the contact buffer region 201 may thus conduct the current from current source 170 to evenly distribute the current across the semiconductor device 300b. Furthermore, by positioning the contact buffer region 201 between the semiconductor device region 130 and the transition buffer 310, the defects of the transition buffer 310 may not impact on the evenly distributed current applied to the semiconductor device region 130 by the metal layer 220 of the contact buffer region 201 .Figure 3c illustrates a semiconductor device 300c comprising a contact buffer region 201 over a porous transition buffer 320. In some examples, the porous transition buffer 320 may comprise a material with poor electrical conductivity properties such that porous transition buffer 320 is substantially non-conductive or insulating. In some examples, the porous transition buffer 320 may comprise porous silicon. However, the use of such aninsulating material over the substrate 110 prevents the ability to apply a contact node to the substrate 110 for application of a current to the semiconductor device 300c.Semiconductor device 300c thus comprises a contact architecture where portions of device region 130 and contact layer 140 have been etched for contact node 150 to be applied to the contact buffer region 201. In conventional solutions, where contact buffer region 201 does not comprise a metal layer, the application of the contact node 150, at the location as illustrated in Figure 3c, would likely result in current hotspots developing throughout the semiconductor device 300c, due to the restrictive contact configuration. Examples according to the present disclosure, however, include a metal layer 220 within the contact buffer region 201 , which enables the current applied at contact node 150 to be evenly distributed across the semiconductor device 300c.In other examples, substrate 110 may comprise a porous material, for example porous Si. Such a substrate material is substantially non-conductive or insulating. Contact buffer region 201 may thus be contacted by contact node 150 in a similar manner to that illustrated in Figure 3c and act to evenly spread a current across the semiconductor device 300c. In such examples, porous transition layer 320 may be removed and contact buffer region 201 may be formed directly on a substrate 110 comprising a porous material.Figure 3d illustrates a semiconductor device 300d comprising a contact buffer region 201 over a rare earth oxide (REO) transition buffer 330. REO transition buffer 330 may enable the ability to grow lll-N materials, such as GaN, on group IV substrates, such as Si(111) or Si(100) substrates. Such a layered structure can utilise the desirable properties of I II- N materials and the widely available group IV substrates, such as Si. However, REO transition buffer 330 may comprise a substantially non-conductive material or an insulating material. Therefore, a current cannot be applied to the semiconductor device 300d by a contact node on substrate 110.Semiconductor device 300d thus comprises a via 340 through the substrate 110 and the REO transition buffer 330. The via 340 thus enables contact node 150 to contact the contact buffer region 201 for application of a current to the semiconductor device 300d. In conventional solutions, where contact buffer region 201 does not comprise a metal layer, the application of the contact node 150, as illustrated in Figure 3d, would likely result in current hotspots developing throughout the semiconductor device 300d, due tothe restrictive contact architecture. Examples according to the present disclosure, however, include a metal layer 220 within the contact buffer region 201 , which enables the current applied at contact node 150 to be evenly distributed across the semiconductor device 300d.In some examples, REO transition buffer 330 may not be present between the contact buffer region 201 and the substrate 110. However, in such examples, the substrate 110 may comprise a substantially non-conductive or insulating material. However, in a similar manner to that illustrated in Figure 3d, a via may be formed through to the insulating substrate 110, such that, contact node 150 contacts the contact buffer region 201 to evenly distribute current across the semiconductor device 300d.Figure 4 illustrates a layered structure 400 according to examples of the present disclosure. Layered structure 400 comprises elements in common with the devices and layered structures described above. Said common elements are labelled with corresponding reference numerals and may operate in substantially the same way to that described above.Layered structure 400 comprises first contact buffer region 201 over the substrate 110 and device region 130 over the contact buffer region 201. Layered structure 400 further comprises a second contact region 440 over the device region 130.Second contact region 440 may thus comprise a third semiconductor layer 410, and a second metal layer 420 over the third semiconductor layer 410. Second contact region 440 further comprises a fourth semiconductor layer 430 over the second metal layer 420.In some examples, the first semiconductor layer 210 and the second semiconductor layer 230 of the first contact buffer region 201 may be doped n-type and the third semiconductor layer 410 and the fourth semiconductor layer 430 of the second contact region 440 may be doped p-type. In such examples, layered structure 400 may thus be used to form a device with a p-on-n configuration where charge carriers flow from the substrate 110 towards the second contact region 440. However, in other examples, first semiconductor layer 210 and the second semiconductor layer 230 of the first contact buffer region 201 may be doped p-type and the third semiconductor layer 410 and the fourth semiconductor layer 430 of the second contact region 440 may be doped n-type. In such examples, layered structure 400 may thus be used to form a device with a n-on-p configuration where charge carriers flow towards the substrate 110 from the second contact region 440.Layered structure 400 thus comprises a contact buffer region 201 and a second contact region 440 on both sides of the device region 130. First contact buffer region 201 and second contact region 440 may thus each comprise a metal layer and may improve current spreading throughout a device formed from layered structure 400. Furthermore, in some examples, a second device region may be formed on the second contact region 440 for forming a second photonic semiconductor device. The second contact region 440 may thus provide current spreading capabilities to the second device region of the second photonic semiconductor device.In some examples, the second metal layer 420 may comprise a metal, for example, Mo, Al or Pt. In such examples, second contact region 440 may thus comprise a substantially corresponding structure to the first contact buffer region 201. The description above in relation to the first semiconductor layer 210, the first metal layer 220 and the second semiconductor layer 230 of the contact buffer region 201 may thus also apply to the third semiconductor layer 410, the second metal layer 420, and the fourth semiconductor layer 430 of contact layer 440, respectively, and in a substantially corresponding manner.In some examples, layered structure 400 may be used to form an edge-emitting photonic device. For example, light 450 may be output from a side of a semiconductor device formed from layered structure 400. In some examples, second metal layer 420 and metal layer 220 may be substantially opaque to an output wavelength of the light 450. Thus, the locations of second metal layer 420 and first metal electrode 220 may improve current spreading throughout a device formed from layered structure 400 without inhibiting the light 450.Figure 5 illustrates another example of a layered structure 500 according to examples of the present disclosure. Layered structure 500 comprises elements in common with the device and layered structures described above. Said common elements are labelled with corresponding reference numerals and may operate in substantially the same way to that described above.Layered structure 500 comprises the contact region 440 over the device region 130. In a similar manner to that described above for Figure 4, metal layer 420 of the contactlayer 500 may thus conduct a current and spread the current evenly across a device formed from layered structure 500.In some examples, layered structure 500 may be used to form a bottom -emitting photonic device where light passes through the substrate 110. In such examples, the third semiconductor layer 410 and the fourth semiconductor layer 430 of the contact layer 540 may be doped n-type and the substrate 110 may be doped p-type. A current may thus be applied to the layered structure 500 such that charge carriers flow from the contact layer 440 towards the substrate 110. In this way, metal layer 420 may spread current evenly for application to the device region 130.Figure 6 illustrates another example of a layered structure 600 according to examples of the present disclosure. Layered structure 600 comprises elements in common with the device and layered structures described above. Said common elements are labelled with corresponding reference numerals and may operate in substantially the same way to that described above.Layered structure 600 comprises contact buffer region 201 over substrate 110. Layered structure 600 further comprises a plurality of device regions 630a-c over the contact buffer region 201 . The plurality of device regions 630a-c comprise a first device region 630a, a second device region 650b and a third device region 630c. The plurality of device regions 630a-c comprise device layers for forming a function in a semiconductor device. Layered structure 600 thus further comprises a plurality of devices 650a-c. First device 650a may thus comprise first device region 630a, second device 650b may comprise second device region 630b and third device 650c may comprise third device region 630c. Due to the configuration of the device regions 630a-c over the contact buffer region 201 , the metal layer 220 of the contact buffer region 201 may thus evenly distribute the current across each of the devices 650a-c to improve current spreading and lead to more consistent device performance.Examples according to present disclosure have thus far presented the buried metal layer as part of a semiconductor device, such as an optoelectronic semiconductor device, to improve current spreading throughout the semiconductor device. In other examples, however, the buried metal layer may be used in other ways in other semiconductor devices. For example, the buried metal layer may be used as a back gate to adjust the conductive properties of a high electron mobility transistor (HEMT).Figure 7 illustrates an example of a HEMT 700 according to examples of the present disclosure. HEMT 700 thus comprises a layered structure according to examples of the present disclosure.HEMT 700 comprises a substrate 110, a nucleation layer 715, a buffer layer 710, a metal layer 720, a channel layer 730 and a barrier layer 740. The nucleation layer 715, buffer layer 710, channel layer 730 and barrier layer 740 comprise semiconductor material. In one example, nucleation layer 715, buffer layer 710, channel layer 730 and barrier layer 740 comprise lll-N semiconductor material. However, in other examples, the buffer layer 710, channel layer 730 and barrier layer 740 comprise other lll-V materials, for example, lll-As materials such as GaAs-based materials. The nucleation layer 715, buffer layer 710, metal layer 720, channel layer 730 and a barrier layer 740 may thus be epitaxially grown on the substrate 110.The nucleation layer 715 and buffer layer 710 may be configured to minimize defects and provide isolation between the substrate 110 and the channel layer 730 above the buffer layer 710. In some examples, the nucleation layer 715 comprises AIN. In some examples, the buffer layer 710 comprises GaN. In some examples, the buffer layer 710 may comprise AIGaN. In some examples, the buffer layer 710 may be doped. In some examples, the buffer layer 710 may be doped with C.Channel layer 730 provides the channel in the HEMT 700 for charge carriers to flow. A 2-dimensional electron gas (2DEG) 750 is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The 2DEG 750 is formed in the channel layer 730 due to electron diffusion from the barrier layer 740 to the channel layer 730 and due to a polarization discontinuity between the barrier layer 740 and the channel layer 730. In some examples, the channel layer 730 comprises GaN and the barrier layer 740 comprises AIGaN.HEMT 700 further comprises a source contact 760, a drain contact 770 and a gate contact 780. As illustrated in Figure 7, the 2DEG 750 is continuous between the source contact 760 and the drain contact 770. As such, with no bias voltage applied to the gate contact 780, the formation of the 2DEG results in current flow between the source contact 760 and drain contact 770, where the HEMT is in the conducting or ‘on-state’. The HEMT 700 may thus exhibit depletion mode (D-mode) behaviour. A negative bias voltage isapplied to the gate contact 780 to turn the HEMT 700 to the non-conducting or ‘off-state’ where the formation of the 2DEG 750 is interrupted.HEMT 700 further comprises a metal layer 720 located between the buffer layer 710 and the channel layer 730. In addition to the gate contact 780, metal layer 720 may be configured to modify carrier movement in the channel layer 730 and control the conductive properties of the channel layer 730. In some examples, metal layer 720 may thus be referred to as a ‘back gate contact’, which in a similar manner to the gate contact 780, can receive a voltage to modify the conductive properties of the channel layer 730 and thus modify the formation of the 2DEG 750. Metal layer 720 may thus be configured to receive a bias voltage VBIAS from a voltage source 790 to modify the conductive properties of the channel layer 730. In such examples, the metal layer 720 may thus be configured to apply an electric field to the channel layer 730 to modify carrier movement in the channel layer 720.In some examples, the bias voltage VBIAS may thus be configured to set the threshold voltage of HEMT 700. In one example, the bias voltage BIAS may be configured to push the 2DEG 750 towards the gate contact 780, to result in HEMT 700 exhibiting a lower magnitude threshold voltage.In some examples, the voltage source 790 may be configured to modify the bias voltage VBIAS on-the-fly to adjust the threshold voltage of the HEMT 700 in situ. For example, the HEMT 700 may form part of field programmable gate array (FPGA), where the threshold voltage of the HEMT 700 may be adjusted for a given application.As the bias voltage VBIAS may be configured to adjust the threshold voltage of the HEMT 700, in some examples, the bias voltage VBIAS may be configured to operate the HEMT 700 with enhancement mode (E-mode) behaviour. For example, VBIAS may comprise a negative voltage configured to interrupt formation of the 2DEG 750 in the channel layer 730. This prevents current flow between the source contact 760 and drain contact 770 and thus configures the HEMT 700 in the non-conducting or ‘off-state’. A voltage may thus be applied to the gate contact 780 to counteract the negative bias voltage VBIAS and enable formation of the 2DEG 750 between the source contact 760 and drain contact 770 in order to transition the HEMT 700 to the conducting or ‘on-state’.The location of the metal layer 720 between the channel layer 730 and the buffer layer 710 may enable improved control of the conductive properties of the channel layer 730, compared to if the metal was further away from the channel layer 730, for example, formed on an exterior surface of the substrate 110. In some examples, however, a second buffer layer may be formed on the metal layer 720 and the channel layer 730 may be formed on the second buffer layer. The second buffer layer may minimize any defects, which may have been brought about by the growth of the metal layer 720 in order to provide improved epitaxial formation of the channel layer 730. In some examples, the second buffer may comprise GaN or AIGaN.Metal layer 720 may comprise substantially corresponding features to the metal layer 220 described above. Metal layer 720 may thus comprise Mo, Al or Pt. Metal layer 720 may comprise a thickness between 10 to 40 nm.HEMT 700 thus provides an example where a metal layer may be used as a back gate to modify carrier movement and the conductive properties of the HEMT channel. In such examples, the metal layer is contacted to apply a voltage to the metal layer. In other examples, however, the metal layer may not be contacted and may be resistive to modify carrier movement in the channel layer in a passive manner.Figure 8 illustrates another example of a HEMT 800 according to examples of the present disclosure. HEMT 800 comprises elements in common with the HEMT 700 described above. Said common elements are labelled with corresponding reference numerals and may operate in substantially the same way to that described above. HEMT 800 thus comprises a layered structure according to examples of the present disclosure.HEMT 800 comprises a metal layer 820 positioned between the buffer layer 710 and channel layer 730, in a similar manner to the metal layer 720 described above with respect to HEMT 700. Metal layer 820, however, comprises a resistive metal. In some examples, a metal layer can be made resistive or non-conductive by forming the metal layer 820 with a thin thickness. In some examples, metal layer 820 may comprise a thickness of less than 10 nm. In some examples, the metal layer may comprise a thickness of less than 2 nm. In some examples, the metal layer 820 may comprise a thickness between 1.5 nm to 2 nm. In some examples the metal layer 820 may comprise a thickness of about 0.3 nm. In some examples, the metal layer 820 may comprise a monolayer. In some examples, the metal layer 820 may comprise Mo, Al or Pt.In conventional HEMTs, it is common for carriers to migrate from the channel layer 730 and into the buffer layer 710. Defects in the buffer layer referred to as ‘traps’ can trap the charge carriers in the buffer layer 710. It can take many milliseconds for the carriers to be released from the traps, which reduces conductivity of the 2DEG 750 and results in drain lag.In examples according to the present disclosure, the resistive properties of the metal layer 820 prevent carriers migrating from the channel layer 730 into the buffer layer 710. The metal layer 820 acts as an electric field terminator and carrier interceptor to prevent the migration of the carriers to thereby minimize or eliminate the effects of drain lag in HEMT 800.The resistive properties of the metal layer 820 may additionally help prevent the metal layer 820 causing a source 760 to drain 770 short or leakage. Furthermore, in applications where HEMT 800 is used for RF communication, the resistive properties of the metal layer 820 may minimize any RF signal noise.As similarly described above for HEMT 700, in some examples, a second buffer layer may be formed on the metal layer 820 and the channel layer 730 may be formed on the second buffer layer. The second buffer layer may minimize any defects, which may have been brought about by the growth of the metal layer 820 in order to provide improved epitaxial formation of the channel layer 730. In some examples, the second buffer may comprise GaN or AIGaN. In such examples, the second buffer layer may be made sufficiently thin such that the second buffer layer does not comprise a significant number of traps that can cause a detrimental drain lag in the HEMT 800.HEMT 700 and HEMT 800 provide examples where the buried epitaxial metal layer can provide functionality in a HEMT. However, the buried metal layer may provide functionality in additional semiconductor devices for electronic applications, such as a Schottky diode.Figure 9 illustrates a schematic example of a three terminal Schottky diode 900 according to examples of the present disclosure. The Schottky diode 900 thus comprises a layered structure according to examples of the present disclosure.Schottky diode 900 comprises a substrate 110, which may comprise any of the features or functionality described above.Schottky diode 900 further comprises a buffer layer 902, first contact layer 904, first semiconductor layer 910, metal layer 920, second semiconductor layer 920 and second contact layer 930. In some examples, buffer layer 902, first contact layer 904, first semiconductor layer 910, metal layer 920, second semiconductor layer 930 and second contact layer 940 may be epitaxially grown on the substrate 110.In some examples, buffer layer 902, first contact layer 904, first semiconductor layer 910, second semiconductor layer 930 and second contact layer 940 comprise lll-V semiconductor material. In some examples, the lll-V semiconductor material may comprise lll-N semiconductor material or lll-As semiconductor material.In some examples, metal layer 920 may be configured to form a Schottky barrier at the interface with the first semiconductor layer 910 and the second semiconductor layer 930. The Schottky barrier height is dictated by the work function of the metal layer 920. In some examples, the Schottky barrier may be between 0.5 to 4 eV. The work function of the metal layer 920 may thus be configured to set the characteristics of the three terminal Schottky diode 900, for example, the breakdown voltage and forward voltage.In some examples, the metal layer 920 may comprise Mo, Al or Pt. In some examples, the work function of the metal layer 920 may be adjusted by doping the metal layer 920. For example, the metal layer 920 may be doped with materials to modify the work function such as N or O. In some examples, the thickness of the metal layer 920 may be between 0 nm to 150 nm. In some examples, the thickness of the metal layer 920 may be between 40 nm to 150 nm. In some examples, a thicker metal layer 920 may be more desirable, as a thicker metal layer 920 may result in the Schottky diode 900 exhibiting lower resistivity.Schottky diode 900 further comprises a first contact node 950 coupled to the first contact layer 904, a second contacted node 960 coupled to the metal layer 920 and a third contact node 970 coupled to the second contact layer 940. The first contact layer 904 and second contact layer 940 may be doped to provide an improved connection to first contact node 950 and third contact node 970, respectively. For example, the first contact layer 904 may be doped n-type and the second contact layer 940 may be doped p-type.In some examples, the first and second contact layer 904, 940 may be heavily doped n+ and p+, respectively. Such a doping scheme may result in the first contact node 950 and the third contact node 970 being contacted with an ohmic nature to the first contact layer 904 and second contact layer 940, respectively.In some examples, the first semiconductor layer 910 and the second semiconductor layer 930 may be doped. For example, doping the first semiconductor layer 910 and the second semiconductor layer 930 may alter the characteristics of the Schottky barrier being formed between the metal layer 920, and the first semiconductor layer 910 and the second semiconductor layer 930. In some examples, the doping concentration of the first semiconductor layer 910 and the second semiconductor layer 930 may set the properties of the Schottky diode, such as breakdown voltage and forward voltage. In some examples, the first semiconductor layer 910 may be doped n-type and the second semiconductor layer 930 may be doped p-type. In some examples, the metal layer 920 may comprise Mo, the first semiconductor layer 910 may comprise n-type GaN and the second semiconductor layer 930 may comprise p-type GaN. In such examples, a first Schottky barrier between the first semiconductor layer 910 and the metal layer 920 may be between about 0.5 eV and about 1 eV, and a second Schottky barrier between the second semiconductor layer 930 and the metal layer 920 may be between about 2.3 eV and about 2.8 eV.The construction of the three terminal Schottky diode 900 forms two Schottky diodes. The first Schottky diode is formed between the metal layer 920 and first semiconductor layer 910 and the second Schottky diode is formed between the metal layer 920 and the second semiconductor layer 930. A voltage may thus be applied across the first Schottky diode by application of a voltage between the first contact node 950 and the second contact node 960, and a voltage may be applied across the second Schottky diode by application of a voltage to the second contact node 960 and the third contact node 970.In some examples, the two Schottky diodes formed in the three terminal Schottky diode 900 may be used in a variety of applications, such as voltage clamping and power regulating circuitry.In examples according to the present disclosure, one or both of the semiconductor layers either side of the metal layer, such as first semiconductor layer 210 and the second semiconductor layer 230, buffer layer 710 and channel layer 730 or first semiconductorlayer 910 and second semiconductor layer 930 may comprise GaN. GaN possesses many properties that are attractive for electronic and photonic device applications.It has been observed, however, that the interface between a lll-N semiconductor material and a metal layer can degrade and lead to defects. For example, referring again to Figure 2, defects may thus be present at the interface between the first semiconductor layer 210 and the metal layer 220. Similarly, defects may be present at the interface between the second semiconductor layer 230 and the metal layer 220. It has been observed that N may separate from a lll-N semiconductor material and react with the surface of metal layer 220 with some combinations of materials. For example, where the lll-N semiconductor material comprises GaN, the bond strength between N and Ga is relatively weak. The metal layer may comprise, for example, Mo and it has been observed that N may separate from GaN and form MoN at the interface between the III- N semiconductor material and the metal layer 220. The presence of MoN at the interface between GaN and Mo can inhibit the advantageous properties of the metal layer in examples according to the present disclosure. For example, MoN below the metal layer may result in a reduction of the crystalline qualities of a Mo layer. MoN above the metal electrode layer further reduces the crystal quality of the semiconductor layers grown over the metal layer.Examples according to the present disclosure thus further provide a layered structure, that comprises an interlayer between a metal layer and a lll-N semiconductor material. The interlayer may thus separate the metal layer from the lll-N semiconductor layer and thereby provide a buffer between these two materials. In one example, the interlayer may prevent N of the lll-N semiconductor material from reacting with the surface of the metal electrode layer. The interlayer comprises a material that is different to the lll-N semiconductor material. The interlayer may thus further comprise a material that does not react with the metal layer and does not result in defects at the interface between the interlayer and the metal layer. In some examples, the interlayer may comprise a group III material. In some examples, the interlayer may comprise a lll-N material.In some examples, the interlayer may be present between a semiconductor layer and a metal layer, where the semiconductor layer does not comprise a lll-N material, and instead comprises another lll-V semiconductor material, such as a lll-As material. The interlayer may provide a chemical or crystallographic transition between the metal layer and semiconductor layer.Figure 10 illustrates a schematic example of a layered structure 1000 according to an example of the present disclosure. Layered structure 1000 comprises elements in common with the layered structures and devices described above, where said common elements may operate in substantially the same way to that described above and are labelled with corresponding reference numerals.Layered structure 1000 comprises a first semiconductor layer 1010 and a second semiconductor layer 1030. First semiconductor layer 1010 and second semiconductor layer 1030 may comprise corresponding features and functionality to first semiconductor layer 210 and second semiconductor layer 230 respectively, buffer layer 710 and channel layer 730 respectively, or first semiconductor layer 910 and second semiconductor layer 930 described above. Layered structure 1000 further comprises a metal layer 1020. Metal layer 1020 may comprise corresponding features and functionality to metal layer 220, metal layer 720, metal layer 820 or metal layer 920 described above.Layered structure 1000 further comprises a first interlayer 1015 between the first semiconductor layer 1010 and the metal layer 1020. First interlayer 1015 may thus separate the first semiconductor layer 1010 from the metal layer 1020. First interlayer 1015 may thus prevent the metal layer 1020 detrimentally reacting with the first semiconductor layer 1010. For example, where the first semiconductor layer 1010 comprises a lll-N semiconductor material such as GaN, the first interlayer 1015 may prevent N from the first semiconductor layer 1010 from reacting with the metal layer 1020.Layered structure 1000 further comprises a second interlayer 1025 between the metal layer 1020 and a second semiconductor layer 1030. Second interlayer 1025 may thus separate the second semiconductor layer 1030 from the metal layer 1020. Second interlayer 1025 may thus prevent the metal layer 1020 detrimentally reacting with the second semiconductor layer 1030. For example, where the second semiconductor layer 1030 comprises a lll-N semiconductor material such as GaN, the second interlayer 1025 may prevent N from the second semiconductor layer 1030 from reacting with the metal layer 1020.In some examples, first interlayer 1015 may be epitaxially grown directly on the first semiconductor layer 1010. In some examples, the metal layer 1020 may be epitaxially grown directly on the first interlayer 1015. In some examples, the second interlayer 1025 may be epitaxially grown directly on the metal layer 1020. In some examples, the second semiconductor layer 1030 may be epitaxially grown directly on the second interlayer 1025. The first semiconductor layer 1010, first interlayer 1015, metal layer 1020, second interlayer 1025 and second semiconductor layer 1030 may thus be epitaxially grown the substrate 110 in the same reactor.In some examples, the first interlayer 1015 may comprise a thin layer, for example a nucleation layer or a monolayer. In such examples, the nucleation layer or the monolayer of the first interlayer 1015 may be sufficient to prevent the metal layer 1020 from detrimentally reacting with the first semiconductor layer 1010. In such examples, the nucleation layer or the monolayer of the first interlayer 1015 may not substantially affect the bulk properties of the first semiconductor layer 1010 and the second semiconductor layer 1030. Thus, in a similar manner, in some examples, the second interlayer 1025 may comprise a thin layer, for example a nucleation layer or a monolayer.In some examples, the first semiconductor layer 1010 and the second semiconductor layer 1030 may comprise lll-N semiconductor material and both the first interlayer 1015 and second interlayer 1025 may comprise a lll-N material. In such examples, the lll-N material of one or both of the first interlayer 1015 and second interlayer 1025 may thus comprise similar properties to the first semiconductor layer 1010 and second semiconductor layer 1030. As such, the lll-N material of the first interlayer 1015 and second interlayer 1025 may therefore have photonic and electronic properties that are consistent with the first lll-N semiconductor layer 1010 and second lll-N semiconductor layer 1030 and thus result in consistent performance. Furthermore, the similar properties of one or both of first interlayer 1015 and second interlayer 1025 and the first semiconductor layer 1010 and second semiconductor layer 1030 may allow the layered structure 1000 to be processed in a similar manner, such as to allow etching of the layered structure 1000 in a consistent and predictable manner.In some examples the first interlayer 1015 and second interlayer 1025 may comprise AIN. AIN comprises a lattice constant that is relatively close to some lll-N semiconductor materials, such as GaN. As such, the AIN may be substantially lattice matched to a lll-N semiconductor material and may thus lead to a layered structure with low strain.Furthermore, N bonds of AIN are relatively strong and thus N may not separate from AIN when interfaced with a metal layer, such as a metal layer comprising Mo. In some examples, the lll-N material of the first interlayer 1015 and second interlayer 1025 may comprise AlxGai.xN, where x > 0.4.In examples, according to the present disclosure, interlayers may thus be incorporated into any of the layered structures or devices described above to prevent the semiconductor layers from detrimentally reacting with a metal layer.First semiconductor layer 1010 and second semiconductor layer 1030 may both comprise a lll-N semiconductor material that reacts with a surface of the metal layer 1020. As such, layered structure 1000 comprises first interlayer 1015 and second interlayer 1025 to prevent first semiconductor layer 1010 and second semiconductor layer 1030 from reacting with a surface of the metal layer 1020. However, in other examples, one of the first semiconductor layer 1010 and second semiconductor layer 1030 may not comprise a lll-N material that reacts with a surface of the metal layer 1020.Figure 11 illustrates an example of a layered structure 1100 according to examples of the present disclosure. Layered structure 1100 comprises elements in common with the layered structure 1000 described above. Said common elements are labelled with corresponding reference numerals and may operate in substantially the same way to that described above.In a similar manner to that described above, layered structure 1100 may thus comprise a metal layer 1020. The metal layer 1020 is over a first semiconductor layer 1110. However, in the example of Figure 10, an interlayer may not be present between the first semiconductor layer 1110 and the metal layer 1020. In such examples, first semiconductor layer 1110 may comprise a material that does not detrimentally react with the metal layer 1020. For example, the first semiconductor layer 1110 may comprise a material with relatively strong N bonds, such as AlxGai.xN, where x > 0.4. For example, buffer layer 710 described above with respect to HEMTs 700, 800, may comprise AlxGai.XN, where x > 0.4. Metal layer 1020 may thus form on the first semiconductor layer 1110 without substantial defects and, for example, without N from the first semiconductor layer 1110 reacting with the metal layer 1020. As such, in some examples, the metal layer 1020 may be formed on a surface of the first semiconductor layer 1110 without the use of an interlayer between the metal layer 1020 and the first semiconductor layer 1110.As illustrated in Figure 11 , layered structure 1100 comprises interlayer 1025 between the metal layer 1020 and the second semiconductor layer 1030. In a similar manner to that described above, interlayer 1025 may prevent defects occurring at the interface between the metal layer 1020 and the second semiconductor layer 1030. In one example, second semiconductor layer 1030 may comprise a material with relatively weak N bonds, such as, GaN. Thus, in some examples, first semiconductor layer 1110 and second semiconductor layer 1030 may comprise different lll-N semiconductor materials.Although layered structure 1100 illustrates that an interlayer 1025 is present between the second semiconductor layer 1030 and the metal layer 1020, and an interlayer is not present between the first semiconductor layer 1110 and the metal layer 1020, in other examples, an interlayer may be present between the first semiconductor layer 1110 and the metal layer 1020 and an interlayer may not be present between the second semiconductor layer 1030 and the metal layer 1020. In such examples, second semiconductor layer 1030 may comprise a material with relatively strong N bonds, such as AlxGai-xN, where x > 0.4, and first semiconductor material 1110 may comprise a material with relatively weak N bonds, such as GaN.Thus, in some examples, an interlayer may be present between the metal layer 1020 and one of the first semiconductor material 1110 and the second semiconductor layer 1030.Interlayers such as those described in relation to layered structures 1000, 1100 may thus be incorporated into any of the layered structures or semiconductor devices described above.The present disclosure thus provides a semiconductor device comprising a layered structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a photonic semiconductor device. In some examples the photonic semiconductor device may comprise one of: a light emitting diode (LED) or a micro LED (pLED). In other examples, the semiconductor device may comprise a electronic semiconductor device. In some examples, the electronic semiconductor device may comprise a HEMT or a Schottky diode.The present disclosure further provides an electronic device comprising a semiconductor device according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console, or similar. In some examples the electronic device may comprise a comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, a mixed reality headset, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar.In some examples the electronic device may comprise a communication device for user operation such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a communications infrastructure device, such as a communication infrastructure device for a base station, a cell tower or similar. In some examples the electronic device may comprise a communication hub, such as a Wi-Fi router or switch. In some examples the electronic device may comprise a communications device for a radar device, such as a radar transmitter, radar receiver, radar transceiver or similar.It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A layered structure (200) comprising: a substrate (110); a first semiconductor layer (210) over the substrate (110); a first interlayer (1015) over the first semiconductor layer (210); an epitaxial metal layer (220) over the first interlayer (1015); a second interlayer (1025) over the epitaxial metal layer (220); and a second semiconductor layer (230) over the second interlayer (1025); wherein the epitaxial metal layer (220) is configured to modify carrier movement in the second semiconductor layer (230) and wherein the epitaxial metal layer (220) comprises a thickness of less than 10 nm.

2. The layered structure according to claim 1 wherein the epitaxial metal layer (220) is configured to apply an electric field to the second semiconductor layer (230) to modify the carrier movement in the second semiconductor layer (230).

3. The layered structure according to claim 1 or 2 wherein the epitaxial metal layer (220) is to spread carriers across the second semiconductor layer (230).

4. The layered structure according to claim 1 wherein the epitaxial metal layer (220) is configured to prevent carriers in the second semiconductor layer (230) migrating into the first semiconductor layer (210).

5. The layered structure according to claim Error! Reference source not found, wherein the epitaxial metal layer (220) comprises a thickness of less than 2 nm.

6. The layered structure according to any preceding claim wherein the second semiconductor layer (230) comprises a lll-N material.

7. The layered structure according to any preceding claim wherein the second semiconductor layer (230) comprises GaN.

8. The layered structure according to any preceding claim wherein the second semiconductor layer (230) comprises a channel layer.

9. The layered structure according to any preceding claim wherein the first semiconductor layer (210) comprises a buffer layer.

10. The layered structure according to any preceding claim wherein the first semiconductor layer (210) comprises a lll-N material.

11. The layered structure according to claim 10 wherein the first semiconductor layer (210) comprises GaN.

12. The layered structure according to claim Error! Reference source not found, wherein the first interlayer (1015) comprises lll-N material.

13. The layered structure according to claim Error! Reference source not found, wherein the first interlayer (1015) comprises AIN.

14. The layered structure according to claim Error! Reference source not found, wherein the second interlayer (1025) comprises lll-N material.

15. The layered structure according to claim 1 wherein the second interlayer (1025) comprises AIN.

16. The layered structure according to any preceding claim wherein the epitaxial metal layer (220) is configured to form a Schottky barrier with at least one of the second semiconductor layer (230) and the first semiconductor layer (210).

17. A layered structure (100) comprising: a substrate (110); a plurality of layers over the substrate (110) comprising: a first lll-N semiconductor layer (210); an epitaxial metal layer (220) over the first lll-N semiconductor layer (210); a second lll-N semiconductor layer (230) over the epitaxial metal layer (220); and an interlayer comprising lll-N material contacting the epitaxial metal layer (220), wherein the interlayer comprises a first interlayer (1015) between the first lll-N semiconductor layer (210) and the epitaxial metal layer (220) and the interlayer comprises a second interlayer (1025) between the second lll-N semiconductor layer (230) and the epitaxial metal layer (220); and wherein the epitaxial metal layer (220) comprises a thickness less than 10 nm.

18. A semiconductor device comprising the layered structure (100) according to any of claims 1-17.

19. An electronic device comprising the semiconductor device according to claim 18.

20. A method of forming a layered structure (100) comprising: forming a first semiconductor layer (210) over a substrate (110); forming a first interlayer (1015) over the first semiconductor layer (210); forming an epitaxial metal layer (220) over the first interlayer (1015); forming a second interlayer (1025) over the epitaxial metal layer (220); and forming a second semiconductor layer (230) over the second interlayer (1025); wherein the epitaxial metal layer (220) is configured to modify carrier movement in the second semiconductor layer (230) and wherein the epitaxial metal layer (220) comprises a thickness of less than 10 nm.

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