Pim memory card and query management

Abstract

The present invention relates to a computing device provided with at least one memory card, and in particular a memory card that comprises a plurality of memory circuits, each of which is provided with an internal processor. The present invention proposes a memory card architecture that is compatible with existing protocols, and in particular DDR5 protocols, while implementing internal memory controllers, hereinafter referred to as internal controllers, and making it possible to associate complete read or write commands with a single memory circuit.

Description

computer device FIELD OF THE INVENTION

[0001] The present invention relates to the field of computer devices provided with memories, and in particular memories equipped with internal processors (hereinafter "PIM memory circuit"). These internal processors give said memories a capacity for processing and / or calculating the data they contain.

[0002] More particularly, the present invention relates to an architecture and a protocol adapted to better take into account the presence of internal processors. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] Illustrates a computer device 1 known from the state of the art. In particular, this computer device comprises a main processor 2, a memory controller 3 and a memory card 4.

[0004] The main processor 2 is, for example, a calculation and control unit of an electronic device such as a computer, a calculator or other equipment capable of executing logical functions. In particular, the main processor 2 may be a central calculation unit (“CPU” or “Central Processing Unit” according to Anglo-Saxon terminology). The main processor 2 is, in the present case, intended to generate read and / or write requests to the memory card 4.

[0005] The memory controller 3 is interposed between the main processor 2 and the memory card 4 and is configured to translate the requests originating (symbolized by the arrow “A” on the) from the main processor 2 according to a particular memory protocol before transmitting them to the memory card 4. The memory controller 3 is also configured to transmit the responses to the requests originating from the memory card 4 to the main processor 2 (symbolized by the arrow “B” on the). Among the known memory protocols, the DDR5 protocol (“Double Data Rate” according to Anglo-Saxon terminology) is of particular interest since it allows a reduction in power consumption compared to a DDR4 protocol while doubling the bandwidth.

[0006] The memory card 4 comprises a plurality of memory circuits, for example four memory circuits 5a, 5b, 5c and 5d. Each of these memory circuits 5a, 5b, 5c and 5d comprises one or more memory banks 6a, 6b, 6c and 6d. Each memory bank 6a, 6b, 6c and 6d comprises a plurality of rank k of memory cells.

[0007] Each of these memory circuits 5a, 5b, 5c and 5d is connected to the memory controller 3 by a first and a second bus. In particular, the first bus, called the channel control and address bus 8, fully and equivalently connects all of the control and address ports of each memory circuit 5a, 5b, 5c and 5d, while the second bus, called the data bus 9, only partially connects each of the data ports of said memory circuits 5a, 5b, 5c and 5d.

[0008] Thus, and by way of example, a memory card, in particular of the DDR5 type and provided with a 32-bit channel, may comprise 4 memory circuits 5a, 5b, 5c and 5d each comprising an 8-bit wide data port. According to this configuration, the memory circuit 5d may be connected to bits [31:24] of the data bus 9, the memory circuit 5c may be connected to bits [23:16] of the data bus 9, the memory circuit 5b may be connected to bits [15:8] of the data bus 9, and the memory circuit 5a may be connected to bits [7:0] of the data bus 9.

[0009] According to this architecture, the main processor 2 perceives a continuous block of memory cells, however distributed over a plurality of distinct memory circuits 4. For example, the writing of 64 bytes of data can be distributed over each of the 4 memory circuits 5.

[0010] As illustrated in the, it may be a question of implementing PIM memory circuits 5a, 5b, 5c and 5d. The latter, like the memory circuits 5a, 5b, 5c and 5d described in relation to the, comprise one or more memory banks 6a, 6b, 6c and 6d, but are each also provided with an internal processor 7a, 7b, 7c and 7d.

[0011] Thus, the architecture shown in differs from that shown in in that the PIM memory circuits 5a, 5b, 5c and 5d each comprise an internal processor 7a, 7b, 7c and 7d. Such PIM memory circuits are described in patent application WO 2017 / 055732 A1.

[0012] Implementing a standard memory protocol, such as DDR5, on an architecture consistent with that shown in the figure remains problematic, however.

[0013] Indeed, each internal processor 7a, 7b, 7c and 7d is only sensitive (i.e.: can only process or read) the data written in the PIM memory circuit 5a, 5b, 5c and 5d in which it is integrated. In other words, information distributed over several memory circuits, as envisaged by the standard memory protocol, cannot be processed, calculated or even read by a single internal processor 7a, 7b, 7c and 7d.

[0014] Furthermore, and still in relation to the architecture represented in the, the implementation of a standard memory protocol of the DDR5 type does not allow hardware arbitration between requests from the main processor 2 and requests from an internal processor 7a, 7b, 7c and 7d.

[0015] In order to overcome the above-mentioned problems, software solutions have been proposed in patent application WO 2017 / 055732 A1 and patent EP 3 259 674 B1.

[0016] However, these solutions, although effective, are delicate to use.

[0017] Alternatively, it could be considered to fundamentally modify standard memory protocols. However, this alternative remains long and costly and cannot, therefore, constitute a preferred solution.

[0018] An aim of the invention is therefore to propose an architecture, and in particular a computer device provided with PIM memory circuits, making it possible to resolve the aforementioned problems without, however, significantly modifying the memory controller and the internal processors. BRIEF DESCRIPTION OF THE INVENTION

[0019] The present invention relates to a computing device which comprises:

[0020] - a memory card provided with a set of n memory circuits, each called circuit i for i ranging from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor, each bank, among the one or more banks, comprising a plurality of ranks, each rank comprising memory cells;

[0021] - a main processor configured to issue requests, called primary requests ik, each primary request ik targeting an address, called address ik, of one or more ranks of one or more banks of the circuit i;

[0022] - a memory controller implementing an access protocol, called native protocol, said native protocol being configured to allow the memory controller to access the n circuits i in parallel;

[0023] - at least one bus configured to carry commands, addresses and data;

[0024] the computing device further comprises a pre-controller interposed between the main processor and the memory controller, while each circuit i is provided with an internal memory controller, called internal controller i, the pre-controller being configured to, upon receiving a primary request ik from the main processor, decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller, this set of secondary requests to the memory circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, called primary execution confirmation, decompose said primary execution confirmation into a set of secondary execution confirmations, and transmit, via the memory controller,this set of secondary execution confirmations to the pre-controller which is also configured to reconstruct the primary execution confirmation from the set of secondary execution confirmations, the pre-controller is also configured to provide the main processor with primary results ik in response to a primary request ik to read data, called data ik, stored in the circuit i, the primary results ik forming a primary execution confirmation and comprising the data ik; each internal controller i is furthermore configured to also execute memory access requests, called internal requests, originating from the internal processor, the internal controller i is also configured to generate, for the execution of the primary requests as well as the internal requests, all the operations necessary to access the memory of the memory circuit i, and when this proves necessary, in place of the memory controller,preload banks, activate memory ranks as well as memory rank refresh operations when such operations are necessary.

[0025] The native protocol, configured to allow the memory controller to access the n circuits i in parallel, implies that said native protocol allows the memory controller to execute requests, in particular send requests described in the remainder of the statement, by generating commands. In particular, and this will appear more clearly in the remainder of the statement, a send request can be formed from several secondary requests, the several secondary requests of said send request, each targeting a different circuit i and are likely to be executed in parallel at the level of the different circuits i actually targeted. Furthermore, it is understood that a read or write command of the native protocol is addressed to all of the circuits i.

[0026] According to one implementation, the primary execution confirmation of a primary read request ik includes the data read by the corresponding read operation.

[0027] According to one embodiment, the pre-controller is configured to encode each secondary request of a set of secondary requests ik in a sending request, a sending request being able to comprise up to n secondary requests each targeting a different circuit i, the pre-controller is also configured to send each sending request to the memory controller, the memory controller is for its part configured to generate a sequence of commands of its native protocol, said sequence of commands allowing the execution of the sending request, the sequence of commands comprising at least one command, called sending command, for writing memory of the native protocol.

[0028] It is understood that the sequence of commands considered above allows the transmission of each secondary request forming the sending request within the circuit i targeted by said secondary request.

[0029] It is understood that a send request can only include one secondary request from a given set of secondary requests ik.

[0030] According to one implementation mode, the internal controller of a circuit i is configured to extract secondary requests from the sending commands that it receives and targeting the circuit i considered.

[0031] According to one embodiment, the pre-controller is configured to, when it expects, in return for sending commands that it has previously sent, that execution confirmations are pending in one or more circuits i, generate read requests, called response requests, and transmit them to the memory controller, so that the latter executes them by generating sequences of commands of the native protocol on the bus or buses connecting the memory controller to the circuits i, this sequence of commands comprising at least one command, called a response command, each response command being a memory read command of the native protocol.

[0032] According to one embodiment, the internal controller i is configured to encode secondary execution confirmations in the responses it provides to the read commands of the native protocol, and because a response to a read command is made up of the responses generated by the plurality of circuits i, such a response is likely to comprise several secondary execution confirmations issued by different circuits i.

[0033] According to one implementation mode, sending requests have the same format and encoding as primary writing requests.

[0034] According to one implementation mode, response requests have the same format and encoding as primary read requests.

[0035] According to one embodiment, a secondary request targeting circuit i is encoded, totally or partially, in the data to be written intended for circuit i, of a sending request, this data to be written being subsequently conveyed by at least one sending command.

[0036] According to one implementation mode, the internal controller of the circuit i is configured to ignore, in a series of commands issued by the memory controller, the commands of the native protocol responsible for precharging one or more memory banks and those responsible for activating one or more memory ranks.

[0037] According to one implementation mode, the internal controller of circuit i is configured to ignore the native protocol commands, issued by the memory controller, responsible for refreshing one or more memory ranks.

[0038] According to one embodiment, the pre-controller comprises a buffer memory, called pre-controller memory, in which each primary request ik is recorded in a register, called pre-register tik, before its processing, and in which each internal controller i comprises a buffer memory called intermediate buffer memory i.

[0039] According to one embodiment, said computing device is configured to assign an identifier, called a primary identifier, to each primary request ik, and one or more identifiers, called secondary identifiers, to each of the secondary requests of a set of secondary requests ik, the set of primary and secondary identifiers making it possible to associate each primary request ik with the set of secondary requests ik resulting from the decomposition of said primary request ik and to associate in return a primary execution confirmation ik with the set of secondary execution confirmation ik resulting from the decomposition of said primary execution confirmation.

[0040] According to one implementation mode, the internal controller is configured to reconstruct a primary request ik by recording in an intermediate buffer memory, as and when they are received, the secondary requests ik, or at least sufficient elements thereof, the internal controller also being configured to execute a primary request once it has been fully reconstructed.

[0041] According to one implementation, the internal controller is configured to store a primary execution confirmation in the intermediate buffer that contained the corresponding primary request, and then to release this intermediate buffer, allowing it to be used to reconstruct another primary request, when the primary execution confirmation has been fully sent, via a set of secondary execution confirmations.

[0042] According to one implementation, the primary and secondary identifiers are used by the internal controller i to reassemble the secondary requests into a primary request in the correct order when the memory controller executes the send requests in a different order than that in which it received them from the pre-controller.

[0043] According to one embodiment, the pre-controller is configured to reconstitute a primary execution confirmation ik by recording in a pre-register tik, as and when they are received, the secondary execution confirmations ik, or at least sufficient elements thereof; the pre-controller also being configured to transmit to the main processor the primary execution confirmations corresponding to primary results once these primary execution confirmations have been reconstituted, and to release the corresponding pre-registers tik in such a way that they can be used to record new primary requests generated by the main processor.

[0044] According to one implementation, the pre-controller is configured to release a tik pre-register containing a primary write request when the primary execution confirmation corresponding to this primary write request has arrived, the register thus released becoming available to record a new primary request generated by the main processor.

[0045] According to one implementation, the primary and secondary identifiers are used by the pre-controller to reassemble the secondary execution confirmations into primary execution confirmations in the correct order when the memory controller executes the response requests in a different order than that in which it received them from the pre-controller.

[0046] According to one embodiment, the at least one bus comprises a control and address bus and a data bus.

[0047] According to one embodiment, the at least one bus comprises a single bus.

[0048] The invention also relates to another computing device which comprises:

[0049] - a memory card provided with a set of n memory circuits, each called circuit i for i ranging from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor, each bank, among the one or more banks, comprising a plurality of ranks, each rank comprising memory cells;

[0050] - a main processor configured to issue requests, called primary requests ik, each primary request ik targeting an address, called address ik, of one or more ranks of one or more banks of the circuit i;

[0051] - a memory controller implementing an access protocol, called native protocol, said native protocol being configured to allow the memory controller to access the n circuits i in parallel;

[0052] - at least one bus configured to carry commands, addresses and data;

[0053] the computing device further comprises a pre-controller interposed between the main processor and the memory controller, while each circuit i is provided with an internal memory controller, called internal controller i, the pre-controller being configured to, upon receiving a primary request ik from the main processor, decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller, this set of secondary requests to the circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, called primary execution confirmation, each internal controller i is furthermore configured to carry out, when necessary, in place of the memory controller, the precharging of banks,the activation of memory ranks of circuit i for the execution of the primary request ik.,

[0054] According to one embodiment, the pre-controller comprises a plurality of command generation units dedicated to the decomposition of the primary requests ik into a set of secondary requests ik, the pre-controller further comprises a command sending unit configured to send the secondary requests

[0055] According to one embodiment, the pre-controller comprises a buffer memory, called pre-controller memory, in which each primary request ik is recorded in a register, called pre-register tik, before its processing, and in which each internal controller i comprises a buffer memory called intermediate buffer memory i.

[0056] According to one embodiment, said computing device is configured to assign an identifier, called primary identifier, to each primary query ik, and one or more identifiers, called secondary identifiers, to each of the secondary queries of a set of secondary queries ik, the set of primary and secondary identifiers making it possible to associate each primary query ik with the set of secondary queries ik resulting from the decomposition of said primary query ik.

[0057] According to one embodiment, the pre-controller is configured to perform in parallel the decomposition of a plurality of primary requests ik each targeting a different memory circuit, the pre-controller is also configured to emit, simultaneously, several secondary requests, each of these secondary requests belonging to a set of secondary requests ik each targeting a different memory circuit.

[0058] It is understood that the simultaneous transmission of several secondary requests, each of these secondary requests belonging to a set of secondary requests ik each targeting a different memory circuit, can in particular implement a sending request. Said sending request comprises in this regard several secondary requests ik each targeting a different memory circuit. This sending request can be transmitted to the memory circuit via the memory controller.

[0059] According to one embodiment, the pre-controller is configured so that following the decomposition of a primary request ik into a set of secondary requests ik, said set of secondary requests ik comprises secondary requests ikl for l ranging from 0 to m, the address ik in the circuit i targeted by the primary request ik being carried by at least one of the secondary requests ikl.

[0060] According to one implementation mode, as soon as the primary request ik is a write request, the internal controller i is configured to record, as they are received, the secondary requests ikl for l ranging from 0 to m of the set of secondary requests ik in a register ik of the intermediate buffer memory i, the internal controller i is also configured to, as soon as all the secondary requests ikl have been recorded in the register ik, reconstruct the primary request ik and execute said primary request ik.

[0061] According to one embodiment, the pre-controller, when it receives at least two primary write requests ik and jh, j being different from i, and targeting, respectively, circuit i and circuit j, decomposes said primary requests ik and jh, respectively, into a set of secondary requests ik and into a set of secondary requests jh, the pre-controller being configured to simultaneously send a secondary request ikl, l being between 0 and m, to circuit i, a secondary request jht, t being between 0 and m, to circuit j, and a so-called NOP command, to circuits h not targeted by a primary request, a NOP command being a command without effect. It is understood that the simultaneous sending is done by means of a sending request as described previously.

[0062] According to one implementation mode, the internal controller i is configured to issue a confirmation of execution of the primary request ik to the pre-controller, and reset the register ik of the intermediate buffer memory i, the pre-controller being configured to reset the pre-register ik upon receipt of the confirmation of execution.

[0063] According to one implementation mode, when the primary request ik is a request to read L bytes of data at the address ik, the internal controller i is configured to reassemble the primary request ik upon receipt of all the secondary requests of the set of secondary requests ik, then to execute said primary request ik in order to write in a register tik of its intermediate buffer memory the L bytes read following the execution by said internal controller i of the primary request ik.

[0064] According to one embodiment, the internal controller is also configured to decompose the L bytes read and recorded in the register tik into a set of secondary results ik and communicate them to the pre-controller, said pre-controller being for its part configured to gather the secondary results of the set of secondary results ik into a primary result ik forming both a response to the primary read request ik and a confirmation of execution of the latter.

[0065] According to one embodiment, the pre-controller, when it receives at least two primary requests ik and jh for reading, j being different from i, and targeting, respectively, circuit i and circuit j, translates said primary requests ik and jh, respectively, into a set of secondary requests ik and into a set of secondary requests jh, the pre-controller being configured to simultaneously send at least one secondary request from the set of secondary requests ik to circuit i, and at least one secondary request from the set of secondary requests jh to circuit j.

[0066] According to one embodiment, the at least one bus comprises a control and address bus and a data bus.

[0067] According to one embodiment, the at least one bus comprises a single bus.

[0068] According to one implementation mode, the secondary requests of a set of secondary requests ik transmitted by the pre-controller to a circuit i, pass through the memory controller.

[0069] Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:

[0070] This is a schematic representation of a computer device provided with a memory card known from the state of the art and adapted to the implementation of a standard memory protocol, in particular the memory card of this computer device comprises memory circuits without an internal processor;

[0071] This is a schematic representation of a computer device provided with a memory card and each memory circuit of which includes an internal processor;

[0072] The is a schematic representation of a computing device in accordance with the principles of the present invention, in particular the computing device shown in the comprises, without limiting the invention to this aspect only, four memory circuits. DETAILED DESCRIPTION OF THE INVENTION

[0073] The present invention relates to a computer device provided with at least one memory card, and more particularly to a memory card which comprises a plurality of memory circuits, each of these circuits being provided with an internal processor. In particular, and according to the terms of the present invention, an internal processor is a microelectronic device configured to execute instructions and for example perform calculations, on data saved in the memory circuit to which it belongs. In this regard, those skilled in the art may refer to patent application WO 2017 / 055732 A1 which describes an example of a memory circuit provided with an internal processor. It is nevertheless understood that the functionalities and architectures provided in patent application WO 2017 / 055732 A1 are given only by way of example and should not in any way limit the scope of the present invention.

[0074] The present invention provides a memory card architecture compatible with existing protocols, and in particular DDR5 protocols, while implementing internal memory controllers, hereinafter referred to as internal controllers.

[0075] Thus, the present invention relates to a computing device which comprises:

[0076] - a memory card provided with a set of n memory circuits, each called circuit i for i ranging from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor, each bank, among the one or more banks, comprising a plurality of ranks, each rank comprising memory cells;

[0077] - a main processor configured to issue requests, called primary requests ik, each primary request ik targeting an address, called address ik, of one or more ranks of one or more banks of the circuit i;

[0078] - a memory controller implementing an access protocol, called native protocol, said native protocol being configured to allow the memory controller to access the n circuits i in parallel;

[0079] - at least one bus configured to carry commands, addresses and data;

[0080] the computing device further comprises a pre-controller interposed between the main processor and the memory controller, while each circuit i is provided with an internal memory controller, called internal controller i, the pre-controller being configured to, upon receiving a primary request ik from the main processor, decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller, this set of secondary requests to the memory circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, called primary execution confirmation, decompose said primary execution confirmation into a set of secondary execution confirmations, and transmit, via the memory controller,this set of secondary execution confirmations to the pre-controller which is also configured to reconstruct the primary execution confirmation from the set of secondary execution confirmations, the pre-controller is also configured to provide the main processor with primary results ik in response to a primary request ik to read data, called data ik, stored in the circuit i, the primary results ik forming a primary execution confirmation and comprising the data ik; each internal controller i is furthermore configured to also execute memory access requests, called internal requests, originating from the internal processor, the internal controller i is also configured to generate, for the execution of the primary requests as well as the internal requests, all the operations necessary to access the memory of the memory circuit i, and when this proves necessary, in place of the memory controller,preload banks, activate memory ranks as well as memory rank refresh operations when such operations are necessary.

[0081] The native protocol, configured to allow the memory controller to access the n circuits i in parallel, implies that said native protocol allows the memory controller to execute requests, in particular send requests described in the remainder of the statement, by generating commands. In particular, and this will appear more clearly in the remainder of the statement, a send request can be formed from one or more secondary requests, the several secondary requests of said send request each targeting a different circuit i and are likely to be executed in parallel at the level of the different circuits i actually targeted. Furthermore, it is understood that a read or write command of the native protocol is addressed to all of the circuits i.

[0082] Thus, according to the present invention, each memory circuit comprises an internal controller having functions equivalent to those of a memory controller. However, an internal controller only performs these functions within the memory circuit in which it is integrated.

[0083] Furthermore, and according to the present invention, each primary request issued by the main processor is allocated via the pre-controller to a single memory circuit.

[0084] Thus, a primary request allocated to a given memory circuit can be fully processed by the internal controller of the memory circuit in question. This configuration makes it possible to take advantage of the computing and data processing capabilities provided by each memory circuit through its internal processor.

[0085] The remainder of this description of the present invention is limited to the description of a computer device and the various functionalities of the elements that compose it. However, it is understood that the invention is not limited to the computer device alone but also relates to the method(s) implemented by the computer device in question.

[0086] Furthermore, the remainder of the statement refers to at least one bus which includes a control and address bus and a data bus. However, it is understood that the at least one bus may include a single bus.

[0087] In this regard, a person skilled in the art, simply by reading this statement, will understand that the present invention may relate to a method for routing a primary request, from its transmission by the main processor, to its execution at the level of a memory circuit by the internal controller of the memory circuit in question. It is also understood that such a method may consider both primary write requests and primary read requests. Finally, it is also understood that the invention may also relate to a computer program which, when implemented, executes all the steps of the method in question. This computer program may in particular comprise sub-programs, for example a sub-program stored and executed by the pre-controller and a sub-program stored and executed by the internal controllers.

[0088] The remainder of the description considers memory circuits equipped with internal processors. However, a person skilled in the art, upon reading this statement alone, may consider that the invention is also applicable to memory circuits without said internal processors.

[0089] Thus, in the, one can see a schematic representation of a computing device 10 in accordance with the disclosed principles of the present invention.

[0090] In particular, the computing device 10 comprises a main processor 100. The main processor 100 may comprise, for example, a calculation and control unit of an electronic device such as a computer, a calculator or other equipment capable of executing logical functions. In particular, the main processor 100 may be a central calculation unit (“CPU” or “Central Processing Unit” according to English terminology). The main processor 100 is, in the present case, intended to generate primary requests to memory circuits described in the remainder of the statement.

[0091] In particular, primary requests may include primary write requests and / or primary read requests.

[0092] In this regard, a primary write request corresponds to the writing of data, for storage purposes, in a memory circuit, while a primary read request corresponds to the reading of data stored in a memory circuit and their communication to the main processor 100.

[0093] The computing device 10 also comprises a memory card 300. By “memory card” is meant a support element, such as a printed circuit, on which one or more memory circuits are arranged. The memory card 300 may comprise connection means making it possible in particular to interface said card 300 with a computer, a computing unit.

[0094] The memory card 300 according to the present invention comprises n memory circuits, each called circuit i for i ranging from 1 to n. It is understood, without it being necessary to specify it, that n is an integer.

[0095] Each circuit i comprises one or more memory banks, each memory bank comprises a plurality of ranks, each rank comprising memory cells.

[0096] The memory cells may comprise dynamic random access memory cells (DRAM). The invention is however not limited to this aspect alone and those skilled in the art may envisage any type of memory cell, in particular static random access memory cells (SRAM).

[0097] Each circuit i includes at least one internal processor.

[0098] In the, given as a non-limiting example, the memory card comprises four memory circuits denoted circuit 1, circuit 2, circuit 3 and circuit 4. In particular, in the, circuit 1 bears the reference 301, circuit 2 bears the reference 302, circuit 3 bears the reference 303 and circuit 4 bears the reference 304.

[0099] As illustrated in, each circuit 301, 302, 303 and 304 includes an internal processor denoted 311, 312, 313 and 314 and one or more memory banks denoted 321, 322, 323 and 324.

[0100] Each circuit i, for i ranging from 1 to n, comprises an internal memory controller, each called an internal controller i. An internal controller is notably configured to execute primary requests recomposed from the secondary requests that it receives via the bus(es), and also execute the requests, generated by the internal processor i, for access to the memory contained in the one or more banks. As illustrated in, each circuit 301, 302, 303 and 304 comprises an internal controller denoted 331, 332, 322 and 334.

[0101] The computing device 10 according to the present invention also comprises a memory controller 200. In particular, the memory controller 200 according to the present invention incorporates the technical characteristics of memory controllers known from the prior art. In particular, the memory controller 200 according to the present invention is configured to issue commands for bank precharging, memory rank activation and / or memory rank refresh. However, the computing device 10 according to the present invention is configured so that some of the commands likely to be issued by the memory controller 200 are ignored by the memory circuits, in particular the bank precharging, rank activation and rank refresh commands. This latter aspect makes it possible in particular to limit the protocol adaptations relating to the operation of the computing device 10.

[0102] The computing device 10 according to the present invention comprises a data bus 500 connecting the memory controller 200 and the memory card 300, as well as a control and address bus 400 connecting the memory controller 200 and the memory card 300. It is also known that each memory circuit is only partially connected to the data bus 500. More particularly, the width (for example measured in “bits” or “bytes”) of the data bus is greater than the width of the data port (for example measured in “bits” or “bytes”) of each of the memory circuits. Thus, and according to the present invention, all the memory circuits can have an identical data port width. Advantageously, the sum of the data port widths of all the memory circuits in the memory card format can be equal to the width of the data bus.

[0103] For example, the data port of each memory chip can be equal to p (p being an integer) while the data bus width can be equal to the product of p and n (n being the number of memory chips carried by the memory card).

[0104] It is thus understood that a write request of a length equal to the product of n by p, or to a multiple of this value, cannot pass through the data port of a memory circuit without modifications.

[0105] The computing device 10 also comprises a pre-controller 600 interposed between the main processor 100 and the memory controller 200. In operation, the main processor 100 is configured to issue requests, and in particular primary requests ik for i ranging from 1 to n, a primary request i targeting an address, called address i, of one or more ranks of one or more banks of the circuit i. The first index “i”, allocated to the primary request ik designates the circuit i targeted by said request. The second index “k” (it being understood that other letters may be considered in the remainder of the statement) designates the request as such and makes it possible in particular to differentiate the primary request ik from the primary request ih, both targeting the circuit i.

[0106] According to the present invention, the pre-controller 600 is adapted to receive and perform pre-processing of primary requests ik issued by the main processor 100. In particular, the pre-controller 600 is configured to decompose a primary request ik (for i ranging from 1 to n), targeting an address ik of the circuit i (issued by the main processor 100), into a set of secondary requests ik.

[0107] The sending of secondary requests is done by encoding them in write requests called send requests. In particular, several secondary requests, intended for different memory circuits i, can be encoded in the same send request. The send requests are transmitted to the memory controller 200, the latter executing each send request by generating a series of commands on the control and address bus 400 as well as by transmitting data on the data bus 500.

[0108] In this regard, the command suite includes:

[0109] - possibly a bench precharge command as well as a rank activation command, (each internal controller is however configured to ignore these two commands.);

[0110] - one or more write commands, these commands conveying, on the data bus 500, data which are normally, in the DDR5 protocol, the data to be written, but which in the context of the invention are data encoding secondary requests.

[0111] Each internal controller i is further configured to extract secondary requests from the data of the write commands generated by the memory controller when the latter executes send requests. The internal controller i reconstructs primary requests from the sets of secondary requests thus extracted, and executes the primary requests once these are reconstituted, performing if necessary bank precharges and rank activations, as well as refresh operations when these are necessary.

[0112] For each primary request executed, the internal controller i will generate an execution confirmation, the latter corresponding for a primary read request, to the data read by this primary read request, and for primary write requests, to a secondary request identifier.

[0113] Each time the internal controller i receives a response command, the internal controller i provides: either a secondary result, that is to say a part of a confirmation of execution of a primary read request, this secondary result comprising a secondary identifier as well as a part of the data read following this primary read request; or one or more confirmations of execution of primary write requests; or a value encoding the absence of confirmation of executions, the controller having either already confirmed in full all the primary requests that it has already executed, or not yet being able to confirm the execution of primary requests in one or other of the following cases: it has not yet received an execution confirmation in its entirety it has not yet executed a primary request in its entirety

[0114] According to a particularly advantageous embodiment, the pre-controller 600 may comprise n command generation units, each called generation unit i for i ranging from 1 to n. Each generation unit i is in particular dedicated to the decomposition of a primary request ik targeting the circuit i into a set of secondary requests ik. Still according to this embodiment, the pre-controller 600 may comprise a sending request generation unit configured to encode several secondary requests in each sending request, these secondary requests having been generated by different generation units i, therefore targeting different memory circuits. The sending requests thus generated are provided to the memory controller 200 which executes them by controlling the buses 400 and 500; The pre-controller 600 will thus send, via the memory controller 200, the secondary requests of each set of secondary requests ik to the memory circuit i, and therefore to the internal controllers i.

[0115] Still advantageously, the pre-controller 600 may comprise a buffer memory, called pre-controller memory, in which each primary request ik is recorded in a register, called pre-register tik, before its processing. Advantageously, each internal controller i may also comprise a buffer memory called intermediate buffer memory i for i ranging from 1 to n.

[0116] In particular, and by way of example, the pre-register tik in which the primary request ik is recorded may comprise a plurality of fields among which may be counted, an identifier, a state of the allocated buffer, the address ik, a data table.

[0117] The state of the allocated buffer may include a free state, a state for which a primary read request is recorded, and a state for which a primary write request is recorded. The state for which a primary read request ik is recorded may be a measure of the progress of sending the set of secondary requests ik (decomposition of the primary read request) to the circuit i. Equivalently, the state for which a primary write request ik is recorded may be a measure of the progress of sending the set of secondary requests ik (decomposition of the primary write request) to the circuit i.

[0118] The computing device 10 can be configured to assign an identifier, called a primary identifier, to each primary query ik, and one or more identifiers, called secondary identifiers, to each of the secondary queries of a set of secondary queries ik. The set of primary and secondary identifiers makes it possible in particular to associate each primary query ik with the set of secondary queries ik resulting from the decomposition of said primary query ik. In other words, the secondary identifiers assigned to the secondary queries of a given set of secondary queries makes it possible to associate the primary query with the set of secondary queries formed from the primary query in question.

[0119] This latter aspect also makes it possible to associate in return a primary execution confirmation ik with the set of secondary execution confirmation ik resulting from the decomposition of said primary execution confirmation.

[0120] According to an advantageous embodiment, the pre-controller 600 can be configured to perform in parallel the decomposition of a plurality of primary requests ik each targeting a different memory circuit i. Still according to this embodiment, the pre-controller 600 can be configured to encode several secondary requests in a single sending request, each of these secondary requests belonging to a set of secondary requests ik each targeting a different memory circuit i.

[0121] The pre-controller 600 can be configured so that following the decomposition of a primary request ik into a set of secondary requests ik, said set of secondary requests ik comprises secondary requests ikl for l ranging from 0 to m, the secondary request ik0 carrying the address ik in the circuit i targeted by the primary request ik.

[0122] The computing device 10 also includes a data bus 500 connecting the memory controller and the memory card, and a control and address bus 400 connecting the memory controller and the memory card.

[0123] The command and address bus 400 is a unidirectional bus which, via appropriate encoding, carries command information and address information. It is understood that command information indicates an action to be performed, for example executing a request, while address information indicates an address within a circuit i where the request in question is to be executed.

[0124] The data bus 500 is a bidirectional bus which comprises several data communication fields i, and more particularly n data communication fields i (i ranging from 1 to n), each data communication field i being dedicated to the circuit i.

[0125] It is understood that the data communicated between a circuit i and the pre-controller 600 pass through the data communication field i.

[0126] Secondary ikl write or read requests carrying write and read requests, respectively, can also pass through the data communication field i.

[0127] Secondary requests ik0 for writing or reading, carrying a write and a read address respectively, can also pass through the data communication field i or through the address communication field ik, or in a distributed manner over these two fields.

[0128] The internal controller i is configured to record, as they are received, the secondary requests ikl of the set of secondary requests ik in a register tik of the intermediate buffer memory i. The internal controller i is also configured to, once all the secondary requests ikl have been recorded in the register tik, reconstruct the primary request ik and execute said primary request ik. By execution of the primary request ik, we mean, for all the ranks targeted by the request where this would be necessary, a preloading of the bank where the rank in question is located and the activation of this rank, then for all the ranks targeted by the request, the reading or writing of the cells of the rank specified by the address of the request.

[0129] Advantageously, the pre-register tik allocated to the primary request ik in the pre-controller memory will report the progress of sending the secondary requests ikl to the internal controller i. The internal controller i also allocates a register tik, in its intermediate buffer memory i, to the set of secondary requests ik. In particular, this register tik reports the progress in terms of receiving the secondary requests ikl from the set of secondary requests.

[0130] The internal controller is also configured to store a primary execution confirmation in the intermediate buffer that contained the corresponding primary request, and then release this intermediate buffer. This latter aspect allows said intermediate buffer (in other words the relevant register) to be used to reconstruct another primary request, when the primary execution confirmation has been fully sent, via a set of secondary execution confirmations.

[0131] According to the present invention, the primary and secondary identifiers can also be used by the internal controller i to reassemble the secondary requests into primary requests in the correct order when the memory controller executes the send requests in a different order than that in which it received them from the pre-controller.

[0132] Still according to the present invention, the primary and secondary identifiers can be used by the pre-controller to reassemble in a correct order the secondary execution confirmations into primary execution confirmations when the memory controller executes the response requests in a different order than that in which it received them from the pre-controller.

[0133] The pre-controller is configured to reconstruct a primary execution confirmation ik by recording in a pre-register tik, as and when they are received, the secondary execution confirmations ik, or at least sufficient elements thereof. The pre-controller is also configured to transmit to the main processor the primary execution confirmations corresponding to primary results once these primary execution confirmations have been reconstructed, and to release the corresponding pre-registers tik so that they can be used to record new primary requests generated by the main processor.

[0134] The pre-controller is configured to release a tik pre-register containing a primary write request when the primary execution confirmation corresponding to that primary write request has arrived, the pre-register thus released becoming available to record a new primary request generated by the main processor.

[0135] A person skilled in the art, based on his general knowledge alone, will be able to design the architecture of the tik pre-register and the tik register.

[0136] Each internal controller i can be configured to, upon receiving all the secondary requests in the secondary request set ik, reassemble said secondary requests in order to reform the primary request and execute the latter.

[0137] The internal controller i is also configured to decompose the data read and recorded in the register tik into a set of secondary results ik and communicate them to the pre-controller, in response to response requests issued by the latter, said pre-controller being for its part configured to extract, from the data returned by the response requests (which are read requests from the point of view of the DDR5 protocol), the secondary results of the set of secondary results ik, and reassemble these secondary results into a primary result ik forming both a response to the primary read request ik and a confirmation of execution of the latter.

[0138] Advantageously, the pre-controller, 600 when it receives at least two primary requests ik and jh in read mode, j being different from i, and targeting, respectively, the circuit i and the circuit j, translates said primary requests ik and jh, respectively, into a set of secondary requests ik and into a set of secondary requests jh, the pre-controller being configured to simultaneously send a secondary request ikl to the circuit i, a secondary request jht to the circuit j. The pre-controller is configured, as soon as it has written all of the data (in particular the read data) into the pre-register, to send said data to the main processor.

[0139] The computing device 10 is therefore configured to process a plurality of primary requests, each of the primary requests targeting a different memory circuit.

[0140] Thus, and according to the present invention, the consideration of secondary requests (of reduced size compared to the primary requests), or of secondary results makes it possible to fully execute a primary request within a single circuit and consequently to be able to benefit from all the potential offered by the presence of an internal processor in the memory circuit considered.

[0141] The remainder of the statement deals with the routing of a primary write request in the context of a computing device for which the memory card comprises four memory circuits. In this example, the data bus 500 is 32 bits distributed equally on each of the circuits 301, 302, 303 and 304.

[0142] The routing of a primary write request includes the generation of said primary request by the main processor. This primary request may in particular include a request identifier, a destination address i aligned on 64 bytes of the circuit i, and 64 bytes of data to be written, called data i, at address i.

[0143] Upon receipt of the primary request, the pre-controller 600 allocates to said primary request i a pre-register tik in its buffer memory.

[0144] The pre-controller 600 then translates the primary request ik into five secondary requests ik, for k ranging from 0 to 4. The pre-controller 600 can be provided with four command generation units, each dedicated to the translation of the primary requests targeting a memory circuit of its own. In other words, the primary request ik, targeting circuit i, will be translated into five secondary requests ikl (l ranging from 0 to 4) by the command generation unit dedicated to circuit i. The address ik targeted in circuit i is contained in the secondary request i0 as well as a small part of the data to be written, while the secondary requests ik, for k ranging from 1 to 4, comprise the rest of the data to be written.

[0145] These different secondary requests ik (k ranging from 0 to 4) are sent by the command sending unit via 5 secondary write requests.

[0146] Secondary requests to different memory circuits can be sent at the same time. In particular, as soon as it is considered, the command sending unit can send four secondary requests from four different secondary request sets. In other words, write commands to the four memory circuits can be implemented at the same time.

[0147] Thus, performing the primary write request from the main processor will require five write accesses instead of 1, but up to 4 write requests from the main processor, each targeting different memory circuits, can be performed in parallel, achieving, from a bandwidth point of view, an efficiency of 80%.

[0148] The internal controller i, when it receives the secondary request i0, and the secondary requests ik for k ranging from 1 to 4, updates the register tik. As soon as the state of the register tik reaches the value indicating that all the secondary requests ikl (for l ranging from 0 to 4) have been received by the internal controller i, the 64 bytes of data i are written to the address ik targeted by the primary request ik in the circuit i.

[0149] The pre-controller, determining that an execution confirmation must be pending in the memory circuit i, for example, without limitation, because sufficient time has elapsed since the sending of the last secondary request of the set of secondary requests corresponding to the primary write request in question, will issue a response command, and the internal controller i will then issue an execution confirmation of the writing of the data i in response to this response command, and reset the register tik. If the internal controller is not ready to provide this execution confirmation upon receipt of the response command, said internal controller provides a non-response value and will provide this execution confirmation in response to a subsequent response command. The pre-controller, upon receiving a non-response, again generates a response request, which once executed by the memory controller, again generates a response command.

[0150] Finally, the execution confirmation is received by the pre-controller (via the memory controller) which in turn resets the tik pre-register, the latter being able to be allocated for the execution of another primary request.

[0151] The remainder of the statement deals with the routing of a primary read request in the context of a computing device for which the memory card comprises four memory circuits. In this example, the data bus 500 is 32 bits distributed equally on each of the circuits 301, 302, 303 and 304.

[0152] The routing of a primary read request includes the generation of said primary request by the main processor. This primary request may notably include a request identifier, a destination address ik aligned on 64 bytes of the circuit i.

[0153] Upon receipt of the primary request, the pre-controller 600 allocates to said primary request ik a pre-register tik in its buffer memory.

[0154] The destination address i is used to determine the memory circuit i concerned by the primary read request. In the present case, the destination address ik may for example concern the circuit 302. The pre-controller then generates the set of secondary requests ik, for example by means of a command generation unit dedicated to the circuit i.

[0155] In this case, in the case of a read request, the set of secondary requests ik comprises a single secondary request i0 which is sent to the circuit 302 via the data bus, and in particular the data communication field associated with the circuit 302. The secondary request i0 carries in particular the read address ik in the circuit 302.

[0156] The internal controller i of the circuit 302, when it receives the secondary request i0, updates the register tik, and executes as soon as possible the corresponding read command, filling the register tik with the read data.

[0157] The pre-controller, determining that a read execution confirmation must be pending in the memory circuit i, for example not limiting because sufficient time has elapsed since the sending of the secondary request i0 corresponding to the primary read request considered, will issue a series of response commands in order to recover the secondary execution confirmation set containing the read data.

[0158] The internal controller i then issues this secondary execution confirmation set, making it the secondary result set, in response to this response command sequence, thus transferring the read data, and resets the tik register.

[0159] As with a write command, the internal controller has the ability, when it is not ready when it receives a response command, to provide a no-response value to a response command, the latter being reissued later in a manner similar to that described in the flow of a write request.

[0160] Data passing via the 500 bus is transported via data blocks (“DATA BURST” in Anglo-Saxon terminology), a data block typically comprising 64 bytes.

[0161] Secondary results ik, emitted by the circuit i, are received by the pre-controller 600. These can be of a compact size of 8 bytes for example (equal to half the quantity of bytes, belonging to a data block, transiting through a data communication field) or of a normal size of 16 bytes for example (equal to the quantity of bytes, belonging to a data block, transiting through a data communication field). Typically, the data can thus be communicated to the pre-controller 600, in the form of a secondary result of compact size and four secondary results of normal size, each secondary result comprising, in addition to the data that it transports, an identifier, for example an identifier relating to the pre-register tik in which the primary request i is recorded.

[0162] For example, but not limited to, the internal controller i encodes the type of response it provides to a response command in a 4-bit field placed at the head of the response. This 4-bit field encodes the following types in particular: a non-response type, a write confirmation type, a compact result type, and a normal result type.

[0163] The non-response, write confirmation, and compact result types are 8 bytes long, while the normal result type is 16 bytes long.

[0164] Accordingly, the 16 bytes provided by the internal controller i in response to a reply command may include one of the following combinations: two non-responses; one non-response and one write confirmation; one non-response and one compact result; two write confirmations; one write confirmation and one compact result; two compact results; one normal result

[0165] Still within the framework of the non-limiting example, a compact result also includes an 8-bit identifier and 6 bytes of data and a normal result also includes an 8-bit identifier and 14.5 bytes of data: 1 compact result (6 bytes) and 4 normal results (4 x 14.5 bytes) carrying a total of 64 bytes of data.

[0166] As soon as all the results i (all the data to be read) are received by the pre-controller 600, the latter assembles them to transmit them to the main processor 100. The assembled data can be accompanied by the identifier of the primary request i.

[0167] It is understood that a compact size (in bytes) corresponds to half the amount of data passing through the data port of a memory circuit during a read or write command, while a normal size (in bytes) corresponds to the entire amount of data.

[0168] The consideration of compact sizes allows to group and send at the same time two results of compact size in response to a single response command, said two results of compact size corresponding to different reading requests. This aspect allows an improvement.

[0169] Equivalently, the secondary read requests i0, which have only one address to transport, can be of compact size, so that the sending of two such requests, corresponding to different primary read requests, can be sent simultaneously to the memory circuit i, via a single sending command.

[0170] Thus, in this case, the implementation of a primary read request will involve: issuing a compact secondary request (8 bytes) issuing a compact secondary result (8 bytes) issuing 4 secondary results of normal size (16 bytes each)

[0171] All of these transmissions therefore correspond to the equivalent of 5 commands on the bus (half a command + half a command + 4 commands). The computing device is thus able to parallelize up to 4 commands as long as they concern different memory circuits, and thus achieves an efficiency from the bandwidth point of view of 80% (4 accesses in 5 commands).

[0172] The examples of routing of a primary write request or a read request given above can be generalized to any number of memory circuits. Furthermore, throughout the statement, the number of secondary requests ik has been a function of the nature of the primary request (read or write) as well as the number of memory circuits included in the computer device. Nevertheless, those skilled in the art will understand that this aspect should not constitute a limiting character. Indeed, the principles of the invention set out above took into account the width of the address and control bus, and the width of the data bus. These widths are however not fixed so that a different number of secondary requests can be considered.

[0173] The computing device 10 may also be configured to handle read errors when executing a primary read request.

[0174] In the example described above, the data bus is only 32-bit wide and is not protected against errors that might affect it transiently.

[0175] Thus, it may be advantageous to implement an optional Cyclical Redundancy Check (CRC) mechanism as specified by the DDR5 protocol. Each chip i provides, in addition to the 16 response bytes, 2 additional bytes, containing 2 8-bit CRCs, each CRC being generated from one half of the 16 response bytes, such that the 2 CRCs protect the entire 16 bytes of the response of each chip i.

[0176] If a transmission error occurs, for example a temporary inversion of a signal on the data bus connecting the memory controller to circuit i: the memory controller will detect this error, because one of the two CRCs associated with the 16 bytes emitted by circuit i is erroneous; although only 8 bytes of data are affected, the memory controller, for reasons of simplicity, will reject all 64 bytes of data returned in response to its read request; the memory controller will reissue said read command

[0177] However, the internal workings of the memory controller may cause this read request not to be immediately reissued, and other read or write requests may be issued in the meantime.

[0178] The problem is that a read request, and therefore a response request, modifies the state of the internal controller: the latter, when it chooses a response to send, also modifies its own internal state, in particular the state of the tik register of the buffer concerned, in such a way that it no longer chooses this response when it receives other response commands.

[0179] Each secondary result to a secondary read request identifies the destination of the data bytes it contains. A read error between the memory circuit and the memory controller affecting a secondary result: does not result in bytes intended for primary read requests ik / jl / kv / lw being erroneously assigned to other primary read requests ia / jb / kc / ld. but does result in bytes intended for primary read requests ik / jl / kv / lw being lost and will not arrive again.

[0180] Thus, the pre-controller noting, after a sufficiently long time, that all the bytes expected by the primary requests ik / jl / kv / lw have not arrived, will consider that they have been lost and proceeds as follows and in order: the pre-controller issues commands to cancel the primary requests ik / jl / kv / lw the pre-controller waits for confirmations of execution of the commands to cancel the primary requests ik / jl / kv / lw the pre-controller re-issues a command to cancel the primary requests ik / jl / kv / lw if this confirmation of execution takes too long to arrive finally, the pre-controller restarts the process of executing the primary requests ik / jl / kv / lw entirely.

[0181] The computing device 10 may also be configured to handle write errors when executing a primary write request.

[0182] When the memory controller issues a primary write request, it generates CRC bytes in a manner identical to the memory circuits 301, 302, 303, 304 when they respond to a primary read request.

[0183] If a transmission error occurs, for example a temporary inversion of a signal on the data bus connecting the memory controller to circuit i: the memory controller will detect this error, because one of the two CRCs associated with the 16 bytes emitted by circuit i is erroneous. Circuit i ignores the command carried by the secondary write request, this command being originally a command that can carry a read address, or a data write command, or a cancellation command or a command without an instruction. Some of the bytes, intended for the primary request i are lost and will no longer arrive: the access, in reading, in writing or the cancellation will never be carried out.the pre-controller noting, after a sufficiently long time, that the primary request i has still not been carried out will consider that some of the bytes which constitute it have been lost and will proceed as follows and in order: the pre-controller issues a command to cancel the primary request i the pre-controller waits for confirmation of execution of the command to cancel the primary request i the pre-controller re-issues a command to cancel the primary request i if this confirmation of execution takes too long to arrive. the pre-controller restarts the entire process of executing the primary request i.

[0184] Alternatively, the memory circuit could explicitly indicate that a transmission error was encountered via a response of a specific type.

[0185] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Computer device (10) which comprises:- a memory card (300) provided with a set of n memory circuits (301, 302, 303, 304) each called circuit i for i ranging from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor (311, 312, 313, 314), each bank, among the one or more banks, comprising a plurality of ranks, each rank comprising memory cells;- a main processor (100) configured to issue requests, called primary requests ik, each primary request ik targeting an address, called address ik, of one or more ranks of one or more banks of the circuit i;- a memory controller (200) implementing an access protocol, called native protocol, said native protocol being configured to allow the memory controller (200) to access the n circuits i in parallel;- at least one bus (400, 500) configured to convey commands,addresses and data; the computing device (10) further comprises a pre-controller (600) interposed between the main processor (100) and the memory controller (200), while each circuit i is provided with an internal memory controller (331, 332, 333, 334), called internal controller i, the pre-controller (600) being configured to, upon receiving a primary request ik from the main processor (100), decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller (200), this set of secondary requests to the memory circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, called primary execution confirmation, decompose said primary execution confirmation into a set of secondary execution confirmations, and transmit,via the memory controller (200), this set of secondary execution confirmations to the pre-controller which is also configured to reconstruct the primary execution confirmation from the set of secondary execution confirmations, the pre-controller is also configured to provide the main processor (100) with primary results ik in response to a primary request ik to read data, called data ik, stored in the circuit i, the primary results ik forming a primary execution confirmation and comprising the data ik; each internal controller i is furthermore configured to also execute memory access requests, called internal requests, originating from the internal processor (311, 312, 313, 314), the internal controller i is also configured to generate, for the execution of the primary requests as well as the internal requests, all the operations necessary to access the memory of the memory circuit i,and when necessary, instead of the memory controller (200), preload the banks, activate the memory ranks as well as the memory rank refresh operations when such operations are necessary. The computing device (10) of claim 1, wherein the primary execution confirmation of a primary read request ik comprises the data read by the corresponding read operation. The computing device (10) of claim 1 or 2, wherein the pre-controller is configured to encode each secondary request of a set of secondary requests ik into a send request, a send request being able to comprise up to n secondary requests each targeting a different circuit i, the pre-controller is also configured to send each send request to the memory controller (200), the memory controller (200) is for its part configured to generate a sequence of commands of its native protocol, said sequence of commands allowing the execution of the send request, the sequence of commands comprising at least one command, called send command, for writing memory of the native protocol. The computing device (10) of claim 3, wherein the internal controller of a circuit i is configured to extract secondary requests from the sending commands it receives and targeting the circuit i in question. Computer device (10) according to claim 3 or 4, in which the pre-controller is configured to, when it expects, in return for sending commands that it has previously sent, that execution confirmations are pending in one or more circuits i, generate read requests, called response requests, and transmit them to the memory controller (200), so that the latter executes them by generating sequences of commands of the native protocol on the bus or buses connecting the memory controller (200) to the circuits i, this sequence of commands comprising at least one command, called a response command, each response command being a memory read command of the native protocol. The computing device (10) of claim 5, wherein the internal controller i is configured to encode secondary execution confirmations in the responses it provides to read commands of the native protocol, and because a response to a read command consists of the responses generated by the plurality of circuits i, such a response is likely to comprise several secondary execution confirmations issued by different circuits i. The computing device (10) of claim 6, wherein the send requests have the same format and encoding as primary write requests. A computing device (10) according to claim 7, the response requests have the same format and encoding as primary read requests. A computing device (10) according to claim 8, wherein a secondary request targeting circuit i is encoded in the data to be written intended for circuit i, of a sending request, these data to be written being subsequently conveyed by at least one sending command. Computer device (10) according to claim 9, wherein the pre-controller comprises a buffer memory, called pre-controller memory, in which each primary request ik is recorded in a register, called pre-register tik, before its processing, and in which each internal controller i comprises a buffer memory called intermediate buffer memory i. Computing device (10) according to claim 10, wherein said computing device (10) is configured to assign an identifier, called primary identifier, to each primary request ik, and one or more identifiers, called secondary identifiers, to each of the secondary requests of a set of secondary requests ik, the set of primary and secondary identifiers making it possible to associate each primary request ik with the set of secondary requests ik resulting from the decomposition of said primary request ik and to associate in return a primary execution confirmation ik with the set of secondary execution confirmation ik resulting from the decomposition of said primary execution confirmation. The computing device (10) of claim 11, wherein the internal controller is configured to reconstruct a primary request ik by recording in an intermediate buffer, as they are received, the secondary requests ik, the internal controller also being configured to execute a primary request once it has been fully reconstructed. The computing device (10) of claim 12, wherein the internal controller is configured to store a primary execution confirmation in the intermediate buffer that contained the corresponding primary request, and then to release that intermediate buffer. The computing device (10) of claim 13, wherein the primary and secondary identifiers are used by the internal controller i to reassemble the secondary requests into primary requests in the correct order when the memory controller (200) executes the send requests in a different order than in which it received them from the pre-controller. The computing device (10) of claim 14, wherein the pre-controller is configured to reconstruct a primary execution confirmation ik by recording in a pre-register tik, as they are received, the secondary execution confirmations ik; the pre-controller also being configured to transmit to the main processor (100) the primary execution confirmations corresponding to primary results once these primary execution confirmations have been reconstructed, and release the corresponding pre-registers tik so that they can be used to record new primary requests generated by the main processor (100). The computing device (10) of claim 15, wherein the pre-controller is configured to release a tik pre-register containing a primary write request when the primary execution confirmation corresponding to that primary write request has arrived. The computing device (10) of claim 16, wherein the primary and secondary identifiers are used by the pre-controller to reassemble the secondary execution confirmations into primary execution confirmations in the correct order when the memory controller executes the response requests in a different order than it received them from the pre-controller. Computer device (10) according to one of claims 3 to 17, in which the internal controller of the circuit i is configured to ignore, in a series of commands issued by the memory controller (200), the commands of the native protocol responsible for preloading one or more memory banks and those responsible for activating one or more memory ranks. Computer device (10) according to one of claims 3 to 18, in which the internal controller of the circuit i is configured to ignore the commands of the native protocol, issued by the memory controller (200), in charge of refreshing one or more memory ranks. A computing device (10) according to one of claims 1 to 19, wherein the at least one bus comprises a control and address bus and a data bus. A computing device (10) according to one of claims 1 to 19, wherein the at least one bus comprises a single bus.

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