Programmable, weighted, true time delay

Abstract

A programmable, weighted, true time delay circuit is described The delay circuit comprises a plurality of weighted delay blocks (i.e., each having a different delay) connected in series, with a bypass path around each. An RF signal is delayed a desired amount by selectively utilizing some delay blocks by passing the RF signal through them, and bypassing the RF signal around the non-5 utilized delay blocks. In one aspect, the weighting is binary, and the control signals defining the delay comprise a digital word. When a delay block is not utilized, it exhibits high isolation so that all of the RF signal flows through the associated bypass path. The isolation is by high impedance and low-pass filtering; there are no series switches in the delay block. Conversely, when a delay block is utilized, its bypass path exhibits high isolation to prevent RF signal leakage around the delay block.

Description

[0001] PROGRAMMABLE, WEIGHTED, TRUE TIME DELAY

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to electronics, and in particular to a programmable true time delay circuit comprising weighted delay blocks connected in series, each with a bypass path, whereby each delay block is either utilized or bypassed to generate different delay values.

[0004] BACKGROUND

[0005] In modern electronics, there are a number of applications in which delaying both Radio Frequency (RF) and baseband (BB) signals is advantageous. As one example, in Full Duplex (FD) wireless communications systems, the Receiver (Rx) and Transmitter (Tx) share both time and frequency resources, so that transmission and reception can be carried out in parallel. A problem in these systems is that at least some of the signal transmitted will inevitably leak into the Rx, referred to as a Self-Interference (SI) signal. For FD to work (and provide the advantage of increased spectral efficiency), the SI signal must be cancelled by combing it with an inverted reconstruction of the SI signal. Because the transmitted signal is attenuated and delayed, due to the transmission channel and antenna isolation, before it appears in the receiver as the SI signal, the output of the transmitter Power Amplifier (PA) can be delayed and inverted (or delayed so as to be out of phase) as a SI cancellation signal.

[0006] FIG. 1 shows the front end of an RF transceiver 10. A digital BB signal is converted in a Digital to Analog Converter (DAC) 12, frequency up converted by a local oscillator (LO) signal in mixer 14, amplified by a PA 16, and transmitted. The transmission may be on a dedicated antenna (or array of antenna elements), or on a shared Tx / Rx antenna (or array), with the Tx and Rx signals separated by a circulator or other isolation device. Simultaneously, in an FD system, an Rx signal received from its own or a shared antenna (or array) is amplified by a Low Noise Amplifier (LNA) 18, frequency down-converted by the LO signal in mixer 20, and digitized by Analog to Digital Converter (ADC) 22. To cancel the SI signal from the Rx signal, an SI Cancellation (SIC) circuit 24 is connected between the PA 16 output and a summing circuit 26 upstream of the input to the LNA 18.

[0007] The SIC 24 may create a version of the Tx signal that is 180° out of phase with the SI signal, in order to cancel it. Additional delay must be programmed in to account for trip time through the air interface. A programmable delay circuit imparting long delay, and exhibiting high delay resolution with low noise injection is required.

[0008] FIG. 2 shows the relationship between programmable delay and beamforming. This is another RF signal processing application requiring accurate, programmable delays. In active antenna arrays comprising multiple (e.g., hundreds or thousands) antenna elements, the Tx and Rx signals provided to and received from each antenna element may be processed individually (or in small groups). By controlling the time delays of signals transmitted to or received by adjacent antenna elements (or groups), constructive and destructive interference are exploited to dramatically increase gain in one direction, creating a main lobe, and decrease gain in surrounding directions, creating nulls. Beamforming is anticipated to be an important aspect of future generations of wireless communication networks.

[0009] For narrowband Tx / Rx signals, phase shifters work well to adjust the time-alignment of RF signals to implement beamforming. However, wireless communication networks are moving to ever-wider bandwidth signals. Phase shifters impart the same absolute phase shift to all frequency component of a signal. In wideband RF signals, this creates an artifact called beam squint, where the resulting relative difference in phase shift between the low and high end of the spectrum causes frequency-dependent beam steering errors. True time delays are a class of delay circuits that impart variable phase shifting across the signal spectrum. This eliminates beam squint, and allows for precise beamforming control of wideband RF signals.

[0010] Another application of interest for long, accurate, delays for RF signals is in an analog or hybrid pre-distortion circuit. In particular, a delay circuit having multiple output, each generating different delays, is useful. A pre-distorter requires signals with a longer delay, but the signals themselves are spread apart with shorter delay. These branches can be combined after the nonlinearities or be kept separate.

[0011] Passive delays have the advantage of very low noise and high linearity, as compared to active delays. For both FD and beamforming applications, it is therefore advantageous to use a passive delay. There are numerous methods of generating passive true time delays. One common approach is an RC-CR all-pass filter, depicted in FIG. 3. This circuit is described by Zhang, et al. in the paper "Wideband Dual-Injection Path Self-Interference Cancellation Architecture for Full-Duplex Transceivers", published in the IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1563-1576, June 2018. Another known approach is a lumped LC transmission line, as depicted in FIG. 4. This circuit is described by Chu, et al. in the paper "An Integrated Ultra-Wideband Timed Array Receiver in 0.13 pm CMOS Using a Path-Sharing True Time Delay Architecture ", published in the IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2834-2850, Dec. 2007.

[0012] In order to create a longer delay and achieve tunability, multiple delay blocks can be cascaded and tapped off along a delay chain, as shown in FIG 5. Each delay tap will have a different delay time, and all the taps are routed into the same combiner. The final tap has the maximum delay, equal to the sum of all delay blocks, and the resolution of the tunability will be equal to the delay time of a single block. See Zhang, et al., cited above.

[0013] In the circuit of FIG. 5, the true time delay, used for SIC, employs RC-CR all-pass filters as the delay blocks. Each tap has a variable gain amplifier in order to combine multiple delays of different lengths using the same delay chain. This is advantageous for FD applications because the SI signal contains multiple delays arising from multipath reflections, all of which require cancellation.

[0014] FIG. 6 depicts a circuit from the Chu, et al. reference cited above, which is used for beamforming. Different to FIG. 5, the delay blocks comprise lumped LC transmission lines. However, the architecture is the same: multiple delay blocks are cascaded, and desired delays are tapped off along the chain and summed.

[0015] FIG. 7A, abstracted from U.S. Patent No. 11,183,995, depicts a digital implementation, with a delay path and a bypass path. FIG. 7B depicts in greater detail the single-ended delay stage Ducand the delay stages of FIG. 7A. This system uses a multiplexer (MUX) at the input of the delay element and a second MUX at the output of the delay element. This means that multiple series switches are present in both the delay path and in the bypass path, which introduces losses, reduces signal integrity, and increases the power consumption, particularly when the delay path is utilized. When the delay path is not utilized, the input signal is prevented from entering the delay path input.

[0016] U.S. Patent No. 5,757,318 discloses a phased array radar system that employs programmable microelectromechanical (MEM) switches and transmission lines to provide true time delays or phase shifts in order to steer the array beam. The array includes an excitation signal source, a power division network for dividing the excitation signal into a plurality of excitation signal components, a plurality of programmable time delay / phase shift circuits including the transmission lines and MEM switches, and a plurality of radiating elements. An adaptive controller provides the control signals to set the MEM switches and select the time delay / phase shift through each time delay / phase shift circuit, thereby steering the array beam to a desired direction. The goals of a programmable, passive, true time delay circuit are to achieve both a high maximum delay and a high delay resolution with good linearity and low noise. To increase both of these parameters using existing technology requires an increase in the number of delay taps. Increasing the number of delay taps requires more circuitry for path selection, since each tap requires circuitry for tapping off the signal. This will cause more noise and greater loss, and require a larger chip area. The paths for the delay taps will also be longer when more taps are used because all taps must be combined at the same place. The routing for these delay taps will therefore require more area on the chip. True time delay circuits of the prior art also require active amplifiers, which adversely contribute to the final receiver noise figure (NF), and they also consume more power.

[0017] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

[0018] SUMMARY

[0019] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later. The invention is defined in the appended claims.

[0020] The present disclosure describes and claims aspects relating to programmable, weighted, true time delay circuit. The delay circuit comprises a plurality of weighted delay blocks (i.e., each having a different delay) connected in series, with a bypass path around each. An RF signal is delayed a desired amount by selectively utilizing some delay blocks by passing the RF signal through them, and bypassing the RF signal around the non-utilized delay blocks. The weighting may follow any pattern. In one aspect, the weighting is binary, and the control signals defining the delay comprise a digital word. The delay circuit may be passive for low noise and high linearity, but amplifiers / buffers may also be added between delay blocks. When a delay block is not utilized, it exhibits high isolation so that all of the RF signal flows through the associated bypass path. Then the delay block is electrically an open circuit presenting a high impedance at its input and output. Conversely, when a delay block is utilized, its bypass path exhibits high isolation to prevent RF signal leakage around the delay block. The delay blocks may be combined in various ways to increase delays and obtain fine delay control.

[0021] One aspect relates to a weighted, true time delay circuit configured to apply a programmable delay to a Radio Frequency (RF) signal. The delay circuit includes a plurality of passive, weighted delay blocks connected in series. Each weighted delay block has an input and output and imparts a different delay to an RF signal passing through it. The delay circuit also includes a bypass path between the input and output of each weighted delay block. The bypass path imparts substantially no delay to an RF signal passing through it. Programmable control signals selectively render each delay block as either utilized, wherein the RF signal passes through it and is delayed and its associated bypass path is electrically isolated, or bypassed, wherein the RF signal passes through the bypass path and the delay block is electrically isolated.

[0022] Another aspect relates to a communication device. The communication device includes at least one of a Self-Interference Cancelation circuit including the delay circuit described above, a beamforming circuit including the delay circuit described above, and an analog or hybrid predistortion circuit including the delay circuit described above.

[0023] BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0025] FIG. 1 is a block diagram of wireless communication device front end.

[0026] FIG. 2 is a diagram showing the relationship between signal delay and beam steering.

[0027] FIG. 3 is a schematic diagram of a known RC-CR all-pass filter circuit.

[0028] FIG. 4 is a schematic diagram of a known lumped LC transmission line.

[0029] FIG. 5 is a block diagram of a known true time delay circuit where delay blocks are cascaded, tapped off, and summed.

[0030] FIG. 6 is a schematic diagram of a known true time delay circuit where delay blocks are cascaded, tapped off, and summed, wherein the delay blocks are lumped LC transmission lines. FIG. 7A is a block diagram of a known digital delay circuit.

[0031] FIG. 7B is a schematic diagram of a portion of the circuit of FIG. 7A.

[0032] FIG. 8 is a schematic diagram of a programmable, passive, binary weighted true time delay circuit.

[0033] FIG. 9A is block diagram showing a delay block of the circuit of FIG. 8 being utilized.

[0034] FIG. 9B is block diagram showing a delay block of the circuit of FIG. 8 being bypassed.

[0035] FIG. 10 is a diagram showing a control word and the path of an RF signal through the circuit of FIG. 8.

[0036] FIG. 11 is a block diagram of a delay block of the circuit of FIG. 8.

[0037] FIG. 12A is a first schematic diagram of the high impedance isolation stage of the circuit of FIG. 11.

[0038] FIG. 12B is a second schematic diagram of the high impedance isolation stage of the circuit of FIG. 11.

[0039] FIG. 13 is a schematic diagram of the delay stage of the circuit of FIG. 11.

[0040] FIG. 14 is a Bode plot showing the operation of a low-pass filter.

[0041] FIG. 15 is a schematic diagram of the low-pass isolation stage of the circuit of FIG. 11.

[0042] FIG. 16 is a block diagram showing signal power attenuation through the circuit of FIG. 8.

[0043] FIG. 17A is a schematic diagram of a bypass switch of the circuit of FIG. 8.

[0044] FIG. 17B is a schematic diagram showing isolation of the bypass switch of FIG. 17A.

[0045] FIG. 18A is a block diagram of a true time delay circuit incorporating the circuit of FIG. 8.

[0046] FIG. 18B is a block diagram of a first multi-output true time delay circuit incorporating the circuit of FIG. 8.

[0047] FIG. 18C is a block diagram of a second multi-output true time delay circuit incorporating the circuit of FIG. 8.

[0048] FIG. 18D is a block diagram of the second multi-output true time delay circuit of FIG. 18C configured to output a single signal including all delays.

[0049] FIG. 19A is a Smith chart plot showing the operation of the high impedance isolation stage of FIG. 11.

[0050] FIG. 19B is a schematic diagram of a single-ended implementation of the high impedance isolation stage of FIG. 11.

[0051] FIG. 19C is a schematic diagram of a differential implementation of the high impedance isolation stage of FIG. 11. FIGs. 20A-20D show various layout options for the circuit of FIG. 8.

[0052] FIG. 21 is a block diagram of the circuit of FIG. 8 with amplifiers / buffers between delay stages.

[0053] FIG. 22A is a block diagram of the circuit of FIG. 8 with amplifiers / buffers between delay stages, including feedback.

[0054] FIG. 22B is a schematic diagram of an amplifier in a single-ended design.

[0055] FIG. 22C is a schematic diagram of an amplifier in a differential design.

[0056] FIG. 23 is a hardware block diagram of a UE.

[0057] FIG. 24 is a hardware block diagram of a base station.

[0058] DETAILED DESCRIPTION

[0059] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0060] FIG. 8 depicts a programmable, passive, weighted, true time delay circuit 30 configured to apply a programmable delay to a Radio Frequency (RF) signal. A plurality of passive, weighted delay blocks 32-0, 32-1, etc. are connected together in series (a representative delay block is simply numbered 32 herein). Each weighted delay block 32 imparts a different time delay to an RF signal passing through it. In the passive, weighted, true time delay circuit 30 depicted in FIG. 8, the weighting is binary. Each delay block 32 imparts a delay NTd, where N = 1, 2, 4, 8, ... , 2kfor a k- block circuit 30. Binary weighting is only one example; other weighting schemes may be used, such a linear, thermometer coding, and the like.

[0061] The programmable, passive, weighted, true time delay circuit 30 also comprises a bypass path between the input and output of each weighted delay block 32. The bypass path - represented as a series bypass switch 34 in FIG. 8 - imparts substantially no delay to an RF signal passing through it.

[0062] In the programmable, passive, weighted, true time delay circuit 30, programmable control signals selectively render each delay block 32 as either utilized, wherein the RF signal passes through it and is delayed, or bypassed, wherein the RF signal passes through the bypass path and is not delayed. When a delay block 32 is utilized, its associated bypass path is electrically isolated by opening the bypass switch 34. When a delay block 32 is bypassed, it is electrically isolated, preventing the RF signal from passing through it. The delay time of an RF signal is programmed by bypassing the delay blocks 32 that are not utilized, and passing the RF signal through the delay blocks 32 that are utilized.

[0063] Using binary weighted delays, the number of switches in the signal path is greatly reduced, compared to linearly weighted solutions. In order to achieve the ratio between the maximum delay and the delay resolution with equally sized delay blocks of the prior art, 16 series switches are required; for the binary weighted delay circuit 30, the equivalent number is 4. Additionally, the binary weighted delay circuit 30 also has much lower complexity, due to less complex signal routing. Furthermore, the linearly weighted delay blocks 32 require careful design to ensure that all delay states cause the same loss.

[0064] FIGs. 9A and 9B show that both the bypass path and delay block 32 use an isolation mechanism to pass an RF signal through or to block it. If and RF signals can pass the delay path without isolation, some of the signal will propagate through the delay path when the associated delay block 32 is utilized, and the bypass path should be disabled. This means the signal will be divided into two parts, one with a delay and one without. This will cause inaccuracy of the delay tuning. The same inaccuracy also arises if a signal can leak through the delay block 32 when the bypass path is enabled. Therefore, an isolation mechanism is required in the both the delay block 32 and the bypass path 34. FIG. 9B shows the case when the delay block 32, Tdceii in the figure, is utilized. The delay block 32 generates the delay Td and the bypass path blocks the signal, i.e., the bypass switch 34 is OFF. FIG. 8B illustrates the other case: when the delay block 32 is bypassed. Here, the bypass path is conducting the signal, i.e., the bypass switch 34 is ON. In this case, the delay block 32 (Tdceii in the figure) is put in a high impedance isolation state, indicated by an open circuit at its input and output terminals. Therefore, no series switches are required internally in the signal path of Tdceii, nor any switches in series with the input or output of the delay cell Tdceii, in contrast to the prior art delay circuits. This functionally is similar to a digital tri-state circuit, in which the output, normally a 1 or 0, may also have a high impedance state, effectively removing it from, e.g., an attached bus. Note that in aspects of the present disclosure, the high impedance state is induced on both the input and the output, when a delay block 34 is being bypassed.

[0065] FIG. 10 depicts one example of programming the passive, binary, weighted, true time delay circuit 30. The digital control word is a series of ones and zeros, each corresponding to one delay block 32. A 1 may indicate the corresponding delay block 32 is utilized, and a 0 may indicate it is bypassed (or vice versa). This forms a binary number equal to the delay time at the output when multiplied by the least significant bit (LSB), in this case Td. The number of tuning levels is equal to the number of delay blocks squared, N2, as in any binary weighted system.

[0066] The architecture of the serial, binary-weighted delays depicted in FIG. 8 may be implemented using any appropriate circuits for the delay blocks 32. In addition, the delay blocks 32 should be able to be turned off, which means that the input impedance should be high. An easy way to do this is to add a series transistor switch in the signal path; however, this will add losses and nonlinearities. Therefore, an isolation mechanism without transistors in the signal path is preferable. According to aspects of the present disclosure, multiple stages of isolation and delay are used, as shown in FIG. 11. The implementation shown in FIG. 11 is differential, but the same concepts can be implemented as single-ended by those of skill in the art.

[0067] As FIG. 11 depicts, a high impedance isolation stage LCv436 is placed at the input of the delay block 32, and another is placed at the output. The high impedance isolation stage LCv436 comprises a lumped LC quarter wavelength (X / 4) transmission line, where X is the wavelength of the RF signal being delayed. Additionally, a shunt isolation switch SWshunt 38 is connected to ground on the inner side of each LCv436. As well known, an impedance applied to one side of a X / 4 transmission line will be inverted at the other side. When the delay block 32 is in bypass state, the shunt isolation switches SWshunt 38 are closed, and a low impedance is applied to the inner side of each LCV436. The transmission lines invert this, presenting a high impedance at their outer sides, and hence at both the input and the output of the delay block 32, contributing to isolation in both directions. Conversely, when the delay block 32 is utilized, the shunt isolation switches SWshunt 38 are open, presenting an open circuit to the inner side of each LC / 436, which the transmission lines invert to a low impedance for the RC signal to flow through the delay block 32 with low loss.

[0068] FIG. 12A shows the basic structure of the LCv436, without calibration. It is a lumped-element LC 7t circuit forming a transmission line. FIG. 12B shows the LC.436 with calibration for delay mismatch from process spread, according to one aspect of the present disclosure. Cfixare fixed capacitors, and Cvar are variable capacitors. The capacitances of the two are added, yielding the capacitance C of FIG. 12A. Cvar, and hence C, is adjusted for different process spread. Further, the trade-off between the values of Cvarand Cfixis based on the losses (capacitor Q) and the tuning range (C max / Cm in ) of the resulting capacitors. A larger Cfixincurs lower losses, but a lower tuning range. If Cvaris larger, then the losses are higher, and the tuning range is higher as well. Additionally, the functionality of the LCv436 of FIG 12B may also be used to increase the frequency range, and this is true both in both the utilized and bypassed states of the delay block 32. Note that the input and output capacitors C in FIG. 12A may have different values. Similarly, the input and output fixed capacitors Cfixin FIG. 12B may have different values, and also the variable capacitors Cvar may differ.

[0069] FIG. 13 shows the structure of the stages referred to in FIG. 11 as LCcc40. These comprise a number of cascaded LC-stages, the number of which determines the delay time of the delay block 32. In each stage, the values of the capacitors C may be different from each other. In order to reduce the delay variation over frequency, and obtain true time functionality, more LC-stages are used in LCcc40, but each with reduced delay time. By reducing the inductance and capacitance in these stages, the cut-off frequency of the low-pass filters is increased, which results in a lower delay time, as shown in the Bode diagram in FIG 14. Therefore, a higher number of stages is used, in order to get the same total delay time. The delay variation over frequency is in total reduced when using smaller, but more, LC-stages because the Q-value is lower for smaller inductors, which will reduce the derivative of the phase response.

[0070] Low-pass filter behavior can also be used for increasing the isolation of the delay block 32. By decreasing the cut-off frequency of a LC-stage, signal amplitude will be more greatly attenuated, according to the Bode diagram. Accordingly, as shown in FIG. 11, two LCSW42 stages are placed in the center of the delay block 32, for which the cut-off frequency is reduced when they are switched on. FIG. 15 shows the structure of these stages. The LCSW42 circuit is an LC it circuit implementing a low-pass filter with filter capacitors C in shunt configuration on either side of an inductor. Additionally, two isolation capacitors Chigh are connected in parallel with the filter capacitors C, and a switch SWLP is connected in series at each side of each isolation capacitors Chigh. The switches SWLP are open when the delay block 32 is utilized, and the filter capacitors C set the cut-off frequency of the low-pass filter above the frequency of the RF filter, allowing it to pass with low loss. When the delay block 32 is bypassed, the switches SWLP are closed, placing the isolation capacitors Chigh in parallel with the filter capacitors C. This increases the total capacitance, and decreases the cut-off frequency below the RF signal frequency, thus increasing the isolation of the delay block 32.

[0071] Referring back to FIG. 11, in some aspects, each pair of LCcc 40 and LCsw 42 stages may be combined to form a X / 4 stage. Additionally, a third set of SWshunt switches 38 may placed at the center, between the X / 4 stages. When a delay block 32 is bypassed, the bypass switches 34 are in the signal path and therefore must be able to handle high power. Furthermore, the delay block 32 with the longest delay will attenuate the signal the most, and should therefore be placed at the front of the chain of delay blocks 32. This is because the signal power is the highest at the input, and will be reduced for the bypass switches 34 in the following delay blocks 32, reducing the power handling requirement of the next stage in the signal chain. This relationship is shown graphically in FIG. 16.

[0072] The bypass switch 34 for the delay block 32 with the longest delay, at the beginning of the chain of serial delay blocks 34, must be designed to handle the highest signal power. The isolation and signal power handling are increased by stacking multiple transistors in series, as shown in FIG. 17A. A large resistance is placed between the gates of the transistors and the enable signal EN so that the gate voltage (Vg) will swing with the transistor drain and source voltages (Vd, and Vs), thus keeping the difference between the gate voltage and the drain and source voltages the same over the complete signal period.

[0073] When the delay block 32 is utilized, all of the switches must exhibit high isolation; therefore ground-connected isolation transistors 44 are used, as shown in FIG 17B. The ground-connected isolation transistors 44 are closed on the inverse of the EN signal, because they should be conducting when the bypass switch 34 is off, so that any RF signal leaking through the bypass switches 34 is shorted to signal ground. By adding more paths to ground, at more places between the series transistors comprising the bypass switch 34, higher isolation is achieved. In the same way as for the series transistors 34, the ground-connected isolation transistors 44 can be stacked in series to increase voltage handling capability.

[0074] FIG. 18 A shows a block diagram of a complete analog true time delay circuit 46, such as may be deployed in a SIC 24, for a single delay. The delay circuit 46 comprises an input attenuator 48, a coarse delay 50, a fine delay 52, and an output attenuator 54. The programmable, passive, binary weighted, true time delay circuit 30 described herein is primarily to be used as a coarse delay 50 but can also to some degree be used as a fine delay 52. In addition, the programmable, passive, binary weighted, true time delay circuit 30 is best used with delays equal to, or longer than, the period of the targeted carrier frequency, i.e., T=l / fcamer. This simply means that in the elements of the coarse delay 50, the delay resolution is one period of the carrier frequency, and therefore each delay element is a complete wavelength. This reduces the complexity of the design.

[0075] FIG. 18B shows an analog true time delay circuit 56 generating N delays of the input signal. The true time delay circuit 56 also has a larger delay spread than the true time delay circuit 46 of FIG. 18A. To generate multiple delays, the chain of delay blocks 34 within the true time delay circuit 56 is split into N branches after the first attenuator 48. Each parallel delay branch may generate any delay within the complete range of the true time delay circuit 46 shown in FIG. 18A. The true time delay circuit 56 is a multiple output, or “fan-out” system, where each output has a signal with a delay and amplitude either equal to or different from the other outputs.

[0076] FIG. 18C shows yet another analog true time delay circuit 56, which is structured and optimized to generate multiple outputs with small delay differences. In the true time delay circuit 56 the chain of delay blocks 32 branches after the coarse delay 50, so the delay differences can maximally be T. Additionally, the signals at the different outputs can have different amplitudes. The true time delay circuit 58 is also a multiple output, or “fan-out” system, where each output imparts the same or a different delay and / or amplitude to the input signal.

[0077] FIG. 18D depicts an analog true time delay circuit 60 generating a single output. A summing circuit 62 combines the disparate outputs into one signal. This may be advantageous, for example, in the SIC circuit 24 of a FD front end 10 (FIG. 1), where a single Rx signal contains multipath reflections, each requiring a slightly different delay for cancellation. The true time delay circuit 60 is shown employing the configuration of FIG. 18C, with smaller delay spreads. However, in some applications, the configuration of FIG. 18B, with larger delay spreads, could alternatively be used.

[0078] Numerous hybrid configurations are possible. For example, an analog true time delay circuit such as depicted in FIGs. 18A-D may have single or multiple inputs and / or outputs, and some, but possibly not all, outputs may be combined. Those of skill in the art can readily implement such variations for any given application, given the teachings of the present disclosure. Accordingly, such permutations are not further elaborated herein.

[0079] Referring again to FIG. 8, the programmable, passive, binary weighted, true time delay circuit 30 according to aspects of the present disclosure uses bypass switches 34 to bypass the binary-weighted delay blocks 34. It is important for the bypass switches 34 to have the same loss as the associated delay blocks 32, so that amplitude variation between different delay settings (that is, different patterns of which delay blocks 34 are utilized or bypassed) is minimized. This also reduces the linearity and reliability requirements of the later delay stages. The programmable, passive, binary weighted, true time delay circuit 30 is also an attenuator. In a dual-panel antenna solution (TX panel and RX panel), the TX-to-RX isolation is in the range of 50-80 dB. The required attenuation of a canceller used in this type of system is 50-80 dB, so it is beneficial to have a constant-delay, independent attenuation in a true-time delay circuit. However, to obtain a functioning system without introducing additional parasitic signals with incorrect delay, the bypass switch 34 must have an isolation of at least 60 dB.

[0080] When a bypass switch 34 is used to bypass a delay block 32, the delay block 32 must also be disabled and placed into a high isolation state, in order to avoid generating parasitic signals with delays other than the intended one. As described with reference to FIG. 11, by positioning quarter wavelength transmission lines LG.4 36 at the input and output, with shunt switches SWshunt at their inner terminals, that low impedance is inverted to a high impedance at the outer terminals. FIG. 19A shows this high impedance on a Smith chart.

[0081] FIG. 19B is a high level block diagram of a fully differential implementation of a delay block 32, where the LCcc 40 and LCsw 42 stages have been combined to form X / 4 stages, as discussed above. The SWshunt switches 38 connect to a virtual ground. The total delay T when the delay block 32 is utilized is depicted as spanning across all of the X / 4 stages. When the delay block 32 is bypassed, the SWshunt switches 38 are closed, and the X / 4 stages present a high impedance for isolation. FIG. 19C shows a pseudo-differential implementation.

[0082] As discussed herein, the delay blocks 32 according to aspects of the present disclosure achieve very high impedance in passthrough mode, through X / 4 inversion of a zero-impedance connection (ground) and low-pass filtering below the frequency of the RF signal. The delay blocks achieve at least 60 dB of isolation, which is considered an open circuits. As used herein, an open circuit state of a circuit is defined as an impedance which is at least 5 times larger than the characteristic impedance (Z0) of the circuit, in relation to how the impedances are measured, either single-ended or differential.

[0083] To implement the programmable, passive, weighted, true time delay circuit 30, the arrangement of the delay block 32 and the bypass switch 34 is important. Routing all bypass switches 34 very close to each together physically enables a very small delay when a delay block 32 is bypassed, and this maximizes the on / off delay ratio. Furthermore, the programmable, passive, weighted, true time delay circuit 30 requires a small area, has a compact layout, and requires a minimum amount of routing.

[0084] FIGs. 20A-D depict various layout examples, suitable for on-chip integration and off-chip PCB implementations. The specific implementation is primarily based on the operating frequency. Furthermore, the characteristic impedance of the implementation can be any impedance. A lower resistive impedance yields smaller inductive elements considering area, but larger capacitors and switches; the opposite is true for a higher resistive impedance, where the inductors consume more area and the capacitors and switches are smaller.

[0085] FIG. 20A depicts a T-line structure. This is a straightforward layout, and this configuration consumes the most area. Note that the bypass switches 34 are not shown. FIG. 20B shows a more compact transmission line solution, achieved by changing the orientation of every second delay block 32. FIG 20C shows another compact solution, in which the delay block 32 is shaped as an inductor. In this case, the individual turns may also have multiple turns to generate the correct binary delays. This layout can be used to implement a solution with transmission lines, by wrapping the traces like a coil. The layout can also be used to implement the inductance needed for an LC lumped delay block 34, then the shunt capacitors are implemented as fixed capacitors to signal ground, distributed along the inductor (in the same way the shunt switches are distributed). FIG 20D shows a “four-leaf clover” design, which achieves better isolation between each delay block 34. The isolation is created by the turn orientation of the individual bit structures, where most of the magnetic fields couple in a way such that no or very small electrical signals are generated from one delay block 34 to another, thus achieving high isolation.

[0086] As stated above, passive delays have the advantages of very low noise and high linearity. However, in some applications, it may be advantageous to interpose active devices such as amplifiers / buffers between each delay element 34. FIG. 21 shows an active, programmable, weighted, true time delay circuit 64. The amplifiers / buffers G0-G3 may have their inputs and outputs matched to the characteristic impedance of the delay blocks 34. Alternatively, if the delay blocks 34 are implemented in the voltage and / or current domain, the amplifier / buffer G0-G3 inputs and outputs may be un-matched. The primary function of the amplifiers / buffers G0-G3 is to maintain or increase the magnitude of the RFsignal being delayed.

[0087] FIGs. 22A-22C depict an active, programmable, weighted, true time delay circuit 64 in which the amplifiers / buffers use positive feedback to maintain the signal amplitude. In a single-ended system (Input, Output), the amplifiers G0-G3 have a requirement of positive gain, as shown in FIG. 22B. However, in a differential system (Inputp, Inputn, Outputp, Outputn), negative crosscoupled inverting amplifiers may be used. FIG 22B shows the negative cross-coupled inverting amplifiers, depicted as cross-coupled inverters. The dual polarity of the signals in the system is used to provide positive feedback, which provides a negative resistance that is regulated by this positive feedback, to compensate for the losses in the delay line. As discussed above, accurate programmable delays may be beneficial in many high-frequency circuits. Of particular interest is generating one or more delays of a transmitted RF signal in an FD system, for cancellation in a SIC of Tx leakage or reflections, prior to processing by the Rx. Referring again to FIG. 1, the SIC 24 may require a single delay to cancel leakage between Tx and Rx antennas, or through the circulator. The programmable, weighted, true time delay circuit 30 may be deployed to provide an accurate, programmable delay, either alone or as part of a more complex delay circuit 46 (FIG. 18A), such as the coarse delay 50. Alternatively or additionally, the SIC 24 may require multiple delays, to cancel one or more Tx reflections in the Rx signal, such as multipath reflections. In this case, the programmable, weighted, true time delay circuit 30 may comprise part of a multi-delay circuit 56, 58, 60 (FIGs. 18B-18D), or a similar delay circuit optimized for a particular application. Alternatively or additionally, the weighted, true time delay circuit 30, or a more complex delay circuit 46 incorporating it, may be advantageously deployed to provide the true time delay 28 (FIG. 2) required for wideband beamforming, without the beam squint that may arise from the use of phase shift circuits. Such an SIC 24 and / or beamforming delay 28 may be beneficial in both User Equipment (UE) and base stations of a wireless communication network.

[0088] FIG. 23 illustrates a hardware block diagram of a UE 70 as implemented in accordance with one or more aspects of the present disclosure. A UE 70 is any type of device capable of communicating with a network node and / or access point using radio signals. A UE 70 may therefore refer to a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB loT) device, etc. The UE 70 may also refer to a cellular telephone or “smartphone,” however, the term UE should be understood to encompass any wireless device 70. A UE 70 may also be referred to as a radio device, a radio communication device, a wireless device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices, or devices capable of machine-to-machine communication, sensors equipped with a wireless device, wireless-enabled table computers, mobile terminals, smart phones, laptop- embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customerpremises equipment (CPE), etc. In the discussion herein, the terms machine-to-machine (M2M) device, machine-type communication (MTC) device, wireless sensor, and sensor may also be used. It should be understood that these devices, although referred to as UEs, but may be configured to transmit and / or receive data without direct human interaction. In some aspects, the UE 70 includes a user interface (not shown), including features such as a display, touchscreen, keyboard or keypad, microphone, speaker, and the like; in other aspects, such as in many M2M, MTC, or NB loT scenarios, the UE 70 may include only a minimal, or no, user interface. The UE 70 also includes processing circuitry 72; memory 74; and communication circuitry 76 to effect wireless communication across an air interface to one or more radio network nodes, such as a base station, and / or access points. The communication circuitry 76 includes one or more instances of a programmable, passive or active, weighted, true time delay circuit 30, 64, such as in a SIC circuit 24 to enable FD, and / or as the delay 28 in a wideband beamforming circuit. The communication circuitry 76 is connected to one or more antennas 78. As indicated by the dashed lines, the antenna(s) 78 may protrude externally from the UE 70, or the antenna(s) 78 may be internal.

[0089] Figure 24 illustrates a hardware block diagram of a base station 80 operative in a wireless communication network. The base station 80 includes processing circuitry 82; memory 84; and communication circuitry 86 to effect wireless communication across an air interface to one or more UEs 40. The communication circuitry 86 includes one or more instances of a programmable, passive or active, weighted, true time delay circuit 30, 64 such as in a SIC circuit 24 to enable FD, and / or as the delay 28 in a wideband beamforming circuit. The communication circuitry 86 is connected to one or more antennas 88. As indicated by the broken connection to the antenna(s) 88, the antenna(s) 88 may be physically located separately from the base station 80, such as mounted on a tower, building, or the like. Although the memory 84 is depicted as being internal to the processing circuitry 82, those of skill in the art understand that the memory 84 may also be external. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 82 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). The base station 80 is known in LTE as an eNodeB or eNB, and in New Radio (NR) as gNB. In general, in other wireless communication networks, the base station 80 may be known as a Radio Base Station, Base Transceiver Station, Access Point, or the like.

[0090] The circuits or circuitry may comprise circuits dedicated to performing certain functional processing and / or one or more microprocessors in conjunction with memory. For instance, the circuitry may include one or more microprocessor or microcontrollers, as well as other digital hardware, which may include digital signal processors (DSPs), special-purpose digital logic, and the like. The processing circuitry may be configured to execute program code stored in memory, which may include one or several types of memory such as read-only memory (ROM), random-access memory, cache memory, flash memory devices, optical storage devices, etc. Program code stored in memory may include program instructions for executing one or more telecommunications and / or data communications protocols as well as instructions for carrying out one or more of the techniques described herein, in several embodiments. In embodiments that employ memory, the memory stores program code that, when executed by the one or more processors, carries out the techniques described herein.

[0091] Aspects of the present disclosure present numerous advantages over the prior art. The programmable, passive, weighted, true time delay circuit 30 provides a single input and output for all available delays. When a delay block 32 is bypassed, it is a true bypass, with the delay block 32 presenting at least 60 dB of isolation. All of the delays in the delay blocks 32 are matched in amplitude, reducing the calibration overhead. Large delays are achievable with passive structures, which also provide compact layout. With fewer path switches than true time delays of the prior art, the maximum delay and delay resolution are increased. Due to short traces and lower signal routing complexity than comparable circuits in the prior art, the complexity and chip area are reduced. The passive design provides low noise and high linearity; however, active buffers may be used where advantageous. By binary weighting the delay blocks 32, delay selection and control is simplified when controlled by a digital system.

[0092] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0093] The term “unit” may have conventional meaning in the field of electronics, electrical devices and / or electronic devices and may include, for example, electrical and / or electronic circuitry, devices, modules, processors, memories, logic solid state and / or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and / or displaying functions, and so on, as such as those that are described herein.

[0094] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0095] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0096] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

CLAIMS1. A weighted, true time delay circuit (30, 64) configured to apply a programmable delay to a Radio Frequency (RF) signal, characterized by: a plurality of passive, weighted delay blocks (32) connected in series, each weighted delay block (32) having an input and output and imparting a separate delay to an RF signal passing through it; and a bypass path between the input and output of each weighted delay block, wherein the bypass path imparts substantially no delay to an RF signal passing through it; wherein programmable control signals selectively render each delay block (32) as: utilized, wherein the RF signal passes through it and is delayed and its associated bypass path is electrically isolated, or bypassed, wherein the RF signal passes through the bypass path and the delay block (32) is electrically an open circuit presenting a high impedance at its input and output.

2. The delay circuit (30, 64) of claim 1, wherein each delay block (32) comprises two high impedance isolation stages, LG.4, (36) one connected to the delay block (32) input and the other connected to the delay block (32) output; each high impedance isolation stage LG.4 (36) comprising a transmission line having an electrical length of one quarter of the wavelength A. of the RF signal.

3. The delay circuit (30, 64) of claim 2, wherein each delay block (32) further comprises: shunt isolation switches, SWshunt, (38) connected between the inner terminal of each LCv4(36) and signal ground.

4. The delay circuit (30, 64) of claim 3, wherein, when the delay block (32) is bypassed, the SWshunt (38) are closed to present a low impedance to inner terminals of each LC / 4 (36), whereby the transmission lines invert the low impedance and present a high impedance at the outer terminals of each LCM (36).

5. The delay circuit (30, 64) of any of claims 2-4, wherein each delay block (32) further comprises: one or more delay stages, LCcc, (40) configured to impart a weighted delay to the RF signal,each LCcc (40) comprising a plurality of LC low-pass filter stages; and one or more low-pass isolation stages, LCsw, (42) configured to provide isolation.

6. The delay circuit (30, 64) of any of claims 2-5, wherein the high impedance presented by the isolation transmission lines is at least 20-60 dB.

7. The delay circuit (30, 64) of claim 5, wherein pairs of LCcc (40) and LCsw (42) stages are combined to form X / 4 transmission line stages.

8. The delay circuit (30, 64) of claim 7, further comprising a SWshunt (38) connected to each X / 4 transmission line stage.

9. The delay circuit (30, 64) of any of claims 2-8, wherein the transmission lines in each LCz 4 (36) are formed as a n circuit comprising a series inductor with shunt capacitors on either side.

10. The delay circuit (30, 64) of claim 9, wherein the circuit further comprises one or more variable shunt capacitors configured to calibrate for delay mismatch due to process spread.

11. The delay circuit (30, 64) of claim 5, wherein each LCsw (42) comprises a low-pass filter implemented as a n circuit comprising: a series inductor; shunt filter capacitors (C) on either side of the inductor; and isolation capacitors (Chigh) in shunt configuration with switches (SWLP) connected in series; wherein when the delay circuit (32) is utilized, the series switches (SWLP) are open, isolating the isolation capacitors (Chigh) from the low-pass filter; and when the delay circuit (32) is bypassed, the series switches (SWLP) are closed, placing the isolation capacitors (Chigh) in parallel with the filter capacitors, lowering the cut-off frequency of the low-pass filter below the frequency of the RF signal, and thus increasing the isolation of the delay block (32).

12. The delay circuit (30, 64) of claim 5, wherein each LCsw (42) comprises a transmission line.

13. The delay circuit (30, 64) of any preceding claim, wherein each bypass path includes one or more series bypass switches (34) configured to be open when the associated delay block (32) is utilized and closed when the associated delay block (32) is not utilized.

14. The delay circuit (30, 64) of any of claim 13, wherein the series bypass switch (34) associated with the delay block (32) having the largest delay comprises a plurality of series-connected bypass transistor switches, each including a resistance interposed between an enabling signal and the gate terminal, the resistance configured to cause the gate voltage of the transistor to follow the drain and source voltages.

15. The delay circuit (30, 64) of claim 13 or 14, wherein each series bypass switch (34) comprises: one or more bypass transistor switches connected in series and collectively closed by an enable signal; and one or more isolation transistor switches connected in series between a node between two bypass transistor switches and ground, the isolation transistor switches collectively closed by the inverse of the enable signal.

16. The delay circuit (30, 64) of any of claims 13-15, wherein when a delay block (32) is utilized, the associated bypass path presents an isolation of at least 20-60 dB.

17. The delay circuit (30, 64) of any preceding claim, wherein, when a delay block (32) is bypassed, the associated bypass path causes the same loss to the RF signal as that delay block (32) causes when it is utilized.

18. The delay circuit (64) of any preceding claim, further comprising an amplifier or buffer connected in series to the output of each delay block (32).

19. The delay circuit (64) of claim 18, wherein the delay circuit is differential, and wherein each amplifier or buffer comprises a pair of cross-coupled inverters.

20. The delay circuit (30, 64) of any preceding claim, wherein the delay block (32) weighting is binary.

21. The delay circuit (30, 64) of any of claims 1-19, wherein the delay block (32) weighting is linear.

22. The delay circuit (30, 64) of any of claims 1-19, wherein the delay block (32) weighting is thermometer coded.

23. The delay circuit (30, 64) of any preceding claim, wherein the weighted delay blocks (32) are connected in series, in order of their weighted delays, with the greatest delay at the input and the smallest delay at the output.

24. A communication device (70, 80), comprising the delay circuit of any of claims 1-23.

25. The communication device of claim 24 wherein the delay circuitry is comprised in one or more of: a Self-Interference Cancelation circuit; a beamforming circuit; and an analog or hybrid pre-distortion circuit.

26. The communication device (70) of claim 24 or 25 wherein the communication device (70) is a User Equipment, UE.

27. The communication device (80) of claim 24 or 25, wherein the communication device (80) is a base station (80) operative in a wireless communication network.

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