Method for manufacturing a plurality of semiconductor chips

Abstract

A method for manufacturing a plurality of semiconductor chips with the following steps is provided: - providing a functional semiconductor wafer (10) comprising a semiconductor body (2) on a growth substrate (1), wherein the semiconductor body (1) comprises an epitaxial semiconductor layer sequence (20) with a plurality of chip regions (3) and a distance holder structure (4) buried in the semiconductor body (2), and - removing the growth substrate (1).

Description

[0001] 2023P01085WO February 5, 2025P2023,1293 WO N -1 –Description METHOD FOR MANUFACTURING A PLURALITY OF SEMICONDUCTOR CHIPSThis patent application claims the priority of the German patent application 102024104856.5, the disclosure content of which is hereby included by reference.A method for manufacturing a plurality of semiconductor chipsis provided. Preferably, an improved method for manufacturinga plurality of semiconductor chips is provided, wherein agrowth substrate is removed from a semiconductor layer sequence on wafer level. This object is achieved by a subject-matter according to the independent claim. Advantageous embodiments and developments of the subject-matter are characterized in the dependent claims, and are also disclosed by the following description and the drawings.According to at least one embodiment, a method formanufacturing a plurality of semiconductor chips is provided.In particular, a functional semiconductor wafer comprising asemiconductor body on a growth substrate can be provided. Furthermore, the growth substrate can be removed. Preferably, the growth substrate can be completely removed, so that the semiconductor chips, when finished, are free of the growth substrate. Particularly, the growth substrate can be removed on wafer level from the functional semiconductorwafer. Such batch process on wafer level particularly has theadvantage of reduced process time. Preferably, after the2023P01085WO February 5, 2025P2023,1293 WO N -2 –removal of the growth substrate, individual semiconductor chips are formed by a singulation process.The semiconductor body can comprise an epitaxialsemiconductor layer sequence with a plurality of chipregions. Particularly, the semiconductor body with theepitaxial semiconductor layer sequence can at least partly beepitaxially grown on the growth substrate. In particular, theepitaxial semiconductor layer sequence can be epitaxiallygrown on or over the growth substrate. Preferably, the growthsubstrate can be lattice matched to the semiconductor body orat least to the epitaxial semiconductor layer sequence. For example, the growth substrate can comprise or consist of gallium nitride or sapphire. The epitaxial semiconductor layer sequence can comprise aplurality of chip regions. Preferably, the chip regions cancover the complete growth substrate so that chip regions can be defined that adjoin an edge of the growth substrate. Preferably, the central region can be surrounded, in a planview, by an edge region. Here and in the following “in a planview” can mean a viewing direction pointing from the growth substrate towards the epitaxial semiconductor layer sequence. In other words, the viewing direction of the plan view can beperpendicular to the main extension plane of the functionalsemiconductor wafer. The edge region can preferably comprisean edge of the growth substrate. In case of a typical circular growth substrate, the edge region can be a ring running along the circular edge of the growth substrate. Particularly preferably, the rig-like structure can be a closed ring surrounding the central region. The semiconductorbody can be divided in a singulation step to form separate2023P01085WO February 5, 2025P2023,1293 WO N -3 –semiconductor chips, wherein each of the semiconductor chips can be formed by or at least comprise a chip region. Particularly, the chip regions of the epitaxial semiconductorlayer sequence comprise an active zone that is configured forgenerating electromagnetic radiation during operation of a finished semiconductor chip. For example, the active zone can be a part of or can be formed by an active layer that is arranged between an n-doped epitaxial semiconductor layer and a p-doped epitaxial semiconductor layer.According to a further embodiment, the semiconductor body orat least the epitaxial semiconductor layer sequence comprisesor consists of one or several III / V semiconductor compoundmaterials, particularly nitride semiconductor compound materials. Nitride semiconductor compound materials are semiconductor compound materials containing nitrogen, such asthe materials from the system InxAlyGa1-x-yN with 0 ^ x ^ 1,0 ^ y ^ 1 and x + y ^ 1.Particularly, the semiconductor body with the epitaxialsemiconductor layer sequence and the growth substrate areprovided as parts of the functional semiconductor wafer.Therefore, the semiconductor body with the epitaxialsemiconductor layer sequence and the growth substrate eachhave a main extension plane arranged particularly preferablyparallel to each other. The extension of the semiconductor body with the epitaxial semiconductor layer sequence and ofthe growth substrate along the main extension plane is muchlarger than a respective thickness perpendicular to the mainextension plane. Particularly preferably, the main extensionplane is perpendicular to a main growth direction along which the semiconductor layers of the epitaxial semiconductor layer2023P01085WO February 5, 2025P2023,1293 WO N -4 –sequence are grown. In other words, the main extension plane can preferably be perpendicular to the arrangement direction of the semiconductor layers of the epitaxial semiconductor layer sequence. According to a further embodiment, the functional semiconductor wafer is provided with the semiconductor body comprising a distance holder structure that is buried in the semiconductor body. Particularly preferably, the distance holder structure is arranged, along an arrangement direction of the semiconductor layers of the epitaxial semiconductor layer sequence, between the growth substrate and at least several layers of the epitaxial semiconductor layer sequence. Particularly, the method for manufacturing a plurality of semiconductor chips comprises the steps:- providing a functional semiconductor wafer comprising asemiconductor body on a growth substrate, wherein the semiconductor body comprises an epitaxial semiconductor layer sequence with a plurality of chip regions and a distance holder structure buried in the semiconductor body, and- removing the growth substrate.The distance holder structure can comprise a ring-likestructure in the edge region surrounding the central region.Thus, in plan view, the ring-like structure surrounds and, preferably, encloses the central region. Furthermore, the distance holder structure can comprise at least one distance holder element arranged in the central region. Consequently, the distance holder structure can comprise, arranged in a plane that is parallel to the main extension plane of the functional semiconductor wafer and, in particular, of the growth substrate, the ring-like structure that surrounds the2023P01085WO February 5, 2025P2023,1293 WO N -5 –at least one distance holder element. Preferably, the distance holder structure comprises more than one distance holder element arranged in the central region. Particularly preferably, the distance holder structure comprises a plurality of separate distance holder elements. In otherwords, the distance holder elements are arranged separatelyfrom each other. In particular, the distance holder elements can be formed as columns penetrating through a part of the semiconductor body. Since the distance holder structure is buried in the semiconductor body, in the functional semiconductor wafer each of the distance holder elements can be completely enclosed by semiconductor material of the semiconductor body. The distance holder elements can preferably be formed, in plan view, between neighboring chip regions. In other words, each of the distance holder elementscan be arranged, in plan view, between two chip regions inthe central region of the functional semiconductor wafer. According to a further embodiment, the distance holderstructure comprises or consists of a dielectric material. Forexample, an oxide or a nitride or a polymer can be used as dielectric material. As an oxide silicon oxide can besuitable, while silicon nitride can be suitable as a nitride.As a polymer a photoresist can be used. In particular, the distance holder structure can be deposited using a non- epitaxial method. For instance, the distance holder structure can be deposited by sputtering or physical vapor deposition(PVD) or a sol-gel process. The distance holder structure canbe formed by disposing a complete layer that is afterwards patterned to form the ring-like structure and the at least one distance element. Alternatively, the distance holderstructure can be formed in a patterned way by disposing the2023P01085WO February 5, 2025P2023,1293 WO N -6 –material of the distance holder structure through one or more masks. For example, at least a first semiconductor layer can be grown on the growth substrate. Here and in the following,“growing” a semiconductor layer or material can, inparticular, mean epitaxially growing the semiconductor layer or material. After growing the first semiconductor layer, the first semiconductor has a top surface opposite to the growthsubstrate. On the top surface of the first semiconductorlayer, the distance holder structure can be deposited. Thering-like structure and the at least one distance holderelement of distance holder structure can cover first regionson the top surface, whereas one or more second regions of the top surface can remain free from the distance holderstructure. Afterwards, one or more semiconductor layers canbe grown, in particular on the one or more second regions ofthe top surface. In other words, after forming the distance holder structure, the growth process can be continued, wherein the growth of the semiconductor material is firstcontinued in all regions that are not covered by the distanceholder structure. When the semiconductor material projects above the distance holder structure, the distance holder structure can be overgrown by the semiconductor material. By this re-growing process that distance holder structure can be covered and, thus, buried in the semiconductor body. According to a further embodiment, the growth substrate can be separated from the epitaxial semiconductor layer sequence.A gap can be formed between the epitaxial semiconductor layersequence and the growth substrate. The gap between the epitaxial semiconductor layer sequence and the growth substrate can preferably have a thickness of equal to or2023P01085WO February 5, 2025P2023,1293 WO N -7 –greater than 20 nm or equal to or greater than 25 nm or equal to or greater than 30 nm or equal to or greater than 40 nm orequal to or greater than 50 nm along a directionperpendicular to the main extension plane of the functional semiconductor wafer. Furthermore, the gap can have athickness of equal to or less than 1000 nm or equal to orless than 800 nm or equal to or less than 500 nm or equal to or less than 100 nm along a direction perpendicular to the main extension plane of the functional semiconductor wafer. For example, the gap can have a thickness of about 50 nmaccording to a preferred embodiment. Particularly, the gapcan be formed by at least partly removing at least one semiconductor layer of the semiconductor body. Preferably, at least one semiconductor layer is completely removed when thegap is formed. In particular, the gap can be formed in thatregion of the semiconductor body where the distance holderstructure is buried. Preferably, the distance holder structure reaches through the at least one semiconductor layer that is at least partly removed. Consequently, after forming the gap, the distance holder structure can reachthrough and, thus, bridge the gap. The gap can preferablydivide the semiconductor body in two parts that are mechanically connected to each other by the distance holderstructure only. Thus, after forming the gap, the distanceholder structure can mechanically connect the growthsubstrate to the epitaxial semiconductor layer sequence. Inother words, the distance holder structure can hold the growth substrate and the epitaxial semiconductor layersequence together after the gap has been formed.Consequently, a first side of the distance holder structure facing the growth substrate can be buried in a first semiconductor layer disposed on the growth substrate. A second side of the distance holder structure facing the2023P01085WO February 5, 2025P2023,1293 WO N -8 –epitaxial semiconductor layer sequence can be buried in a second semiconductor layer of that part of the semiconductor body that comprises the epitaxial semiconductor layer sequence.According to a further embodiment, the gap is formed byelectrochemically etching (ECE), in particular by electrochemical etching of a sacrificial layer that is a partof the semiconductor body and that can be arranged betweenthe epitaxial semiconductor layer sequence and the growthsubstrate. The distance holder structure can reach throughthe sacrificial layer. Preferably, the sacrificial layerextends completely over the growth substrate except thoseregions where the distance holder structure is present. Thus, that the sacrificial layer extends completely over the growth substrate can in particular mean that the sacrificial layer extends, in plan view, over the growth substrate except for those regions where the distance holder structure is located. For example, the sacrificial layer can be arranged in directcontact with the growth substrate and particularly preferablycan also be epitaxially grown on the growth substrate. Alternatively, at least one further semiconductor layer can be arranged between the sacrificial layer and the growth substrate. Preferably, the epitaxial semiconductor layer sequence is arranged on or over the sacrificial layer and is, for example, epitaxially grown on or over the sacrificial layer. By electrochemically etching the sacrificial layer, the sacrificial layer can be dissolved and removed from the semiconductor body and, thus, from the functionalsemiconductor wafer such that the gap is generated.Particularly, the distance holder structure is not dissolved and removed during electrochemical etching of the sacrificial layer.2023P01085WO February 5, 2025P2023,1293 WO N -9 –For electrochemical etching, the functional semiconductor wafer can be arranged in an electrochemical etchant and an ECE voltage can be applied between a first ECE contact on the functional semiconductor wafer and a second ECE contact within the electrochemical etchant. When the ECE voltage is applied the sacrificial layer is dissolved. According to a further embodiment, the sacrificial layer comprises or consists of a highly n-doped semiconductor material, particularly of a highly n-doped nitride semiconductor compound material. Particularly, a highly n- doped nitride semiconductor compound material has a higher etching rate in the electrochemical etchant than a lower n- doped or an undoped nitride semiconductor compound material. Particularly, the active zone of the chip regions is low doped, non-doped or only unintentionally doped. Therefore, the sacrificial layer comprising the highly n-doped semiconductor material can be electrochemically etched against the chip regions. Particularly, the highly n-doped semiconductor material has a dopant concentration of at least 1018 / cm3. According to a further embodiment, after forming the gap the distance holder structure can be removed in a further step, for example, by etching. In case the distance holder structure comprises or consists of silicon dioxide, for instance HF can be used for etching the distance holder structure. In case the distance holder structure comprises or consists of a polymer, a solvent can be used for removing the distance holder structure.2023P01085WO February 5, 2025P2023,1293 WO N -10 –When the distance holder structure is removed, the growth substrate is not connected to the epitaxial semiconductor layer sequence anymore, so that the growth substrate can bephysically separated from the epitaxial semiconductor layersequence by the formation of the gap and the subsequent removal of the distance holder structure. Consequently, in the method described herein the growth substrate can be separated and removed from the epitaxial semiconductor layer sequence in a controlled manner with the help of the distance holder structure. Particularly, the removal of the growth substrate takes place in at least two different steps. First, the sacrificial layer is removed in a first step. After removal of the sacrificial layer, the growth substrate isseparated from the epitaxial semiconductor layer sequence ofthe semiconductor body, but still fixed to the functionalsemiconductor wafer by the distance holder structure. Thus,the distance holder structure prevents sticking of the growthsubstrate to the functional semiconductor wafer in anuncontrolled manner. Then, the growth substrate is finallyremoved in a second step by removing the distance holderstructure. The method described herein can enhance theproduction reliability and prevent damage to the chip regionsduring manufacturing. According to a further embodiment, electrochemical etching of the sacrificial layer and / or etching of the distance holderstructure can be carried out through etching channelspenetrating partially through the functional semiconductorwafer. Particularly, the etching channels are arranged between the chip regions and extend perpendicular to the main extension plane. The etching channels can have any geometry. For example, the etching channels can have, in plan view on the functional semiconductor wafer, a round, in particular a2023P01085WO February 5, 2025P2023,1293 WO N -11 –circular, cross-section or a cross-formed cross-section. Alateral distance between two directly adjacent etching channels can be equal to or greater than 100 µm and equal to or less than 1 mm. For instance, the etching channels can be arranged, in plan view, in a square matrix with rows and columns. The lateral distance of directly adjacent row and columns, respectively, can also be denoted as pitch. Preferably, the pitch can be 500 µm. A size, for instance adiameter, of the round or cross-like cross-section can beequal to or greater than 10 µm and equal to or less than 100 µm, preferably 20 µm. Particularly preferably, the distance between two directly adjacent etching channels, for instance the pitch, is at least twice the size of the etching channels. Particularly, at least several etching channels penetratethrough the growth substrate and the sacrificial layer suchthat the sacrificial layer is accessible through the etchingchannels. Furthermore, at least one etching channel can penetrate through a distance holder element of the distance holder structure. An etching channel penetrating a distance holder element can facilitate etching the distance holder element, since etchant for etching the distance holder structure can flow through that etching channel directly to the distance holder element. Preferably, each of the distance holder elements is penetrated by an etching channel. In particular, several but not all etching channels can penetrate a distance holder element. Consequently, a first group of the etching channels can reach into the semiconductor body without penetrating the distance holder elements, whereas a second group of etching channels penetrates the distance holder elements. The first group of etching channels can be provided for the electrochemical2023P01085WO February 5, 2025P2023,1293 WO N -12 –etching of the sacrificial layer, whereas the second group of etching channels can be provided for etching the distance holder elements. According to a further embodiment, the distance holder structure and, in particular, the ring-like structure of the distance holder structure acts as an etch stop element. For instance, the distance holder structure acts as an etch stopelement during electrochemical etching of the sacrificiallayer. After the formation of the gap, the ring-likestructure of the distance holder structure arranged in theedge region of the functional semiconductor wafer can befreely accessible through the etching channels and the gap. According to a further embodiment, the growth substrate is thinned prior to the generation of the etching channels. This has the advantage that the material to be penetrated for forming the etching channels is reduced. In such a way the etching channels can, for example, be formed by reactive ionetching (RIE) in a timely manner. For instance, the distanceholder structure can act as an etch stop element during RIE.For example, after thinning the growth substrate has a thickness equal to or less than 50 µm or equal to or less than 20 µm or equal to or less than 15 µm. According to a further embodiment, the functionalsemiconductor wafer is bonded to a carrier wafer prior to theremoval of the growth substrate such that a wafer compound isformed. Particularly, the functional semiconductor wafer isbonded to the carrier wafer before the sacrificial layer isremoved. The carrier wafer comprises, for example, asemiconductor material such as silicon, germanium or gallium nitride. Particularly, the etching channels are generated2023P01085WO February 5, 2025P2023,1293 WO N -13 –after bonding the functional semiconductor wafer to thecarrier wafer. Also, thinning of the growth substratepreferably is carried out after bonding the carrier wafer tothe functional semiconductor wafer. For example, bonding is achieved by connecting a metal layer on or over the carrier wafer with a further metal layer on or over the functionalsemiconductor wafer. Particularly, the carrier wafer has thesame diameter as the functional semiconductor wafer.The carrier wafer is particularly configured and intended tobe part of the finished semiconductor chips and mechanicallystabilizes the epitaxial semiconductor layer sequence in thefinished semiconductor chip. Furthermore, the carrier wafercan be used as an electrical contact during electrochemical etching the sacrificial layer. Furthermore, prior to bonding the carrier wafer to the functional semiconductor wafer, at least one electrical via can provided that reaches from the surface to be facing the carrier wafer into the semiconductor body. In particular, the epitaxial semiconductor layer sequence can comprise an active layer and at least one electrical via is provided that reaches, after bonding the carrier wafer to the functional semiconductor wafer, from the carrier wafer through the active layer. In particular, the method described herein can be suitablefor manufacturing nitride-based devices such as lasers,light-emitting diodes (LED), solar cells, integratedcircuits, sensor and others. Consequently, for examplesemiconductor chips embodied as an edge-emitting laser deviceor a vertical cavity surface emitting laser (VCSEL) can bemanufactured. Furthermore, light-emitting diode (LED) chips,particularly, ultra-violet (UV) LED chips can be manufactured.2023P01085WO February 5, 2025P2023,1293 WO N -14 –The semiconductor chips manufactured with the describedmethod can be used in applications related to automotive,lighting, display, visualization, sensing and others. Thesemiconductor chips manufactured with the method can be used, for example, in augmented reality applications as well as in a micro-AFS (microstructured adaptive front lighting system). Further advantages, advantageous embodiments and furtherdevelopments are revealed by the embodiments described belowin connection with the figures.Figures 1 to 16 show schematic illustrations of steps of amethod for manufacturing a plurality of semiconductor chipsaccording to an embodiment. Figures 17 and 18 show schematic illustrations of a functional semiconductor wafer used in a method for manufacturing a plurality of semiconductor chips according to further embodiments.Figures 19 to 29 show schematic illustrations of steps of amethod for manufacturing a plurality of semiconductor chipsaccording to a further embodiment. In the embodiments and figures, identical, similar or identically acting elements are provided in each case with the same reference numerals. The elements illustrated and their size ratios to one another should not be regarded asbeing to scale, but rather individual elements, such as forexample layers, components, devices and regions, may have been made exaggeratedly large to illustrate them better and / or to aid comprehension.2023P01085WO February 5, 2025P2023,1293 WO N -15 –According to the method of the exemplary embodiment ofFigures 1 to 16, a functional semiconductor wafer 10 isprovided as indicated in Figure 5. Figures 1 to 5 show stepsfor manufacturing the functional semiconductor wafer 10. Thefunctional semiconductor wafer 10 comprises a growthsubstrate 1, onto which a semiconductor body 2 with anepitaxial semiconductor layer sequence 20 is arranged. Theepitaxial semiconductor layer sequence 20 comprises aplurality of chip regions 3 which are indicated in Figures 5to 16 by dashed lines.As indicated in Figure 1, the growth substrate 1 is provided.For instance, the growth substrate 1 can be a GaN substratewith a diameter of 2 inches. Onto the growth substrate 1 afirst semiconductor layer 21 is grown. In particular, thefirst semiconductor layer 21 can be an unintentionally doped or low doped gallium nitride layer that can be directly grownon a growing surface of the growth substrate 1.Alternatively, at least one further semiconductor layer can be grown on the growth substrate 1 before said first semiconductor layer 21 is grown.After growing the first semiconductor layer 21, the firstsemiconductor layer 21 has a top surface that is directedopposite to the growth substrate 1. On the top surface of thefirst semiconductor layer 21, a distance holder structure 4is deposited as indicated in Figure 2.The distance holder structure 4 comprises or consists of adielectric material such as an oxide or a nitride or apolymer. The distance holder structure 4 can be deposited by sputtering or physical vapor deposition (PVD) or a sol-gel2023P01085WO February 5, 2025P2023,1293 WO N -16 –process and can be formed by disposing a complete layer that is afterwards patterned to form structures as described in the following. Alternatively, the distance holder structure 4 can be formed in a patterned way by a mask-based depositionprocess. By way of example, in the shown embodiment thedistance holder structure 4 is formed by depositing SiO2.The distance holder structure 4 comprises a ring-likestructure 41 in an edge region 11 surrounding a centralregion 12. Thus, in plan view, the ring-like structure 41surrounds and, preferably, encloses the central region 12.Furthermore, the distance holder structure 4 comprises at least one distance holder element 42 arranged in the centralregion 12. Preferably, the distance holder structure 4comprises more than one distance holder element 42 arrangedin the central region 12 as indicated in Figure 2. The number of distance holder elements 42 shown in the figures is only purely exemplary and not limiting. The distance holderelements 42 are arranged island-like, i.e. separately fromeach other, and can be formed as columns. The distance holderelements 42 can preferably be formed, in plan view, betweenneighboring chip regions 3 as indicated in Figure 5. In otherwords, each of the distance holder elements 42 can bearranged, in plan view, at the interface between two adjacentchip regions 3 in the central region 12 of the functionalsemiconductor wafer 10. Consequently, the distance holderstructure 4 comprises island-like elements forming thedistance holder elements 42 disposed in the central region 12at interfaces of some adjacent chip regions 3. The distanceholder elements 42 can have, for instance, a circular cross-section and, thus, can be formed as circular cylinders. Other shapes like, for instance, polygonal cross-sections are also possible.2023P01085WO February 5, 2025P2023,1293 WO N -17 –In further steps, the distance holder structure 4 is buried in the semiconductor body 2 that is formed on the growthsubstrate 1. As described in the following, each of thedistance holder elements 42 will be completely enclosed bysemiconductor material of the semiconductor body 2.As can be understood from Figure 2, the ring-like structure41 and the at least one distance holder element 42 of the distance holder structure 4 cover first regions on the topsurface of the first semiconductor layer 21, whereas one ormore second regions of the top surface remain free from the distance holder structure. As indicated in Figure 3, a re- growth process can be initiated in order to continue the growth of the first semiconductor layer 21in the one or more second regions. Alternatively or additionally, anothersemiconductor layer as, for instance, an n-dopedsemiconductor layer (not shown) can be grown in the one ormore second regions on the first semiconductor layer 21.As shown in Figure 4, a sacrificial layer 22 comprising ahighly n-doped semiconductor material is grown on or over thefirst semiconductor layer 21. In particular, the sacrificiallayer 22 has a thickness small enough so that the distanceholder structure 4 protrudes from the sacrificial layer 22.Afterwards, an etch stop layer 23 can be grown on thesacrificial layer 22. Preferably, the etch stop layer 23 hasa thickness small enough so that the distance holder structure 4 also protrudes from the etch stop layer 23.The etch stop layer 23 preferably comprises or consists ofAlN or AlInN. The etch stop layer 23 is configured to stopelectrochemical etching of the sacrificial layer 22.2023P01085WO February 5, 2025P2023,1293 WO N -18 –Particularly, the etch stop layer 23 has an etching rate in an electrochemical etchant for etching the sacrificial layer22 that is lower than the etching rate of the sacrificiallayer 22 during the electrochemical etching.As mentioned before, the distance holder structure 4 is preferably higher than the layers grown in the steps according to Figures 3 and 4, so that the distance holder structure can project from the semiconductor layers grown in the steps according to Figures 3 and 4. Furthermore, as shown in Figure 5, the epitaxial semiconductor layer sequence 20 is grown as further part ofthe semiconductor body 2 on the growth substrate 1. Theepitaxial semiconductor layer sequence 20 comprises at leastone n-doped semiconductor layer 24 and at least one p-dopedsemiconductor layer 25. An active layer 26 comprising orforming an active zone is arranged therebetween and can beformed as a conventional pn junction, a doubleheterostructure, a single quantum well structure (SQW structure) or a multiple quantum well structure (MQWstructure) for generating light.Additionally, between the etch stop layer 23 and the at leastone n-doped semiconductor layer 24 a second semiconductorlayer 27 formed by an unintentionally doped or low doped gallium nitride layer can be grown. Preferably, the secondsemiconductor layer 27 overgrows the distance holderstructure as indicated in Figure 5, so that the distanceholder structure 4 is buried in the semiconductor body 2.Alternatively, the n-doped semiconductor layer 24 can overgrow the distance holder structure 4.2023P01085WO February 5, 2025P2023,1293 WO N -19 –The functional semiconductor wafer 10 is further processed starting from the top surface of the at least one p-dopedsemiconductor layer 25, as shown in Figure 6. For example, p-contact layers 5, for instance comprising or consisting of atransparent conductive oxide like indium tin oxide, and firstmirror layers 6, for instance as part of a resonator of aVCSEL, can be applied on or over the top surface of at leastone p-doped semiconductor layer 25. For the sake of clarity,only in one of the chip regions 3 layers 5 and 6 are denotedwith reference numerals. Then, a first metal layer 7 isapplied on or over the functional semiconductor wafer. The first metal layer 7, which can be a single layer or a layerstack comprising two or more metal layers, preferably coversthe functional semiconductor wafer 10 completely. Furthermore, further structures of semiconductor chips, if desired, can be formed. In particular, all process steps for forming structures in the chip regions, the chip regions corresponding to semiconductor chips after a singulationprocess as described below, can be carried out on waferlevel, for example process steps for forming mesas, contacts, reflectors like distributed Bragg reflectors, mentalizations and other structures.In a next step, as indicated in Figure 7, a carrier wafer 50,for example comprising or consisting of a electrically conductive material like gallium nitride, silicon orgermanium, is provided. Particularly preferably, the carrierwafer 50 has the same diameter as the functionalsemiconductor wafer 10. A metal layer 51 is arranged on afront side of the carrier wafer 50, wherein the front side ofthe carrier wafer 50 is that side of the carrier wafer 50 that is facing the functional semiconductor wafer 10 after the carrier wafer 50 has been bonded to the functional2023P01085WO February 5, 2025P2023,1293 WO N -20 –semiconductor wafer 10. The metal layer 51 preferablycompletely covers the front side of the carrier wafer 50. Afurther metal layer 52 can be formed on the backside of thecarrier wafer 50, wherein the backside of the carrier wafer50 is opposite to the front side and wherein the furthermetal layer 52 can completely or only partially cover thebackside of the carrier wafer 50. The further metal layer 52can be configured for being used as electrical contact during electrochemical etching as explained further below.In a further step indicated in Figure 8, the carrier wafer 50and the functional semiconductor wafer 10 are bonded togethervia the first metal layer 7 of the functional semiconductorwafer 10 and the metal layer 51 on the front side of thecarrier wafer 50. In this way, a mechanically stable wafercompound 90 comprising the carrier wafer 50 and thefunctional semiconductor wafer 10 is generated.As shown in Figure 9, the growth substrate 1 can be thinned,for example by grinding or polishing, such that a remainingthickness of the growth substrate is for example equal to orless than 50 µm or equal to or less than 20 µm.In a next step, as shown in Figure 10, etching channels 30are introduced in the functional semiconductor wafer 10 thatpartially penetrate the functional semiconductor wafer 10.The etching channels 30 are, for example, formed by reactiveion etching (RIE). In particular, the etching channels 30penetrate the functional semiconductor wafer 10 starting fromthe growth substrate 1. The etching channels 30 penetrate thegrowth substrate 1, the first semiconductor layer 21 and,particularly, the sacrificial layer 22 such that thesacrificial layer 22 is freely accessible from the backside2023P01085WO February 5, 2025P2023,1293 WO N -21 –of the growth substrate 1 that is remote from thesemiconductor body 2. As can be seen in Figure 10, theetching channels 30 preferably extend beyond the sacrificiallayer 22 to open the sacrificial layer 22 to an etchant forremoving the sacrificial layer 22.The etching channels 30 are arranged in the central region 12of the functional semiconductor wafer 10. The edge region 11of the functional semiconductor wafer 10 can be free ofetching channels. Particularly, the etching channels 30 arearranged between chip regions 3 and extend perpendicular tothe main extension plane of the functional semiconductorwafer 10. Furthermore, at least one etching channel 30 canpenetrate through a distance holder element 42 of thedistance holder structure 4. Preferably, each of the distanceholder elements 42 is penetrated by an etching channel 30. Inparticular, several but not all etching channels 30 canpenetrate a distance holder element 42. Consequently, a firstgroup of the etching channels 30 can reach into thesemiconductor body 2 without penetrating the distance holderelements 42, whereas a second group of etching channels 30penetrates the distance holder elements 42.A sealing ring 99 can be placed on the growth substrate asindicated in Figure 11. Particularly, the sealing ring 99 ispositioned so that all etching channels 30 are enclosed by the sealing ring 99 when viewed in plan view. For instance, the sealing ring 99 can overlap with the ring-like structure41 of the distance holder structure 4 in the edge region 11in plan view or can, as shown in Figure 11 be placed in thecentral region 12 around all etching channels 30.2023P01085WO February 5, 2025P2023,1293 WO N -22 –The carrier wafer 50 is used as a first ECE contact that canbe electrically connected to a voltage source via the furthermetal layer 52 on the backside. A second ECE contact (notshown) connected to the voltage source is placed togetherwith the wafer compound 99 in an electrochemical etchant (notshown) that can access through the etching channels 30 asindicated by arrows E in Figure 11. As an electrochemicaletchant, for example, a 0.3 molar nitridic acid can be used.An ECE voltage V is applied between the first ECE contact andthe second ECE contact. In Figure 12 the ECE current flowingthrough the epitaxial semiconductor layer sequence 20 to thesacrificial layer 22 is indicated by arrows C.As a result, the sacrificial layer is dissolved and removed as indicated in Figure 13. The surrounding ring-like structure 41 of the distance holder structure 4 acts as an etch stop element during electrochemical etching of thesacrificial layer 22 and prevents the flow of etchant inlateral direction parallel to the main extension plane of thefunctional semiconductor wafer 10. Furthermore, the etch stoplayer 23 can prevent significant electrochemical etching in a vertical direction perpendicular to the lateral direction.After removal of the sacrificial layer 22 by electrochemicaletching the growth substrate 1 and the first semiconductorlayer 21 form a structure 91 that is still mechanicallyconnected to the epitaxial semiconductor layer 20 sequence bythe distance holder structure 4.A gap 31 is generated between the epitaxial semiconductorlayer sequence 20 and the structure 91 comprising the growthsubstrate 1 due to the removal of the sacrificial layer 22.The distance holder structure 4 reaches through the gap 31,2023P01085WO February 5, 2025P2023,1293 WO N -23 –wherein a first side of the distance holder structure 4facing the growth substrate 1 is buried in the firstsemiconductor layer 21 disposed on the growth substrate 1 anda second side of the distance holder structure 4 facing theepitaxial semiconductor layer sequence 20 is buried in thesecond semiconductor layer 27 of that part of thesemiconductor body 2 that comprises the epitaxialsemiconductor layer sequence 20.In order to separate the structure 91 comprising the growthsubstrate 1 from the epitaxial semiconductor layer sequence20, the distance holder structure 4 is removed by wetetching, in particular by HF wet etching. The etchant for thewet etching can also enter through the etching channels 30.After the distance holder structure 4 is removed, as can be seen in Figure 14, the structure comprising the growthsubstrate is completely loose, as indicated in Figure 14, andcan drop off inside the etchant, as indicated in Figure 15. Consequently, the growth substrate 1 can completely fall off and the n-side of the epitaxial semiconductor layer sequence 20 is now accessible.Furthermore, as shown in Figure 16, further processing of then-side of the epitaxial semiconductor layer sequence 20 is carried out, for instance providing reflectors like distributed Bragg reflectors, mesas, electrical contacts etcetera. In the shown embodiment, further mirror layers 8 areapplied to the now accessible side of the chip regions 3 inorder to form, together with the mirror layers 6, resonatorsof finished semiconductor chips embodied as VCSELs.Furthermore, n-contacts 9, particularly made from a metal,are inserted in the epitaxial semiconductor layer sequence 20for electrical contact of the at least one n-doped2023P01085WO February 5, 2025P2023,1293 WO N -24 –semiconductor layer 24 of the epitaxial semiconductor layersequence 20.In a further step, the chip regions 3 are separated in asingulation process along the indicated separation linesrunning between the chip regions 3. Preferably, thesingulation process results in removing the remains of theetching channels and the regions where the distance holderstructure was arranged. During separation, the layers of thewafer compound are separated in single sections, wherein oneof said sections is indicated by the dotted lines and whereineach section is part of a finished semiconductor chip 100.Figure 17 shows a plan view of a functional semiconductorwafer 10 of a wafer compound generated during a methodaccording to an exemplary embodiment. Particularly, thecentral region 12 of the functional semiconductor wafer 10comprises etching channels 30 that are formed as holesdistributed over the central region 12. As described above,several etching channels 30 penetrate the distance holderelements 42. For instance, the etching channels 30 can bearranged in a square or rectangular matrix array, wherein forinstance every second etching channel 30 or every thirdetching channel 30 or every fourth etching channel 30 goesthrough a distance holder element 42. Each etching channel 30is electrically connected to the ECE contact formed by the carrier wafer via the epitaxial semiconductor layer sequence. As described above, the ring-like structure 41 of thedistance holder structure 4 in the edge region 11 forms aclosed ring around the central region 12.A distance between two directly adjacent etching channels 30is, for example, equal to or greater than 100 µm and equal to2023P01085WO February 5, 2025P2023,1293 WO N -25 –or less than 1 mm, preferably 500 µm. A width W of an etchingchannel 30 is, for example, equal to or greater than 10 µmand equal to or less than 100 µm, preferably 20 µm. As shown in Figure 17, the etching channels 30 can have a round, for instance circular cross-section. However, other shapes of cross-sections are possible, for instanceelliptical, square or rectangular cross-sections, or morecomplex shapes as, for instance, polygonal shapes like crosses as indicated in Figure 18.Figures 19 to 29 shows method steps of a modification of themethod for manufacturing a plurality of semiconductor chips according to a further embodiment. Figure 19 shows a method step that follows the growth ofepitaxial semiconductor layer sequence 20 as described inconnection with Figures 1 to 5 and corresponds to the step shown in Figure 6. As explained in connection with Figure 6, contact layers 5 and mirror layers 6 are deposited on the epitaxial semiconductor layer sequence 20. Additionally, inat least one and, preferably, in several chip areas 3, forinstance in 5% or less or in 2% or less or in 1% or less ofthe chip areas 3, an opening is formed that reaches from thep-side to the n-side and that is filled with the p-metalcontact material, thereby forming electrical via regions withan electrical via 60 reaching from the p-side to the n-sideof the epitaxial semiconductor layer sequence 20.The method steps shown in Figures 20 to 25 correspond to thesteps explained in connection with Figures 7 to 12. However,as can be seen in Figure 25, due to the electrical via(s) 60,the active layer 26 is short circuited and the ECE current C2023P01085WO February 5, 2025P2023,1293 WO N -26 –can be directly injected into the n-side of the epitaxialsemiconductor layer sequence 20, so that the active layer26can be protected. The method steps shown in Figures 26 to 29 correspond to thesteps explained in connection with Figures 13 to 16. Afterthe singulation, the chip regions 3 with the electrical vias60 regions are discarded.The method described herein is focused on the complete de-attachment of the growth substrate, preferably by a two-stepetching process without any necessary post treatment. A key aspect lies in the introduction of the distance holderstructure within the semiconductor body and the re-growth ofsemiconductor layers after deposition of the distance holderstructure. The distance holder structure is configured forholding the growth substrate and for preventingunintentionally bending and / or cracking due to stress issues,for instance caused by a mismatch of the coefficients ofthermal expansion of the growth substrate and the carrierwafer. The method can provide a complete de-attachment of thegrowth substrate due to a wet chemical process, whereas thedistance holder structure can provide an etch stop, so noadditional lateral etch stop is required. Furthermore, thefull wafer surface of the growth substrate can be used for the formation of semiconductor chips.In particular after finishing the ECE, the wet etching of thedistance holder structure can lead to a spontaneous releaseof the growth substrate. Also, there is no requirement for acircular peripheral etching from the backside to define theborder for a falling area of the growth wafer or a circulardielectric deposition of a circular etch stop.2023P01085WO February 5, 2025P2023,1293 WO N -27 –The method described herein can be easily scalable. Due to the complete release of the growth substrate the growthsubstrate can be re-used.Consequently, the method can provide the following features and advantages:- Introduction of the distance holder structure within thesemiconductor body.- Formation of a nano-structured distance holder structureas a distance holder to hold the growth substrate.- The distance holder structure can prevent the breakingand / or sticking of wafers and / or of the semiconductor body.- The distance holder structure can serve as an etch stopidentification layer. In particular, the distance holder structure in the edge region and, thus, at the periphery of the wafer, can prevent a lateral flow of the ECE etchant.- There are no circular and / or ring-shaped etching channelsnecessary, and there is no need for an edge exclusionspace, so that the complete wafer surface can be used for chip development, which can maximize the number of chips per wafer.- The method is a easily controllable process.- A backside ECE contact can be used.- No post treatment like thinning is required to remove thegrowth substrate. The features and embodiments described in connection with the figures can also be combined with one another according to further embodiments, even if not all such combinations are explicitly described. Furthermore, the embodiments described2023P01085WO February 5, 2025P2023,1293 WO N -28 –in connection with the figures can alternatively or additionally have further features according to the description in the general part. The invention is not limited by the description based on the embodiments to these embodiments. Rather, the invention includes each new feature and each combination of features, which includes in particular each combination of features in the patent claims, even if this feature or this combination itself is not explicitly explained in the patent claims or embodiments.

[0002] 2023P01085WO February 5, 2025P2023,1293 WO N -29 –Reference list1 growth substrate2 semiconductor body3 chip region4 distance holder structure5 contact layer6 mirror layer7 first metal layer8 mirror layer9 contact10 functional semiconductor wafer11 edge region12 central region20 epitaxial semiconductor layer sequence21 first semiconductor layer22 sacrificial layer23 etch stop layer24 n-doped semiconductor layer25 p-doped semiconductor layer26 active layer27 second semiconductor layer30 etching channel31 gap41 ring-like structure42 distance holder element50 carrier wafer51 metal layer52 metal layer60 electrical via90 wafer compound91 structure99 sealing ring2023P01085WO February 5, 2025P2023,1293 WO N -30 –E etchant entering

Claims

2023P01085WO February 5, 2025P2023,1293 WO N -31 –Claims 1. Method for manufacturing a plurality of semiconductor chips (100), comprising the steps:- providing a functional semiconductor wafer (10) comprisinga semiconductor body (2) on a growth substrate (1),wherein the semiconductor body (1) comprises anepitaxial semiconductor layer sequence (20) with aplurality of chip regions (3) and a distance holderstructure (4) buried in the semiconductor body (2), and- removing the growth substrate (1).

2. Method according to claim 1, wherein the distance holder structure (4) comprises a ring-like structure (41)adjoining an edge of the growth substrate (1)surrounding a central region (12).

3. Method according to claim 2, wherein the distance holder structure (4) comprises distance holder elements (42)arranged in the central region, wherein the distance holder elements are formed as columns penetrating through a part of the semiconductor body (2).

4. Method according to claim 3, wherein the distance holder elements (42) are formed between neighboring chipregions (3).

5. Method according to any of the preceding claims, whereinthe distance holder structure (4) comprises a dielectricmaterial.2023P01085WO February 5, 2025P2023,1293 WO N -32 –6. Method according to any of the preceding claims, wherein agap (31) is formed between the epitaxial semiconductorlayer sequence (20) and the growth substrate (1).

7. Method according to claim 6, wherein the gap (31) isformed by at least partly removing at least one semiconductor layer of the semiconductor body (2).

8. Method according to claim 6 or 7, wherein the distance holder structure (4) reaches through the gap (31) andmechanically connects the growth substrate (1) with theepitaxial semiconductor layer sequence (20) afterforming the gap (31).

9. Method according to any of the claims 6 to 8, wherein, after forming the gap (31), the growth substrate (1) is removed by etching the distance holder structure (4).

10. Method according to any of the preceding claims, whereinthe gap (31) is formed by electrochemical etching asacrificial layer (22) of the semiconductor body (2).

11. Method according to claim 10, wherein the electrochemicaletching of the sacrificial layer (22) is carried out through etching channels (30) penetrating partially through the functional semiconductor wafer (10).

12. Method according to claim 11, wherein at least one etching channel (30) penetrates through a distanceholder element (42) of the distance holder structure(4).2023P01085WO February 5, 2025P2023,1293 WO N -33 –< / sub>13. Method according to claim 11 or 12, wherein the etching channels (30) have, in plan view on the functionalsemiconductor wafer (10), a round cross-section or across-like cross-section.

14. Method according to any of the claims 11 to 13, wherein the growth substrate (1) is thinned prior to forming the etching channels (30).

15. Method according to any of the claims 10 to 14, whereinthe distance holder structure (4) acts as an etch stopelement.

16. Method according to any of the preceding claims, wherein,prior to the removal of the growth substrate (1), the functional semiconductor wafer (10) is bonded to a carrier wafer (50) such that a wafer compound (90) is formed.

17. Method according to claim 16 with reference to any of the claims 10 to 15, wherein the carrier wafer (50) is used as an electrical contact during electrochemical etchingthe sacrificial layer (22).

18. Method according to claim 16 or 17, wherein the epitaxial semiconductor layer sequence (20) comprises an activelayer (26) and at least one electrical via (60) thatreaches from the carrier wafer (50) through the activelayer (26).

19. Method according to any of the preceding claims, wherein, after removal of the growth substrate (1), individual2023P01085WO February 5, 2025P2023,1293 WO N -34 –semiconductor chips (100) are formed by a singulationprocess.

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