Method for manufacturing semiconductor device, and semiconductor device

Abstract

Provided is a method for manufacturing a semiconductor device that has a transistor having a large on-current. This method for manufacturing a semiconductor device includes: forming a crystalline metal oxide film on a layer; forming a mask layer on a first region of the metal oxide film; supplying a first element to the metal oxide film using the mask layer as a mask, thereby forming, on the metal oxide film, a second region that does not overlap the mask layer and contains the first element; and removing the second region by etching, thereby exposing the surface of the layer. The first element is a noble gas. The concentration of the first element in the second region is 1 × 1019 atoms / cm3 to 1 × 1023 atoms / cm3. The layer has a region that overlaps the second region and that contains the first element.

Description

Method for manufacturing semiconductor device and semiconductor device

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a manufacturing method of the above-described transistor, semiconductor device, or display device. Another object is to provide a highly productive manufacturing method of a transistor, semiconductor device, or display device. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] In one embodiment of the present invention, a crystalline metal oxide film is formed on a layer, a mask layer is formed on a first region of the metal oxide film, a first element is supplied to the metal oxide film using the mask layer as a mask, and a second region that does not overlap with the mask layer and contains the first element is formed in the metal oxide film, and the second region is removed by etching to expose a surface of the layer, the first element being a noble gas, and the concentration of the first element in the second region is 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ The method for manufacturing a semiconductor device includes the following steps, in which the layer overlaps with the second region and has a region containing a first element.

[0012] In one embodiment of the present invention, a crystalline metal oxide film is formed on a layer, a mask layer is formed on a first region of the metal oxide film, a first element is supplied to the metal oxide film using the mask layer as a mask, and a second region that does not overlap with the mask layer and has the first element is formed in the metal oxide film, impurities are diffused from the first region to the second region by heat treatment, and the second region is removed by etching to expose a surface of the layer, the first element is a noble gas, and the concentration of the first element in the second region is 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ The method for manufacturing a semiconductor device includes the following steps, in which the layer overlaps with the second region and has a region containing a first element.

[0013] In the above-described method for manufacturing a semiconductor device, the temperature of the heat treatment is preferably 200° C. or higher and 450° C. or lower.

[0014] In the above-described method for manufacturing a semiconductor device, the impurity is preferably one or more selected from the group consisting of hydrogen, carbon, and hydrocarbon.

[0015] In the above-described method for manufacturing a semiconductor device, the metal oxide film preferably contains indium.

[0016] In the above-described method for manufacturing a semiconductor device, the metal oxide film preferably contains indium and one or more elements selected from the group consisting of gallium, zinc, and tin.

[0017] In the above-described method for manufacturing a semiconductor device, the first element is preferably one or more selected from the group consisting of argon, krypton, and xenon.

[0018] In the above-described method for manufacturing a semiconductor device, the first element is preferably argon.

[0019] In the above-described method for manufacturing a semiconductor device, the first element is preferably supplied by ion implantation.

[0020] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, and a metal oxide layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The second conductive layer and the first insulating layer have an opening reaching the first conductive layer. The metal oxide layer has a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The first insulating layer has a first region overlapping with the metal oxide layer and a second region not overlapping with the metal oxide layer. The second region includes a first element. The concentration of the first element in the second region is higher than the concentration of the first element in the first region. The first element is one or more selected from argon, krypton, and xenon.

[0021] In the above-described semiconductor device, it is preferable that the second region does not overlap the second conductive layer.

[0022] The aforementioned semiconductor device preferably has a second insulating layer. The first conductive layer and the first insulating layer are preferably located on the second insulating layer. The first insulating layer preferably has a third insulating layer and a fourth insulating layer on the third insulating layer. The second insulating layer preferably contains nitrogen. The third insulating layer preferably contains nitrogen. The fourth insulating layer preferably contains oxygen.

[0023] According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a manufacturing method for the above-described transistor, semiconductor device, or display device can be provided. Alternatively, a highly productive manufacturing method for a transistor, semiconductor device, or display device can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0025] 1A to 1F are cross-sectional views showing an example of a semiconductor device. FIG. 2 is a flowchart showing an example of a manufacturing method of a semiconductor device. FIGS. 3A to 3D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 4 is a flowchart showing an example of a manufacturing method of a semiconductor device. FIGS. 5A to 5F are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 6 is a flowchart showing an example of a manufacturing method of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 8 is a flowchart showing an example of a manufacturing method of a semiconductor device. FIG. 9 is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. FIG. 10A is a top view showing an example of a semiconductor device. FIGS. 10B and 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A to 11D are perspective views showing an example of a semiconductor device. FIGS. 12A to 12C are cross-sectional views showing an example of a semiconductor device. FIGS. 13A to 13C are cross-sectional views showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a top view showing an example of a semiconductor device. FIG. 15B is a cross-sectional view showing an example of a semiconductor device. FIGS. 16A to 16C are cross-sectional views showing an example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing an example of a semiconductor device. FIGS. 18A to 18C are cross-sectional views showing an example of a semiconductor device. FIGS. 19A to 19C are diagrams illustrating structural examples of a transistor. FIGS. 20A to 20C are diagrams illustrating structural examples of a transistor. FIGS. 21A to 21C are diagrams illustrating structural examples of a transistor. FIGS. 22A to 22D are diagrams illustrating structural examples of a semiconductor device. FIGS. 23A to 23E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24A to 24D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 25A to 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26A to 26C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27 is a perspective view showing an example of a display device. FIGS. 28A and 28B are cross-sectional views showing an example of a display device. FIG. 29 is a cross-sectional view showing an example of a display device. FIGS. 30A to 30C are cross-sectional views showing an example of a display device.31A and 31B are cross-sectional views showing an example of a display device. FIG. 32 is a cross-sectional view showing an example of a display device. FIG. 33 is a cross-sectional view showing an example of a display device. FIG. 34 is a cross-sectional view showing an example of a display device. FIGS. 35A to 35D are views showing an example of an electronic device. FIGS. 36A to 36F are views showing an example of an electronic device. FIGS. 37A to 37G are views showing an example of an electronic device. FIG. 38 is a STEM image of a sample according to an example. FIGS. 39A and 39B are STEM images of a sample according to an example. FIGS. 40A and 40B are STEM images of a sample according to an example. FIGS. 41A and 41B are views showing XRD measurement results of a sample according to an example. FIGS. 42A and 42B are views showing XRD measurement results of a sample according to an example. FIG. 43A is a view showing ion concentrations according to an example. FIG. 43B is a view showing XRD measurement results of a sample according to an example. FIG. 43C is a view showing the correlation between ion concentrations and XRD measurement results according to an example.

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0027] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0028] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0029] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0030] In this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0031] The words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0034] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0035] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0036] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0037] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0038] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

[0039] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0040] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0041] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0043] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0044] In this specification, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0045] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0046] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer is physically separated from the adjacent metal oxide layer.

[0047] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0048] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (light-emitting devices) with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, thereby expanding the range of material and configuration options and facilitating improvements in brightness and reliability.

[0049] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0050] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element has a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer functioning as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0051] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0052] 1A shows a cross-sectional view of a semiconductor device 10 according to one embodiment of the present invention.

[0053] The semiconductor device 10 includes a layer 31 and a metal oxide layer 21 on the layer 31. The metal oxide layer 21 has a region in contact with the top surface of the layer 31.

[0054] The metal oxide layer 21 can be applied to, for example, one or more of a semiconductor layer of a transistor, an electrode of a transistor, an electrode of a capacitor, and a wiring. Examples of metal oxides contained in the metal oxide layer 21 include indium oxide (also referred to as indium oxide), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The crystallinity of the metal oxide contained in the metal oxide layer 21 is not particularly limited. The metal oxide layer 21 can be an amorphous, single-crystalline, microcrystalline, polycrystalline, or a mixture of two or more of these metal oxides.

[0055] When the metal oxide layer 21 is used as a semiconductor layer of a transistor, a metal oxide exhibiting semiconductor characteristics (also referred to as an oxide semiconductor (OS)) is used for the metal oxide layer 21. A transistor using an oxide semiconductor (hereinafter also referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. In addition, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device. Furthermore, the use of a crystalline metal oxide layer 21 as a semiconductor layer is preferable because it can suppress deterioration of transistor characteristics. Note that a transistor using silicon in a channel formation region may be referred to as a Si transistor.

[0056] It is preferable to use an oxide containing indium as the oxide semiconductor. It is more preferable that the oxide semiconductor have a high indium content. By using an oxide semiconductor with a high indium content for a semiconductor layer of a transistor, the transistor can have a large on-state current. For example, indium oxide can be preferably used as the oxide semiconductor.

[0057] An oxide containing indium and zinc can be used as the oxide semiconductor. By including zinc, the oxide semiconductor can have high crystallinity, resulting in a highly reliable transistor. Furthermore, the oxide semiconductor can be an oxide containing one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0058] Examples of oxide semiconductors include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), and aluminum zinc oxide (Al-Zn oxide). Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0059] Note that the oxide semiconductor can have one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap between the orbitals of metal elements, the greater the carrier conduction in a metal oxide. Therefore, the presence of a metal element having a higher period number can sometimes improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0060] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0061] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0062] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0063] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage (Vg) is 0 V can be reduced, and a normally-off transistor can be obtained. In addition, a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0064] When the metal oxide layer 21 is used as an electrode or wiring, a metal oxide having electrical conductivity (also called an oxide conductor (OC)) is used for the metal oxide layer 21 .

[0065] Examples of oxide conductors include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also called ITO containing silicon, or ITSO), zinc oxide doped with gallium, and In—Ga—Zn oxide. Oxide conductors containing indium are particularly preferred because of their high conductivity.

[0066] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0067] The metal oxide layer 21 can be formed, for example, by forming a metal oxide film that will become the metal oxide layer 21 and processing the metal oxide film into a desired shape. The metal oxide film can be processed by either or both of a wet etching method and a dry etching method.

[0068] Here, depending on the material used for the metal oxide film, the etching rate of the metal oxide film may be slow. In particular, when a material with high crystallinity is used for the metal oxide film, the etching rate of the metal oxide film may be extremely slow, which may make it difficult to process the metal oxide film into the metal oxide layer 21.

[0069] Therefore, in a method for manufacturing a semiconductor device according to one embodiment of the present invention, a mask layer is provided over a first region of the metal oxide film that will become the metal oxide layer 21, and a first element is supplied using the mask layer as a mask (this can also be referred to as adding or implanting the first element). Thus, the first element is supplied to a second region of the metal oxide film that does not overlap with the mask layer. Supplying the first element to the second region reduces the crystallinity of the second region, thereby increasing the etching rate of the second region. Then, by removing the second region by etching, the first region remains, and the metal oxide layer 21 can be formed. Supplying the first element to the second region that will be removed later facilitates processing of the metal oxide film, thereby improving the productivity of the semiconductor device.

[0070] The mask layer can be made of either or both of an organic material and an inorganic material, and a resist mask, for example, can be suitably used as the mask layer.

[0071] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0072] The first element is not limited to the above elements, and one or more of first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in rare earth elements can be used.

[0073] The first element preferably has a large mass number. When the mass number is large, the collision energy when the first element is supplied to the metal oxide film increases, and the crystallinity of the metal oxide film can be more efficiently reduced. Furthermore, the first element preferably has a large atomic radius. This allows the first element supplied to the metal oxide film to significantly disturb the atomic arrangement of the metal oxide film, and the crystallinity of the metal oxide film can be more efficiently reduced. For these reasons, it is preferable to use a noble gas as the first element. Argon is particularly suitable as the first element.

[0074] Ion implantation can be suitably used to supply the first element. The ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. The acceleration energy can be adjusted by adjusting the acceleration voltage during ion implantation. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurity element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0075] Ion implantation equipment is also used to manufacture Si transistors such as transistors having low temperature polysilicon (LTPS) in the semiconductor layer (hereinafter also referred to as LTPS transistors), and is therefore advantageous because it allows the use of equipment from existing LTPS manufacturing lines and does not require new capital investment, thereby reducing the initial capital investment costs involved in manufacturing semiconductor devices.

[0076] A gas containing the first element can be used as the source gas. When argon is used as the first element, argon gas can be used as the source gas. Alternatively, a mixed gas of a gas containing the first element and another gas can be used. Note that the source material used to supply the first element is not limited to a gas, and a solid or liquid can also be heated and vaporized for use.

[0077] The supply of the first element is not limited to the above-described method, and for example, plasma treatment can also be used. When plasma treatment is used, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing the plasma treatment. Devices that can generate the plasma include a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, and the like. By supplying the first element at an accelerated rate, the collision energy when the first element is supplied to the metal oxide film increases, and the crystallinity of the metal oxide film can be more effectively reduced, which is preferable.

[0078] When a material with a high indium content (e.g., indium oxide) is used for the metal oxide layer 21, the high crystallinity of the metal oxide film can result in an extremely slow etching rate, making etching difficult. Therefore, a mask layer is formed on a first region of the metal oxide film that will become the metal oxide layer 21, and argon is supplied to the metal oxide film using the mask layer as a mask by ion implantation. This allows argon to be supplied to a second region of the metal oxide film that does not overlap with the mask layer, reducing the crystallinity of the second region. The second region is then removed by etching to form the metal oxide layer 21. Using the metal oxide layer 21 containing a material with a high indium content as the semiconductor layer of a transistor can result in a transistor with a large on-state current. It can also be used as a semiconductor device that operates at high speed.

[0079] The metal oxide layer 21 has a region in contact with the top surface of the layer 31. The layer 31 can be referred to as a surface on which the metal oxide layer 21 is to be formed. The structure of the layer 31 is not particularly limited, and for example, the layer 31 can have a structure including a plurality of layers. Furthermore, two or more layers constituting the layer 31 can be in contact with the metal oxide layer 21. The conductivity of the layer 31 and each layer constituting the layer 31 is not particularly limited, and for example, the layer 31 can be an insulating layer, a semiconductor layer, or a conductive layer. Note that the cross-sectional views such as FIG. 1A show a structure example in which the top surface of the layer 31 is flat, but one embodiment of the present invention is not limited thereto. For example, the layer 31 can have grooves (slits), and the metal oxide layer 21 can be provided along the grooves.

[0080] When the metal oxide layer 21 is used as a semiconductor layer of a transistor, an insulating layer can be used for the layer 31 or part of the layer 31. The insulating layer can function as, for example, a gate insulating layer, an interlayer insulating layer, or a base insulating layer of the transistor, or part of any of these.

[0081] The layer 31 has a region 31N in contact with the metal oxide layer 21. The layer 31 also has a region 31D that is not in contact with the metal oxide layer 21. The region 31D contains a first element. The region 31D is located on the top surface of the layer 31 and in its vicinity. The region 31D is a region that is not covered with a mask layer when the first element is supplied to the metal oxide film, and the first element is supplied to the second region of the metal oxide film and also to the region 31D. Note that the layer 31 may be configured without the region 31D.

[0082] Examples of configurations different from the configuration shown in FIG. 1A are shown in FIGS. 1B to 1F.

[0083] FIG. 1B is a cross-sectional view of the semiconductor device 10A. The semiconductor device 10A differs from the semiconductor device 10 described above mainly in that the height of the upper surface of region 31D is different from the height of the upper surface of region 31N. FIG. 1B shows an example in which the height of the upper surface of region 31D is lower than the height of the upper surface of region 31N. For example, when removing the second region of the metal oxide film, part of region 31D may also be etched, lowering the height of the upper surface of region 31D. Alternatively, as in the semiconductor device 10B shown in FIG. 1C, region 31D may be removed, and no region 31D may remain.

[0084] 1D is a cross-sectional view of the semiconductor device 10C. The semiconductor device 10C differs from the semiconductor device 10 described above mainly in that it includes a mask layer 23 on the metal oxide layer 21. The mask layer 23 has a region that contacts the upper surface of the metal oxide layer 21. FIG. 1D shows an example in which the edge of the mask layer 23 coincides with the edge of the metal oxide layer 21.

[0085] A mask film that will become the mask layer 23 is formed on the metal oxide film that will become the metal oxide layer 21, and a resist mask is formed on the mask film. The mask film is processed using the resist mask to form the mask layer 23. Using the resist mask as a mask, a first element is supplied to the metal oxide film to form a second region in the metal oxide film. The second region is then removed to form the metal oxide layer 21. This allows the edges of the mask layer 23 to coincide or approximately coincide with the edges of the metal oxide layer 21. It is also possible to configure the edges of the mask layer 23 so that they do not coincide with the edges of the metal oxide layer 21. By providing the mask layer 23 between the metal oxide film and the resist mask, the metal oxide film does not come into contact with the resist mask, thereby preventing organic matter from the resist mask from adhering to the surface of the metal oxide film. The resist mask can be referred to as the first mask layer, and the mask layer 23 as the second mask layer. An organic material can be suitably used for the first mask layer, and an inorganic material can be suitably used for the second mask layer.

[0086] The mask layer 23 can be made of an inorganic material. The conductivity of the mask layer 23 is not particularly limited, and the mask layer 23 can be, for example, an insulating layer, a semiconductor layer, or a conductive layer. When the metal oxide layer 21 is used as a semiconductor layer of a transistor, the mask layer 23 can be made of an insulating layer. The mask layer 23 can function as, for example, a gate insulating layer, an interlayer insulating layer, or a base insulating layer of a transistor, or as a part of any of these.

[0087] FIG. 1E is a cross-sectional view of a semiconductor device 10D. The semiconductor device 10D differs from the semiconductor device 10C described above mainly in that the height of the upper surface of region 31D is different from the height of the upper surface of region 31N. FIG. 1E shows an example in which the height of the upper surface of region 31D is lower than the height of the upper surface of region 31N. For example, when removing the second region of the metal oxide film, part of region 31D may also be etched, lowering the height of the upper surface of region 31D. Alternatively, as in the semiconductor device 10E shown in FIG. 1F, region 31D may be removed, and no region 31D may remain.

[0088] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described.

[0089] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method, a thermal CVD method, etc. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0090] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0091] When processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0092] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0093] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0094] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0095] <Manufacturing Method Example 1> Here, an example of a manufacturing method of the semiconductor device 10 shown in Fig. 1A will be described. A flow of the manufacturing method of the semiconductor device 10 is shown in Fig. 2. Cross-sectional views of the semiconductor device during manufacturing are shown in Fig. 3A to Fig. 3D.

[0096] First, a metal oxide film 21f that will become the metal oxide layer 21 is formed on the layer 31 (step S11 in FIG. 2, FIG. 3A). The metal oxide film 21f is provided in contact with the upper surface of the layer 31. The configuration of the layer 31 can be referred to as described above.

[0097] The metal oxide film 21f is preferably formed by sputtering using a metal oxide target. Alternatively, the metal oxide film 21f is preferably formed by ALD. The ALD method makes it easy to control the film formation rate, allowing a thin film to be formed with a high yield. Therefore, the ALD method is preferably used when the metal oxide film 21f is thin. Furthermore, the ALD method has high coverage, so the metal oxide film 21f can be formed with high coverage even if the surface on which the metal oxide film 21f is to be formed is uneven. Instead of sputtering and ALD, a CVD method can also be used to form the metal oxide film 21f.

[0098] The metal oxide film 21f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 21f is preferably a high-purity film in which impurities including hydrogen (e.g., water and hydrogen) are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 21f.

[0099] When forming the metal oxide film 21f, it is preferable to use oxygen gas. This reduces the oxygen deficiency (V Ｏ ) can be reduced.

[0100] The metal oxide film 21f can be formed by mixing oxygen gas with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of the flow rate of oxygen gas to the total film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber of the film-forming apparatus, the higher the crystallinity of the metal oxide film 21f. When a highly crystalline metal oxide layer 21 is used as the semiconductor layer of a transistor, a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or the oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, resulting in a transistor with a large on-state current.

[0101] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 21f does not become polycrystalline. Because the ease with which a metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 21f. However, one embodiment of the present invention is not limited thereto, and a polycrystalline metal oxide can be used. When the grain boundaries of a polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a polycrystalline metal oxide can have higher reliability than a transistor using a metal oxide with low crystallinity.

[0102] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0103] The substrate temperature during the formation of the metal oxide film 21f is preferably from room temperature (e.g., 25°C) to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, a substrate temperature of from room temperature to 140°C is preferable because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0104] If the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 21f.

[0105] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0106] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0107] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0108] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0109] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0110] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0111] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0112] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0113] Oxidizing agents include, for example, ozone, oxygen, and water.

[0114] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 21f can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film 21f whose composition changes continuously.

[0115] Before forming the metal oxide film 21f, it is preferable to perform a treatment to remove water, hydrogen, organic substances, and the like adsorbed on the surface of the layer 31. For example, a heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. After the heat treatment, it is more preferable to continuously form the metal oxide film 21f without exposing the surface of the layer 31 to the atmosphere.

[0116] When the metal oxide layer 21 has a laminated structure, it is preferable to deposit a metal oxide film first, and then deposit the next metal oxide film without exposing the surface to the atmosphere.

[0117] When the metal oxide layer 21 has a laminated structure, all layers constituting the metal oxide layer 21 can be formed by the same film formation method (e.g., sputtering or ALD). Alternatively, different film formation methods can be used for different layers. For example, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0118] Next, a resist mask 90 is formed on the metal oxide film 21f (step S21 in FIG. 2, FIG. 3B). The resist mask 90 is provided in the region where the metal oxide layer 21 is to be provided. The resist mask 90 can be formed by applying a photosensitive resin, exposing it to light, and developing it. The resist mask 90 can be made of a positive resist material or a negative resist material.

[0119] Next, using the resist mask 90 as a mask, a first element is supplied to the metal oxide film 21f (step S31 in FIG. 2, FIG. 3C). Here, element 75 is supplied to the metal oxide film 21f. The above-mentioned first element can be used as element 75. Element 75 is supplied to a region of the metal oxide film 21f that does not overlap with the resist mask 90, thereby forming region 21D. FIG. 3C schematically shows, with dashed arrows, how element 75 is supplied to the metal oxide film 21f.

[0120] The acceleration energy and dose amount in supplying the element 75 are preferably set in consideration of the type of element 75, the composition, film density, and thickness of the metal oxide film 21f. The concentration of the element 75 in the depth direction can be simulated using software, for example. Examples of simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method. The type of impurity element to be supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy can be used as simulation parameters.

[0121] It is preferable that the amount of element 75 supplied to region 21D is large. In other words, it is preferable that the concentration of element 75 in region 21D is high. By increasing the amount of element 75 supplied to region 21D, the crystallinity of region 21D can be more efficiently reduced. The number of ions in region 21D per unit area in top view (hereinafter also referred to as ion concentration) is 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Preferably, it is equal to or less than 1×10 １４ ions / cm ２ 1x10 or more １７ ions / cm ２ Preferably, it is less than 5×10 １４ ions / cm ２ 1x10 or more １７ ions / cm ２ Preferably, it is equal to or less than 1×10 １５ ions / cm ２ 1x10 or more １７ ions / cm ２ The following is preferable. The number of ions is the total number of ions from the upper surface to the lower surface of the metal oxide film 21f (region 21D). The number of ions can be calculated, for example, by simulation. It is preferable to set the acceleration energy and dose amount so that the ion concentration in region 21D falls within the above-mentioned range. Note that the ion concentration in region 21D is not limited to the above-mentioned range.

[0122] It is preferable to set the acceleration energy for supplying the element 75 so that the concentration of the element 75 is highest in the metal oxide film 21f or at or near the interface between the metal oxide film 21f and the layer 31. Increasing the amount of the element 75 supplied to the interface between the metal oxide film 21f and the layer 31 or near the interface may damage the metal oxide film 21f at or near the interface, resulting in the formation of an altered layer between the metal oxide film 21f and the layer 31. The altered layer caused by the damage may have a faster etching rate in wet etching than the metal oxide film 21f. Furthermore, during wet etching, an etchant may penetrate into the altered layer, removing the altered layer and causing lift-off of the metal oxide film 21f. This may have the effect of making the metal oxide film 21f easier to remove, even if the metal oxide film 21f has high crystallinity.

[0123] In the region 21D, the concentration of the element 75 is 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below, and further 1 x 10 ２０ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below, and further 1 x 10 ２１ atoms / cm ３ 1x10 or more ２３ atoms / cm ３It is preferable that the region 21D includes a region where the concentration of argon is within the aforementioned range. For example, when argon is used as the first element, the region 21D preferably includes a region where the concentration of argon is within the aforementioned range. If the amount of the element 75 supplied is small, the crystallinity of the region 21D may be high, resulting in a slow etching rate, which may make etching of the region 21D difficult. On the other hand, if the amount of the first element supplied is large, the productivity of the semiconductor device may be reduced. By setting the concentration of the first element in the region 21D within the aforementioned range, the etching rate of the region 21D can be increased and the productivity of the semiconductor device can be improved. It is preferable to set the acceleration energy and dose amount so that the concentration of the element 75 in the region 21D is within the aforementioned range. Note that the concentration of the element 75 in the region 21D is not limited to the aforementioned range.

[0124] Supplying element 75 to region 21D reduces the crystallinity, thereby increasing the etching rate of region 21D. Then, by removing region 21D by etching, region 21N remains, and metal oxide layer 21 can be formed. In this way, supplying element 75 to region 21D, which will be removed later, makes it easier to process metal oxide film 21f, thereby improving the productivity of semiconductor devices.

[0125] The crystallinity of region 21D is preferably lower than that of region 21N. The crystallinity of metal oxide film 21f can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, analysis can be performed by combining a plurality of these techniques.

[0126] When supplying the element 75, it is preferable to determine the material and thickness of the resist mask 90 and the conditions for the supplying process of the element 75 so that as little of the element 75 as possible is supplied to the region 21N of the metal oxide film 21f that overlaps with the resist mask 90. ​​This makes it possible to reduce the concentration of the element 75 in the region 21N. The region 21D is later removed. Meanwhile, the region 21N remains and becomes the metal oxide layer 21. By reducing the concentration of the element 75 in the region 21N, the purity of the region 21N (later the metal oxide layer 21) can be increased.

[0127] The concentration of element 75 in region 21D is preferably high. On the other hand, the concentration of element 75 in region 21N is preferably low. The concentration of element 75 in region 21N is preferably lower than the concentration of the first element in region 21D. The concentration of element 75 in region 21N is preferably 5×10 of the concentration of element 75 in region 21D. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the concentration of the element 75 in the region 21N is equal to or less than 1 / 2 times the concentration of the element 75 in the region 21N. By lowering the concentration of the element 75 in the region 21N, a highly reliable transistor can be obtained. Note that the concentration of the element 75 in the region 21N is not limited to the above range.

[0128] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS or Electron Spectrometry for Chemical Analysis (ESCA)) can be used to analyze the concentration of the first element in the metal oxide film 21f, the metal oxide layer 21, and the layer 31. When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis.

[0129] The element 75 is also supplied to a region of the layer 31 that does not overlap with the resist mask 90, forming a region 31D having the element 75. The region 31D is provided in a region of the layer 31 that overlaps with the region 21D. The region 31D is located near the interface with the region 21D. The region 31D has a concentration of the element 75 of 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below, and further 1 x 10 ２０ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below, and further 1 x 10 ２１ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ It is preferable that the region 31D includes a region where the concentration of the first element is less than or equal to 1 / 2 of the concentration of the first element in the metal oxide film 21f. As described above, it is preferable to set the acceleration energy for supplying the element 75 so that the concentration of the element 75 is highest in the metal oxide film 21f or at or near the interface between the metal oxide film 21f and the layer 31. Therefore, it is preferable that the concentration of the element 75 in the region 31D increases toward the region 21D side (here, the upper surface side of the layer 31). Note that the concentration of the element 75 in the region 31D is not limited to the above-mentioned range. Furthermore, there are cases where the concentration of the first element in the layer 31 is below the lower detection limit. In this case, it can also be said that the layer 31 does not have the region 31D.

[0130] Subsequently, the region 21D is removed, thereby leaving the region 21N and forming the metal oxide layer 21 (step S41 in FIG. 2, FIG. 3D).

[0131] The region 21D can be removed by either or both of a wet etching method and a dry etching method. For example, a chemical solution containing oxalic acid or a chemical solution containing phosphoric acid, acetic acid, and nitric acid (also referred to as PAN) can be used as an etchant for the wet etching. For example, a chemical solution containing CH ４Gas and Ar gas can be used. Region 21D has low crystallinity and a fast etching rate, so it can be removed by etching. On the other hand, region 21N has high crystallinity and a slow etching rate, so it remains in the etching process of region 21D. Furthermore, since a resist mask 90 is provided on region 21N when region 21D is removed, damage to region 21N can be suppressed.

[0132] Next, the resist mask 90 is removed (step S51 in FIG. 2, FIG. 10A). The resist mask 90 can be removed by either or both of a wet etching method and a dry etching method. The wet etching method is preferable because it can prevent damage to the metal oxide layer 21.

[0133] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0134] In step S41, a portion of region 31D can be removed by etching to lower the height of the upper surface of region 31D. This allows the semiconductor device 10A to be fabricated. Alternatively, by removing region 31D, the semiconductor device 10B can be fabricated.

[0135] <Manufacturing Method Example 2> A manufacturing method of the semiconductor device 10 different from the manufacturing method of the semiconductor device 10 described above in <Manufacturing Method Example 1> will be described. A flow of the manufacturing method of the semiconductor device 10 is shown in Figure 4. Cross-sectional views of the semiconductor device during manufacturing are shown in Figures 5A to 5F.

[0136] First, a metal oxide film 21f to become the metal oxide layer 21 is formed on the layer 31 (step S11 in FIG. 4, FIG. 3A). For the formation of the metal oxide film 21f, the description of step S11 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0137] Subsequently, a mask film 23f that will become the mask layer 23 is formed on the metal oxide film 21f (step S12 in FIG. 4, FIG. 5A). The mask film 23f is provided in contact with the upper surface of the metal oxide film 21f.

[0138] The mask film 23f can be formed by, for example, PECVD, sputtering, or ALD. The mask film 23f provided in contact with the metal oxide film 21f is preferably formed by a method that causes less damage to the metal oxide film 21f. The mask film 23f can be formed by, for example, PECVD or ALD. When an insulating layer is used for the mask layer 23, for example, a silicon oxynitride film can be formed as the mask film 23f by PECVD.

[0139] Subsequently, a resist mask 90 is formed on the mask film 23f (step S21 in FIG. 4, FIG. 5B). For the formation of the resist mask 90, the description of step S21 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0140] Next, the mask film 23f is processed using the resist mask 90 as a mask to form the mask layer 23 (step S22 in FIG. 4, FIG. 5C). As a result, the region of the metal oxide film 21f that does not overlap with the resist mask 90 is exposed. The mask film 23f can be processed by either or both of a wet etching method and a dry etching method.

[0141] Next, using the resist mask 90 as a mask, the first element is supplied to the metal oxide film 21f to form a region 21D (step S31 in FIG. 4, FIG. 5D). Furthermore, a region 31D is formed in the layer 31. The region 21D and the region 31D are provided at positions that do not overlap with either the resist mask 90 or the mask layer 23. For the supply of the element 75, the description of step S31 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0142] Next, the region 21D is removed, leaving the region 21N, and forming the metal oxide layer 21 (step S41 in FIG. 4 and FIG. 5E). For the removal of the region 21D, the description of step S41 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0143] Next, the resist mask 90 is removed (step S51 in FIG. 4 and FIG. 5F). For the removal of the resist mask 90, the description of step S51 in the above-mentioned <Fabrication Method Example 1> can be referred to. Note that, since the mask layer 23 is provided on the metal oxide layer 21, damage to the metal oxide layer 21 can be suppressed during the removal of the resist mask 90. ​​Therefore, the range of options for the method of removing the resist mask 90 can be expanded.

[0144] Subsequently, the mask layer 23 is removed (step S61 in FIG. 4, FIG. 10A), thereby exposing the upper surface of the metal oxide layer 21.

[0145] The mask layer 23 can be removed by either or both of a wet etching method and a dry etching method. The wet etching method is preferable because it can prevent damage to the metal oxide layer 21.

[0146] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0147] In step S41, a portion of region 31D can be removed by etching to lower the height of the upper surface of region 31D. This allows the semiconductor device 10A to be fabricated. Alternatively, by removing region 31D, the semiconductor device 10B can be fabricated.

[0148] By not performing step S61 and leaving the mask layer 23, the semiconductor device 10C, the semiconductor device 10D, or the semiconductor device 10E can be fabricated.

[0149] <Manufacturing Method Example 3> A manufacturing method of the semiconductor device 10 different from the manufacturing methods shown in the above-described <Manufacturing Method Example 1> and <Manufacturing Method Example 2> will be described. A flow of the manufacturing method of the semiconductor device 10 is shown in Figure 6. Cross-sectional views of the semiconductor device during manufacturing are shown in Figures 7A and 7B.

[0150] Similar to steps S11 to S31 in Manufacturing Method Example 2, steps up to the supply of the first element are performed (steps S11 to S31 in FIG. 6, FIG. 3A, and FIGS. 5A to 5D).

[0151] Next, the resist mask 90 is removed (step S31 in FIG. 6, FIG. 7A). For the removal of the resist mask 90, the description of step S51 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0152] Next, the region 21D is removed, leaving the region 21N, and forming the metal oxide layer 21 (step S41 in FIG. 6 and FIG. 7B). For the removal of the region 21D, the description of step S41 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0153] The resist mask 90 functions as a mask when the element 75 is supplied in step S31. When the element 75 is also supplied to the resist mask 90, carbonization and crosslinking occur in the material of the resist mask 90, which may make the resist mask 90 difficult to remove. Furthermore, when the metal oxide layer 21 is formed by dry etching in step S41 while the resist mask 90 remains, the resist mask 90 may become even more difficult to remove when exposed to a plasma atmosphere in the dry etching. In this case, it is preferable to remove the resist mask 90 (step S32) after supplying the element 75 (step S31), and then form the metal oxide layer 21 (step S41).

[0154] Next, the mask layer 23 is removed (step S61 in FIG. 6, FIG. 10A). This exposes the upper surface of the metal oxide layer 21. For the removal of the mask layer 23, refer to the description of step S61 in the above-mentioned <Fabrication Method Example 2>.

[0155] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0156] In step S41, a portion of region 31D can be removed by etching to lower the height of the upper surface of region 31D. This allows the semiconductor device 10A to be fabricated. Alternatively, by removing region 31D, the semiconductor device 10B can be fabricated.

[0157] By not performing step S61 and leaving the mask layer 23, the semiconductor device 10C, the semiconductor device 10D, or the semiconductor device 10E can be fabricated.

[0158] <Manufacturing Method Example 4> A manufacturing method of the semiconductor device 10 different from the manufacturing methods shown in the above-described <Manufacturing Method Example 1> to <Manufacturing Method Example 3> will be described. A flow of the manufacturing method of the semiconductor device 10 is shown in Figure 8. A cross-sectional view of the semiconductor device during manufacturing is shown in Figure 9.

[0159] Similar to steps S11 to S32 in Manufacturing Method Example 3, steps up to removal of the resist mask 90 are performed (steps S11 to S32 in FIG. 8, FIGS. 3A, 5A to 5D, and FIG. 7A).

[0160] Next, a heat treatment is performed (step S33 in FIG. 8 , FIG. 9 ). The heat treatment temperature is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, even more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that it is preferable that the content of hydrogen, water, and the like in the atmosphere be minimized. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere. By using an atmosphere with a content of hydrogen, water, and the like as small as possible, it is possible to prevent hydrogen, water, and the like from being incorporated into the metal oxide film 21f as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0161] By the heat treatment, impurities (e.g., hydrogen, carbon, and hydrocarbon) contained in the region 21N diffuse into the region 21D, thereby reducing the impurity concentration in the region 21N. Also, the impurity concentration in the region 21D increases. In FIG. 9, the dashed arrows schematically show how the impurities contained in the region 21N diffuse into the region 21D. Compared to the region 21N, the region 21D has an oxygen deficiency (V Ｏ ) is large. Also, there is a large amount of oxygen deficiency (V Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ In metal oxides, V Ｏ H can exist stably. Therefore, the impurities diffused into region 21D are captured (also called gettered) by region 21D. Region 21D can also be said to function as a gettering site. This can reduce the impurity concentration in region 21N (later to be formed into metal oxide layer 21), thereby increasing the purity of region 21N.

[0162] If the amount of the first element supplied to the region 21D is small, the crystallinity of the region 21D may increase due to the heat treatment. The increased crystallinity may make it difficult to remove the region 21D. By increasing the amount of the first element supplied to the region 21D, crystallization due to the heat treatment can be suppressed. It is more preferable to set the amount of the first element in the region 21D within the aforementioned range.

[0163] Next, the region 21D is removed, leaving the region 21N, and forming the metal oxide layer 21 (step S41 in FIG. 6 and FIG. 7B). For the removal of the region 21D, the description of step S41 in the above-mentioned <Fabrication Method Example 1> can be referred to.

[0164] Next, the mask layer 23 is removed (step S61 in FIG. 6, FIG. 10A). This exposes the upper surface of the metal oxide layer 21. For the removal of the mask layer 23, refer to the description of step S61 in the above-mentioned <Fabrication Method Example 2>.

[0165] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0166] In step S41, a portion of region 31D can be removed by etching to lower the height of the upper surface of region 31D. This allows the semiconductor device 10A to be fabricated. Alternatively, by removing region 31D, the semiconductor device 10B can be fabricated.

[0167] By not performing step S61 and leaving the mask layer 23, the semiconductor device 10C, the semiconductor device 10D, or the semiconductor device 10E can be fabricated.

[0168] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0169] 10 to 26. Here, a structure example in which the metal oxide layer described in Embodiment 1 is applied to a semiconductor layer of a transistor will be described. Note that there is no particular limitation on the structure of a transistor to which the metal oxide layer can be applied.

[0170] <Configuration Example 1> A top view (also referred to as a plan view) of the semiconductor device 20 is shown in FIG. 10A . FIG. 10B shows a cross-sectional view of the cut surface taken along dashed-dotted line A1-A2 in FIG. 10A , and FIG. 10C shows a cross-sectional view of the cut surface taken along dashed-dotted line B1-B2 in FIG. 10A . Note that some components of the semiconductor device 20 (such as a gate insulating layer) are omitted in FIG. 10A . As with FIG. 10A , some components are also omitted in the top views of the semiconductor device in subsequent drawings. Perspective views of the semiconductor device 20 are shown in FIGS. 11A to 11D . FIG. 11B shows a cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 11A . In FIG. 11C , the insulating layer shown in FIG. 11A is transparent, and its outline is indicated by a dashed line. Similarly, in FIG. 11D , the insulating layer shown in FIG. 11B is transparent, and its outline is indicated by a dashed line.

[0171] The semiconductor device 20 includes a transistor 100 and an insulating layer 110. The semiconductor device 20 is provided on an insulating surface. FIG. 10B and other figures show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film.

[0172] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 108 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108 that is in contact with the drain electrode functions as a drain region. In the semiconductor layer 108, the channel formation region is located between the source region and the drain region.

[0173] A conductive layer 112a is provided on a substrate 102, an insulating layer 110 is provided on the conductive layer 112a, and a conductive layer 112b is provided on the insulating layer 110. The insulating layer 110 is in contact with the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them. The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141. Note that in FIG. 10A and other drawings, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 112b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 112b have openings that reach the conductive layer 112a.

[0174] The semiconductor layer 108 is provided to cover the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0175] The metal oxide layer 21 described in Embodiment 1 can be applied to the semiconductor layer 108. The insulating layer 110, the conductive layer 112a, and the conductive layer 112b, which are surfaces on which the semiconductor layer 108 is to be formed, correspond to the layer 31 described in Embodiment 1.

[0176] The first element is supplied to regions of the insulating layer 110, the conductive layer 112a, and the conductive layer 112b that are not in contact with the semiconductor layer 108. FIG. 10B and other figures illustrate an example in which the insulating layer 110 includes a region 110D containing the first element, and the conductive layer 112b includes a region 112bD containing the first element. The region 110D is located in a region of the insulating layer 110 that is not in contact with either the semiconductor layer 108 or the conductive layer 112b. The region 112bD is located in a region of the conductive layer 112b that is not in contact with the semiconductor layer 108. The description of the region 31D in Embodiment 1 can be referred to for the region 110D and the region 112bD. Note that the concentration of the first element in the conductive layer 112b may be below the lower limit of detection. In this case, it can also be said that the conductive layer 112b does not include the region 112bD. The same applies to the insulating layer 110.

[0177] Note that the thickness of the region 110D (which can also be referred to as the thickness of the region in the insulating layer 110 where the first element is detected) may differ from the thickness of the region 112bD (which can also be referred to as the thickness of the region in the conductive layer 112b where the first element is detected). When an element is supplied (e.g., by ion implantation), the stopping power varies depending on the type of element, and therefore the depth to which the element is supplied (here, corresponding to the thickness of the region 110D and the thickness of the region 112bD) varies depending on the composition of the layer to which the element is supplied. Furthermore, a high film density of the layer increases the stopping power and decreases the depth to which the element is supplied. Therefore, when the material used for the insulating layer 110 and the material used for the conductive layer 112b are different, the thickness of the region 110D and the thickness of the region 112bD will differ. For example, the thickness of the region 110D will be thicker than the thickness of the region 112bD.

[0178] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0179] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0180] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0181] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ ), and V Ｏ H can be reduced.

[0182] The insulating layer 106, which functions as a gate insulating layer of the transistor 100, is provided to cover the openings 141 and 143. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the conductive layer 112a.

[0183] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.

[0184] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. In other words, the drain current flows vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0185] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0186] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the characteristic variation among the plurality of transistors 100 is also reduced. Therefore, the operation of the semiconductor device 20 can be stabilized and the reliability can be improved. Furthermore, the reduced characteristic variation of the transistors increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0187] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the area occupied by the transistor 100 and the wirings can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0188] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0189] 10B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143; however, one embodiment of the present invention is not limited to this. A structure can be employed in which a step is formed between the insulating layer 110, the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step.

[0190] [Insulating Layer 106] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be formed using the materials listed for the insulating layer 110.

[0191] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0192] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0193] 10B and the like, the insulating layer 106 has a single-layer structure; however, one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0194] 12A and 12B are cross-sectional views of a semiconductor device 20A according to one embodiment of the present invention. For a top view of the semiconductor device 20A, refer to FIG. 10A . FIG. 12A is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 10A , and FIG. 12B is a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 10A . FIG. 12C is an enlarged view of FIG. 12A .

[0195] The semiconductor device 20A includes a transistor 100A and an insulating layer 110. The transistor 100B differs from the transistor 100 shown in Figure 10B and other figures mainly in that the insulating layer 106 has a stacked structure. Figure 12A and other figures show a configuration in which the insulating layer 106 has a two-layer structure including an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0196] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer on the semiconductor layer 108 side (the insulating layer 106a here) preferably contains oxide or oxynitride. The insulating layer 106a can be preferably formed using, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0197] It is preferable to use a material that is difficult for substances to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 from diffusing into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ ) can be suppressed. In addition, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the semiconductor layer 108, which can prevent the electrical resistance of the conductive layer 104 from increasing. As a result, a transistor with good electrical characteristics and high reliability can be obtained. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0198] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b.

[0199] An example of a configuration different from that of semiconductor device 20A is shown in Figures 13A and 13B. Figures 13A and 13B are cross-sectional views of semiconductor device 20B. For a top view of semiconductor device 20B, refer to Figure 10A. Figure 13A is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in Figure 10A, and Figure 13B is a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 shown in Figure 10A. An enlarged view of Figure 13A is shown in Figure 13C.

[0200] The semiconductor device 20B includes a transistor 100B and an insulating layer 110. 13A to 13C illustrate an example in which the mask layer 23 described in Embodiment 1 is applied to part of the insulating layer 106 of the transistor 100B.

[0201] The insulating layer 106 includes an insulating layer 106a and an insulating layer 106b over the insulating layer 106a. The mask layer 23 described in Embodiment 1 can be applied to the insulating layer 106a. The description of the mask layer 23 can be referred to for the insulating layer 106a. For example, silicon oxynitride can be suitably used for each of the insulating layer 106a and the insulating layer 106b. Note that the insulating layer 106a and the insulating layer 106b can be formed using the same material, or different materials can be used for them.

[0202] An end of the insulating layer 106a coincides with or substantially coincides with an end of the semiconductor layer 108. The insulating layer 106b is provided so as to cover the insulating layer 106a, the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106b has a region in contact with the top surface and side surfaces of the insulating layer 106a, the side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. By providing the insulating layer 106b, the conductive layer 112b and the conductive layer 104 are electrically insulated from each other, and short-circuiting between them can be suppressed.

[0203] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0204] The configuration of the insulating layer 106 shown here can also be applied to other configuration examples.

[0205] [Insulating Layer 110] The insulating layer 110 preferably has a stacked-layer structure. Cross-sectional views of a semiconductor device 20C according to one embodiment of the present invention are shown in FIGS. 14A and 14B. For a top view of the semiconductor device 20C, see FIG. 10A. FIG. 14A is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 10A, and FIG. 14B is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 10A. An enlarged view of FIG. 10A is shown in FIG. 15A. An enlarged view of FIG. 14A is shown in FIG. 15B.

[0206] The semiconductor device 20C includes a transistor 100 and an insulating layer 110. Figure 14A and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, an insulating layer 110d on the insulating layer 110c, and an insulating layer 110e on the insulating layer 110d. The insulating layers 110a, 110b, 110c, 110d, and 110e can each be made of the materials listed for the insulating layer 110.

[0207] A region of the semiconductor layer 108 in contact with the insulating layer 110c functions as a channel formation region. The insulating layer 110c preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110c can be made of silicon oxide, silicon oxynitride, or both.

[0208] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110c. When heat is applied during the manufacturing process of the semiconductor device 20, the insulating layer 110c releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110c to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0209] For example, oxygen can be supplied to the insulating layer 110c by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming a film on the top surface of the insulating layer 110c by a sputtering method in an oxygen-containing atmosphere. Then, the film can be removed.

[0210] The insulating layer 110c is preferably formed by a deposition method such as a sputtering method or a PECVD method. In particular, by forming the insulating layer 110c by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. The sputtering method is particularly suitable for forming the insulating layer 110c. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0211] The insulating layer 110b is provided between the insulating layer 110c and the conductive layer 112a. The insulating layer 110d is provided between the insulating layer 110c and the conductive layer 112b. The insulating layers 110b and 110d preferably release small amounts of impurities (e.g., water and hydrogen). Furthermore, the insulating layers 110b and 110d preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layers 110b and 110d can also be said to function as barrier films. Specifically, the insulating layers 110b and 110d preferably are impermeable to impurities. This can prevent impurities contained in the insulating layers 110b and 110d from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0212] It is preferable that the insulating layer 110b and the insulating layer 110d are made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110c from diffusing to the conductive layer 112a side through the insulating layer 110b. Similarly, it can prevent oxygen contained in the insulating layer 110c from diffusing to the conductive layer 112b side through the insulating layer 110d. This increases the amount of oxygen supplied from the insulating layer 110c to the channel formation region of the semiconductor layer 108, and reduces oxygen vacancies (V Ｏ ) and V ＯH can be reduced. Therefore, a transistor exhibiting favorable electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110c, which would prevent the electrical resistance of the conductive layer 112a from increasing. Similarly, the conductive layer 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110c, which would prevent the electrical resistance of the conductive layer 112b from increasing. Therefore, a transistor with a large on-state current can be obtained.

[0213] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering).

[0214] The insulating layer 110b and the insulating layer 110d, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110b and the insulating layer 110d can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110b and the insulating layer 110d can be made of the same material. Alternatively, the insulating layer 110b and the insulating layer 110d can be made of different materials.

[0215] By using an oxide or oxynitride for the insulating layer 110d, oxygen can be supplied to the insulating layer 110c (or the insulating film that becomes the insulating layer 110c) when forming the insulating layer 110d (or the insulating film that becomes the insulating layer 110d).

[0216] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0217] One or more of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110e can have a stacked structure.

[0218] When the insulating layer 110d has a stacked structure, the layers constituting the insulating layer 110d can be made of the materials listed for the insulating layer 110d. An oxide or oxynitride can be preferably used for the layer provided on the insulating layer 110c side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110c side. By using an oxide or oxynitride for the layer provided on the insulating layer 110c side, oxygen can be supplied to the insulating layer 110c (or the insulating film that will become the insulating layer 110c) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110d can have a stacked structure, for example, of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110d can have a stacked structure, for example, of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0219] The insulating layer 110a is provided between the substrate 102 and the conductive layer 112a and the insulating layer 110b. The insulating layer 110a is provided to cover the conductive layer 112a. The insulating layer 110a has regions in contact with the top surface and side surfaces of the conductive layer 112a, the top surface of the substrate 102, and the side surface of the semiconductor layer 108.

[0220] The insulating layer 110e is provided between the insulating layer 110d and the conductive layer 112b and the insulating layer 106. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110d, the bottom surface of the conductive layer 112b, the bottom surface of the insulating layer 106, and the side surface of the semiconductor layer 108.

[0221] It is more preferable that the insulating layer 110a and the insulating layer 110e each be made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. This allows the region of the semiconductor layer 108 in contact with the insulating layer 110a to be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110e, the region of the semiconductor layer 108 in contact with the insulating layer 110e can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region can function as a buffer region for reducing the drain electric field. Note that these low-resistance regions may function as source or drain regions.

[0222] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. For example, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110a a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110e a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor.

[0223] When a region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be made more uniform. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.

[0224] The insulating layer 110b preferably emits a small amount of impurities and is less likely to transmit impurities. This can prevent impurities from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layers 110b and 110c. Similarly, the insulating layer 110d preferably emits a small amount of impurities and is less likely to transmit impurities. This can prevent impurities from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layers 110d and 110c. This can provide a transistor with good electrical characteristics and high reliability.

[0225] When a metal oxide is used for the semiconductor layer 108, the impurities released from the insulating layer 110a and the insulating layer 110e preferably contain hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen (V Ｏ H) functions as a donor, generating electrons as carriers. As a result, the carrier concentration in the region of the semiconductor layer 108 that is in contact with the insulating layer 110a and the region that is in contact with the insulating layer 110e becomes high, and the electrical resistance can be reduced.

[0226] The insulating layer 110a preferably has a region with a higher hydrogen content than the insulating layer 110b. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0227] The amount of released hydrogen can be adjusted by varying the deposition conditions between the insulating layer 110a and the insulating layer 110b. Specifically, the insulating layer 110a and the insulating layer 110b can be made different from each other in one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of the insulating layer 110a lower than the deposition power density of the insulating layer 110b, the hydrogen content in the insulating layer 110a can be made higher than the hydrogen content in the insulating layer 110b. This increases the amount of hydrogen released from the insulating layer 110a due to heat applied to the insulating layer 110a.

[0228] The hydrogen content in the deposition gas used to form the insulating layer 110a is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110b. Specifically, when silicon nitride films or silicon nitride oxide films are formed as the insulating layers 110a and 110b by PECVD, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 110a (hereinafter also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow rate of the deposition gas used to form the insulating layer 110b. By forming the insulating layer 110a under conditions with a high ammonia flow ratio, the hydrogen content in the insulating layer 110a can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110a due to heat applied to the insulating layer 110a can be increased.

[0229] The film density of the insulating layer 110b is preferably higher than that of the insulating layer 110a. This can prevent hydrogen contained in the insulating layer 110a from diffusing into the channel formation region of the semiconductor layer 108 via the insulating layers 110b and 110c. The film density can be evaluated by, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dark transmitted electron (TE) image, whereas a low film density results in a light transmitted electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110b may appear darker than the insulating layer 110a. Even if the same material is used for the insulating layers 110a and 110b, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0230] The insulating layer 110e preferably has a region with a higher hydrogen content than the insulating layer 110d. The film density of the insulating layer 110d is more preferably higher than that of the insulating layer 110e. For the insulating layers 110d and 110e, the description of the insulating layers 110b and 110a can be referred to.

[0231] 16A to 16C are enlarged views of the conductive layer 112b, the insulating layer 110, and their vicinity. As shown in FIG. 16A, the region 110D may be provided in the insulating layer 110e. Alternatively, as shown in FIG. 16B, the region 110D may be provided in the insulating layer 110e and the insulating layer 110d. Alternatively, as shown in FIG. 16C, the region 110D may be provided in the insulating layer 110e, the insulating layer 110d, and the insulating layer 110c. The area where the region 110D is provided is not particularly limited.

[0232] Although the insulating layer 110 is shown here as having a five-layer stacked structure, one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110c. A structure without one or more of the insulating layer 110a, the insulating layer 110b, the insulating layer 110d, and the insulating layer 110e is also possible. The insulating layer 110 can have a stacked structure of two, three, four, or six or more layers. Alternatively, the insulating layer 110 can have a single-layer structure.

[0233] The configuration of the insulating layer 110 can be applied to other configuration examples.

[0234] [Semiconductor Layer 108] Metal oxides that can be used for the semiconductor layer 108 will be specifically described.

[0235] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0236] As described above, the metal oxide preferably contains indium. Indium oxide can be suitably used as the metal oxide. By using indium oxide for the semiconductor layer 108, a transistor with large on-state current can be obtained.

[0237] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0238] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0239] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0240] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0241] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0242] For example, compared to indium tin oxide (ITO), indium tin oxide (ITSO) containing silicon is less likely to form a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide (ITSO) containing silicon is used for the semiconductor layer 108, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0243] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0244] The composition of the semiconductor layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the lower detection limit.

[0245] The metal oxide layer can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide layer is formed by sputtering, the composition of the formed metal oxide layer may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide layer may decrease to about 50% of the zinc content in the sputtering target.

[0246] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0247] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0248] The CAAC-OS has a plurality of layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b and layered crystals parallel or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface where the semiconductor layer 108 is formed, in the opening 141. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0249] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0250] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for formation or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0251] When a metal oxide is used for the semiconductor layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, it is necessary to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the ＯBy using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0252] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0253] A region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of a source region and a drain region of the transistor 100, and a region of the semiconductor layer 108 in contact with the conductive layer 112b functions as the other. The source region and the drain region have lower electrical resistance than the channel formation region. The source region and the drain region can also be said to have a higher carrier concentration or a higher oxygen defect density than the channel formation region.

[0254] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0255] The semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0256] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0257] The semiconductor layer 108 can have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers included in the semiconductor layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0258] [Opening 141, Opening 143] The top surface shapes of openings 141 and 143 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 10A and other figures, the top surface shapes of openings 141 and 143 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0259] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface end portion of the insulating layer 110 on the opening 141 side. Also, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion of the conductive layer 112b on the opening 143 side.

[0260] As shown in FIG. 10A and other figures, the top shapes of the openings 141 and 143 can be identical or substantially identical to each other. In this case, as shown in FIGS. 10B and 10C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be identical or substantially identical to the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. The top shapes of the openings 141 and 143 can also be configured to not be identical to each other. When the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 can also be concentric. Alternatively, the openings 141 and 143 can be configured not to be concentric.

[0261] The channel length and channel width of the transistor 100 will be described with reference to FIGS. 15A and 15B.

[0262] In FIG. 15B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110c on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110c of the insulating layer 110c and the angle θ110 between the side surface of the insulating layer 110c on the opening 141 side and the surface on which the insulating layer 110c is to be formed (here, the upper surface of the insulating layer 110b). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0263] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0264] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0265] The channel length L100 can be controlled by adjusting the thickness T110c and angle θ110 of the insulating layer 110c.

[0266] The thickness T110c of the insulating layer 110c can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0267] When the angle θ110 is 90 degrees or less, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0268] 15B and the like, the angle θ110 is shown as being less than 90 degrees; however, one embodiment of the present invention is not limited to this. The angle θ110 can be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0269] 10B and the like show a structure in which the shape of the side surface of the insulating layer 110 on the opening 141 side is straight in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side can be curved. Alternatively, a structure having both a straight region and a curved region in the shape of the side surface is also possible.

[0270] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110c, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141 or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).

[0271] 15A and 15B, the width D141 of the opening 141 is indicated by a two-dot chain line with a double-headed arrow. FIG. 15A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the length of the circumference of the circle. In other words, the channel width W100 is π×D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0272] The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three points of the insulating layer 110c (or the insulating layer 110) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be any one of the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these three points of the insulating layer 110c (or the insulating layer 110) in a cross-sectional view.

[0273] When the opening 141 is formed using lithography, the width D141 of the opening 141 is equal to or greater than the minimum exposure dimension of the exposure device. The width D141 can be, for example, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0274] Note that although the example in which the region of the semiconductor layer 108 in contact with the insulating layer 110c functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110b may also function as a channel formation region. Similarly, the region in contact with the insulating layer 110d may also function as a channel formation region.

[0275] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0276] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be formed using an oxide conductor.

[0277] The conductive layers 112a, 112b, and 104 can each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0278] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0279] Note that the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be formed using the same material, or at least one of them can be formed using a different material.

[0280] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a and the conductive layer 112b, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor.

[0281] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108.

[0282] The conductive layer 112 a and the conductive layer 112 b can each be formed using any of the above-described oxide conductors, such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium.

[0283] The conductive layer 112a and the conductive layer 112b may each be formed using a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 may also be formed using any of the nitride conductors described above.

[0284] [Substrate 102] The material of the substrate 102 is not particularly limited, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0285] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0286] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0287] The configuration of the insulating layer 106 shown here can also be applied to other configuration examples.

[0288] 17A and 17B are cross-sectional views of a semiconductor device 20D according to one embodiment of the present invention. For a top view of the semiconductor device 20D, refer to FIG. 10A . FIG. 17A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 10A , and FIG. 17B is a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG. 10A .

[0289] The semiconductor device 20D includes a transistor 100, an insulating layer 110, and an insulating layer 109. The semiconductor device 20D differs from the semiconductor device 20C shown in FIG. 13A and other drawings mainly in that the semiconductor device 20D includes the insulating layer 109 between the substrate 102 and the conductive layer 112a.

[0290] An insulating layer 109 is provided over the substrate 102, a conductive layer 112a is provided over the insulating layer 109, and an insulating layer 110 is provided over the conductive layer 112a. The insulating layer 109 has regions in contact with a lower surface of the conductive layer 112a and a lower surface of the insulating layer 110. The conductive layer 112a has regions in contact with each of the insulating layers 109 and 110 and sandwiched therebetween. The insulating layer 110 has regions in contact with a top surface and side surfaces of the conductive layer 112a, a top surface of the insulating layer 109, a side surface of the semiconductor layer 108, a bottom surface of the conductive layer 112b, and a bottom surface of the insulating layer 106.

[0291] The insulating layer 109 is preferably formed using a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. The insulating layer 109 can be formed using the same material as the insulating layer 110a and the insulating layer 110e. For example, the insulating layer 109 can be formed using silicon nitride or silicon nitride oxide.

[0292] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a also diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a. This reduces the electrical resistance of the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, that is, one of the source region and the drain region. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0293] When a metal oxide is used for the semiconductor layer 108, the impurities released from the insulating layer 109 preferably contain hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 108 through the conductive layer 112a increases the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a, thereby reducing the electrical resistance of one of the source and drain regions.

[0294] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 112a. For example, when a metal oxide is used for the conductive layer 112a, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 108.

[0295] The materials that can be used for the conductive layer 112a are as described above. Note that the conductive layer 112a preferably easily transmits impurities and more preferably does not easily adsorb impurities.

[0296] The insulating layer 110b has a region in contact with the top surface of the insulating layer 109 and the top surface and side surfaces of the conductive layer 112a, which can suppress diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 through the insulating layer 110c.

[0297] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110b. The film density of the insulating layer 110b is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110a and 110e can be referred to.

[0298] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110c to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110c, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0299] 17A and other drawings show the insulating layer 110 having a four-layer structure including the insulating layer 110b, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a structure including the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110e. Alternatively, the insulating layer 110 can have a structure including the insulating layer 110b, the insulating layer 110c, and the insulating layer 110d.

[0300] The structure of the insulating layer 109 shown here can also be applied to other structure examples.

[0301] 18A is a cross-sectional view of a semiconductor device 20E according to one embodiment of the present invention. For a top view of the semiconductor device 20E, refer to FIG. 10A. FIG. 18A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 10A.

[0302] The semiconductor device 20E includes a transistor 100D and an insulating layer 110. The transistor 100D differs mainly from the transistor 100 shown in FIG. 17A and the like in that the semiconductor layer 108 has a stacked structure.

[0303] FIG. 18A shows a configuration in which the semiconductor layer 108 has a three-layer structure including a semiconductor layer 108a, a semiconductor layer 108b on the semiconductor layer 108a, and a semiconductor layer 108c on the semiconductor layer 108b.

[0304] The semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c can each be formed using the materials listed for the semiconductor layer 108. The semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c each preferably contain a metal oxide that exhibits semiconductor properties.

[0305] The band gap of each of the first metal oxide in the semiconductor layer 108a, the second metal oxide in the semiconductor layer 108b, and the third metal oxide in the semiconductor layer 108c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0306] The band gap of the first metal oxide is preferably larger than that of the second metal oxide. The band gap of the third metal oxide is preferably larger than that of the second metal oxide. The semiconductor layer 108b is sandwiched between the semiconductor layers 108a and 108c, which have larger band gaps than the semiconductor layer 108b, to form a buried channel. As a result, the main current path in the semiconductor layer 108 is the semiconductor layer 108b.

[0307] The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

[0308] The conduction band minimum of the first metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0309] The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, analysis can be performed by combining a plurality of these techniques. The electron affinity or the conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0310] Trap levels due to impurities or defects can be formed at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of an etchant or etching gas used to form the opening 141, and components of the conductive layers 112a and 112b that are attached to the side surfaces of the insulating layer 110 when the opening 141 is formed. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be kept away from the trap levels.

[0311] Damage may occur to the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity when the insulating layer 106 is formed. As a result, trap states may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity. By providing the semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be kept away from the trap states.

[0312] By sandwiching the semiconductor layer 108b, which is the main current path of the semiconductor layer 108, between the semiconductor layer 108a and the semiconductor layer 108c, it is possible to reduce trap levels at the interface of the semiconductor layer 108b and in the vicinity of the interface. This makes it possible to provide a transistor with high on-state current and high reliability. Therefore, it is possible to provide a semiconductor device that achieves both high-speed operation and high reliability.

[0313] The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The composition of the third metal oxide is preferably different from the composition of the second metal oxide. By varying the compositions of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

[0314] The indium content of the second metal oxide is preferably higher than the indium content of the first metal oxide and the indium content of the third metal oxide, thereby enabling a transistor with a large on-state current to be obtained.

[0315] For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 (atomic ratio) or thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide may be the same as or partially or entirely different from one another. When one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, each of the elements M may be the same as or partially or entirely different from the elements M contained in the other metal oxides.

[0316] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:40 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0317] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Zn=1:4 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0318] The thickness of the semiconductor layer 108b is preferably thicker than the thickness of the semiconductor layer 108a and thicker than the thickness of the semiconductor layer 108c. By increasing the thickness of the semiconductor layer 108b, which is the main current path, a transistor with a large on-state current can be obtained. However, if the thickness is too thick, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. The thickness of the semiconductor layer 108b is preferably 1 nm to 50 nm, more preferably 3 nm to 30 nm, further preferably 3 nm to 20 nm, further preferably 5 nm to 20 nm, and further preferably 5 nm to 15 nm.

[0319] The thickness of the semiconductor layer 108c is preferably thicker than the thickness of the semiconductor layer 108a. By increasing the thickness of the semiconductor layer 108c, trap states that may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and in the vicinity thereof can be separated from the semiconductor layer 108b. Furthermore, damage to the semiconductor layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness of the semiconductor layer 108c is too thick, the distance between the conductive layer 104, which functions as a gate electrode, and the semiconductor layer 108b becomes long, which may result in a small on-state current. The thickness of the semiconductor layer 108c is preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, even more preferably 1 nm to 10 nm, and even more preferably 2 nm to 10 nm.

[0320] Oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b through the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a is easily permeable to oxygen. By making the thickness of the semiconductor layer 108a thinner than that of the semiconductor layer 108c, oxygen contained in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This reduces oxygen vacancies (V Ｏ ) and V ＯH can be reduced. If the thickness of the semiconductor layer 108a is too thin, the distance between the interface between the insulating layer 110 and the semiconductor layer 108 and the trap level at or near the interface and the semiconductor layer 108b, which is the main current path, becomes short, which may result in a small on-state current. Furthermore, reliability may be deteriorated. The thickness of the semiconductor layer 108a is preferably 0.1 nm to 10 nm, more preferably 0.3 nm to 5 nm, further preferably 0.5 nm to 5 nm, and further preferably 0.5 nm to 3 nm.

[0321] It is more preferable that the semiconductor layers 108a, 108b, and 108c each have crystallinity. When the semiconductor layer 108a has crystallinity, the crystallinity of the semiconductor layer 108b formed thereon can be increased. Similarly, when the semiconductor layer 108b has crystallinity, the crystallinity of the semiconductor layer 108c formed thereon can be increased.

[0322] The band gap of the first metal oxide and the band gap of the third metal oxide may be different.

[0323] The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the semiconductor layer 108c located on the conductive layer 104 side functioning as the gate electrode, generation and induction of carriers in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (the insulating layer 106 here) can be suppressed, thereby making the transistor highly reliable. For example, generation and induction of carriers in the semiconductor layer 108c and at the interface thereof due to light incident on the transistor can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor due to light.

[0324] The semiconductor layer 108a has regions in contact with the conductive layers 112a and 112b, which function as a source electrode and a drain electrode. By making the band gap of the first metal oxide in the semiconductor layer 108a smaller than the band gap of the third metal oxide, the contact resistance between the semiconductor layer 108a and the conductive layer 112a and the contact resistance between the semiconductor layer 108a and the conductive layer 112b can be reduced. Therefore, a transistor with a large on-state current can be obtained.

[0325] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

[0326] The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide, thereby making it possible to make the band gap of the third metal oxide larger than the band gap of the first metal oxide.

[0327] When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout.

[0328] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition.

[0329] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout.

[0330] 18A illustrates an example in which the semiconductor layer 108 has a three-layer structure including semiconductor layers 108a, 108b, and 108c, but one embodiment of the present invention is not limited to this. For example, a structure without one or both of the semiconductor layers 108a and 108c is also possible. Specifically, as shown in FIG. 18B, the semiconductor layer 108 can have a two-layer structure including semiconductor layers 108a and 108b. Alternatively, as shown in FIG. 18C, the semiconductor layer 108 can have a two-layer structure including semiconductor layers 108b and 108c. Alternatively, the semiconductor layer 108 can have a stacked structure of four or more layers.

[0331] The structure of the semiconductor layer 108 shown here can also be applied to other structure examples.

[0332] Here, a structural example in which the metal oxide layer 21 described in Embodiment 1 is applied to a VFET is shown, but one embodiment of the present invention is not limited thereto. The metal oxide layer 21 can also be applied to a planar transistor.

[0333] 19A is a top view of a semiconductor device 20F according to one embodiment of the present invention, FIG. 19B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 19A , and FIG. 19C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG.

[0334] The semiconductor device 20F includes a transistor 200A. The transistor 200A includes an insulating layer 202 over a substrate 102 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also includes an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also includes a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap with each other with the insulating layer 204 interposed therebetween.

[0335] The metal oxide layer 21 described in Embodiment 1 can be applied to the semiconductor layer 203. For the semiconductor layer 203, the descriptions of the metal oxide layer 21 and the semiconductor layer 108 can be referred to. The insulating layer 202, which is a surface on which the semiconductor layer 203 is formed, corresponds to the layer 31 described in Embodiment 1. The insulating layer 202 includes a region 202D containing the first element. The region 202D is located in a region of the insulating layer 202 that does not overlap with the semiconductor layer 203. For the region 202D, the description of the region 31D can be referred to.

[0336] The semiconductor layer 203 has a region 203P, a channel formation region 203Q, and a region 203R. The region 203P functions as one of a source region and a drain region. The region 203R functions as the other of the source region and the drain region. In the semiconductor layer 203, a region overlapping with the conductive layer 205 functions as the channel formation region 203Q. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating layer of the transistor 200A.

[0337] The length of the channel formation region 203Q in the X direction is the channel length L of the transistor 200A (see FIG. 19B), and the length of the channel formation region 203Q in the Y direction is the channel width W of the transistor 200A (see FIG. 19C).

[0338] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203P of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203R of the semiconductor layer 203.

[0339] A conductive layer 208a is provided to cover the opening 207a, and a conductive layer 208b is provided to cover the opening 207b. The conductive layer 208a is connected to the region 203P of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is connected to the region 203R of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of the source and drain electrodes of the transistor 200A, and the conductive layer 208b functions as the other of the source and drain electrodes of the transistor 200A.

[0340] An insulating layer 209 is provided over the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0341] 20A to 20C show examples of structures different from those shown in FIGS. 20A to 20C . Fig. 20A is a top view of a semiconductor device 20G according to one embodiment of the present invention. Fig. 19B is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in Fig. 19A , and Fig. 19C is a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in Fig. 19A .

[0342] The semiconductor device 20G includes a transistor 200B. The transistor 200B differs from the transistor 200A mainly in that a conductive layer 219 is provided between the substrate 102 and the insulating layer 202. The conductive layer 219 functions as a backgate electrode of the transistor 200B. The conductive layer 219 is provided in a position overlapping with the channel formation region 203Q. The conductive layer 219 preferably extends beyond the end of the channel formation region 203Q. That is, the conductive layer 219 preferably covers the channel formation region 203Q. Covering the channel formation region 203Q with the conductive layer 219 can enhance the effect of preventing an electric field generated outside the transistor from acting on the channel formation region (also referred to as an electric field shielding effect). The insulating layer 202 functions as a backgate insulating layer of the transistor 200B.

[0343] 21A is a top view of a semiconductor device 20H according to one embodiment of the present invention, FIG. 21B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 21A , and FIG. 21C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG.

[0344] The semiconductor device 20H includes a transistor 200C. The transistor 200C includes a semiconductor layer 520a disposed on the substrate 102, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, and an insulating layer 550 disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, and the insulating layer 580. As shown in FIGS. 21B and 21C , the top surface of the conductive layer 560 is substantially flush with the top surfaces of the insulating layers 550 and 580. The semiconductor layers 520a and 520b may be collectively referred to as the semiconductor layer 520. The conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0345] 21A to 21C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, and the conductive layer 542b and the insulating layer 580. The insulating layer 554 is in contact with the side surface of the insulating layer 550, the top surface and side surface of the conductive layer 542a, the top surface and side surface of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0346] The metal oxide layer 21 described in Embodiment 1 can be applied to the semiconductor layer 520. For the semiconductor layer 520, the descriptions of the metal oxide layer 21 and the semiconductor layer 108 can be referred to. The insulating layer 524, which is a surface on which the semiconductor layer 520 is to be formed, corresponds to the layer 31 described in Embodiment 1. The insulating layer 524 includes a region 524D containing the first element. The region 524D is located in a region of the insulating layer 524 that does not overlap with the semiconductor layer 520. For the region 524D, the description of the region 31D can be referred to.

[0347] Although the transistor 200C has a two-layer structure of the semiconductor layer 520a and the semiconductor layer 520b in the channel formation region and its vicinity, the present invention is not limited to this. For example, a single-layer structure or a stacked structure of three or more layers may be provided. Furthermore, each of the semiconductor layer 520a and the semiconductor layer 520b may have a stacked structure of two or more layers.

[0348] Here, the conductive layer 560 functions as the gate electrode of the transistor, and the conductive layers 542a and 542b function as source and drain electrodes, respectively. As described above, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and in the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200C, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200C. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0349] 21A to 21C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 in the transistor 200C has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0350] The transistor 200C includes an insulating layer 202 disposed on the substrate 102, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0351] An insulating layer 574 and an insulating layer 581 functioning as interlayer films are provided over the transistor 200C. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the insulating layer 554, and the insulating layer 580.

[0352] The insulating layers 522, 554, and 574 may be insulating layers having a function of suppressing diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, and the like). For example, the insulating layers 522, 554, and 574 may be insulating layers having lower hydrogen permeability than the insulating layers 524, 550, and 580. The insulating layers 522 and 554 may be insulating layers having a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulating layers 522 and 554 may be insulating layers having lower oxygen permeability than the insulating layers 524, 550, and 580.

[0353] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0354] 21B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200C and functioning as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 functioning as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 21B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0355] Here, the height of the top surface of the conductive layer 545 and the height of the top surface of the insulating layer 581 can be approximately the same. Note that although the transistor 200C shows a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0356] The thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a region with low electrical resistance may be formed near the interface with the conductive film. In this way, removing the region with low electrical resistance located between the conductive layers 542a and 542b on the top surface of the semiconductor layer 520b can prevent a channel from being formed in that region.

[0357] Next, the detailed structure of the transistor 200C that can be used in the semiconductor device of one embodiment of the present invention will be described.

[0358] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0359] The conductive layer 505 includes a conductive layer 505a and a conductive layer 505b. The conductive layer 505a is provided in contact with the bottom surface and sidewalls of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to be embedded in a recess formed in the conductive layer 505a. The height of the top surface of the conductive layer 505b is approximately the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0360] The conductive layer 505a is made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ A conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is used.

[0361] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 505a, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 via the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layer 505a, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0362] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0363] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 21C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0364] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0365] The conductive layer 505 may be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, the present invention is not limited to this, and a conductive layer that functions as a wiring may be provided under the conductive layer 505.

[0366] The insulating layer 514 may be formed using an insulating material that functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 200C from the substrate side. Therefore, the insulating layer 514 may be formed using an insulating material that functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 200C from the substrate side. ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., impurities are difficult to permeate), or an insulating material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is difficult to permeate).

[0367] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200C. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0368] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, are preferably made of an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0369] When the conductive layer 560 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0370] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like can be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200C is improved.

[0371] 21C , the thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b may be thinner than the thickness of the other region. The thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b is preferably set to a thickness that allows sufficient diffusion of the oxygen.

[0372] As the insulating layer 522, like the insulating layer 514, a material that functions as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 200C from the substrate side is used. For example, a material that has lower hydrogen permeability than the insulating layer 524 is used for the insulating layer 522. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200C from the outside.

[0373] Furthermore, the insulating layer 522 is preferably made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., a material through which the oxygen is less likely to permeate). For example, the insulating layer 522 is made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, which can reduce oxygen diffusing from the semiconductor layer 520 toward the substrate. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0374] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200C.

[0375] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layers. For example, the insulating layer 522 may have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0376] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as BST may be used as a single layer or a laminate. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0377] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0378] The semiconductor layer 520 includes a semiconductor layer 520a and a semiconductor layer 520b on the semiconductor layer 520a. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. The content of element M in the semiconductor layer 520a is preferably higher than the content of element M in the semiconductor layer 520b.

[0379] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0380] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200C. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0381] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520b. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0382] As the insulating layer 550, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similarly to the insulating layer 524. The thickness of the insulating layer 550 is 1 nm to 20 nm.

[0383] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0384] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 21A to 21C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0385] The conductive layer 560a is formed of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0386] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress oxidation of the conductive layer 560b by oxygen contained in the insulating layer 550. This can suppress a decrease in the conductivity of the conductive layer 560b. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0387] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0388] 21B and 21C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200C, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200C and improves its frequency characteristics.

[0389] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200C from the insulating layer 580 side. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 21B and 21C , the insulating layer 554 is provided in contact with the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layers 520a and 520b, and the top surface of the insulating layer 524. With this structure, hydrogen contained in the insulating layer 580 can be prevented from entering the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layers 542a, 542b, the semiconductor layers 520a, 520b, and the insulating layer 524.

[0390] Furthermore, an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., is less permeable to oxygen) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0391] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0392] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0393] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0394] The insulating layer 574, like the insulating layer 514, is made of an insulating material that functions as a barrier film that prevents impurities such as water or hydrogen from entering the insulating layer 580 from above. The insulating layer 574 is made of an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0395] 21A to 21C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524 and the like.

[0396] The conductive layers 545a and 545b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided opposite to each other with the conductive layer 560 interposed therebetween. Note that the height of the top surfaces of the conductive layers 545a and 545b may be flush with the top surface of the insulating layer 581.

[0397] Note that an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the openings, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the openings, and the conductive layer 545b is in contact with the conductive layer 542b.

[0398] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b may have a stacked structure of two or more layers.

[0399] When the conductive layer 545 has a stacked structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used for the conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0400] The insulating layers 541a and 541b can be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layers 541a and 541b are provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0401] 22A is a top view of a semiconductor device 20I according to one embodiment of the present invention. FIG. 22B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 22A , FIG. 22C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4, and FIG. 22D shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6.

[0402] The semiconductor device 20I includes a transistor 200D. Fig. 22B is a cross-sectional view of the transistor 200D in the channel length direction. Fig. 22C and Fig. 22D are cross-sectional views of the transistor 200D in the channel width direction.

[0403] The transistor 200D includes a conductive layer 505 (conductive layer 505a and conductive layer 505b) provided to be embedded in the insulating layer 816, an insulating layer 521 on the insulating layer 816 and the conductive layer 505, an insulating layer 522 on the insulating layer 521, an insulating layer 524 on the insulating layer 522, a semiconductor layer 520 (semiconductor layer 520a and semiconductor layer 520b) on the insulating layer 524, a conductive layer 542a (conductive layer 542a1 and conductive layer 542a2) and a conductive layer 542b (conductive layer 542b1 and conductive layer 542b2) on the semiconductor layer 520, an insulating layer 871a on the conductive layer 542a, an insulating layer 871b on the conductive layer 542b, an insulating layer 850 on the semiconductor layer 520, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) on the insulating layer 850.

[0404] The metal oxide layer 21 described in Embodiment 1 can be applied to the semiconductor layer 520. For the semiconductor layer 520, the descriptions of the metal oxide layer 21 and the semiconductor layer 108 can be referred to. The insulating layer 524, which is a surface on which the semiconductor layer 520 is to be formed, corresponds to the layer 31 described in Embodiment 1. The insulating layer 524 includes a region 524D containing the first element. The region 524D is located in a region of the insulating layer 524 that does not overlap with the semiconductor layer 520. For the region 524D, the description of the region 31D can be referred to.

[0405] An insulating layer 875 is provided over the insulating layers 871a and 871b, and an insulating layer 885 is provided over the insulating layer 875. The insulating layer 855, the insulating layer 850, and the conductive layer 560 are disposed inside openings provided in the insulating layer 885 and the insulating layer 875. An insulating layer 882 is provided over the insulating layer 885 and the conductive layer 560. An insulating layer 883 is provided over the insulating layer 882. An insulating layer 815 is provided under the insulating layer 816 and the conductive layer 505. An insulating layer 855 is provided between the insulating layer 850 and the conductive layer 542a2, the conductive layer 542b2, the insulating layer 871a, the insulating layer 871b, the insulating layer 875, and the insulating layer 885.

[0406] Note that insulating layer 815, insulating layer 816, conductive layer 505, insulating layer 521, insulating layer 522, insulating layer 524, semiconductor layer 520, conductive layer 542a, conductive layer 542b, insulating layer 871a, insulating layer 871b, insulating layer 875, insulating layer 885, insulating layer 855, insulating layer 850, conductive layer 560, insulating layer 882, and insulating layer 883 may each have a single-layer structure or a stacked-layer structure.

[0407] The semiconductor layer 520 has a region that functions as a channel formation region. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode). The insulating layer 850 has a region that functions as a first gate insulator. The conductive layer 505 has a region that functions as a second gate electrode (lower gate electrode). The insulating layer 524, the insulating layer 522, and the insulating layer 521 each have a region that functions as a second gate insulator.

[0408] The conductive layer 542a has a region which functions as one of a source electrode and a drain electrode, and the conductive layer 542b has a region which functions as the other of the source electrode and the drain electrode.

[0409] The semiconductor layer 520 preferably includes a semiconductor layer 520a on the insulating layer 524 and a semiconductor layer 520b on the semiconductor layer 520a. By including the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Note that the semiconductor layer 520 may have a single-layer structure of the semiconductor layer 520b, or may have a stacked structure of three or more layers.

[0410] The conductive layer 542a has a stacked structure of a conductive layer 542a1 and a conductive layer 542a2, and the conductive layer 542b has a stacked structure of a conductive layer 542b1 and a conductive layer 542b2. The conductive layers 542a1 and 542b1 in contact with the semiconductor layer 520b are preferably made of a conductor that is resistant to oxidation, such as a metal nitride. This prevents the conductive layers 542a and 542b from being excessively oxidized by oxygen contained in the semiconductor layer 520b. The conductive layers 542a2 and 542b2 are preferably made of a conductor such as a metal layer that has higher conductivity than the conductive layers 542a1 and 542b1. This allows the conductive layers 542a and 542b to function as highly conductive wirings or electrodes.

[0411] For example, the conductive layers 542a1 and 542b1 can be made of tantalum nitride or titanium nitride, and the conductive layers 542a2 and 542b2 can be made of tungsten.

[0412] The openings in the insulating layer 885 and the insulating layer 875 overlap with the region between the conductive layer 542a2 and the conductive layer 542b2. In a plan view, the side surfaces of the openings in the insulating layer 885 coincide or substantially coincide with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2. Furthermore, portions of the conductive layers 542a1 and 542b1 are formed to protrude into the openings. Here, a portion of the top surface of the conductive layer 542a1 contacts the conductive layer 542a2, and a portion of the top surface of the conductive layer 542b1 contacts the conductive layer 542b2. Therefore, the insulating layer 855 contacts another portion of the top surface of the conductive layer 542a1, another portion of the top surface of the conductive layer 542b1, the side surfaces of the conductive layer 542a2, and the side surfaces of the conductive layer 542b2 within the openings. The insulating layer 850 is in contact with the top surface of the semiconductor layer 520 , the side surface of the conductive layer 542 a 1 , the side surface of the conductive layer 542 b 1 , and the side surface of the insulating layer 855 .

[0413] The insulating layer 855 is preferably an insulator that is resistant to oxidation, such as nitride. The insulating layer 855 is formed by anisotropic etching so as to be in contact with the sidewalls of the openings (here, the sidewalls of the openings correspond to, for example, the side surfaces of the insulating layer 885) provided in the insulating layer 885 or the like. The insulating layer 855 is formed in contact with the side surfaces of the conductive layers 542a2 and 542b2 and has a function of protecting the conductive layers 542a2 and 542b2. In order to supply oxygen to the semiconductor layer 520b, heat treatment is preferably performed in an oxygen-containing atmosphere after the conductive layers 542a1 and 542b1 are separated and before the insulating layer 850 is formed. At this time, since the insulating layer 855 is formed in contact with the side surfaces of the conductive layers 542a2 and 542b2, excessive oxidation of the conductive layers 542a2 and 542b2 can be prevented. For example, the insulating layer 855 can be made of silicon nitride.

[0414] The insulating layer 850 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 520b. Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0415] The insulating layer 850 functions as a gate insulator. The insulating layer 850, together with the insulating layer 855 and the conductive layer 560, is provided in an opening formed in the insulating layer 885. To miniaturize the transistor 200D, the insulating layer 850 preferably has a small thickness. The thickness of each of the layers constituting the insulating layer 850 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each layer constituting the insulating layer 850 preferably has a region with the above thickness in at least a portion thereof.

[0416] The insulating layer 850 is preferably formed by an ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma-enhanced ALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0417] The thickness of the insulating layer 855 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and still more preferably 0.5 nm to 3 nm. By setting the insulating layer 855 to the above thickness, excessive oxidation of the conductive layer 542a2 and the conductive layer 542b2 can be suppressed. Note that the insulating layer 855 preferably has a region with the above thickness in at least a portion. If the insulating layer 855 is excessively thick, the deposition time of the insulating layer 855 by the ALD method increases, resulting in reduced productivity. Therefore, the thickness of the insulating layer 855 is preferably within the above range.

[0418] The insulating layer 815, the insulating layer 521, the insulating layer 522, the insulating layer 882, and the insulating layer 883 each preferably include an insulator that suppresses the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layer 883 and the insulating layer 521 are preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, for example, the insulating layer 882 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulating layer 522 is preferably made of hafnium oxide, which is a high-dielectric-constant (high-k) material and has a high ability to capture or fix hydrogen.

[0419] The conductive layer 505 is disposed so as to overlap with the semiconductor layer 520 and the conductive layer 560. Here, the conductive layer 505 is preferably provided so as to be embedded in an opening formed in the insulating layer 816. Furthermore, the conductive layer 505 is preferably provided so as to extend in the channel width direction as shown in FIGS. 22A and 22C. With such a structure, the conductive layer 505 functions as a wiring when a plurality of transistors are provided.

[0420] 22B and 22C , the conductive layer 505 preferably includes a conductive layer 505a and a conductive layer 505b. The conductive layer 505a is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 505b is provided so as to fill a recess in the conductive layer 505a formed along the opening. Here, the height of the upper surface of the conductive layer 505 coincides with or approximately coincides with the height of the upper surface of the insulating layer 816.

[0421] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 505a, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 816 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 505a, oxidation of the conductive layer 505b and a decrease in conductivity can be suppressed. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 505a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 505a preferably contains titanium nitride.

[0422] The conductive layer 505b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0423] The conductive layer 505 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200D can be controlled by changing the potential applied to the conductive layer 505 independently of the potential applied to the conductive layer 560. In particular, applying a negative potential to the conductive layer 505 can increase the Vth of the transistor 200D and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 505 can reduce the drain current when the potential applied to the conductive layer 560 is 0 V, compared to when no negative potential is applied.

[0424] The insulating layer 524 in contact with the semiconductor layer 520 preferably contains, for example, silicon oxide or silicon oxynitride, so that oxygen can be supplied from the insulating layer 524 to the semiconductor layer 520 and oxygen vacancies can be reduced.

[0425] Note that the insulating layer 524 can be formed in an island shape, similar to the semiconductor layer 520. As a result, when a plurality of transistors 200D are provided, each transistor 200D has an insulating layer 524 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 524 to the semiconductor layer 520 in each transistor 200D becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200D within the substrate surface can be suppressed.

[0426] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for each of the conductive layers 542a, 542b, and 560. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 542a, 542b, and 560.

[0427] The insulating layers 871a and 871b are inorganic insulators that function as etching stoppers and protect the conductive layers 542a2 and 542b2 when the conductive layers 542a2 and 542b2 are processed. Furthermore, since the insulating layers 871a and 871b are in contact with the conductive layers 542a2 and 542b2, they are preferably inorganic insulators that do not easily oxidize the conductive layers 542a and 542b. The insulating layers 871a and 871b preferably have a stacked structure of, for example, a nitride insulator and an oxide insulator.

[0428] The conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. The conductive layer 560a has the function of suppressing oxygen diffusion, which can suppress oxidation of the conductive layer 560b by oxygen contained in the insulating layer 885, etc. This can suppress a decrease in the conductivity of the conductive layer 560b. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0429] The conductive layer 560b is preferably formed using a conductor with high conductivity. For example, the conductive layer 560b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0430] The insulating layers 816 and 885 preferably have a dielectric constant lower than that of the insulating layer 522. When a material with a low dielectric constant is used as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0431] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0432] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described.

[0433] 23A to 26C show a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 in FIG.

[0434] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be preferably formed by a sputtering method or a PECVD method.

[0435] Next, a conductive film to be the conductive layer 112a is formed over the insulating layer 109 and processed to form the conductive layer 112a (FIG. 23A). The conductive film can be preferably formed by a sputtering method.

[0436] Subsequently, an insulating film 110bf that will become the insulating layer 110b and an insulating film 110cf that will become the insulating layer 110c are formed on the conductive layer 112a (FIG. 23B).

[0437] The insulating films 110bf and 110cf can be preferably formed by sputtering or PECVD. After forming the insulating film 110bf, it is preferable to form the insulating film 110cf without exposing the surface of the insulating film 110bf to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110bf. Examples of such impurities include water and organic substances. For example, it is preferable to form the insulating film 110cf continuously using the same device after forming the insulating film 110bf.

[0438] The substrate temperature during the formation of the insulating film 110bf and the insulating film 110cf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, even more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating film 110bf and the insulating film 110cf within the above-mentioned range, the amount of impurities (e.g., water and hydrogen) released from the insulating film 110bf and the insulating film 110cf can be reduced, and the diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0439] Since the insulating films 110bf and 110cf are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to heat applied during the formation of the insulating films 110bf and 110cf.

[0440] After the insulating films 110bf and 110cf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110bf and from the insulating films 110cf and their surfaces.

[0441] After the insulating film 110cf is formed, oxygen can be supplied to the insulating film 110cf. Examples of a method for supplying oxygen include ion implantation, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ The plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment.

[0442] After the insulating film 110cf is formed, nitrogen can be supplied to the insulating film 110cf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0443] In the insulating layer (here, the insulating film 110cf or the later insulating layer 110c), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO and NO ２In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level at which the charge of the indium oxide changes between a 0 state and a -1 state is located within the band gap of indium oxide. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer and the semiconductor layer having the metal oxide or near the interface, the level traps electrons. As a result, the trapped electrons remain at the interface between the insulating layer and the semiconductor layer or near the interface, and the threshold voltage of the transistor can be increased in the positive direction. This allows a normally-off transistor to be obtained, resulting in a semiconductor device with low power consumption.

[0444] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0445] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of released nitrogen oxides in thermal desorption spectrometry (TDS) or the amount of electron spins in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (m / z) = 30), N ２ O (m / z=44), and NO ２ (m / z=46) can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0446] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0447] After the insulating film 110cf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110cf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110cf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110cf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0448] Next, a film 139 is preferably formed on the insulating film 110cf ( FIG. 23D ). The film 139 can be formed by a sputtering method. By forming the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110cf. FIG. 23C shows a schematic diagram of oxygen being supplied to the insulating film 110cf using solid arrows.

[0449] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 139.

[0450] The film 139 is preferably formed using an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0451] When forming the film 139, the amount of oxygen supplied to the insulating film 110cf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0452] In this way, by forming the film 139 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110cf during the formation of the film 139, and oxygen desorption from the insulating film 110cf can be prevented. As a result, a large amount of oxygen can be confined in the insulating film 110cf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0453] Heat treatment may be performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110cf.

[0454] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, and even more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being incorporated into the insulating films 110bf and 110cf. The heat treatment can be performed in an oven, a rapid thermal annealing (RTA) apparatus, or the like. By using an RTA device, the heat treatment time can be shortened.

[0455] After the film 139 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110cf through the film 139. Oxygen can be supplied by, for example, ion implantation, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore, detailed description thereof will be omitted.

[0456] Next, the film 139 is removed ( FIG. 23E ). Although there is no particular limitation on the method for removing the film 139, a wet etching method can be suitably used. By using the wet etching method, etching of the insulating film 110cf can be suppressed when removing the film 139. This can suppress the thickness of the insulating film 110cf from becoming thin, and can make the thickness of the insulating layer 110c uniform.

[0457] The process of supplying oxygen to the insulating film 110cf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110cf by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110cf, and then oxygen can be supplied to the insulating film 110cf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0458] Next, an insulating film 110df that will become the insulating layer 110d and an insulating film 110ef that will become the insulating layer 110e are formed on the insulating film 110cf ( FIG. 24A ). The insulating film 110df can be preferably formed by sputtering. The description of the formation of the insulating film 110bf and the insulating layer 109 can be referenced for the formation of the insulating film 110df and the insulating film 110ef, and therefore detailed description thereof will be omitted.

[0459] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating film 110ef (FIG. 24B). The conductive film 112bf can be preferably formed by sputtering.

[0460] Next, the conductive film 112bf is processed to form the conductive layer 112B (FIG. 24C). The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B can be preferably formed by, for example, wet etching.

[0461] Subsequently, a part of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. The conductive layer 112b can be preferably formed by wet etching.

[0462] Subsequently, the insulating films 110bf, 110cf, and 110df are partially removed to form the insulating layer 110 having an opening 141 ( FIG. 24D ). The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 112a. The insulating layer 110 can be preferably formed by dry etching.

[0463] The opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, a resist mask is formed over the conductive layer 112B, part of the conductive layer 112B is removed using the resist mask to form the opening 143, and part of the insulating films 110bf, 110cf, and 110df is removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0464] Next, a metal oxide film 108f to be the semiconductor layer 108 is formed so as to cover the openings 141 and 143 ( FIG. 25A ). The metal oxide film 108f is provided in contact with the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a. The metal oxide film 108f corresponds to the metal oxide film 21f described in Embodiment 1. For the metal oxide film 108f, the description of the metal oxide film 21f can be referred to.

[0465] When the metal oxide film 108f is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied into the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110c, oxygen can be suitably supplied into the insulating layer 110c. By supplying oxygen to the insulating layer 110c, oxygen is supplied to the semiconductor layer 108 in a later step, and oxygen vacancies and V in the semiconductor layer 108 are reduced. Ｏ H can be reduced.

[0466] Subsequently, a resist mask 180 is formed over the metal oxide film 108f (FIG. 25B). The resist mask 180 is provided in a region where the semiconductor layer 108 is to be provided. The resist mask 180 corresponds to the resist mask 90 described in Embodiment 1. For the resist mask 180, the description of the resist mask 90 can be referred to.

[0467] Next, using the resist mask 180 as a mask, the element 75 is supplied to the metal oxide film 108f ( FIG. 25C ). The element 75 is supplied to a region of the metal oxide film 21f that does not overlap with the resist mask 180, forming a region 108D. FIG. 25C schematically shows with dashed arrows how the element 75 is supplied to the metal oxide film 108f. The region 108D corresponds to the region 21D described in Embodiment 1. For the region 108D, the description of the region 21D can be referred to. For the supply of the element 75, the description of Embodiment 1 can be referred to.

[0468] The concentration of element 75 in region 108D is preferably within the range set forth above for region 21D, thereby reducing the crystallinity of region 21D. Note that the concentration of element 75 in region 108D is not limited to the range set forth above.

[0469] The first element is also supplied to regions of the insulating layer 110 and the conductive layer 112b that do not overlap with the resist mask 180, thereby forming regions 110D and 112bD. The regions 110D and 112bD correspond to the region 31D described in Embodiment 1. For the region 110D and the region 112bD, the description of the region 31D can be referred to.

[0470] Subsequently, the region 108D is removed to form the semiconductor layer 108 ( FIG. 26A ). A region of the metal oxide film 108f that overlaps with the resist mask 180 (corresponding to the region 21N in the first embodiment) remains and becomes the semiconductor layer 108. For the removal of the region 108D, the description regarding the removal of the region 21D can be referred to.

[0471] When the semiconductor layer 108 is formed, a portion of the conductive layer 112b in a region that does not overlap with the semiconductor layer 108 may be etched and thinned. Similarly, a portion of the insulating layer 110 in a region that does not overlap with either the semiconductor layer 108 or the conductive layer 112b may be etched and thinned. For example, the insulating layer 110d of the insulating layer 110 may be removed by etching, exposing the surface of the insulating layer 110c. Note that, in etching the metal oxide film 108f, using a material with a high selectivity for the insulating layer 110d can prevent the insulating layer 110d from becoming thin.

[0472] Next, the resist mask 180 is removed (FIG. 26B), thereby exposing the semiconductor layer 108.

[0473] After removing the resist mask 180, heat treatment is preferably performed. The heat treatment can remove water and hydrogen contained in the semiconductor layer 108 or adsorbed on the surface thereof. Furthermore, the heat treatment may improve the film quality of the semiconductor layer 108 (for example, reduce defects or increase crystallinity).

[0474] By the heat treatment, oxygen can also be supplied from the insulating layer 110c to the semiconductor layer 108. In this case, it is preferable to perform the heat treatment before processing into the semiconductor layer 108. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0475] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0476] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (FIG. 26C). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0477] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 106 to the conductive layer 104, thereby suppressing oxidation of the conductive layer 104. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0478] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, causing oxygen vacancies and V in the semiconductor layer 108. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0479] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0480] Subsequently, the conductive layer 104 is formed over the insulating layer 106 (FIGS. 17A and 17B). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0481] Through the above steps, the semiconductor device 20C of one embodiment of the present invention can be manufactured.

[0482] 2 is used to form the semiconductor layer 108, but one embodiment of the present invention is not limited to this. The manufacturing methods shown in the flowcharts of FIGS. 4, 6, and 8 can also be applied. When a metal oxide is used for one or more of the conductive layers 112a, 112b, and 104, the conductive layers can also be formed by the manufacturing methods shown in the flowcharts of FIGS. 2, 4, 6, and 8.

[0483] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0484] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0485] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0486] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0487] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0488] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0489] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0490] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0491] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0492] <Display Device 50A> FIG. 27 shows a perspective view of the display device 50A.

[0493] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 27, the substrate 152 is indicated by a dashed line.

[0494] The display device 50A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 27 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 27 can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0495] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 27 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0496] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0497] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0498] 27 shows an example in which an IC 173 is provided on a substrate 151 by a COG method. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0499] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0500] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0501] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 27 shows an enlarged view of one pixel 201.

[0502] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0503] 27 includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0504] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0505] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0506] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0507] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0508] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0509] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0510] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0511] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0512] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0513] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0514] Figure 28A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0515] 28A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0516] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0517] The display device 50A is a top emission type, which allows transistors and the like to be arranged so as to overlap the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0518] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured in the same process. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0519] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0520] Specifically, the transistors 205D, 205R, 205G, and 205B each include a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, a conductive layer 112a and a conductive layer 112b that function as a source and a drain, a semiconductor layer 108 containing metal oxide, and an insulating layer 110. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0521] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0522] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0523] The display device of this embodiment may have a Si transistor.

[0524] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0525] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0526] In terms of the saturation of the current that flows when a transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0527] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0528] All the transistors included in the display portion 162 may be OS transistors, all the transistors included in the display portion 162 may be Si transistors, or some of the transistors included in the display portion 162 may be OS transistors and the rest may be Si transistors.

[0529] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0530] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0531] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0532] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218.

[0533] The insulating layer 218 preferably functions as a protective layer for the transistor. The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 218 to function as a barrier film. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0534] The insulating layer 218 preferably includes one or more inorganic insulating layers. The insulating layer 218 can be made of the same material as that used for the insulating layer 110.

[0535] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0536] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0537] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 28A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0538] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 28A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0539] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 28A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0540] 28A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element can be improved.

[0541] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0542] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0543] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 50A.

[0544] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0545] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0546] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0547] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof, as appropriate. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0548] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0549] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0550] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 28A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 28A , but this is not limited to this. That is, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap but are spaced apart.

[0551] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0552] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0553] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0554] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth, allowing efficient emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0555] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0556] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0557] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0558] In Figure 28A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0559] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 28A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0560] The protective layer 131 is preferably provided in at least the display portion 162 and is provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162 but also the connection portion 140 and the circuit portion 164. The protective layer 131 is also preferably provided up to the edge of the display device 50A. Meanwhile, in the connection portion 197, a region where the protective layer 131 is not provided is generated in order to connect the FPC 172 and the conductive layer 166.

[0561] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0562] The protective layer 131 can have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0563] The protective layer 131 has an inorganic film, which can prevent the common electrode 115 from being oxidized, suppress impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0564] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0565] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0566] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0567] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0568] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0569] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. In this example, the conductive layer 165 is a conductive layer obtained by processing the same conductive film as the conductive layer 112b. In this example, the conductive layer 166 is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode 111 and the conductive layer 112b. Specifically, FIG. 28A shows an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242.

[0570] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0571] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0572] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0573] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.

[0574] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ By providing a protective layer (layer), it is possible to suppress the occurrence of surface contamination and scratches, which is preferable. Furthermore, DLC (diamond-like carbon), aluminum oxide, polyester-based materials, polycarbonate-based materials, etc. may be used as the surface protective layer. It is preferable to use a material with high transmittance to visible light for the surface protective layer. It is also preferable to use a material with high hardness for the surface protective layer.

[0575] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0576] Substrate 151 and substrate 152 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrate 151 and substrate 152 can be made of glass having a thickness sufficient to provide flexibility.

[0577] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0578] The adhesive layer 142 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0579] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0580] <Display Device 50B> Figure 28B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. The configuration shown in Figure 28B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the end portion configuration shown in Figure 28A. Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.

[0581] A display device 50B shown in FIG. 28B includes light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0582] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0583] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0584] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0585] The light-emitting elements 130R, 130G, and 130B each s...

Claims

forming a crystalline metal oxide film on the layer; forming a mask layer on a first region of the metal oxide film; supplying a first element to the metal oxide film using the mask layer as a mask to form a second region in the metal oxide film that does not overlap with the mask layer and that contains the first element; removing the second region by etching to expose a surface of the layer; the first element is a noble gas; The concentration of the first element in the second region is 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ is as follows: The method for manufacturing a semiconductor device, wherein the layer overlaps with the second region and has a region containing the first element. 　 forming a crystalline metal oxide film on the layer; forming a mask layer on a first region of the metal oxide film; supplying a first element to the metal oxide film using the mask layer as a mask to form a second region in the metal oxide film that does not overlap with the mask layer and that contains the first element; performing a heat treatment to diffuse impurities from the first region into the second region; removing the second region by etching to expose a surface of the layer; the first element is a noble gas; The concentration of the first element in the second region is 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ is as follows: The method for manufacturing a semiconductor device, wherein the layer overlaps with the second region and has a region containing the first element. 　 In claim 2, The method for manufacturing a semiconductor device, wherein the temperature of the heat treatment is 200° C. or more and 450° C. or less. 　 In claim 2, The method for manufacturing a semiconductor device, wherein the impurity is one or more selected from the group consisting of hydrogen, carbon, and hydrocarbon. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the metal oxide film contains indium. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the metal oxide film contains indium and one or more elements selected from the group consisting of gallium, zinc, and tin. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the first element is one or more selected from the group consisting of argon, krypton, and xenon. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the first element is argon. 　 In any one of claims 1 to 4, The method for manufacturing a semiconductor device, wherein the first element is supplied by an ion implantation method. 　 a transistor and a first insulating layer; the transistor includes a first conductive layer, a second conductive layer, and a metal oxide layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the second conductive layer and the first insulating layer have an opening that reaches the first conductive layer; the metal oxide layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the first insulating layer has a first region overlapping the metal oxide layer and a second region not overlapping the metal oxide layer; the second region has a first element; a concentration of the first element in the second region is higher than a concentration of the first element in the first region; The semiconductor device, wherein the first element is one or more selected from the group consisting of argon, krypton, and xenon. 　 In claim 10, The second region does not overlap the second conductive layer. 　 In claim 10 or claim 11, a second insulating layer; the first conductive layer and the first insulating layer are located on the second insulating layer; the first insulating layer has a third insulating layer and a fourth insulating layer on the third insulating layer; the second insulating layer comprises nitrogen; the third insulating layer contains nitrogen; the fourth insulating layer contains oxygen; The second insulating layer has a region having a higher hydrogen concentration than the third insulating layer.

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