Design improvement device, design improvement method, and design improvement program

Abstract

This design improvement device (100) comprises: a status acquisition unit (23) that acquires, in accordance with a prescribed acquisition rule, a usage status of a CPU core (41) to be used when a target application (10) is executing a process; an improvement determination unit (25) that, on the basis of the usage status of the CPU core (41) acquired by the status acquisition unit (23) and a prescribed determination rule, identifies, as improvement information, a cause of excessive consumption of power; and an improvement output unit (26) that outputs the improvement information identified by the improvement determination unit (25).

Description

Design improvement device, design improvement method, and design improvement program

[0001] The present invention relates to a design improvement device, a design improvement method, and a design improvement program.

[0002] With the spread of highly real-time services, there is a demand for low-latency data processing on general-purpose servers. In cases where low-latency processing is particularly required, "pinning" - assigning application threads to specific CPU cores - can reduce latency by avoiding task scheduling conflicts. Examples of pinning are the following settings: - Setting a thread so that it does not run on any core other than the pinned core. - Excluding that core from the OS's scheduling targets so that other threads do not run on that core. - Setting interrupts so that thread-related interrupts are raised only to that core (this setting is optional).

[0003] FIG. 9 is an explanatory diagram showing an example of allocating application threads to CPU cores. Thread #1 is pinned to CPU core #X, thread #2 is pinned to CPU core #Y, and thread #3 is pinned to CPU core #Z. This allows each of threads #1 to #3 to exclusively use one CPU core, thereby achieving high performance and satisfying low-latency performance requirements. With the development of network function virtualization (NFV) and the proliferation of highly real-time services, low-latency data processing is required on general-purpose servers. In cases where low-latency processing is particularly required, allocating application threads to specific CPU cores, as shown in FIG. 9, is effective in avoiding task scheduling conflicts and achieving low latency.

[0004] 10 is an explanatory diagram showing the difference between setting pinning on one CPU core and not setting it. As shown by reference numeral 801, when pinning is not set, the currently running thread switches over time, such as thread #1 → #2 → #1. This switching process (context switch) delays the completion of processing for thread #1. As shown by reference numeral 802, when pinning is set, the currently running thread #1 is not interrupted by other threads from the start to the completion of its operation, and processing is completed with little delay.

[0005] When developing and operating applications that allocate threads to specific cores, developers may adopt the following performance-specific settings to meet latency performance requirements: (Example 1) It is recommended to turn off all power-saving functions of the CPU core to which the application's threads are allocated (disabling the CPU's idle function and operating at a fixed maximum frequency). (Example 2) Utilizing an excess number of CPU cores by dividing / pooling tasks into separate execution threads and allocating dedicated cores to each of them. (Example 3) While enabling the CPU idle function, increasing latency can be prevented by waking up the receiving thread periodically or before the arrival of packets, taking into account the packet arrival interval (Patent Document 1).

[0006] International Publication No. 2023 / 199519

[0007] While performance-specific settings are expected to meet the performance requirements of an application, a side effect is excessive power consumption. Therefore, a method that achieves "minimum power consumption to meet performance requirements" is desirable. However, while conventional power-saving technologies such as those disclosed in Patent Document 1 disclose how to execute power-saving control based on a given power-saving setting, they do not support how to create optimal power-saving settings. An optimal power-saving setting is one that meets performance requirements while also achieving a significant effect in reducing power consumption.

[0008] Therefore, developers must analyze the CPU usage characteristics and task characteristics of their applications to identify the causes of excessive power consumption. Creating optimal power-saving settings therefore requires time and expertise in analyzing CPU behavior, making it a highly individual task.

[0009] Therefore, a main object of the present invention is to support the improvement of power saving settings of applications.

[0010] In order to solve the above problems, the design improvement device of the present invention comprises the following means: A status acquisition unit that acquires, in accordance with a predetermined acquisition rule, the usage status of hardware used when an application is executing a process, An improvement determination unit that identifies factors causing excessive power consumption as improvement information based on the usage status of the hardware acquired by the status acquisition unit and a predetermined determination rule, And an improvement output unit that outputs the improvement information identified by the improvement determination unit.

[0011] According to the present invention, it is possible to support improvement of power saving settings of applications.

[0012] FIG. 1 is a configuration diagram of a design improvement device according to the present embodiment. FIG. 2 is a table showing a list of C-state states in the CPU idle function according to the present embodiment. FIG. 3 is a table showing time indexes defined for each C-state state of FIG. 2 according to the present embodiment. FIG. 4 is a flowchart showing the processing of a status acquisition unit according to the present embodiment. FIG. 5 is a flowchart showing the processing of an improvement determination unit according to the present embodiment. FIG. 6 is a flowchart showing the processing of an improvement output unit according to the present embodiment. FIG. 7 is a configuration diagram showing a modified example of the design improvement device 100 of FIG. 1 according to the present embodiment. FIG. 8 is a hardware configuration diagram of the design improvement device 100 according to the present embodiment. FIG. 9 is an explanatory diagram showing an example of allocating threads of an application to CPU cores. FIG. 10 is an explanatory diagram showing the difference between setting pinning to one CPU core or not.

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0014] 1 is a configuration diagram of a design improvement device 100. In the design improvement device 100, software runs on hardware 40 having one or more CPU cores 41. The software includes an OS (Operating System) / driver 30, a target application 10 in a user space 20, and an improvement support unit 20A. The design improvement device 100 also includes a user interface 50 such as a touch panel liquid crystal display.

[0015] Each CPU core 41 has a built-in performance monitor unit 42, which monitors the performance of the CPU core 41 to measure behavior information of the CPU core 41. This performance monitoring includes, for example, measuring the time the CPU core 41 is active / idle and measuring the number of times the CPU core 41 has interrupted its calculations. The performance monitor unit 42 is implemented, for example, as a PMU (Performance Monitoring Unit) from Intel Corporation ("Intel" is a registered trademark). The hardware 40 also includes a CPU power measurement unit 43 that measures power consumption information, temperature information, and the like of each CPU core 41. The CPU power measurement unit 43 is implemented, for example, as a RAPL (Running Average Power Limit) from Intel Corporation.

[0016] The OS / driver 30 includes a core allocation setting input unit 31, a performance monitor unit driver 32, and a CPU power measurement unit driver 33. The core allocation setting input unit 31 is a function within the OS that sets which CPU core 41 each thread will use to execute calculations. The core allocation setting input unit 31 can change the allocation of the CPU cores 41 in response to instructions from the improvement support unit 20A. The performance monitor unit driver 32 relays access from the improvement support unit 20A to the performance monitor unit 42. The CPU power measurement unit driver 33 relays access from the improvement support unit 20A to the CPU power measurement unit 43.

[0017] The target application 10 is an application that is subject to power-saving settings. The improvement support unit 20A acquires the usage status of the hardware 40 (mainly the CPU core 41) of the target application 10 while the target application 10 is running, and identifies wasteful parts of the power-saving settings (parts that are not optimally designed). The improvement support unit 20A has a used core acquisition unit 21, an acquired rule recording unit 22, a status acquisition unit 23, a judgment rule recording unit 24, an improvement judgment unit 25, and an improvement output unit 26. The used core acquisition unit 21 acquires the operating status of the CPU cores 41, i.e., which CPU core 41 each thread of the target application 10 is running on, and records the result in the acquired rule recording unit 22 as core allocation information for the target application 10.

[0018] The acquisition rule recording unit 22 records rules (acquisition rules) for acquiring the utilization status of the CPU core 41. The acquisition rule is defined by, for example, the hardware 40 for which information is to be acquired, which is specified by the core allocation information from the utilized core acquisition unit 21, and the acquisition frequency and acquisition period for that hardware 40. The status acquisition unit 23 acquires the CPU utilization status used by the target application 10 via the OS / driver 30 in accordance with the acquisition rule read from the acquisition rule recording unit 22.

[0019] The judgment rule recording unit 24 pre-records rules (judgment rules) for judging design improvements for the target application 10. These judgment rules may be added or modified by the developer / operator of the target application 10 who is running the test. The improvement judgment unit 25 identifies factors causing excessive power consumption (areas that are no longer optimally designed) based on the CPU usage status information acquired by the status acquisition unit 23 and the judgment rules read from the judgment rule recording unit 24. The improvement output unit 26 outputs information on the factors identified by the improvement judgment unit 25 as design improvement information to the user interface 50 (for example, to the console, which is the standard output, or to a file).

[0020] The main parts of the improvement support unit 20A (the status acquisition unit 23, the improvement determination unit 25, and the improvement output unit 26) will be described in detail below. In addition to the CPU usage status acquired from the performance monitor unit 42 and the CPU power measurement unit 43, the status acquisition unit 23 may acquire the following indicators: Software indicators that can be acquired from the OS / driver 30 and the target application 10 Indicators that can be acquired from a hardware accelerator (not shown) in the hardware 40, such as a GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), or ASIC (Application Specific Integrated Circuit) CPU power saving function governor in the OS / driver 30

[0021] As a result, the status acquisition unit 23 acquires the following information: Power consumption of the CPU used by the target application 10 Core behavior information such as the number of instructions executed / frequency fluctuation of the CPU core used by the target application 10 Information on control executed on the core used by the target application 10 (number and content of CPU idle function and CPU frequency transition instructions) Usage rate of the hardware accelerator

[0022] The improvement determination unit 25 determines the following examples, for example, as combinations of "information used for determination," "determination rule," and "factors to be identified." "Information used for determination" = "idle time of the CPU core 41 used by the target application 10 obtained from the performance monitor unit 42" and "usage status of the CPU idle function obtained from the CPU power saving function governor." "Determination rule" = If the average idle time of a core is longer than the target residency of state X of the CPU idle function (C-state in FIG. 2), enable the state X. "factors to be identified" = Since the restriction on the CPU idle function for the core corresponding to the determination rule is excessive and is consuming excessive power, the restriction on the CPU idle function may be lifted.

[0023] Alternatively, the improvement determination unit 25 may make a determination based on the following examples: "Information used for determination" = "Idle time of the first core and idle time of the second core used by the target application 10, obtained from the performance monitor unit 42" "Determination rule" = If a first thread running on the first core and a second thread running on the second core are not executed in parallel in time, a core is allocated so that the first thread and the second thread are executed on the same core (e.g., the first core). "Cause to identify" = Although the first thread and the second thread can be executed on the same core, they are executed on different cores, increasing the number of cores and increasing power consumption.

[0024] The improvement output unit 26 outputs information on the factors identified by the improvement determination unit 25 as design improvement information to the user interface 50 (console output, file output, etc.). This allows the developer or operator of the target application 10 to improve the design (mainly power saving settings) of the target application 10 based on the fed-back design improvement information. Note that the improvement output unit 26 may use the following exemplary formats as the output format for the design improvement information: Text (information received from the improvement determination unit 25 is output as text to the console or file) Images or tables (table output by attribute, such as thread configuration improvement factors / CPU power saving function improvement factors)

[0025] Below, examples of combinations of information acquired by the status acquisition unit 23 and examples of judgments made by the improvement judgment unit 25 are listed. A first example of a combination will be described. The information acquired by the status acquisition unit 23 is as follows: - Information on the idle time of each core from the performance monitor unit 42 - Information on the setting of the CPU idle function in the OS An example judgment made by the improvement judgment unit 25 is that "if the average idle time of a certain core is x and C-states whose Target Residency ( FIG. 3 ) is below x are disabled, all of those C-states should be enabled." For example, if the average idle time of core #5 is 120 [usec] and C3 states whose Target Residency is 100 [usec], which is less than 120 [usec], are disabled, the improvement judgment unit 25 judges that the C3 states should be enabled.

[0026] A second example of a combination will be explained. The information acquired by the status acquisition unit 23 is information on the active / idle time of each core acquired from the performance monitor unit 42. An example of a judgment made by the improvement judgment unit 25 is that when the active times of a first core and a second core do not overlap, the following two improvements are possible. - The core assignment should be such that the thread running on the first core and the thread running on the second core are run on the same core. - The thread running on the first core and the thread running on the second core should be run as the same thread.

[0027] A third example combination will be explained. The information acquired by the status acquisition unit 23 is as follows: Hardware accelerator usage rate CPU usage rate acquired from the performance monitor unit 42 An example of a judgment made by the improvement judgment unit 25 is to offload part of the processing being performed by the CPU to the hardware accelerator when the total CPU usage rate is higher than a certain threshold (first threshold) but the hardware accelerator usage rate is lower than a certain value (second threshold). This improvement reduces the CPU usage rate and saves power.

[0028] A fourth example combination will be described. The information acquired by the status acquisition unit 23 is as follows: C-state statistics recorded in the OS (the number of times the OS decided to transition to each state and the duration of the transition measured in the OS); C-state statistics acquired from the performance monitor unit 42. For example, the improvement determination unit 25 determines that, if the number of C-state transitions / time acquired from the CPU core 41 for a given first core is less than the number of C-state transitions / time recorded in the OS, the thread is unable to transition to the C-state determined in the OS due to the processing influence of another logical core on the same physical core. In this case, an improvement is possible in which the core allocation is changed so that a thread running on the first core or a thread running on another logical core on the same physical core as the first core is run on another core, thereby enabling the thread to transition to the C-state determined in the OS.

[0029] A fifth example combination will be described. The information acquired by the status acquisition unit 23 is as follows: Information from the CPU power measurement unit 43; and CPU utilization acquired from the performance monitor unit 42. An example of the determination made by the improvement determination unit 25 is that while the power of the first CPU is high enough to reach the thermal design power (TDP), the first CPU may be experiencing thermal throttling (a function that reduces performance to suppress heat generation), resulting in reduced processing efficiency. In this case, if the total CPU utilization of the second CPU in the same chassis is low, an improvement is made by reassigning the threads assigned to the cores in the first CPU to the cores in the first CPU. For example, if the TDP of the first CPU is 120 W and the average power consumption over the most recent 5-second measurement period is consistently above 108 W, which is 90% of 120 W, an improvement is made by reassigning the threads assigned to core #5 in the first CPU to core #48 in the second CPU.

[0030] A sixth example of a combination will be described. The information acquired by the status acquisition unit 23 is information about the active time of each core, which can be acquired from the performance monitor unit 42. The improvement determination unit 25 determines that if the active time of a core per unit time is longer than the latency requirement, the processing is likely not completed within the time limit. In this case, an improvement is made by changing the frequency setting of the CPU core to increase the operating frequency. In this sixth example, the test executor specifies in advance the latency requirement of the target application 10 and the operating period (unit time) of the target application 10 as a determination rule. For example, if the test executor specifies a determination rule such as "the target application 10 is launched once per 1 msec and has a latency requirement of 100 usec," the improvement determination unit 25 can determine that the processing is not completed within the time limit if the core is active for 100 usec or more within a unit time of 1 msec.

[0031] Figure 2 is a table listing the C-states for the CPU idle function. The CPU idle function is defined in order, as shown in the table, from the C0 state (operating state) with the highest power consumption to the C6 state (deep power down) with the lowest power consumption. In other words, as n in Cn (n = 0, 1, ... 6) increases, the power saving effect increases, but the time required to return also increases. Note that the C-state definitions may differ depending on the CPU hardware specifications and the OS / driver 30 that handles the CPU idle function, such as not having C4 or C5, or having a state C1E after C1.

[0032] Figure 3 is a table showing the time indices defined for each C-state in Figure 2. As shown in the table in Figure 3, C-states have the following indices, and within the OS, this information is used to determine which C-state to enter when entering an idle state. Exit Latency: The worst-case delay time for returning from that state to an active state Target residency: The minimum idle time required to achieve power-saving effects. Note that the deeper the state, the greater the power-saving effect, but because it takes time to transition and return, power-saving effects cannot be achieved unless a certain amount of idle time is expected.

[0033] 4 is a flowchart showing the processing of the status acquisition unit 23. This flowchart begins operation when the improvement support unit 20A is started. In S101, the status acquisition unit 23 receives, from the acquisition rule recording unit 22, information to be acquired from the target application 10 (e.g., information on active / idle times acquired by the performance monitor unit 42), the information acquisition interval (time t), and the information acquisition period (time s of the measurement period). In S102, the status acquisition unit 23 acquires information on active / idle times for the most recent t seconds from the performance monitor unit 42.

[0034] In S103, the status acquisition unit 23 notifies the improvement determination unit 25 of information on the active / idle times of the cores for the most recent t seconds via the shared memory. In S104, the status acquisition unit 23 determines whether or not a time s has elapsed since the start of acquisition. If Yes in S104, the process proceeds to S105, and if No, the process proceeds to S106. In S105, the status acquisition unit 23 notifies the improvement output unit 26 that the time s has elapsed, using a signal or the shared memory. In S106, the status acquisition unit 23 sleeps for the time t, and returns the process to S102.

[0035] 5 is a flowchart showing the processing of the improvement determination unit 25. By executing this flowchart, the improvement determination unit 25 outputs information about C-states that are not currently set but will improve power saving by setting them to the improvement output unit 26. In S201, the improvement determination unit 25 receives information about the active / idle time of the CPU for each time t. In S202, the improvement determination unit 25 acquires a determination rule based on the information about the active / idle time of the CPU. This determination rule is, for example, a rule that compares the average idle time with the target residency of each C-state.

[0036] In S203, the improvement determination unit 25 calculates the average idle time at time t and initializes a variable K representing a state to 0. In S204, the improvement determination unit 25 determines whether a state equal to or greater than state K exists as a C-state of the CPU core 41 shown in FIG. 2. If Yes in S204, the process proceeds to S205; if No, the process of FIG. 5 ends. In S205, the improvement determination unit 25 determines whether a setting change of state K is appropriate. If Yes in S205, the process proceeds to S206; if No, the process proceeds to S207. For example, if state K is currently disabled and the current average idle time in the current interval of time t is equal to or greater than the target residency of state K, the improvement determination unit 25 determines that it is appropriate to change the setting of the current C-state to state K (Yes in S205).

[0037] In S206, the improvement determination unit 25 outputs, via the shared memory, to the improvement output unit 26, information indicating that "state K should have been enabled in the current time interval t of the measurement period (time s)." In S207, the improvement determination unit 25 increments K by 1, and returns the process to S204.

[0038] 6 is a flowchart showing the processing of the improvement output unit 26. In S301, the improvement output unit 26 receives the information of S206 from the improvement determination unit 25 via shared memory or a signal, stating that "state K of the CPU in the interval at time t during the measurement period (time s) should have been enabled." In S302, the improvement output unit 26 adds t to the time T during which state K should be enabled.

[0039] In S311, the improvement output unit 26 receives a notification of the end of the measurement period (S105) from the status acquisition unit 23 via the shared memory or a signal. In S312, the improvement output unit 26 generates information for each C-state, indicating that state K should have been enabled only for the section T during the measurement period (time s). In S313, the improvement output unit 26 outputs the information generated in S312 to the user via the standard output of the user interface 50.

[0040] Fig. 7 is a configuration diagram showing a modified example of the design improvement device 100 in Fig. 1. The design improvement device 100 in Fig. 7 includes a means for feeding back the output content of the improvement output unit 26 to the control content of the design improvement device 100, in addition to a means for communicating the output content (improvement settings) of the improvement output unit 26 to the operator via a user interface 50. Therefore, the design improvement device 100 in Fig. 7 additionally includes a thread / core allocation setting unit 11, a CPU power saving function setting unit 12, and a CPU power saving function setting input unit 34, compared to the design improvement device 100 in Fig. 1. The improvement output unit 26 outputs improvement settings to these added processing units and the core allocation setting input unit 31.

[0041] For example, the improvement output unit 26 receives from the improvement determination unit 25 information that power consumption is increasing because threads assigned to CoreX and CoreY are executing processes on different cores. In this case, the improvement output unit 26 outputs an improvement setting to allocate cores so that both threads assigned to CoreX and CoreY can execute processes on CoreX to the core allocation setting input unit 31 via the thread / core allocation setting unit 11. In addition, the improvement output unit 26 outputs an improvement setting to reduce power by utilizing the CPU power saving function with CoreY as an inactive core to the CPU power saving function setting input unit 34 via the CPU power saving function setting unit 12.

[0042] The thread / core allocation setting unit 11 generates threads from within the target application 10 and requests core allocation settings from the core allocation setting input unit 31. The CPU power saving function setting unit 12 inputs settings for the CPU power saving function setting input unit 34 from within the target application 10 and sets the target application 10 itself to support power saving operation if it supports it. The CPU power saving function setting input unit 34 sets power saving functions for the CPU core 41, such as enabling / disabling C-state.

[0043] FIG. 8 is a hardware configuration diagram of the design improvement device 100. The design improvement device 100 is configured as a computer 900 having a CPU 901, a RAM 902, a ROM 903, a HDD 904, a communication I / F 905, an input / output I / F 906, and a media I / F 907. The communication I / F 905 is connected to an external communication device 915. The input / output I / F 906 is connected to an input / output device 916. The media I / F 907 reads and writes data from a recording medium 917. Furthermore, the CPU 901 controls each unit by executing a program (design improvement program) loaded into the RAM 902. This program (also called an application, or an app for short) can be distributed via a communication line or recorded on a recording medium 917 such as a USB memory.

[0044] [Effect] The design improvement device 100 of the present invention is characterized by having: a status acquisition unit 23 that acquires, in accordance with predetermined acquisition rules, the usage status of the CPU core 41 that is being used when the target application 10 is executing processing; an improvement determination unit 25 that identifies, as improvement information, factors that are causing excessive power consumption based on the usage status of the CPU core 41 acquired by the status acquisition unit 23 and predetermined determination rules; and an improvement output unit 26 that outputs the improvement information identified by the improvement determination unit 25.

[0045] As a result, the design improvement device 100 can support improvement of the power saving settings of the target application 10 by outputting the cause of excessive power consumption, such as in the CPU core 41, as improvement information.

[0046] The design improvement device 100 of the present invention is characterized in that the improvement output section 26 outputs the improvement information to the user interface 50 .

[0047] This allows application developers and operators to identify the causes of excessive power consumption in their applications without having to perform specialized hardware behavior analysis themselves.

[0048] The design improvement device 100 of the present invention is characterized in that the improvement output unit 26 outputs the improvement information as setting information for the CPU core 41.

[0049] As a result, the design improvement device 100 can improve the application design by feeding back the setting information to itself so that power consumption can be minimized while satisfying performance.

[0050] The present invention is characterized in that the predetermined acquisition rule is a rule for acquiring information on the idle time of each CPU core 41 and setting information on the CPU idle function, and the predetermined judgment rule is a rule for validating setting information on the CPU idle function when setting information for a time shorter than the idle time of each CPU core 41 exists.

[0051] This allows the design improvement device 100 to detect a time period during which power is being wasted despite the occurrence of idle time in each CPU core 41.

[0052] The present invention is characterized in that the predetermined acquisition rule is a rule for acquiring information on the active time of threads running on each CPU core 41, and the predetermined judgment rule is a rule for improving the different threads to run on a single CPU core 41 if the active times of the different threads running on multiple CPU cores 41 do not overlap.

[0053] As a result, the design improvement device 100 can identify the cause of excessive power consumption, such as a thread set that can be operated on a single CPU core 41 being operated separately on multiple CPU cores 41. Therefore, the application developer or operator can appropriately modify the performance-oriented setting of "subdividing / pooling threads and allocating dedicated cores to all threads."

[0054] The present invention is characterized in that the predetermined acquisition rule is a rule for acquiring the utilization rate of the CPU core 41 and the utilization rate of the hardware accelerator, and the predetermined judgment rule is a rule for offloading part of the processing of the CPU core 41 to the hardware accelerator when the utilization rate of the CPU core 41 is higher than a first threshold value but the utilization rate of the hardware accelerator is lower than a second threshold value.

[0055] As a result, the design improvement device 100 can identify the cause of excessive power consumption that occurs when processing is performed by the CPU core 41 even when a hardware accelerator is available.

[0056] 10 Target application (application) 11 Thread / core allocation setting unit 12 CPU power saving function setting unit 20 User space 20A Improvement support unit 21 Used core acquisition unit 22 Acquisition rule recording unit 23 Status acquisition unit 24 Judgment rule recording unit 25 Improvement judgment unit 26 Improvement output unit 30 OS / driver 31 Core allocation setting input unit 32 Performance monitor unit driver 33 CPU power measurement unit driver 34 CPU power saving function setting input unit 40 Hardware 41 CPU core (hardware) 42 Performance monitor unit 43 CPU power measurement unit 50 User interface 100 Design improvement device

Claims

1. A design improvement device comprising: a status acquisition unit that acquires the usage status of hardware used by an application when it is executing processing in accordance with predetermined acquisition rules; an improvement judgment unit that identifies factors causing excessive power consumption as improvement information based on the usage status of the hardware acquired by the status acquisition unit and predetermined judgment rules; and an improvement output unit that outputs the improvement information identified by the improvement judgment unit.

2. The design improvement device according to claim 1, wherein the improvement output unit outputs the improvement information to a user interface.

3. The design improvement device according to claim 1, wherein the improvement output unit outputs the improvement information as setting information for the hardware.

4. The design improvement device according to claim 1, wherein the predetermined acquisition rule is a rule for acquiring information on the idle time of each piece of hardware and setting information for a CPU idle function, and the predetermined judgment rule is a rule for validating setting information for a CPU idle function whose time is shorter than the idle time of each piece of hardware if such setting information exists.

5. The design improvement device according to claim 1, wherein the predetermined acquisition rule is a rule for acquiring information on the active time of threads running on each of the hardware components, and the predetermined judgment rule is a rule for improving different threads running on multiple pieces of hardware so that they run on a single piece of hardware if the active times of the different threads do not overlap.

6. The design improvement device according to claim 1, wherein the predetermined acquisition rule is a rule for acquiring the utilization rate of the hardware and the utilization rate of a hardware accelerator, and the predetermined judgment rule is a rule for offloading part of the processing of the hardware to the hardware accelerator when the utilization rate of the hardware is higher than a first threshold value but the utilization rate of the hardware accelerator is lower than a second threshold value.

7. A design improvement method, comprising: a design improvement device having a status acquisition unit, an improvement judgment unit, and an improvement output unit; wherein the status acquisition unit acquires the usage status of hardware used when an application is executing processing in accordance with a predetermined acquisition rule; the improvement judgment unit identifies factors causing excessive power consumption as improvement information based on the hardware usage status acquired by the status acquisition unit and the predetermined judgment rule; and the improvement output unit outputs the improvement information identified by the improvement judgment unit.

8. A design improvement program for causing a computer to function as the design improvement device according to any one of claims 1 to 6.

Images