Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a semiconductor element; an insulating substrate which has a substrate main surface that faces the semiconductor element in the thickness direction, and which supports the semiconductor element; a conductor part which is bonded to the substrate main surface; and a sealing resin which covers a part of the conductor part, the semiconductor element, and the insulating substrate. The conductor part has a conductor main surface that faces the same direction as the substrate main surface in the thickness direction, and is electrically connected to the semiconductor element. The insulating substrate is positioned further inward than the peripheral edge of the sealing resin when viewed in the thickness direction. The sealing resin has a resin main surface that faces the same direction as the substrate main surface, and an opening that is provided in the resin main surface so as to expose a part of the conductor main surface therefrom.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, semiconductor devices incorporating semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) have been widely known. Patent Document 1 discloses an example of a conventional semiconductor device (semiconductor module). The semiconductor module described in Patent Document 1 includes multiple semiconductor elements, a conductive substrate, multiple input terminals, multiple output terminals, and a sealing resin. The multiple semiconductor elements are, for example, MOSFETs and are bonded to the conductive substrate. The sealing resin covers the multiple semiconductor elements. The multiple input terminals and multiple output terminals are electrically connected to one of the multiple semiconductor elements. The multiple input terminals and multiple output terminals are all power supply terminals that handle a power supply voltage. The multiple input terminals and multiple output terminals each protrude from one of multiple resin side surfaces of the sealing resin.

[0003] In the semiconductor module described in Patent Document 1, the input terminals and the output terminals are arranged before the sealing resin is formed. In this configuration, areas on the top or bottom surfaces of the input terminals and the output terminals may be created where the sealing resin is difficult to form properly. Therefore, in order to properly form the sealing resin, a configuration is required in which the power supply terminals (input terminals or output terminals) can be arranged after the sealing resin is formed.

[0004] Japanese Patent Application Laid-Open No. 2023-181544

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device in which a power supply terminal can be disposed after forming a sealing resin.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a first semiconductor element, an insulating substrate having a substrate main surface facing the first semiconductor element in a thickness direction of the first semiconductor element and supporting the first semiconductor element, a first conductor portion bonded to the substrate main surface, and a sealing resin covering the first semiconductor element, a portion of the first conductor portion, and the insulating substrate. The first conductor portion has a first conductor main surface facing the same direction as the substrate main surface in the thickness direction and is electrically connected to the first semiconductor element. The insulating substrate is located inward from a peripheral edge of the sealing resin as viewed in the thickness direction. The sealing resin has a resin main surface facing the same direction as the substrate main surface and a main surface opening formed in the resin main surface. The main surface opening includes a first opening exposing a portion of the first conductor main surface from the resin main surface.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: a substrate bonding process for bonding an insulating substrate and a substrate including a conductor portion to a heat dissipation member; a molding process for forming a sealing resin covering the substrate on the heat dissipation member; a terminal connection process for connecting a power terminal electrically connected to the conductor portion; and an element bonding process for mounting a semiconductor element on the substrate prior to the molding process. The insulating substrate has a substrate main surface facing the semiconductor element in a thickness direction of the semiconductor element. The sealing resin has a resin main surface facing the same direction as the substrate main surface in the thickness direction. The conductor portion has a conductor main surface facing the same direction as the substrate main surface in the thickness direction. In the molding process, a main surface opening is formed in the resin main surface to expose a portion of the conductor main surface. In the terminal connection process, the power terminal is connected to a portion of the conductor main surface through the main surface opening.

[0008] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a view of the perspective view of FIG. 1 , with the sealing resin of each semiconductor package omitted. FIG. 3 is a perspective view (different from FIG. 1 ) showing a semiconductor device according to the first embodiment. FIG. 4 is a plan view showing the semiconductor device according to the first embodiment. FIG. 5 is a front view showing the semiconductor device according to the first embodiment. FIG. 6 is a bottom view showing the semiconductor device according to the first embodiment. FIG. 7 is a rear view showing the semiconductor device according to the first embodiment. FIG. 8 is a left side view showing the semiconductor device according to the first embodiment. FIG. 9 is a partially enlarged plan view of a portion of FIG. 4 . FIG. 10 is a view of FIG. 9 , with multiple power terminals omitted. FIG. 11 is a view of FIG. 9 , with the heat dissipation member omitted and the sealing resin shown in imaginary lines. FIG. 12 is a view of FIG. 11 , with the multiple power terminals omitted. FIG. 13 is a view of FIG. 12 , with one of two conductive members and the sealing resin omitted. FIG. 14 is a diagram of FIG. 13 with the other of the two conductive members omitted. FIG. 15 is a bottom view showing one of the multiple semiconductor packages of the semiconductor device according to the first embodiment. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11. FIG. 17 is a partially enlarged cross-sectional view of FIG. 16. FIG. 18 is a partially enlarged cross-sectional view of FIG. 16 (a portion different from FIG. 17). FIG. 19 is a partially enlarged cross-sectional view of FIG. 16 (a portion different from FIG. 17 and FIG. 18). FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 11. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 11. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 11. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 11. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 11. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 11. Fig. 26 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. Fig. 27 is a cross-sectional view showing a step (substrate bonding step) of the method for manufacturing a semiconductor device according to the first embodiment, corresponding to the cross section of Fig. 16. Fig. 28 is a cross-sectional view showing a step (element bonding step) of the method for manufacturing a semiconductor device according to the first embodiment, corresponding to the cross section of Fig. 16.29 is a cross-sectional view showing a step (a signal substrate bonding step, a conductive member bonding step, and a sleeve bonding step) of the method for manufacturing the semiconductor device according to the first embodiment, and corresponds to the cross section of FIG. 16 . FIG. 30 is a plan view showing a step (a molding step) of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 31 is a cross-sectional view showing a step (a molding step) of the method for manufacturing the semiconductor device according to the first embodiment, and corresponds to the cross section of FIG. 16 . FIG. 32 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 33 is a front view showing a power conversion unit including the semiconductor device according to the first embodiment. FIG. 34 is an enlarged cross-sectional view of a main part of the power conversion unit shown in FIG. 33 . FIG. 35 is a front view showing another example of the configuration of the power conversion unit including the semiconductor device according to the first embodiment. FIG. 36 is a schematic diagram of a vehicle including a power conversion unit including the semiconductor device according to the first embodiment. FIG. 37 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment, and corresponds to the cross section of FIG. 20 . FIG. 38 is a cross-sectional view showing a semiconductor device according to the first modification of the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 39 is a cross-sectional view showing a semiconductor device according to a second modified example of the first embodiment, corresponding to the cross section of FIG. 20 . FIG. 40 is a cross-sectional view showing a semiconductor device according to a third modified example of the first embodiment, corresponding to the cross section of FIG. 20 . FIG. 41 is a cross-sectional view showing another configuration example of a semiconductor device according to the third modified example of the first embodiment, corresponding to the cross section of FIG. 20 . FIG. 42 is a cross-sectional view showing a semiconductor device according to the second embodiment, corresponding to the cross section of FIG. 20 . FIG. 43 is a cross-sectional view showing a semiconductor device according to a first modified example of the second embodiment, corresponding to the cross section of FIG. 20 . FIG. 44 is a cross-sectional view showing a semiconductor device according to a second modified example of the second embodiment, corresponding to the cross section of FIG. 20 . FIG. 45 is a cross-sectional view showing a semiconductor device according to the third embodiment, corresponding to the cross section of FIG. 16 . FIG. 46 is a flowchart showing a manufacturing method of the semiconductor device according to the third embodiment. FIG. 47 is a plan view showing one of multiple semiconductor packages of a semiconductor device according to another configuration example, with the sealing resin shown by imaginary lines. FIG. 48 is a front view showing a semiconductor device according to another configuration example. FIG. 49 is a bottom view of the semiconductor device shown in FIG. 48 .Fig. 50 is a perspective view showing a semiconductor package according to a modified example, and Fig. 51 is a plan view showing another semiconductor device, showing a configuration including the semiconductor package shown in Fig. 50.

[0009] DETAILED DESCRIPTION A preferred embodiment of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B," unless otherwise specified. Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, "a surface A faces in a certain direction B (one side or the other side of a certain direction B)," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted with respect to direction B. Furthermore, "a surface A is perpendicular to a surface B," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted with respect to surface B. Furthermore, unless otherwise specified, "an object A (surface A) being parallel to an object B (surface B)" is not limited to a strict definition, and includes cases where an object A (surface A) is tilted relative to an object B (surface B) (for example, a slight deviation due to a manufacturing error, etc.).

[0011] 1 to 25 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes three semiconductor packages B10 and a heat dissipation member C10. The semiconductor device A10 is used, for example, in an inverter for driving a three-phase AC motor, but the use of the semiconductor device A10 is not limited to this.

[0012] For ease of explanation, reference will be made to the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of the semiconductor device A10. "Planar view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. One side of the first direction x is referred to as the x1 side of the first direction x, and the other side of the first direction x is referred to as the x2 side of the first direction x. One side of the second direction y is referred to as the y1 side of the second direction y, and the other side of the second direction y is referred to as the y2 side of the second direction y. One side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z. The z2 side of the thickness direction z is sometimes referred to as the upper side, and the z1 side of the thickness direction z is sometimes referred to as the lower side. The terms "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each part in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0013] The three semiconductor packages B10 are each bonded to a heat dissipation member C10. In a plan view, the heat dissipation member C10 has a rectangular shape with its longitudinal direction aligned in the first direction x. The plan view shape of the heat dissipation member C10 is not limited to the example shown in the figure. The three semiconductor packages B10 are each disposed on the heat dissipation member C10 along the first direction x. A detailed configuration example of each semiconductor package B10 will be described later.

[0014] The heat dissipation member C10 supports the multiple semiconductor packages B10. The heat dissipation member C10 is, for example, a heat sink. Instead of a heat sink, the heat dissipation member C10 may be a housing (e.g., a frame) of an electronic device, an electric vehicle, or the like. Most of the heat dissipation member C10 is located below the multiple semiconductor packages B10 in the thickness direction z (on the z1 side). The heat dissipation member C10 faces the bottom surface (the surface facing the z1 side in the thickness direction z) of each of the multiple semiconductor packages B10. The material of the heat dissipation member C10 includes, for example, aluminum. The material is not limited to aluminum and may be other metal materials or resin materials (preferably those with good thermal conductivity). The heat dissipation member C10 includes a main body portion 71 and a heat dissipation portion 73.

[0015] The main body portion 71 is a plate material. The semiconductor packages B10 are mounted on the main body portion 71. The semiconductor packages B10 are arranged on the main body portion 71 along the first direction x. The main body portion 71 faces the bottom surface of each of the semiconductor packages B10. The main body portion 71 contacts each semiconductor package B10. The main body portion 71 has, for example, a rectangular shape in a plan view, but the shape of the main body portion 71 in a plan view is not limited in any way.

[0016] The main body portion 71 has a main body surface 71a and a main body back surface 71b. As shown in Figures 5, 7, and 8, the main body surface 71a and the main body back surface 71b are spaced apart in the thickness direction z. The main body surface 71a and the main body back surface 71b face opposite each other in the thickness direction z. The main body surface 71a faces upward in the thickness direction z, and the main body back surface 71b faces downward in the thickness direction z. Multiple semiconductor packages B10 are mounted on the main body surface 71a.

[0017] The heat dissipation portion 73 protrudes in the thickness direction z from the back surface 71b of the main body portion 71. The heat dissipation portion 73 is located on the opposite side of the main body portion 71 from each of the semiconductor packages B10 in the thickness direction z. As shown in FIG. 6 , the heat dissipation portion 73 is a plurality of pins spaced apart from each other in a direction perpendicular to the thickness direction z. In the example shown in FIG. 6 , the pins are arranged in a face-centered rectangular lattice pattern of a two-dimensional Bravais lattice in a planar view. However, the pins may be arranged in a square lattice pattern, a rectangular lattice pattern, a diagonal lattice pattern, or a hexagonal lattice pattern. Furthermore, although the pins are arranged in three regions corresponding to the three semiconductor packages B10, they do not have to be arranged in such a divided manner.

[0018] Next, a detailed configuration example of each semiconductor package B10 will be described. As shown in Figures 9 to 25, each of the multiple semiconductor packages B10 includes a support substrate 10, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, two conductive members 31 and 32, multiple connecting members 41 to 45, a sealing resin 50, and two signal boards 601 and 602. Note that the multiple connecting members 41 to 45 are not shown in Figure 2. In the following description, the support substrate 10, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, two conductive members 31 and 32, multiple connecting members 41 to 45, a sealing resin 50, and two signal boards 601 and 602 are common to each semiconductor package B10 unless otherwise specified. The plurality of signal terminals 19 includes a plurality of signal terminals 191 , 192 , 193 , 194 , 196 , and 197 .

[0019] Each semiconductor package B10 converts a DC power supply voltage applied to power terminals 15 and 16 into an AC voltage using multiple semiconductor elements 21 and 22. The converted AC voltage is input from power terminal 17 to a power supply target such as a motor.

[0020] As shown in FIGS. 13 and 14 , the support substrate 10 supports a plurality of semiconductor elements 21 and 22 in the thickness direction z. The support substrate 10 is, for example, an active metal brazing (AMB) substrate. Alternatively, the support substrate 10 may be a direct copper bonding (DCB) substrate. The support substrate 10 includes an insulating substrate 11, a main surface metal layer 12, and a back surface metal layer 13. In this embodiment, the support substrate 10 is covered with a sealing resin 50.

[0021] As shown in Figures 16 and 20 to 25, the insulating substrate 11 is interposed between the main surface metal layer 12 and the back surface metal layer 13 in the thickness direction z. The insulating substrate 11 supports a plurality of semiconductor elements 21 and a plurality of semiconductor elements 22 via the main surface metal layer 12. The insulating substrate 11 includes a material with relatively high thermal conductivity. The insulating substrate 11 is made of ceramics including aluminum nitride (AlN), for example. The insulating substrate 11 may include an insulating resin sheet in addition to ceramics.

[0022] The insulating substrate 11 has a substrate main surface 11a and a substrate back surface 11b. As shown in Figures 16 and 20 to 25, the substrate main surface 11a and the substrate back surface 11b are spaced apart in the thickness direction z. The substrate main surface 11a and the substrate back surface 11b face opposite each other in the thickness direction z. The substrate main surface 11a faces upward in the thickness direction z, and the substrate back surface 11b faces downward in the thickness direction z. The substrate main surface 11a faces the multiple semiconductor elements 21 and the multiple semiconductor elements 22.

[0023] As shown in Figures 16 and 20 to 25, the main surface metal layer 12 is located above the insulating substrate 11 in the thickness direction z. The main surface metal layer 12 is in contact with and bonded to the substrate main surface 11a. The main surface metal layer 12 contains copper (Cu), but may contain other metals. In a plan view, the main surface metal layer 12 is surrounded by the periphery of the insulating substrate 11. As shown in Figure 14, the main surface metal layer 12 includes a conductor portion 121, a conductor portion 122, and two conductor portions 123. The conductor portion 121, the conductor portion 122, and the two conductor portions 123 are spaced apart from each other.

[0024] The conductor portion 121 and the conductor portion 122 are spaced apart in the second direction y. The conductor portion 121 and the conductor portion 122 are aligned in the second direction y. The two conductor portions 123 are respectively arranged near two corners on one side (y2 side) of the four corners of the support substrate 10 in a plan view in the second direction y. The two conductor portions 123 are located on the opposite side of the conductor portion 121 in the second direction y, sandwiching a part of the conductor portion 122 (a partition portion 1221 described below). The dimension of the conductor portion 121 in the thickness direction z, the dimension of the conductor portion 122 in the thickness direction z, and the dimensions of the two conductor portions 123 in the thickness direction z are all the same.

[0025] The conductor portion 121 is located on the other side (y1 side) in the second direction y relative to the conductor portion 122. The conductor portion 121 is located closer to the power terminal 17 than the conductor portion 122 in the second direction y. The conductor portion 121 has, for example, a rectangular shape in a plan view, but the shape of the conductor portion 121 in a plan view is not limited in any way. A plurality of semiconductor elements 21 and a signal board 601 are joined to the conductor portion 121. In this embodiment, the conductor portion 121 is an example of a "second conductor portion" as defined in the claims.

[0026] The conductor portion 121 has a conductor principal surface 121a. As shown in FIG. 20 and other figures, the conductor principal surface 121a faces upward in the thickness direction z. The conductor principal surface 121a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 121a is flat and parallel to the substrate principal surface 11a. The conductor principal surface 121a faces the multiple semiconductor elements 21.

[0027] As shown in FIGS. 12 to 14 , the conductor portion 121 includes two exposed regions 121b. For ease of understanding, the two exposed regions 121b are depicted as dots in FIGS. 12 to 14 . Each of the two exposed regions 121b is exposed from the upper surface of the sealing resin 50 (the resin principal surface 51 described below). As shown in FIG. 12 , the two exposed regions 121b are disposed near the edge of the conductor principal surface 121a on the y1 side in the second direction y. The two exposed regions 121b are located closer to the y1 side of the semiconductor element 21 in the second direction y. The two exposed regions 121b are located on both sides of the signal substrate 602 in the first direction x, sandwiching the signal substrate 602 therebetween. In this embodiment, the exposed regions 121b are an example of a "second exposed region" as defined in the claims.

[0028] The conductor portion 122 is located on one side (y2 side) of the conductor portion 121 in the second direction y. The conductor portion 122 includes two partition portions 1221, 1222. A plurality of semiconductor elements 22 are joined to the partition portion 1221. The partition portion 1222 is located on the opposite side of the conductor portion 121 in the second direction y with respect to the partition portion 1221. The partition portion 1222 is located closer to the power terminal 15 than the partition portion 1221. The partition portion 1222 is connected to one side (y2 side) of the partition portion 1221 in the second direction y. The dimension of the partition portion 1221 in the first direction x is the same as the dimension of the conductor portion 121 in the first direction x. The dimension of the partition portion 1222 in the first direction x is smaller than the dimension of the partition portion 1221 in the first direction x. In this embodiment, the conductor portion 122 is an example of a "third conductor portion" as defined in the claims.

[0029] The conductor portion 122 has a conductor principal surface 122a. As shown in FIG. 20 and other figures, the conductor principal surface 122a faces upward in the thickness direction z. The conductor principal surface 122a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 122a is flat and parallel to the substrate principal surface 11a. The conductor principal surface 122a faces the multiple semiconductor elements 22.

[0030] As shown in FIGS. 12 to 14 , the conductor principal surface 122a includes two exposed regions 122b. For ease of understanding, the two exposed regions 122b are depicted as dots in FIGS. 12 to 14 . Each of the two exposed regions 122b is exposed from the upper surface of the sealing resin 50 (the resin principal surface 51 described below). As shown in FIG. 12 , the two exposed regions 122b are disposed near the edge of the conductor principal surface 122a on the y2 side in the second direction y. The two exposed regions 122b are located on the opposite side of the signal substrate 601 from the multiple semiconductor elements 22 in the second direction y. In this embodiment, the exposed region 122b is an example of a "third exposed region" as defined in the claims.

[0031] The two conductor portions 123 are located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 as the reference. The two conductor portions 123 are located closer to the power terminal 16 than the conductor portion 121 in the second direction y. The two conductor portions 123 are located on opposite sides of the partition portion 1222 in the first direction x. The power terminal 16 and the conductive member 32 are respectively joined to the two conductor portions 123. In this embodiment, the conductor portion 123 is an example of a "first conductor portion" as defined in the claims.

[0032] Each of the two conductor portions 123 has a conductor principal surface 123a. As shown in Figure 20 and other figures, the conductor principal surface 123a of each conductor portion 123 faces upward in the thickness direction z. The conductor principal surface 123a of each conductor portion 123 faces in the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 123a of each conductor portion 123 is flat and parallel to the substrate principal surface 11a.

[0033] As shown in Figures 12 to 14, each of the conductor principal surfaces 123a of the two conductor portions 123 includes an exposed region 123b. For ease of understanding, the two exposed regions 123b are depicted as dots in Figures 12 to 14. The exposed region 123b of each conductor portion 123 is exposed from the upper surface of the sealing resin 50 (the resin principal surface 51 described below). In each conductor portion 123, the exposed region 123b is located near the edge of the conductor principal surface 123a on the y2 side in the second direction y, as shown in Figure 12. In each conductor portion 123, the exposed region 123b is located on the y2 side in the second direction y relative to the portion of the conductor principal surface 123a to which the conductive member 32 is joined. In this embodiment, the exposed region 123b is an example of a "first exposed region" as defined in the claims.

[0034] As shown in Figures 16 and 20 to 25, the back surface metal layer 13 is located below (on the z1 side of) the insulating substrate 11 in the thickness direction z. The back surface metal layer 13 is in contact with and bonded to the substrate back surface 11b. The composition of the back surface metal layer 13 includes copper (Cu), similar to the main surface metal layer 12, but may be other metals. Unlike this example, the composition of the back surface metal layer 13 may be different from that of the main surface metal layer 12. In the illustrated example, the back surface metal layer 13 is rectangular in plan view. The back surface metal layer 13 is surrounded by the periphery of the insulating substrate 11 in plan view.

[0035] The main surface metal layer 12 and the back surface metal layer 13 are metal bodies individually bonded to both sides of the insulating substrate 11 in the thickness direction z. In the main surface metal layer 12, the metal body is divided into multiple conductor portions 121, 122, and 123 by patterning. That is, the conductor portions 121, 122, and two conductor portions 123 are patterns of metal bodies formed on the substrate main surface 11a of the insulating substrate 11. In an example where the support substrate 10 is an AMB substrate, the main surface metal layer 12 and the back surface metal layer 13 are each bonded by an active metal bonding method. In contrast to this example, in an example where the support substrate 10 is a DCB substrate, the main surface metal layer 12 and the back surface metal layer 13 are each bonded to the insulating substrate 11 by a direct bonding method.

[0036] As shown in Figures 16 to 25, each semiconductor package B10 further includes a bonding layer 109. The bonding layer 109 bonds the back surface metal layer 13 (support substrate 10) and the heat dissipation member C10. The bonding layer 109 is interposed between the lower surface of the back surface metal layer 13 and the main body surface 71a of the main body portion 71. The bonding layer 109 may be conductive or non-conductive, and may be, for example, solder. Alternatively, the bonding layer 109 may be a sintered body of metal particles. Preferably, the bonding layer 109 has high thermal conductivity. As can be seen from Figures 15 and 19, the periphery of the bonding layer 109 in plan view is covered by the sealing resin 50. Therefore, the bonding layer 109 is located inward of the periphery of the sealing resin 50 in plan view. The lower surface of the bonding layer 109 (the surface facing downward in the thickness direction z) is flush with the lower surface of the sealing resin 50 (the resin back surface 52 described below).

[0037] The plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 may be other transistors such as insulated gate bipolar transistors (IGBTs) and bipolar transistors, or diodes. In this embodiment, the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are each n-channel MOSFETs with a vertical structure.

[0038] The plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 each include a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon (Si), a wide bandgap semiconductor having a wider bandgap than Si, or an ultra-wide bandgap semiconductor having an even wider bandgap than the wide bandgap semiconductor. Examples of wide bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Examples of ultra-wide bandgap semiconductors include, but are not limited to, gallium oxide (GaO). ２ O ３), diamond, and aluminum nitride (AlN), but are not limited to these. In this embodiment, the composition of each compound semiconductor substrate of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 includes SiC. Note that the types and compositions of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are not limited to being the same, and may be different.

[0039] As shown in Figures 14 and 17, the multiple semiconductor elements 21 are mounted on the conductor portion 121. The multiple semiconductor elements 21 are arranged along the first direction x. In the illustrated example, each semiconductor package B10 includes six semiconductor elements 21, but the number of semiconductor elements 21 is not limited to six and can be changed as appropriate depending on the specifications of the semiconductor device A10 (each semiconductor package B10). In this embodiment, the semiconductor elements 21 are an example of a "first semiconductor element" as defined in the claims.

[0040] 17 , each of the multiple semiconductor elements 21 has an element main surface 21a and an element back surface 21b. The element main surface 21a and the element back surface 21b are spaced apart in the thickness direction z. The element main surface 21a and the element back surface 21b face opposite each other in the thickness direction z. The element main surface 21a faces upward in the thickness direction z, and the element back surface 21b faces downward in the thickness direction z. The element main surface 21a faces in the same direction as the substrate main surface 11a in the thickness direction z. The element back surface 21b faces the support substrate 10.

[0041] Each of the semiconductor elements 21 has a back surface electrode 211 and a plurality of principal surface electrodes 212, 213, and 214. The back surface electrode 211 and the plurality of principal surface electrodes 212, 213, and 214 described below are common to all the semiconductor elements 21 unless otherwise specified.

[0042] As shown in FIG. 17 , the back surface electrode 211 is disposed on the element back surface 21b and exposed thereon. As shown in FIGS. 14 and 17 , the plurality of principal surface electrodes 212, 213, and 214 are disposed on the element main surface 21a and exposed thereon. In the illustrated example, the principal surface electrode 212 is divided into two regions in a plan view. The two regions are aligned in the first direction x. Unlike this example, the principal surface electrode 212 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 213 in a plan view is smaller than the area of ​​the principal surface electrode 212 in a plan view. The two principal surface electrodes 214 are disposed on either side of the principal surface electrode 213 in the first direction x, sandwiching the principal surface electrode 213 therebetween. Unlike the illustrated example, each semiconductor element 21 may include only one of the two principal surface electrodes 214 or may include neither of the two principal surface electrodes 214 .

[0043] Each semiconductor element 21 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 213. The operation of each semiconductor element 21 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 211 and the principal surface electrode 212 are conductive, and in the OFF state, the back surface electrode 211 and the principal surface electrode 212 are non-conductive. In each semiconductor element 21, the back surface electrode 211 and the principal surface electrode 212 are conductive in response to a drive signal input to the principal surface electrode 213. The two principal surface electrodes 214 are short-circuited to the principal surface electrode 212 inside each semiconductor element 21. In this example, the potential of each of the two principal surface electrodes 214 is equal to the potential of the principal surface electrode 212. In an example where each semiconductor element 21 is a MOSFET, the back surface electrode 211 is a drain electrode, the main surface electrode 212 is a source electrode, the main surface electrode 213 is a gate electrode, and each main surface electrode 214 is a source sense electrode.

[0044] The semiconductor device A10 further includes a plurality of conductive bonding layers 219. As shown in Fig. 17, each of the plurality of semiconductor elements 21 is bonded to the conductor 121 by a corresponding one of the plurality of conductive bonding layers 219. Each of the plurality of conductive bonding layers 219 is interposed between the back electrode 211 of the corresponding semiconductor element 21 and the conductor 121, and provides electrical continuity therebetween. Each of the conductive bonding layers 219 is, for example, solder. Alternatively, each of the conductive bonding layers 219 may include a sintered body of metal particles.

[0045] As shown in FIG. 14 and other figures, the semiconductor elements 22 are mounted on the partition portions 1221 of the conductor portion 122. The semiconductor elements 22 are arranged along the first direction x. In the illustrated example, each semiconductor package B10 includes six semiconductor elements 22, but the number of semiconductor elements 22 is not limited to six and can be changed as appropriate depending on the specifications of the semiconductor device A10 (each semiconductor package B10). In this embodiment, the semiconductor elements 22 are an example of a "second semiconductor element" as defined in the claims.

[0046] 18 , each of the multiple semiconductor elements 22 has an element main surface 22 a and an element back surface 22 b. The element main surface 22 a and the element back surface 22 b are spaced apart in the thickness direction z. The element main surface 22 a and the element back surface 22 b face opposite each other in the thickness direction z. The element main surface 22 a faces upward in the thickness direction z, and the element back surface 22 b faces downward in the thickness direction z. The element main surface 22 a faces the same direction as the substrate main surface 11 a in the thickness direction z. The element back surface 22 b faces the support substrate 10.

[0047] Each of the semiconductor elements 22 has a back surface electrode 221 and a plurality of principal surface electrodes 222, 223, and 224. The back surface electrode 221 and the plurality of principal surface electrodes 222, 223, and 224 described below are common to all the semiconductor elements 22 unless otherwise specified.

[0048] As shown in FIG. 18 , the back surface electrode 221 is disposed on the element back surface 22b and exposed thereon. As shown in FIGS. 14 and 18 , the plurality of principal surface electrodes 222, 223, and 224 are disposed on the element main surface 22a and exposed thereon. In the illustrated example, the principal surface electrode 222 is divided into two regions in a plan view. The two regions are aligned in the first direction x. Unlike this example, the principal surface electrode 222 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 223 in a plan view is smaller than the area of ​​the principal surface electrode 222 in a plan view. The two principal surface electrodes 224 are disposed on either side of the principal surface electrode 223 in the first direction x, sandwiching the principal surface electrode 223 therebetween. Unlike the illustrated example, each semiconductor element 22 may include only one of the two principal surface electrodes 224 or may include neither of the two principal surface electrodes 224 .

[0049] Each semiconductor element 22 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 223. The operation of each semiconductor element 22 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 221 and the principal surface electrode 222 are conductive, and in the OFF state, the back surface electrode 221 and the principal surface electrode 222 are non-conductive. In each semiconductor element 22, the back surface electrode 221 and the principal surface electrode 222 are conductive in response to a drive signal input to the principal surface electrode 223. The two principal surface electrodes 224 are short-circuited to the principal surface electrode 222 inside each semiconductor element 22. In this example, the potential of each of the two principal surface electrodes 224 is equal to the potential of the principal surface electrode 222. In an example in which each semiconductor element 22 is a MOSFET, the back surface electrode 221 is a drain electrode, the main surface electrode 222 is a source electrode, the main surface electrode 223 is a gate electrode, and each main surface electrode 224 is a source sense electrode.

[0050] The semiconductor device A10 further includes a plurality of conductive bonding layers 229. As shown in FIG. 18 , each of the plurality of semiconductor elements 22 is bonded to the conductor portion 122 (partition portion 1221) by a corresponding one of the plurality of conductive bonding layers 229. Each of the plurality of conductive bonding layers 229 is interposed between the back electrode 221 of the corresponding semiconductor element 22 and the conductor portion 122, thereby establishing electrical continuity therebetween. Each of the conductive bonding layers 229 is, for example, solder. Alternatively, each of the conductive bonding layers 229 may include a sintered body of metal particles.

[0051] In the semiconductor device A10, the back electrodes 211 (drain electrodes) of the multiple semiconductor elements 21 are electrically connected, and the main surface electrodes 212 (source electrodes) are electrically connected. That is, the multiple semiconductor elements 21 are electrically connected in parallel with each other. In the multiple semiconductor elements 22, the back electrodes 221 (drain electrodes) of the multiple semiconductor elements 22 are electrically connected, and the main surface electrodes 222 (source electrodes) of the multiple semiconductor elements 22 are electrically connected. That is, the multiple semiconductor elements 22 are electrically connected in parallel with each other. Furthermore, in the semiconductor device A10, the back electrodes 211 (drain electrodes) of the multiple semiconductor elements 21 are electrically connected to the main surface electrodes 222 (source electrodes) of the multiple semiconductor elements 22. That is, the multiple semiconductor elements 21 and the multiple semiconductor elements 22 are connected in series. The semiconductor device A10 configures a half-bridge circuit in which the multiple semiconductor elements 22 form an upper arm circuit and the multiple semiconductor elements 21 form a lower arm circuit.

[0052] As shown in FIGS. 9 to 12 and 14 to 25 , the sealing resin 50 covers the semiconductor elements 21, portions of the two conductor portions 123, and the insulating substrate 11. Furthermore, the sealing resin 50 covers portions of the conductor portion 121, portions of the conductor portion 122, the semiconductor elements 22, the two conductive members 31, 32, the connecting members 41 to 45, the two signal boards 601, 602, and portions of the signal terminals 19 (the signal terminals 191 to 194, 196, and 197 described below). In this embodiment, the power terminals 15, 16, and 17 are disposed outside the sealing resin 50. The sealing resin 50 has electrical insulation properties. The sealing resin 50 includes, for example, a black epoxy resin. The sealing resin 50 is formed, for example, by molding. The sealing resin 50 has a resin main surface 51, a resin back surface 52, and multiple resin side surfaces 531 to 534.

[0053] As shown in FIGS. 16 and 20 to 25, the resin main surface 51 and the resin back surface 52 are spaced apart in the thickness direction z. The resin main surface 51 and the resin back surface 52 face opposite each other in the thickness direction z. The resin main surface 51 faces upward in the thickness direction z, and the resin back surface 52 faces downward in the thickness direction z. The resin main surface 51 faces the same direction in the thickness direction z as the substrate main surface 11a, the element main surface 21a, and the element main surface 22a. Each of the signal terminals 19 protrudes upward in the thickness direction z from the resin main surface 51. As shown in FIGS. 15, 16, and 20 to 25, the lower surface of the bonding layer 109 is exposed from the resin back surface 52. As shown in FIG. 15, the resin back surface 52 has a rectangular ring shape surrounding the bonding layer 109 in a plan view.

[0054] Each of the multiple resin side surfaces 531 to 534 is connected to the resin main surface 51. As shown in FIGS. 9 and 16 , the pair of resin side surfaces 531, 532 are spaced apart in the second direction y. The resin side surface 531 faces one side of the second direction y (the y2 side), and the resin side surface 532 faces the other side of the second direction y (the y1 side). Each of the pair of resin side surfaces 531, 532 extends in the first direction x. In the illustrated example, the pair of resin side surfaces 531, 532 are connected to the resin main surface 51 as well as the resin back surface 52. As shown in FIGS. 9 and 20 to 25 , the pair of resin side surfaces 533, 534 are spaced apart in the first direction x. The resin side surface 533 faces one side of the first direction x (the x2 side), and the resin side surface 534 faces the other side of the first direction x (the x1 side). 15 to 17, each of the pair of resin side surfaces 533 and 534 is connected to the resin main surface 51 as well as the resin rear surface 52.

[0055] The sealing resin 50 has a main surface opening 56. The main surface opening 56 is formed in the resin main surface 51. As shown in Fig. 10 , the main surface opening 56 exposes a portion of the main surface metal layer 12 from the resin main surface 51. The main surface opening 56 includes two openings 561, two openings 562, and two openings 563.

[0056] Each of the two openings 561 overlaps the conductor portion 121 in a planar view. As shown in FIG. 12 and other figures, the two openings 561 individually expose two different regions (two exposed regions 121b) of the conductor principal surface 121a of the conductor portion 121. The two openings 561 expose the two exposed regions 121b from the resin principal surface 51. A power terminal 17 is inserted into each of the two openings 561. The two openings 561 are aligned in the first direction x. In the illustrated example, the two openings 561 are arranged on both sides of the signal terminals 191, 193, and 197 in the first direction x. Each of the two openings 561 has a rectangular shape in a planar view. The long sides of each of the two openings 561 extend in the first direction x and the short sides extend in the second direction y. Unlike this example, each of the two openings 561 may have a short side in the first direction x and a long side in the second direction y. Furthermore, the planar shape of each of the two openings 561 is not limited to a rectangle. In the illustrated example (e.g., FIGS. 20 and 25 ), each of the two openings 561 is tapered. In this example, each opening 561 has a cross section perpendicular to the thickness direction z that gradually decreases in size from the resin main surface 51 toward the conductor portion 121. Unlike this example, each opening 561 does not need to be tapered. In this embodiment, the opening 561 is an example of a "second opening" as defined in the claims.

[0057] Each of the two openings 562 overlaps the conductor portion 122 in a planar view. As shown in FIG. 12 and other figures, the two openings 562 individually expose two different regions (two exposed regions 122b) of the conductor principal surface 122a of the conductor portion 122. The two openings 562 expose the two exposed regions 122b from the resin principal surface 51. A power terminal 15 is inserted into each of the two openings 562. The two openings 562 are aligned in the first direction x. Each of the two openings 562 has a rectangular shape in a planar view. Each of the two openings 562 has a long side extending in the second direction y and a short side extending in the first direction x. Unlike this example, each of the two openings 562 may have a short side extending in the second direction y and a long side extending in the first direction x. The planar view shape of each of the two openings 562 is not limited to a rectangle. In the illustrated example (e.g., FIG. 21 ), each of the two openings 562 is tapered. In this example, the cross section of each opening 562 perpendicular to the thickness direction z gradually decreases in the thickness direction z from the resin main surface 51 toward the conductor portion 122. Unlike this example, each opening 562 does not need to be tapered. In this embodiment, the opening 562 is an example of a "third opening" as defined in the claims.

[0058] The two openings 563 overlap the two conductor portions 123, respectively, in a plan view. As shown in FIG. 12 and other figures, the two openings 563 each expose a portion (exposed region 123b) of the conductor principal surface 123a of the corresponding conductor portion 123. Each of the two openings 563 exposes the exposed region 123b of the corresponding conductor portion 123 from the resin principal surface 51. A power terminal 16 is inserted through each of the two openings 563. The two openings 563 are aligned in the first direction x. The two openings 563 are arranged on both sides of the two openings 562 in the first direction x. Each of the two openings 563 has a rectangular shape in a plan view. The long side of each of the two openings 563 is in the second direction y and the short side is in the first direction x. Unlike this example, the short side of each of the two openings 563 may be in the second direction y and the long side is in the first direction x. Furthermore, the planar shape of each of the two openings 563 is not limited to a rectangle. In the illustrated example (for example, FIGS. 20 and 21 ), each of the two openings 563 is tapered. In this example, the cross section of each opening 563 perpendicular to the thickness direction z gradually becomes smaller in the thickness direction z from the resin main surface 51 toward the conductor portion 123. Unlike this example, each opening 563 does not need to be tapered. In this embodiment, the opening 563 is an example of a "first opening" as defined in the claims.

[0059] 9, 10, 16, and 25, the resin main surface 51 has a recess 571 and two recesses 572. As shown in these figures, the recess 571 and the two recesses 572 are each recessed downward in the thickness direction z from the resin main surface 51. In a plan view, the recess 571 and the two recesses 572 are each interposed between the main surface opening 56 and any one of the plurality of signal terminals 19.

[0060] In a plan view, the recess 571 is disposed between the two openings 562 and 563 and the plurality of signal terminals 192, 194, and 196. In a plan view, the recess 571 has a strip shape extending in the first direction x. In the illustrated example, the recess 571 extends from the resin side surface 533 to the resin side surface 534.

[0061] One of the two recesses 572 is located between one of the two openings 561 and the plurality of signal terminals 191, 193, and 197. The other of the two recesses 572 is located between the other of the two openings 561 and the plurality of signal terminals 191, 193, and 197. Each of the two recesses 572 has a strip shape extending in the second direction y in plan view.

[0062] Each of the plurality of power terminals 15, 16, and 17 is electrically connected to one of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22. A current corresponding to the power before or after conversion by the switching operations of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 flows through each of the plurality of power terminals 15, 16, and 17.

[0063] The power terminal 15 is joined to the conductor portion 122 (partition portion 1222). This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 15 is inserted through the two openings 562 and joined to the two exposed regions 122b of the conductor portion 122, respectively. The power terminal 15 is electrically connected to the back electrodes 221 (drain electrodes of the upper arm circuits) of the multiple semiconductor elements 22 via the conductor portion 122. The power terminal 15 is a P terminal (positive terminal) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 11 and other figures, the power terminal 15 is located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 (part of the conductor portion 122) sandwiched therebetween. As shown in FIG. 11, the power terminal 15 is located on the opposite side of the multiple semiconductor elements 21 in the second direction y, with the multiple semiconductor elements 22 sandwiched therebetween. In this embodiment, the power terminal 15 is an example of a "third power terminal" as defined in the claims.

[0064] As shown in FIGS. 9, 11, 21, and the like, the power terminal 15 includes two joining portions 151, a suspension portion 152, and an extension portion 153.

[0065] The two joints 151 are each individually joined to a portion of the conductor main surface 122a of the conductor portion 122 (specifically, the two exposed regions 122b). The two joints 151 are each individually housed in the two openings 562. Therefore, the peripheries of the two joints 151 are each inwardly aligned with the peripheries of the corresponding openings 562 in a plan view. In this embodiment, the joints 151 are an example of a "third joint" as defined in the claims.

[0066] The suspension portion 152 connects two joint portions 151. In the illustrated example, the suspension portion 152 extends in the first direction x from each joint portion 151. In a plan view, the suspension portion 152 has a strip shape extending in the first direction x. Most of the suspension portion 152 is located above each joint portion 151 in the thickness direction z. Furthermore, most of the suspension portion 152 is located above the resin main surface 51 in the thickness direction z. The end of the suspension portion 152 on the side connected to each joint portion 151 is bent downward in the thickness direction z and inserted into the corresponding opening 562.

[0067] The extension portion 153 protrudes from the suspension portion 152 to one side in the second direction y (y2 side). The extension portion 153 causes a part of the power terminal 15 to protrude from the power terminal 16 in a plan view.

[0068] The power terminal 16 is joined to a corresponding one of the two conductor portions 123. This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 16 is inserted through the two openings 563 and joined to the exposed regions 123b of the two conductor portions 123. Each of the two power terminals 16 is electrically connected to the principal surface electrodes 212 (source electrodes of the lower arm circuits) of the multiple semiconductor elements 21 via the corresponding conductor portion 123 and the conductive member 32. The power terminal 16 is an N-terminal (negative terminal) to which a DC power supply voltage to be converted is applied. As shown in FIG. 11 and other figures, the power terminal 16 is located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 (part of the conductor portion 122) sandwiched therebetween. 11 , the power terminal 16 is located on the opposite side of the semiconductor elements 22 from the semiconductor elements 21 in the second direction y. In this embodiment, the power terminal 16 is an example of a “first power terminal” as defined in the claims.

[0069] As shown in FIGS. 9, 11, and 21, the power terminal 16 includes two joining portions 161 and a suspension portion 162.

[0070] The two joint portions 161 are individually joined to portions of the conductor principal surfaces 123a (specifically, exposed regions 123b) of the two conductor portions 123. The two joint portions 161 are individually housed in the two openings 563. Thus, the peripheries of the two joint portions 161 are inwardly positioned relative to the peripheries of the corresponding openings 563 in plan view. In this embodiment, the joint portions 161 are an example of a "first joint portion" as defined in the claims.

[0071] The suspension portion 162 connects two joint portions 161. In the illustrated example, the suspension portion 162 extends from each joint portion 161 in the first direction x. In a plan view, the suspension portion 162 has a strip shape extending in the first direction x. Most of the suspension portion 162 is located above each joint portion 161 in the thickness direction z. The end of the suspension portion 162 connected to each joint portion 161 is bent downward in the thickness direction z and inserted into the corresponding opening 563. In the illustrated example, most of the suspension portion 162 is located above the suspension portion 152 (power terminal 15) in the thickness direction z. Furthermore, most of the suspension portion 162 is located above the resin main surface 51 in the thickness direction z. In a plan view, the suspension portion 152 completely overlaps the suspension portion 162. In this embodiment, the suspension portion 162 is an example of a "first suspension portion" as defined in the claims.

[0072] The power terminal 17 is joined to the conductor portion 121. This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 17 is inserted through the two openings 561 and joined to the two exposed regions 121b of the conductor portion 121, respectively. The power terminal 17 is electrically connected to the back electrodes 211 (drain electrodes of the lower arm circuit) of the multiple semiconductor elements 21 via the conductor portion 121, and is electrically connected to the main surface electrodes 222 (source electrodes of the upper arm circuit) of the multiple semiconductor elements 22 via the conductor portion 121 and the conductive member 31. AC power converted by the multiple semiconductor elements 21 and the multiple semiconductor elements 22 is output from the power terminal 17. In other words, the power terminal 17 is an output terminal for the AC power. As shown in FIG. 11 , the power terminal 17 is located on the opposite side of the multiple semiconductor elements 22 from the multiple semiconductor elements 21 in the second direction y. In this embodiment, the power terminal 17 is an example of a "second power terminal" as defined in the claims.

[0073] As shown in FIGS. 9, 11, 25, and the like, the power terminal 17 includes two joining portions 171 and a suspension portion 172.

[0074] The two joints 171 are each individually joined to a portion of the conductor principal surface 121a of the conductor portion 121 (specifically, the two exposed regions 121b). The two joints 171 are each individually housed in the two openings 561. Therefore, the peripheries of the two joints 171 are each inwardly aligned with the peripheries of the corresponding openings 561 in a plan view. In this embodiment, the joints 171 are an example of a "second joint" as defined in the claims.

[0075] The suspension portion 172 connects the two joint portions 171. In the illustrated example, the suspension portion 172 extends a short distance from each joint portion 171 along the second direction y and then bends in the first direction x. More specifically, in a plan view, the suspension portion 172 extends from one of the two joint portions 171 (e.g., the joint portion 171 on the x1 side in the first direction x) along the second direction y (e.g., the y1 side) and bends in the first direction x (e.g., the x2 side). Then, it bends in the second direction y (e.g., the y2 side) and connects to the other of the two joint portions 171 (e.g., the joint portion 171 on the x2 side in the first direction x). With this configuration, the strip-shaped portion of the suspension portion 172 extending along the first direction x is located outside the sealing resin 50 in a plan view. Most of the suspension portion 172 is strip-shaped and extends in the first direction x in a plan view. Most of this suspension portion 172 is located above each joint 171 in the thickness direction z. Also, most of this suspension portion 172 is located above each resin main surface 51 in the thickness direction z. The end of the suspension portion 172 that is connected to each joint 171 is bent downward in the thickness direction z and inserted into the corresponding opening 561.

[0076] The shapes of the multiple power terminals 15, 16, and 17 are not limited to the above example and can be modified as appropriate depending on the specifications of each semiconductor package B10. For example, in the power terminal 15, the two joint portions 151 do not have to be connected by the suspension portion 152. In this example, each semiconductor package B10 includes two power terminals 15. This configuration can also be similarly modified for the other power terminals 16 and 17.

[0077] The pair of signal boards 601, 602 constitute part of the conductive paths between the multiple signal terminals 19 and the multiple semiconductor elements 21 and the multiple semiconductor elements 22. As shown in FIGS. 13 and 14 , the signal board 601 is located on the y1 side of the multiple semiconductor elements 21 in the second direction y. As shown in FIGS. 16 and 25 , the signal board 601 is bonded to the conductor portion 121. As shown in FIGS. 13 and 14 , the signal board 602 is located on the y2 side of the multiple semiconductor elements 22 in the second direction y. As shown in FIGS. 16 and 22 , the signal board 602 is bonded to the conductor portion 122. In the illustrated example, the signal board 602 is bonded so as to overlap the boundary between the two partition portions 1221, 1222 in a plan view. Each of the pair of signal boards 601, 602 is, for example, a DCB board or an AMB board. Unlike this example, each of the pair of signal boards 601, 602 may be a printed circuit board.

[0078] Each of the pair of signal substrates 601, 602 has an insulating layer 61, a wiring layer 62, a metal layer 63, and a plurality of sleeves 64. Each of the pair of signal substrates 601, 602 is covered with a sealing resin 50 except for a portion of each of the plurality of sleeves 64. Unless otherwise specified, the insulating layer 61, the wiring layer 62, the metal layer 63, and the plurality of sleeves 64 described below are common to each of the pair of signal substrates 601, 602.

[0079] The insulating layer 61 is interposed between the wiring layer 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 may be made of, for example, ceramics. Alternatively, the insulating layer 61 may be made of an insulating resin sheet.

[0080] 22 and 25, the wiring layer 62 is located above the insulating layer 61 in the thickness direction z. The composition of the wiring layer 62 is not limited in any way, but may include copper. As shown in FIG. 14, the wiring layer 62 includes a plurality of wiring portions 621 to 624. The plurality of wiring portions 621 to 624 are spaced apart from one another. The planar shape, arrangement, size, and the like of each of the wiring portions 621 to 624 are not limited to the examples shown in the drawings.

[0081] 22 and 25 , the metal layer 63 is located on the opposite side of the wiring layer 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The composition of the metal layer 63 is not limited in any way, but may include copper. The metal layer 63 of the signal substrate 601 is bonded to the conductor portion 121 by an adhesive layer (not shown). The metal layer 63 of the signal substrate 602 is bonded to the conductor portion 122 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. These adhesive layers are, for example, solder.

[0082] 16 , 22 , and 25 , each of the multiple sleeves 64 is bonded to the wiring layer 62 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z1 side in the thickness direction z) is conductively bonded to the wiring layer 62. As shown in FIGS. 16 , 22 , and 25 , the other end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z2 side in the thickness direction z) is exposed from the sealing resin 50.

[0083] 14 , the thermistor 23 is conductively connected across the wiring portion 623 of the signal substrate 601 and the wiring portion 624 of the signal substrate 601. The thermistor 23 is, for example, an NTC (Negative Temperature Coefficient) thermistor. An NTC thermistor has the characteristic that its resistance decreases gradually with increasing temperature. The thermistor 23 is used as a temperature detection sensor for the semiconductor device A10.

[0084] Each of the signal terminals 19 (signal terminals 191 to 194, 196, and 197) is formed by a metal pin and extends in the thickness direction z. The signal terminals 19 protrude from the sealing resin 50 (a resin main surface 51, described below). The signal terminals 19 (signal terminals 191 to 194, 196, and 197) are individually press-fitted into the sleeves 64 of the pair of signal boards 601 and 602. As a result, each of the signal terminals 19 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62 of the pair of signal boards 601 and 602. The signal terminals 191 to 194 and 196 are electrically connected to one of the semiconductor elements 21 and the semiconductor elements 22, respectively. The two signal terminals 197 are not electrically connected (non-conductive) to either the semiconductor elements 21 or the semiconductor elements 22, but are electrically connected to the thermistor 23.

[0085] 14 , the signal terminal 191 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal substrate 601. The signal terminal 191 is electrically connected to each of the main surface electrodes 213 of the plurality of semiconductor elements 21. A drive signal for driving each semiconductor element 21 is input to the signal terminal 191 (a gate voltage is applied).

[0086] 14 , the signal terminal 192 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal board 602. As a result, the signal terminal 192 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal board 602. The signal terminal 192 is electrically connected to each of the main surface electrodes 223 of the plurality of semiconductor elements 22. A drive signal for driving each semiconductor element 22 is input to the signal terminal 192 (a gate voltage is applied).

[0087] 14 , the signal terminal 193 is located next to the signal terminal 191 in the first direction x. As shown in FIG. 14 , the signal terminal 193 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 601. As a result, the signal terminal 193 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 601. The signal terminal 193 is electrically connected to the main surface electrodes 214 of the multiple semiconductor elements 21. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 214 of the multiple semiconductor elements 21 is applied to the signal terminal 193.

[0088] 14 , the signal terminal 194 is located next to the signal terminal 192 in the first direction x. As shown in FIG. 14 , the signal terminal 194 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 602. As a result, the signal terminal 194 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 602. The signal terminal 194 is electrically connected to the main surface electrodes 224 of the multiple semiconductor elements 22. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 224 of the multiple semiconductor elements 22 is applied to the signal terminal 194.

[0089] As shown in Fig. 14 , the signal terminal 196 is located on the opposite side of the signal terminal 192 in the first direction x, with the signal terminal 194 sandwiched therebetween. As shown in Fig. 14 , the signal terminal 196 is press-fitted into the sleeve 64 joined to the wiring portion 623 of the signal board 602. As a result, the signal terminal 196 is supported by the sleeve 64 and is electrically connected to the wiring portion 623 of the signal board 602. The signal terminal 196 is electrically connected to the conductor portion 122. A voltage equivalent to the DC power input to the power terminal 15 is applied to the signal terminal 196.

[0090] 14 , the pair of signal terminals 197 are located on the opposite side of the signal terminal 191 in the first direction x with the signal terminal 193 sandwiched therebetween, and the pair of signal terminals 197 are adjacent to each other in the first direction x. As shown in FIG. 14 , the pair of signal terminals 197 are individually press-fitted into a pair of sleeves 64 joined to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601, respectively. As a result, the pair of signal terminals 197 are individually supported by the pair of sleeves 64 and are individually conducted to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601. The pair of signal terminals 197 are conducted to the thermistor 23.

[0091] Each of the plurality of connection members 41 to 45 electrically connects parts spaced apart from one another. Each of the plurality of connection members 41 to 45 is, for example, a bonding wire. Unlike this example, each of the plurality of connection members 41 to 45 may be a metal plate material. Each of the plurality of connection members 41 to 45 contains gold (Au). Each of the plurality of connection members 41 to 45 may contain copper or aluminum. Note that the plurality of connection members 41 to 45 are omitted from FIGS. 2 and 16.

[0092] 14 , each of the plurality of connection members 41 is conductively joined to the corresponding main surface electrode 213 of the semiconductor element 21 and the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is conductively connected to the main surface electrodes 213 of the plurality of semiconductor elements 21.

[0093] 14 , each of the plurality of connection members 42 is conductively joined to the corresponding main surface electrode 223 of the semiconductor element 22 and the wiring portion 621 of the signal substrate 602. As a result, the signal terminal 192 is conductively connected to the main surface electrodes 223 of the plurality of semiconductor elements 22.

[0094] 14 , each of the plurality of connection members 43 is electrically connected to the corresponding main surface electrode 214 of the semiconductor element 21 and the wiring portion 622 of the signal substrate 601. This allows the signal terminal 193 to be electrically connected to the main surface electrodes 214 of the plurality of semiconductor elements 21. Note that when each semiconductor element 21 does not include either of the two main surface electrodes 214, each of the plurality of connection members 43 is connected to the main surface electrode 212 of the corresponding semiconductor element 21.

[0095] 14 , each of the plurality of connection members 44 is conductively joined to the corresponding main surface electrode 224 of the semiconductor element 22 and the wiring portion 622 of the signal substrate 602. This allows the signal terminal 194 to be conductively connected to the main surface electrodes 224 of the plurality of semiconductor elements 22. Note that when each semiconductor element 22 does not include either of the two main surface electrodes 224, each of the plurality of connection members 44 is joined to the main surface electrode 222 of the corresponding semiconductor element 22.

[0096] 14 , the connection member 45 is electrically connected to the wiring portion 623 of the signal substrate 602 and the conductor portion 122 (partition portion 1222). As a result, the signal terminal 196 is electrically connected to the back surface electrodes 221 of the plurality of semiconductor elements 22 via the conductor portion 122.

[0097] As shown in Fig. 13 and other figures, the conductive member 31 is bonded to the main surface electrodes 222 of the plurality of semiconductor elements 22 and the conductor portion 121 of the support substrate 10. The main surface electrodes 222 of the plurality of semiconductor elements 22 are electrically connected to the conductor portion 121 via the conductive member 31. The conductive member 31 may contain copper. The conductive member 31 is a metal clip. As shown in Fig. 13 and other figures, the conductive member 31 has a main body portion 311 and a plurality of joint portions 312, 313.

[0098] The main body portion 311 forms a main part of the conductive member 31. As shown in FIG. 13 , the main body portion 311 extends in the first direction x. As shown in FIG. 13 , the main body portion 311 straddles the conductor portion 121 and the conductor portion 122. As shown in FIG. 13 , a plurality of through holes 311 a are formed in the main body portion 311. The plurality of through holes 311 a penetrate the main body portion 311 in the thickness direction z. The plurality of through holes 311 a overlap between the conductor portion 121 and the conductor portion 122 in a plan view. This allows the sealing resin 50 to flow smoothly downward in the thickness direction z of the main body portion 311 when forming the sealing resin 50.

[0099] As shown in FIG. 13 , the multiple bonding portions 312 are individually bonded to the principal surface electrodes 222 of the multiple semiconductor elements 22. Each of the multiple bonding portions 312 faces one of the principal surface electrodes 222 of the multiple semiconductor elements 22. In a plan view, each bonding portion 312 extends from the main body portion 311 toward the y2 side in the second direction y. In the illustrated example, the multiple bonding portions 312 are bifurcated from the main body portion 311, but they do not have to be bifurcated. The tip of each bonding portion 312 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 312 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each bonding portion 312, which is located at a different position in the thickness direction z, to the main body portion 311.

[0100] 13 , the multiple joints 313 are joined to the conductor portion 121. The multiple joints 313 face the conductor portion 121. In a plan view, each joint 313 extends from the main body portion 311 to the y1 side in the second direction y. The tip of each joint 313 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each joint 313 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each joint 313, which is located at a different position in the thickness direction z, to the main body portion 311.

[0101] 18 , the semiconductor device A10 further includes a conductive bonding layer 33. The conductive bonding layer 33 is interposed between the main surface electrodes 222 of the plurality of semiconductor elements 22 and the plurality of bonding portions 312. The conductive bonding layer 33 conductively bonds the main surface electrodes 222 of the plurality of semiconductor elements 22 to the plurality of bonding portions 312. The conductive bonding layer 33 is, for example, solder. Alternatively, the conductive bonding layer 33 may include a sintered body of metal particles.

[0102] 17 , the semiconductor device A10 further includes a conductive bonding layer 34. The conductive bonding layer 34 is interposed between the conductor portion 121 and the bonding portion 313. The conductive bonding layer 34 conductively bonds the conductor portion 121 and the bonding portion 313. The conductive bonding layer 34 is, for example, solder. Alternatively, the conductive bonding layer 34 may include a sintered body of metal particles.

[0103] As shown in FIG. 12 , the conductive member 32 is conductively bonded to the principal surface electrodes 212 of the semiconductor elements 21 and the two conductor portions 123 of the support substrate 10. As a result, the principal surface electrodes 212 of the semiconductor elements 21 are electrically connected to each of the two conductor portions 123 via the conductive member 32. As described above, the power terminals 16 are each bonded to the two conductor portions 123, and therefore the principal surface electrodes 212 of the semiconductor elements 21 are electrically connected to the power terminals 16. The conductive member 32 may contain, for example, copper. The conductive member 32 is a metal clip. In this embodiment, the conductive member 32 is an example of the "conductive member" defined in the claims. As shown in FIG. 12 and other figures, the conductive member 32 includes two main body portions 321, multiple joint portions 322, an intermediate portion 323, and multiple joint portions 324.

[0104] As shown in FIG. 12 , the two main bodies 321 are spaced apart from each other in the first direction x. The two main bodies 321 extend in the second direction y. As shown in FIG. 20 and other figures, the two main bodies 321 are arranged parallel to the conductor principal surface 121 a of the conductor portion 121, the conductor principal surface 122 a of the conductor portion 122, and the conductor principal surface 123 a of each conductor portion 123. In the thickness direction z, the two main bodies 321 are farther from the main surface metal layer 12 (the conductor portion 121, the conductor portion 122, and the two conductor portions 123) than the main body 311 of the conductive member 31. Each of the two main bodies 321 intersects the conductor portion 122 (the partition portion 1221) in a plan view. That is, each of the two main bodies 321 extends from one edge to the other edge of the partition portion 1221 of the conductor portion 122 in the second direction y in a plan view. Both surfaces of the two main body portions 321 in the thickness direction z are covered with sealing resin 50 .

[0105] The intermediate portion 323 is located between the two main body portions 321 in the first direction x. The intermediate portion 323 extends in the first direction x from each of the two main body portions 321. As can be seen from FIG. 12 , the intermediate portion 323 overlaps some of the multiple joint portions 312 of the conductive member 31 in a planar view. The intermediate portion 323 straddles the two conductor portions 121, 122 in a planar view. The intermediate portion 323 has multiple through holes 323a. The multiple through holes 323a penetrate the intermediate portion 323 in the thickness direction z. The multiple through holes 323a are arranged along the first direction x. Each of the multiple through holes 323a overlaps between the two conductor portions 121, 122 in a planar view.

[0106] 12 and 24 , the multiple bonding portions 322 are individually bonded to the principal surface electrodes 212 of the multiple semiconductor elements 21. Each of the multiple bonding portions 322 faces one of the principal surface electrodes 212 of the multiple semiconductor elements 21. In a plan view, the multiple bonding portions 322 extend in the first direction x from the multiple intermediate portions 323. The tip of each bonding portion 322 (the end opposite to the side connected to the intermediate portion 323) is located below the intermediate portion 323 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 322 (the end connected to the intermediate portion 323) is bent in the thickness direction z so as to connect the tip of each bonding portion 322 and each intermediate portion 323, which are located at different positions in the thickness direction z.

[0107] 12 and 22 , the pair of joints 324 are individually joined to the conductors 123. The joining is, for example, solder joining. Alternatively, joining using a joining material containing a sintered body of metal particles, joining by laser welding, ultrasonic joining, or the like may be used. Each of the pair of joints 324 faces a corresponding one of the two conductors 123. Each of the pair of joints 324 is joined to the corresponding conductor 123 on the y1 side in the second direction y relative to the exposed region 123b.

[0108] 17 , the semiconductor device A10 further includes a conductive bonding layer 35. The conductive bonding layer 35 is interposed between the main surface electrodes 212 of the plurality of semiconductor elements 21 and the plurality of bonding portions 322. The conductive bonding layer 35 conductively bonds the main surface electrodes 212 of the semiconductor elements 21 to the plurality of bonding portions 322. The conductive bonding layer 35 is, for example, solder. Alternatively, the conductive bonding layer 35 may include a sintered body of metal particles.

[0109] The shapes of the two conductive members 31, 32 are not limited to the illustrated example. The conductive member 31 may be any member that electrically connects the conductor portion 121 to each of the main surface electrodes 222 of the plurality of semiconductor elements 22. The conductive member 32 may be any member that electrically connects the two conductor portions 123 to each of the main surface electrodes 212 of the plurality of semiconductor elements 21.

[0110] Next, a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 26 to 31. FIG. 26 is a flowchart showing an example of a method for manufacturing the semiconductor device A10. FIGS. 27 to 29 and 31 are cross-sectional views showing a step in the method for manufacturing the semiconductor device A10. The cross sections in FIGS. 27 to 29 and 31 are at the same cross-sectional position as FIG. 16. FIG. 30 is a plan view showing a step in the method for manufacturing the semiconductor device A10.

[0111] As shown in FIG. 26, the manufacturing method of the semiconductor device A10 according to this embodiment includes a substrate preparation step S101, a substrate bonding step S102, an element bonding step S103, a signal substrate bonding step S104, a conductive member bonding step S105, a sleeve bonding step S106, a thermistor bonding step S107, a wire bonding step S108, a molding step S109, and a terminal connection step S110.

[0112] In the substrate preparation step S101, a support substrate 10 including an insulating substrate 11, a main surface metal layer 12, and a back surface metal layer 13 is prepared. In the substrate bonding step S102, the support substrate 10 is bonded to a heat dissipation member C10, as shown in Fig. 27. For example, a bonding layer 109 is used to bond the back surface metal layer 13 of the support substrate 10 to the main body surface 71a of the main body portion 71 of the heat dissipation member C10. In this embodiment, the substrate bonding step S102 is an example of a "substrate bonding step" as defined in the claims.

[0113] 28 , in the element bonding step S103, a plurality of semiconductor elements 21 are mounted on the conductor portion 121, and a plurality of semiconductor elements 22 are mounted on the conductor portion 122. For example, each of the plurality of semiconductor elements 21 is bonded to the conductor main surface 121 a of the conductor portion 121 by a conductive bonding layer 219, and each of the plurality of semiconductor elements 22 is bonded to the conductor main surface 122 a of the conductor portion 122 (partition portion 1221) by a conductive bonding layer 229.

[0114] In the signal substrate bonding process S104, the two signal substrates 601, 602 are each bonded to a corresponding one of the two conductor portions 121, 122. In the conductive member bonding process S105, the conductive member 31 is bonded to the plurality of semiconductor elements 22 and the conductor portion 121, and then the conductive member 32 is bonded to the plurality of semiconductor elements 21 and the two conductor portions 123. In the sleeve bonding process S106, the plurality of sleeves 64 are bonded to the wiring layers 62 of the pair of signal substrates 601, 602 with a conductive adhesive (not shown). In the thermistor bonding process S107, the thermistor 23 is mounted on the signal substrate 601. For example, the thermistor 23 is disposed across the two wiring portions 623, 624 of the signal substrate 601, and the two wiring portions 623, 624 of the signal substrate 601 are electrically connected to the thermistor 23 with a conductive adhesive (not shown). The signal board bonding step S104, the conductive member bonding step S105, the sleeve bonding step S106, and the thermistor bonding step S107 result in the state shown in FIG.

[0115] In the wire bonding step S108, a plurality of connection members 41 to 45 are formed. In an example in which the plurality of connection members 41 to 45 are bonding wires, in the wire bonding step S108, each of the connection members 41 to 45 is formed sequentially by ball bonding using a capillary. Note that the order in which the plurality of connection members 41 to 45 are formed is not limited in any way. Alternatively, each of the connection members 41 to 45 may be formed sequentially by wedge bonding using a wedge tool.

[0116] 30 and 31 , the sealing resin 50 is formed by, for example, molding. The sealing resin 50 is formed on the main body main surface 71 a of the main body portion 71 of the heat dissipation member C10, and covers the bonding layer 109 together with the support substrate 10 (and each component supported by the support substrate 10). The main surface openings 56 (plurality of openings 561, 562, 563) and the plurality of recesses 571, 572 in the resin main surface 51 of the sealing resin 50 are formed in the molding process S109.

[0117] In the terminal connection step S110, the multiple power terminals 15, 16, and 17 and the multiple signal terminals 19 are connected. Specifically, the power terminal 15 is inserted through each of the two openings 562 and joined to a portion of the conductor principal surface 122a (each exposed region 122b) exposed through the two openings 562 of the conductor portion 122. The power terminal 16 is inserted through each of the two openings 563 and joined to a portion of the conductor principal surface 123a (each exposed region 123b) exposed through the two openings 563 of each conductor portion 123. The power terminal 17 is inserted through each of the two openings 561 and joined to a portion of the conductor principal surface 121a (each exposed region 121b) exposed through the two openings 561 of the conductor portion 121. The power terminals 15, 16, and 17 are joined by, for example, laser welding. Alternatively, ultrasonic joining or other joining methods may be used. Furthermore, each signal terminal 19 is press-fitted into a corresponding one of the plurality of sleeves 64 .

[0118] The semiconductor device A10 shown in FIGS. 1 to 25 can be manufactured through the above steps. The manufacturing method of the semiconductor device A10 shown in FIG. 26 is merely an example and is not limited thereto. For example, the timing of the substrate bonding step S102 is not limited as long as it is performed between the substrate preparation step S101 and the molding step S109. As an example, as shown in FIG. 32, the substrate bonding step S102 may be performed between the wire bonding step S108 and the molding step S109. Note that in the manufacturing method of the semiconductor device A10, the order of the element bonding step S103, signal substrate bonding step S104, conductive member bonding step S105, sleeve bonding step S106, thermistor bonding step S107, and wire bonding step S108 may be changed as appropriate. However, the element bonding step S103 must be performed before both the conductive member bonding step S105 and the wire bonding step S108, and the signal substrate bonding step S104 must be performed before the sleeve bonding step S106.

[0119] Next, a power conversion unit U10 including the semiconductor device A10 will be described with reference to Fig. 33. The power conversion unit U10 includes the semiconductor device A10 and a control board E1.

[0120] As shown in FIG. 33 , the control substrate E1 is provided in common for the three semiconductor packages B10. Alternatively, multiple control substrates E1 may be provided individually for each of the three semiconductor packages B10. As can be seen from FIG. 33 , the signal terminals 19 of the three semiconductor packages B10 are inserted into the control substrate E1. The control substrate E1 is electrically connected to each of the signal terminals 19. The control substrate E1 includes, for example, a control circuit that controls the operation of the semiconductor elements 21 and 22 of the three semiconductor packages B10. In an example in which the semiconductor elements 21 and 22 are MOSFETs or IGBTs, the control substrate E1 is a gate driver. The control substrate E1 faces the upper surface (resin main surface 51) of the sealing resin 50 of each of the three semiconductor packages B10. The control substrate E1 is located on the opposite side of the three semiconductor packages B10 from the main body 71 of the heat dissipation member C10. In a plan view, the control substrate E1 overlaps the sealing resin 50 of each of the three semiconductor packages B10. The control substrate E1 is held at a fixed distance in the thickness direction z by a plurality of pedestals (not shown). The plurality of pedestals may be provided, for example, on the main body surface 71 a of the main body 71 of the heat dissipation member C10.

[0121] As shown in FIG. 34 , the control board E1 has a base material 91, main wiring 92, back wiring 93, and internal wiring 94. The base material 91 has a plurality of through holes 911 that penetrate in the thickness direction z. The main wiring 92 is formed on the upper surface of the base material 91 (the surface facing the z1 side in the thickness direction z). The back wiring 93 is formed on the lower surface of the base material 91 (the surface facing the z2 side in the thickness direction z). The internal wiring 94 is disposed on the inner surfaces of the plurality of through holes 911. The internal wiring 94 is connected to the main wiring 92 and the back wiring 93. The main wiring 92 forms a path for mutual conduction between the back wiring 93 and the internal wiring 94 and circuits provided on the control board E1.

[0122] Each signal terminal 19 of the three semiconductor packages B10 is inserted into a corresponding one of the multiple through holes 911 of the control board E1. Fig. 34 shows a state in which the signal terminal 19 of any one of the three semiconductor packages B10 is inserted into the through hole 911 of the base material 91. As can be seen from Fig. 34, all of the signal terminals 19 of the three semiconductor packages B10 are inserted into the through hole 911 of the base material 91.

[0123] As shown in Fig. 34 , each signal terminal 19 includes a tip portion 190. The tip portion 190 is an end portion of each signal terminal 19 that is far from the sealing resin 50. The tip portion 190 has a bulging portion 190A. As shown in Fig. 34 , the bulging portion 190A bulges out in a direction perpendicular to the thickness direction z in the signal terminal 19. In the illustrated example (e.g., Fig. 5 ), the bulging portion 190A of each signal terminal 19 is located higher in the thickness direction z than any of the multiple power terminals 15, 16, and 17.

[0124] As shown in FIG. 34 , the bulging portion 190A of each signal terminal 19 is press-fitted into one of the plurality of through holes 911 of the control board E1. As a result, the internal wiring 94 arranged in one of the plurality of through holes 911 is pressed against the bulging portion 190A of the signal terminal 19 inserted into the corresponding through hole 911. Therefore, each signal terminal 19 is press-fitted into the through hole 911 in the thickness direction z, thereby providing electrical continuity with the control board E1 (its control circuit). The control board E1 is supported by each signal terminal 19 by press-fitting each signal terminal 19 into a corresponding one of the plurality of through holes 911. As can be seen from this configuration, the control board E1 is attached to the tip portion 190 of each signal terminal 19. Alternatively, each signal terminal 19 may not include a bulging portion 190A. That is, each signal terminal 19 may be a straight pin with no change in thickness. In this case, each signal terminal 19 is inserted into a through-hole 911 and then soldered to the control board E1.

[0125] The configuration of the power conversion unit U10 is not limited to the example shown in FIG. 33 . FIG. 35 shows a power conversion unit U11 according to a modified example. In the power conversion unit U11, the control board E1 includes two circuit boards E11 and E12. The two circuit boards E11 and E12 are spaced apart in the thickness direction z. The control board E1 of the power conversion unit U11 includes a plurality of interconnecting wires 96. The two circuit boards E11 and E12 are electrically connected to each other via the interconnecting wires 96. The configuration of the interconnecting wires 96 is not limited in any way, but may be configured as follows, for example. Each interconnecting wire 96 includes a plurality of connection pins provided on the circuit board E11 and a connector provided on the circuit board E12. In each interconnecting wire 96, the plurality of connection pins are connected to the connector, thereby electrically connecting the circuit board E11 and the circuit board E12. The power conversion unit U11 also includes a plurality of positioning pins 97. Each positioning pin 97 is interposed between the two circuit boards E11 and E12 and is used to determine the position of the circuit board E12 relative to the circuit board E11 and to support the circuit board E12.

[0126] First embodiment: Vehicle F1: Next, a vehicle F1 equipped with a semiconductor device A10 will be described with reference to FIG. 36. The vehicle F1 is, for example, an electric vehicle (EV). In FIG. 36, the semiconductor device A10 is described as being equipped in the vehicle F1 as the power conversion unit U10, but the semiconductor device A10 may also be equipped in the vehicle F1 as the semiconductor device A10. In this case, a control board E1 is separately provided in the vehicle F1.

[0127] As shown in FIG. 36 , the vehicle F1 includes an on-board charger F11, a storage battery F12, and a drive system F13. The on-board charger F11 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger F11 via a wired connection. The on-board charger F11 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger F11 is stepped up by the converter and then supplied to the storage battery F12. The stepped-up voltage is, for example, 600 V.

[0128] The drive system F13 drives the vehicle F1. The drive system F13 includes an inverter F131 and a drive source F132. The power conversion unit U10 (semiconductor device A10) constitutes part of the inverter F131. Power stored in the storage battery F12 is supplied to the inverter F131. The power supplied from the storage battery F12 to the inverter F131 is DC power. Alternatively, unlike the power system shown in FIG. 36 , a step-up DC-DC converter may be further provided between the storage battery F12 and the inverter F131. The inverter F131 converts DC power into AC power. The inverter F131, including the power conversion unit U10 (semiconductor device A10), is electrically connected to the drive source F132. The drive source F132 includes an AC motor and a transmission. When AC power converted by the inverter F131 is supplied to the drive source F132, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of the vehicle F1, thereby driving the vehicle F1. To drive the vehicle F1, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the power conversion unit U10 (semiconductor device A10) in the inverter F131 is necessary to output AC power whose frequency is appropriately changed to correspond to the required rotational speed of the AC motor.

[0129] The functions and effects of the semiconductor device A10 and the method for manufacturing the semiconductor device A10 are as follows.

[0130] The semiconductor device A10 includes a semiconductor element 21, an insulating substrate 11, a conductor portion 123, and a sealing resin 50. The conductor portion 123 has a conductor principal surface 123a and is electrically connected to the semiconductor element 21. The insulating substrate 11 is located inward from the periphery of the sealing resin 50 in the thickness direction z. The sealing resin 50 has a resin principal surface 51 and a principal surface opening 56 formed in the resin principal surface 51. The principal surface opening 56 includes an opening 563 that exposes a portion of the conductor principal surface 123a from the resin principal surface 51. With this configuration, the conductor principal surface 123a (the conductor portion 123) is exposed from the resin principal surface 51 of the sealing resin 50 through the opening 563, making it possible to electrically connect a power terminal 16 to the conductor portion 123 after the sealing resin 50 is formed. In other words, the semiconductor device A10 allows for the placement of a power terminal for handling power supply voltage after the sealing resin 50 is formed.

[0131] The manufacturing method of the semiconductor device A10 includes a substrate bonding process S102 in which a support substrate 10 including an insulating substrate 11 and a conductor portion 123 is bonded to a heat dissipation member C10, and a molding process S109 in which a sealing resin 50 covering the support substrate 10 is formed on the heat dissipation member C10. The manufacturing method of the semiconductor device A10 also includes an element bonding process S103 in which a semiconductor element 21 is mounted on the support substrate 10 before the molding process S109. The insulating substrate 11 has a substrate main surface 11a facing the semiconductor element 21 in the thickness direction (thickness direction z) of the semiconductor element 21. The sealing resin 50 has a resin main surface 51 facing the same direction as the substrate main surface 11a in the thickness direction z. The conductor portion 123 has a conductor main surface 123a facing the same direction as the substrate main surface 11a in the thickness direction z. In the molding process S109, a main surface opening 56 exposing a portion of the conductor main surface 123a is formed in the resin main surface 51. According to this configuration, the terminal connection step S110 (a step of connecting the power terminal 16 to a part of the conductor main surface 123a through the main surface opening 56, thereby connecting the power terminal 16 that is electrically connected to the conductor portion 123) can be performed after the molding step S109. In other words, the manufacturing method of the semiconductor device A10 allows the power terminal that handles the power supply voltage to be arranged after the sealing resin 50 is formed.

[0132] In the semiconductor device A10, the opening 563 is rectangular with its longer side extending in the second direction y when viewed in the thickness direction z. Also, in the semiconductor device A10, the power terminal 16 includes a joint 161 and a suspension 162. The joint 161 is a portion joined to the exposed region 123b (the region of the conductor principal surface 123a exposed through the opening 563). The suspension 162 is a portion extending from the joint 161 when viewed in the thickness direction z. The suspension 162 extends from the joint 161 in the first direction x when viewed in the thickness direction z. In this configuration, the opening 563 is rectangular with its shorter side extending in the direction (first direction x) in which the suspension 162 extends from the joint 161. That is, the longer side of the opening 563 is in the direction (second direction y) perpendicular to the direction (first direction x) in which the suspension 162 extends from the joint 161. This configuration allows the size (width) of the power terminal 16 to be increased in the direction perpendicular to the direction of current flow, which means that the cross-sectional area of ​​the power terminal 16 can be increased relative to the flow of current, thereby reducing the wiring resistance of the power terminal 16.

[0133] The semiconductor device A10 includes an insulating substrate 11, a conductor portion 121, a conductor portion 123, and a conductive member 32. The conductor portion 121 and the conductor portion 123 are bonded to the substrate main surface 11a of the insulating substrate 11. The semiconductor element 21 is mounted on the conductor portion 121. The conductor portion 123 is spaced from the conductor portion 121. The conductive member 32 is bonded to a main surface electrode 212 of the semiconductor element 21. The conductive member 32 is electrically connected to the conductor portion 123 and supported by the conductor portion 123. With this configuration, heat generated by the semiconductor element 21 is transferred to the conductive member 32. Furthermore, when a current flows through the conductive member 32, the conductive member 32 generates heat due to parasitic resistance (wiring resistance). The heat transferred to or generated by the conductive member 32 is then transferred to the conductor portion 123 and dissipated to the outside of the semiconductor device A10 via the insulating substrate 11. Therefore, the semiconductor device A10 can dissipate heat that may accumulate in the conductive member 32 more effectively than the semiconductor module described in Patent Document 1 by dissipating heat via the conductor portion 123. In other words, the semiconductor device A10 can improve heat dissipation.

[0134] In the semiconductor device A10, the conductive member 32 forms a path through which a main current flows. The main current refers to a current corresponding to the power before or after conversion by the switching operations of the multiple semiconductor elements 21 and the multiple semiconductor elements 22. In this configuration, a large current flows through the conductive member 32, which can lead to increased heat generation due to the parasitic resistance (wiring resistance) of the conductive member 32. This means that the amount of heat that can accumulate in the conductive member 32 can be large. In other words, improving the heat dissipation performance of the semiconductor device A10 is important. In particular, the main body 321 of the conductive member 32 is strip-shaped extending in the second direction y and has a small cross-sectional area relative to the main current. This increases the parasitic resistance of the main body 321, which can lead to increased self-heat generation in the main body 321. In other words, improving the heat dissipation performance of the conductive member 32 is particularly important in the semiconductor device A10. Therefore, in the semiconductor device A10, as described above, the heat dissipation properties of the conductive member 32 are improved by connecting the conductive member 32 to the conductor portion 123. In other words, the semiconductor device A10 has a preferable structure for improving the heat dissipation properties of the semiconductor device A10.

[0135] In the semiconductor device A10, the conductor portion 121 has a conductor principal surface 121a. Furthermore, in the semiconductor device A10, the principal surface opening 56 includes an opening 561 that exposes a portion of the conductor principal surface 121a from the resin principal surface 51. With this configuration, the conductor principal surface 121a (conductor portion 121) is exposed from the resin principal surface 51 of the sealing resin 50 by the opening 561, so that it becomes possible to electrically connect the power terminal 17 to the conductor portion 121 after the sealing resin 50 is formed. In other words, in the semiconductor device A10, it is possible to arrange a power supply terminal that handles power supply voltage after the sealing resin 50 is formed.

[0136] In the semiconductor device A10, the opening 561 is rectangular with its longer side extending in the first direction x as viewed in the thickness direction z. Also, in the semiconductor device A10, the power terminal 17 includes a joint 171 and a suspension 172. The joint 171 is a portion joined to the exposed region 121b (the region of the conductor principal surface 121a exposed through the opening 561). The suspension 172 is a portion extending from the joint 171 as viewed in the thickness direction z. The end of the suspension 172 connected to the joint 171 extends from the joint 171 in the second direction y as viewed in the thickness direction z. In this configuration, the opening 561 is rectangular with its shorter side extending in the direction in which the suspension 172 extends from the joint 171 (the second direction y). That is, the long side of the opening 561 is in a direction (first direction x) perpendicular to the direction (second direction y) in which the suspension portion 172 extends from the joint portion 171. With this configuration, the size (width) of the power terminal 17 can be increased in the direction perpendicular to the direction of current flow. In other words, the cross-sectional area of ​​the power terminal 17 can be increased relative to the flowing current, thereby reducing the wiring resistance of the power terminal 17.

[0137] In the semiconductor device A10, the semiconductor element 22 is mounted on the conductor portion 122. The conductor portion 122 is electrically connected to the semiconductor element 22 (back electrode 221). In the semiconductor device A10, the conductor portion 122 has a conductor principal surface 122a. Furthermore, in the semiconductor device A10, the principal surface opening 56 includes an opening 562 that exposes a portion of the conductor principal surface 122a from the resin principal surface 51. With this configuration, the conductor principal surface 122a (conductor portion 122) is exposed from the resin principal surface 51 of the sealing resin 50 through the opening 562, making it possible to electrically connect the power terminal 15 to the conductor portion 122 after the sealing resin 50 is formed. In other words, in the semiconductor device A10, it is possible to arrange a power terminal that handles power supply voltage after the sealing resin 50 is formed.

[0138] In the semiconductor device A10, the opening 562 is rectangular with a longer side extending in the second direction y when viewed in the thickness direction z. Also, in the semiconductor device A10, the power terminal 15 includes a joint 151 and a suspension 152. The joint 151 is a portion joined to the exposed region 122b (a region of the conductor principal surface 122a exposed through the opening 562). The suspension 152 is a portion extending from the joint 151 when viewed in the thickness direction z. An end of the suspension 152 connected to the joint 151 extends from the joint 151 in the first direction x when viewed in the thickness direction z. In this configuration, the opening 562 is rectangular with a shorter side extending in the direction in which the suspension 152 extends from the joint 151 (first direction x). That is, the long side of the opening 562 is in a direction (second direction y) perpendicular to the direction (first direction x) in which the suspension portion 152 extends from the joint portion 151. With this configuration, the size (width) of the power terminal 15 can be increased in the direction perpendicular to the direction of current flow. In other words, the cross-sectional area of ​​the power terminal 15 can be increased relative to the flowing current, thereby reducing the wiring resistance of the power terminal 15.

[0139] The semiconductor device A10 includes two conductor portions 123. In the semiconductor device A10, the main surface opening 56 includes two openings 563, which expose the two conductor portions 123 from the resin main surface 51. Furthermore, in the semiconductor device A10, the main surface opening 56 includes two openings 562. The two openings 562 are aligned in the first direction x between the two openings 563. Unlike this configuration, it is possible to connect the two openings 563 to form a single opening. However, if the two openings 563 are connected to form a single opening, regions on both sides of the single opening in the second direction y may be created where it is difficult to properly form the sealing resin 50. In contrast, if two openings 563 are provided, a flow path for the sealing resin 50 can be secured between the two openings 563. In other words, the semiconductor device A10 has a structure that is preferable for properly forming the sealing resin 50.

[0140] The semiconductor device A10 includes a heat dissipation member C10. With this configuration, heat transferred from either the plurality of semiconductor elements 21 or the plurality of semiconductor elements 22 to the main surface metal layer 12 (any of the conductor portion 121, the conductor portion 122, and the conductor portion 123) of the support substrate 10 is transferred to the heat dissipation member C10 via the support substrate 10. In other words, the semiconductor device A10 can improve the heat dissipation properties of the main surface metal layer 12 (the conductor portion 121, the conductor portion 122, and the conductor portion 123).

[0141] In the semiconductor device A10, the resin main surface 51 has a recess 571 recessed downward in the thickness direction z from the resin main surface 51. In plan view, the recess 571 is located between the two openings 562 and 563 and the multiple signal terminals 192, 194, and 196. This configuration increases the creepage distance along the resin main surface 51 between the signal terminals 192, 194, and 196 and the power terminal 15 inserted through the two openings 562 and the power terminal 16 inserted through the two openings 563. In other words, the semiconductor device A10 can reduce unintended short circuits between the multiple signal terminals 192, 194, and 196 and the two power terminals 15 and 16.

[0142] In the semiconductor device A10, the resin main surface 51 has two recesses 572 that are recessed downward in the thickness direction z from the resin main surface 51. Each of the two recesses 572 is located between the corresponding opening 561 and the multiple signal terminals 191, 193, and 197. This configuration increases the creepage distance along the resin main surface 51 between the signal terminals 191, 193, and 197 and the power terminals 17 that are inserted through the two openings 561. In other words, the semiconductor device A10 can reduce unintended short circuits between the multiple signal terminals 191, 193, and 197 and the power terminals 17.

[0143] In the terminal connection step S110 of the manufacturing method of the semiconductor device A10, the power terminals 15, 16, and 17 are joined to the corresponding conductor portions 121, 122, and 123, for example, by laser welding. Alternatively, the power terminals 15, 16, and 17 may be joined to the corresponding conductor portions 121, 122, and 123 by, for example, soldering. However, in the manufacturing method of the semiconductor device A10, the terminal connection step S110 is performed after the molding step S109. Therefore, soldering may require exposure to a higher temperature than the temperature at which the encapsulating resin 50 is formed. On the other hand, when the power terminals 15, 16, and 17 are joined by laser welding, heating is localized and short, minimizing the thermal impact on the surrounding area. Therefore, thermal deformation of the encapsulating resin 50 can be suppressed. In other words, the manufacturing method of the semiconductor device A10 allows the encapsulating resin 50 to maintain its shape better.

[0144] Other embodiments and modifications of the semiconductor device A10 of the present disclosure will be described below. The configurations of the components in the embodiments and modifications can be combined with each other as long as no technical contradiction occurs.

[0145] 37 and 38 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respects. First, the resin main surface 51 has a protrusion 573 instead of a recess 571. Second, the resin main surface 51 has two protrusions 574 instead of two recesses 572.

[0146] The protrusion 573 and the two protrusions 574 each protrude upward in the thickness direction z from the resin main surface 51. In plan view, the protrusion 573 and the two protrusions 574 are each interposed between the main surface opening 56 and one of the multiple signal terminals 19. Like the recess 571, the protrusion 573 is located between the two openings 562 and 563 and the multiple signal terminals 192, 194, and 196 in plan view. Like one of the two recesses 572, one of the two protrusions 574 is located between one of the two openings 561 and the multiple signal terminals 191, 193, and 197. Like the other of the two recesses 572, the other of the two protrusions 574 is located between the other of the two openings 561 and the multiple signal terminals 191, 193, and 197.

[0147] In the semiconductor device A11, the protrusion 573, instead of the recess 571, can increase the creeping distance along the resin main surface 51 between the multiple signal terminals 192, 194, 196 and the power terminal 15 inserted into the two openings 562 and the power terminal 16 inserted into the two openings 563. In addition, in the semiconductor device A11, the protrusion 574, instead of the recess 572, can increase the creeping distance along the resin main surface 51 between the multiple signal terminals 191, 193, 197 and the power terminal 17 inserted into the two openings 561.

[0148] 39 shows a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: the semiconductor device A12 further includes two metal blocks 120.

[0149] The two metal blocks 120 are each provided on a corresponding one of the two conductor portions 123. The two metal blocks 120 are bonded to the conductor main surfaces 123a of the corresponding conductor portions 123. The bonding may be performed using a conductive bonding material (e.g., solder or a sintered body of metal particles), laser bonding, or crimping. The constituent material of each metal block 120 is not limited in any way. Each metal block 120 faces one of two bonding portions 324 (conductive members 32). Each bonding portion 324 (conductive members 32) is bonded to the corresponding metal block 120 and is electrically connected to the conductor portion 123 via the metal block 120.

[0150] In the semiconductor device A12, as can be seen from FIG. 39, it is not necessary to bend the end of each main body portion 321 that is connected to the corresponding joint portion 324.

[0151] 40 shows a semiconductor device A13 according to a third modified example of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respects. First, the sealing resin 50 has a recess 521 recessed in the thickness direction z from the resin rear surface 52. Second, the main body 71 (heat dissipation member C10) has a protrusion 711 protruding in the thickness direction z from the main body main surface 71 a.

[0152] The protrusions 711 are fitted into the recesses 521. At least one recess 521 and one protrusion 711 are arranged around the periphery of the support substrate 10 in a plan view. The number of recesses 521 and protrusions 711 is not limited in any way.

[0153] In the semiconductor device A13, the sealing resin 50 exhibits an anchoring effect with respect to the main body 71 (heat dissipation member C10), which can prevent the sealing resin 50 from peeling off from the main body surface 71a.

[0154] 41 , in an example different from the semiconductor device A13, the main body 71 (heat dissipation member C10) may have, instead of the protrusion 711, a recess 712 recessed from the main body surface 71 a in the thickness direction z, and the sealing resin 50 may have, instead of the recess 521, a protrusion 522 protruding from the resin back surface 52 in the thickness direction z. In this example, the protrusion 522 is fitted into the recess 712. In the semiconductor device shown in FIG. 41 , as in the semiconductor device A13, the sealing resin 50 exhibits an anchoring effect with respect to the main body 71 (heat dissipation member C10). This makes it possible to prevent the sealing resin 50 from peeling off from the main body surface 71 a.

[0155] 42 shows a semiconductor device A20 according to a second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respect: each of the two conductor portions 123 is not part of the main surface metal layer 12 of the support substrate 10, but is formed of a metal block different from the main surface metal layer 12.

[0156] In this embodiment, each conductor 123 is individually bonded to the substrate main surface 11a of the insulating substrate 11. The two conductors 123 in this embodiment are located at the same positions as the two conductors 123 in the semiconductor device A10. Each conductor 123, formed of a metal block, is bonded to the substrate main surface 11a of the insulating substrate 11 with an adhesive (not shown). The adhesive may be conductive or non-conductive, and may be, for example, a brazing material or solder. In an example where the insulating substrate 11 is made of ceramic, the adhesive is preferably a brazing material in consideration of adhesion to the insulating substrate 11. The adhesive preferably has high thermal conductivity. In the illustrated example, the dimension in the thickness direction z of each conductor 123 in this modification is the same as the dimension in the thickness direction z of each conductor 123 in the semiconductor device A10, but may be different.

[0157] In this embodiment, each conductor 123 has a uniform dimension in the thickness direction z. That is, as shown in Fig. 42 , in each conductor 123, the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 161 (power terminal 16) is joined is the same as the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 324 (conductive member 32) is joined.

[0158] In the semiconductor device A20, similar to the semiconductor device A10, the conductor main surface 123a (conductor portion 123) is exposed from the resin main surface 51 of the sealing resin 50 by the opening 563, and therefore, after the sealing resin 50 is formed, it is possible to electrically connect the power terminal 16 to the conductor portion 123. In other words, similar to the semiconductor device A10, the semiconductor device A20 allows a power supply terminal that handles the power supply voltage to be disposed after the sealing resin 50 is formed. This is also true for each of the openings 561 and 562. In addition, the semiconductor device A20 has a common configuration with the semiconductor device A10, and therefore achieves the same effects as the semiconductor device A10.

[0159] Furthermore, as can be understood from each semiconductor device A10, A20, each conductor portion 123 of the present disclosure may not be part of the main surface metal layer 12, but may be composed of a metal block different from the main surface metal layer 12 (the pattern of the main surface metal layer 12).

[0160] 43 shows a semiconductor device A21 according to a first modified example of the second embodiment. The semiconductor device A21 differs from the semiconductor device A20 in the following respect. In each conductor 123, the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 161 (power terminal 16) is joined is different from the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 324 (conductive member 32) is joined. In other words, in each conductor 123, there is a step on the conductor main surface 123a.

[0161] In the semiconductor device A21, the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 161 (power terminal 16) is joined is larger than the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 324 (conductive member 32) is joined. In the example shown in Figure 43, the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 324 (conductive member 32) is joined is the same as the thickness (dimension in the thickness direction z) of the conductor 123 in the semiconductor device A20.

[0162] In the semiconductor device A21, as shown in FIG. 43, the depth (dimension in the thickness direction z) of each opening 563 can be reduced.

[0163] 44 shows a semiconductor device A22 according to a second modification of the second embodiment. The semiconductor device A22 differs from the semiconductor device A21 in the following respect: in each conductor 123, the thickness relationship between the portion to which the corresponding joint 161 (power terminal 16) is joined and the portion to which the corresponding joint 324 (conductive member 32) is joined is different.

[0164] In the semiconductor device A22, the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 161 (power terminal 16) is joined is smaller than the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 324 (conductive member 32) is joined. In the example shown in Figure 44, the thickness (dimension in the thickness direction z) of the portion to which the corresponding joint 161 (power terminal 16) is joined is the same as the thickness (dimension in the thickness direction z) of the conductor 123 in the semiconductor device A20.

[0165] In the semiconductor device A22, as shown in FIG. 44, it is not necessary to bend the end of each main body 321 that is connected to the corresponding joint 324.

[0166] 45 shows a semiconductor device A30 according to a third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respect: a bonding layer 109 is interposed between the resin rear surface 52 and the main body surface 71 a.

[0167] In the semiconductor device A30, unlike the semiconductor device A10, the periphery of the bonding layer 109 in plan view is exposed from the sealing resin 50.

[0168] The semiconductor device A30 can be manufactured, for example, by the manufacturing method shown in Fig. 46. The manufacturing method shown in Fig. 46 differs from the manufacturing method of the semiconductor device A10 (see Fig. 26) in the following respect: the substrate bonding step S102 (a step of bonding the support substrate 10 to the heat dissipation member C10) is performed after the molding step S109 and before the terminal connection step S110.

[0169] In the semiconductor device A30, similar to the semiconductor devices A10 and A20, the conductor main surface 123a (conductor portion 123) is exposed from the resin main surface 51 of the sealing resin 50 by the opening 563, so that the power terminal 16 can be electrically connected to the conductor portion 123 after the sealing resin 50 is formed. In other words, similar to the semiconductor devices A10 and A20, the semiconductor device A30 allows a power terminal that handles power supply voltage to be disposed after the sealing resin 50 is formed. This also applies to the openings 561 and 562. In addition, the semiconductor device A30 has a common configuration with the other semiconductor devices A10 and A20, and therefore achieves the same effects as the semiconductor devices A10 and A20.

[0170] Furthermore, as can be seen from each of the semiconductor devices A10 and A30, in the semiconductor device of the present disclosure, there is no limitation as to whether or not the periphery of the bonding layer 109 in plan view is covered with the sealing resin 50.

[0171] Furthermore, in the manufacturing method of the semiconductor device of the present disclosure, there is no limitation as to whether the substrate bonding step S102 is performed before the molding step S109 (manufacturing method of the semiconductor device A10 shown in Figure 26) or after the molding step S109 (manufacturing method of the semiconductor device A30 shown in Figure 46).

[0172] In a configuration different from the first to third embodiments (including their modifications), in the semiconductor device of the present disclosure, one or two of the multiple power terminals 15, 16, and 17 may be configured to protrude from either of the resin side surfaces 531 and 532, as in the semiconductor module described in Patent Document 1. FIG. 47 illustrates a semiconductor device according to such a modification. In the semiconductor device illustrated in FIG. 47 , the main surface opening 56 of the sealing resin 50 includes two openings 563, but does not include either two openings 561 or two openings 562. In the semiconductor device illustrated in FIG. 47 , the power terminal 15 is formed in a flat plate shape. The joint portion 151 of the power terminal 15 is joined to the conductor portion 122 (compartment portion 1222) inside the sealing resin 50. Furthermore, the power terminal 15 includes an extension portion 154 extending from the joint portion 151 in the second direction y and protruding from the resin side surface 531. 47 includes two power terminals 17, each formed in a flat plate shape. A joint 171 of each power terminal 17 is joined to a conductor 121 inside the sealing resin 50. The power terminal 17 further includes an extension 174 that extends from the joint 171 in the second direction y and protrudes from the resin side surface 532. As can be understood from this modification, the semiconductor device of the present disclosure is not limited to one in which all of the multiple power terminals 15, 16, and 17 are connected from the upper surface (resin main surface 51) of the sealing resin 50 to the main surface metal layer 12 (any of the multiple conductors 121, 122, and 123).

[0173] In a configuration different from the first to third embodiments (including their variations), in the semiconductor device of the present disclosure, the heat dissipation section 73 may be configured, for example, as a block, or may be configured as a box that allows fluid to flow inside. For example, FIGS. 48 and 49 show a semiconductor device in which the heat dissipation section 73 is configured as a block. Unlike the example shown in FIGS. 48 and 49 , the heat dissipation section 73 may be divided into three blocks corresponding to each semiconductor package B10. As can be understood from this variation, in the semiconductor device of the present disclosure, the configuration of the heat dissipation section 73 of the heat dissipation member C10 is not limited in any way. Furthermore, in the semiconductor device of the present disclosure, the heat dissipation member C10 does not have to include the heat dissipation section 73.

[0174] In the first to third embodiments (including their modified examples), the arrangement of the multiple signal terminals 19 in each semiconductor package B10 is not limited to the illustrated example. For example, the multiple signal terminals 19 may be arranged closer to either the side where the two power terminals 15 and 16 are arranged or the side where the power terminal 17 is arranged in the second direction y. FIG. 50 shows an example (semiconductor package B11) in which the multiple signal terminals 19 are arranged closer to the power terminal 17 in the second direction y. In the semiconductor package B11, the multiple signal terminals 19 are aligned in a single row along the first direction x. Unlike this example, the multiple signal terminals 19 may be arranged in multiple rows closer to the power terminal 17. In the example shown in FIG. 50 , the multiple signal terminals 19 include multiple signal terminals 191 to 194. However, the multiple signal terminals 19 may include other signal terminals 196 and 197 instead of or in addition to at least one of the multiple signal terminals 191 to 194. In the example shown in FIG. 50 , signal terminals 191 and 193 electrically connected to multiple semiconductor elements 21 and signal terminals 192 and 194 electrically connected to multiple semiconductor elements 22 are arranged on opposite sides of the center of the sealing resin 50 in the first direction x. However, the order of the multiple signal terminals 19 along the first direction x is not limited to this. In the modified example shown in FIG. 50 , the arrangement, number, size, shape, etc. of each component of each semiconductor package may be appropriately changed depending on the arrangement of the multiple signal terminals 19. This semiconductor package B11 may be bonded to a single heat dissipation member C10, similar to the semiconductor device A10. FIG. 51 shows a semiconductor device including the semiconductor package B11, in which three semiconductor packages B11 are bonded to a single heat dissipation member C10. The three semiconductor packages B11 are arranged along the first direction x on a single heat dissipation member C10.

[0175] In a configuration different from the first to third embodiments (including their modified examples), in the semiconductor device of the present disclosure, the number of semiconductor packages B10 is not limited to three, and may be one, two, or four or more. For example, in a semiconductor device including one semiconductor package B10, one semiconductor package B10 is mounted on one heat dissipation member C10.

[0176] The semiconductor device and semiconductor device manufacturing method according to the present disclosure are not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the semiconductor device manufacturing method according to the present disclosure can be freely designed and modified in various ways. For example, the semiconductor device and semiconductor device manufacturing method according to the present disclosure include embodiments related to the following appendices. Note that, although examples of each component in the following appendices are shown in parentheses using the symbols in the above-described embodiment (including modified examples), the present disclosure is not limited to these. Appendix 1. a first semiconductor element (21); an insulating substrate (11) having a substrate main surface (11a) facing the first semiconductor element (21) in a thickness direction (z) of the first semiconductor element (21) and supporting the first semiconductor element (21); a first conductor portion (123) joined to the substrate main surface (11a); and a sealing resin (50) covering the first semiconductor element (21), a part of the first conductor portion (123), and the insulating substrate (11), wherein the first conductor portion (123) has a first conductor main surface (123a) facing in the same direction as the substrate main surface (11a) in the thickness direction (z) and is electrically connected to the first semiconductor element (21), the insulating substrate (11) is located inward from the periphery of the sealing resin (50) as viewed in the thickness direction (z), The semiconductor device (A10) according to Appendix 1 further includes a first power terminal (16) inserted through the first opening (563), the first conductor main surface (123a) including a first exposed region (123b) exposed through the first opening (563), and the first power terminal (16) including a first bonding portion (161) bonded to the first exposed region (123b). Appendix 3. The semiconductor device (A10) according to Appendix 2, wherein the first opening (563) is rectangular when viewed in the thickness direction (z).Supplementary Note 4. The semiconductor device (A10) according to Supplementary Note 3, wherein the first power terminal (16) includes a first suspension portion (162) extending from the first joint portion (161) when viewed in the thickness direction (z), and the first opening (562) has a short side in a direction (first direction x) in which the first suspension portion (162) extends from the first joint portion (161) when viewed in the thickness direction (z). Supplementary Note 5. The semiconductor device (A10) according to any one of Supplementary Notes 2 to 4, further comprising a second conductor (122) bonded to the substrate main surface (11a) and spaced apart from the first conductor (123), wherein the first semiconductor element (21) has an element main surface (21a) facing the same direction as the substrate main surface (11a) in the thickness direction (z) and a main surface electrode (212) formed on the element main surface (21a), wherein the first semiconductor element (21) is mounted on the second conductor (122), and the first conductor (123) is electrically connected to the main surface electrode (212).Supplementary Note 6. The semiconductor device (A10) according to Supplementary Note 5, further comprising a conductive member (32) electrically connecting the first conductor (123) and the main surface electrode (212), wherein the conductive member (32) is covered with the sealing resin (50).Supplementary Note 7. The semiconductor device (A10) according to Appendix 5 or Appendix 6, wherein the second conductor portion (121) has a second conductor main surface (121a) facing in the same direction as the substrate main surface (11a) in the thickness direction (z), and the main surface opening (56) includes a second opening (561) exposing a portion of the second conductor main surface (121a) from the resin main surface (51). Appendix 8. The semiconductor device (A10) according to Appendix 7, further comprising a second power terminal (17) inserted through the second opening (561), wherein the second conductor main surface (121a) includes a second exposed region (121b) exposed from the second opening (561), and the second power terminal (17) includes a second bonding portion (171) bonded to the second exposed region (121b). Appendix 8-1. The semiconductor device (A10) according to Appendix 8, wherein the second opening (561) is rectangular when viewed in the thickness direction (z).Supplementary Note 8-2. The semiconductor device (A10) according to Supplementary Note 8-1, wherein the second power terminal (17) includes a second suspension portion (172) extending from the second joint portion (171) when viewed in the thickness direction (z), and the second opening (561) has a short side in a direction (second direction y) in which the second suspension portion (172) extends from the second joint portion (171) when viewed in the thickness direction (z). Supplementary Note 9. The semiconductor device (A10) according to any one of Supplementary Note 4 to Supplementary Note 8, further comprising: a second semiconductor element (22) covered with the sealing resin (50); and a third conductor portion (122) bonded to the substrate main surface (11a) and on which the second semiconductor element (22) is mounted. Supplementary Note 10. The semiconductor device (A10) according to Appendix 9, wherein the third conductor portion (122) has a third conductor main surface (122a) facing in the same direction as the substrate main surface (11a) in the thickness direction (z), and the main surface opening (56) includes a third opening (562) exposing a portion of the third conductor main surface (122a) from the resin main surface (51). Appendix 11. The semiconductor device (A10) according to Appendix 10, further comprising a third power terminal (15) inserted into the third opening (562), wherein the third conductor main surface (122a) includes a third exposed region (122b) exposed from the third opening (562), and the third power terminal (15) includes a third bonding portion (151) bonded to the third exposed region (122b). Appendix 11-1. The semiconductor device (A10) according to Appendix 11, wherein the third opening (562) is rectangular as viewed in the thickness direction (z). Appendix 11-2. The semiconductor device (A10) according to Appendix 11-1, wherein the third power terminal (15) includes a third suspension portion (152) extending from the third joint portion (151) as viewed in the thickness direction (z), and the third opening (562) has a short side in a direction in which the third suspension portion (152) extends from the third joint portion (151) (first direction x) as viewed in the thickness direction (z).Supplementary Note 12. The semiconductor device (A10) according to Supplementary Note 11, further comprising an additional first conductor portion (123), wherein the main surface opening portion (56) includes an additional first opening (563) that exposes the additional first conductor portion (123) from the resin main surface (51), thereby including two first openings (563), wherein the two first openings (563) are arranged along a first direction (x) perpendicular to the thickness direction (z), and the third opening (562) is located between the two first openings (563) in the first direction (x). Supplementary Note 13. The semiconductor device (A10) according to Supplementary Note 12, wherein the main surface opening (56) includes an additional third opening (562) that exposes a portion of the third conductor main surface (122a) from the resin main surface (51), thereby including two third openings (562), and the two third openings (562) are aligned in the first direction (x) between the two first openings (563).Supplementary Note 14. The semiconductor device (A10) according to Supplementary Note 13, wherein a portion of the first power terminal (16) and a portion of the third power terminal (15) overlap each other when viewed in the thickness direction (z).Supplementary Note 15. The semiconductor device (A10) according to any one of Supplements 1 to 14, further including a heat dissipation member (C10) located on the opposite side of the insulating substrate (11) from the first semiconductor element (21) in the thickness direction (z).Supplementary Note 16. The semiconductor device (A10) according to Appendix 15, wherein the sealing resin (50) is formed on the heat dissipation member (C10) and is located inward from the periphery of the heat dissipation member (C10) as viewed in the thickness direction (z). Appendix 17. The semiconductor device (A10) according to any one of Appendixes 1 to 16, further comprising a signal terminal (19) protruding from the resin main surface (51). Appendix 18. The semiconductor device (A10) according to Appendix 17, wherein the resin main surface (51) has a recess (571, 572) located between the signal terminal (19) and the main surface opening (561). Appendix 18-1. The semiconductor device (A11) according to Appendix 18, wherein the resin main surface (51) has a protrusion (571, 572) located between the signal terminal (19) and the main surface opening (56).Supplementary Note 18-2. The semiconductor device (A10) according to any one of Supplementary Note 1 to Supplementary Note 18, Supplementary Note 8-1, Supplementary Note 8-2, Supplementary Note 11-1, Supplementary Note 11-2, and Supplementary Note 18-1, wherein the first semiconductor element (21) includes a semiconductor substrate. Supplementary Note 18-3. The semiconductor device (A10) according to Supplementary Note 18-2, wherein the semiconductor substrate includes either silicon, a wide bandgap semiconductor having a wider bandgap than silicon (e.g., silicon carbide or gallium nitride), or an ultra-wide bandgap semiconductor having a wider bandgap than a wide bandgap semiconductor (e.g., gallium oxide, diamond, or aluminum nitride). Supplementary Note 18-4. Supplementary Note 1 to Supplementary Note 18, Supplementary Note 8-1, Supplementary Note 8-2, and Supplementary Note 11-1. A power conversion unit (U10, U11) further comprising: a semiconductor device according to any one of Supplementary Note 11-2, Supplementary Note 18-1, Supplementary Note 18-2, and Supplementary Note 18-3; and a control board (E1) for driving the first semiconductor element (21). Supplementary Note 18-5. A vehicle (F1) comprising: a semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 18, Supplementary Note 8-1, Supplementary Note 8-2, and Supplementary Note 11-1; and a drive source (F132), wherein the semiconductor device is electrically connected to the drive source (F132).Supplementary Note 19. The method includes a substrate bonding step (S101) of bonding a substrate (10) including an insulating substrate (11) and a conductor portion (123) to a heat dissipation member (C10), a molding step (S109) of forming a sealing resin (50) covering the substrate (10) on the heat dissipation member (C10), and a terminal connection step (S110) of connecting a power terminal (16) that is conductive to the conductor portion (123), and further includes an element bonding step (S103) of mounting a semiconductor element (21) on the substrate (10) before the molding step (S109), wherein the insulating substrate (11) has a substrate main surface (11a) that faces the semiconductor element (21) in a thickness direction (z) of the semiconductor element (21), and the sealing resin (50) has a resin main surface (51) that faces the same direction as the substrate main surface (11a) in the thickness direction (z), A method for manufacturing a semiconductor device (A10), wherein the conductor portion (123) has a conductor main surface (123a) facing in the same direction as the substrate main surface (11a) in the thickness direction (z), and in the molding step (S109), a main surface opening (56) exposing a portion of the conductor main surface (123a) is formed in the resin main surface (51), and in the terminal connection step (S110), the power terminal (16) is connected to the portion of the conductor main surface (123a) from the main surface opening (56). Appendix 19-1. A method for manufacturing a semiconductor device according to Appendix 19, wherein the element bonding step is performed before the substrate bonding step. Appendix 19-2. A method for manufacturing a semiconductor device according to Appendix 19, wherein the element bonding step is performed after the substrate bonding step. Appendix 19-3. The method for manufacturing a semiconductor device according to any one of Supplementary Note 19, Supplementary Note 19-1, and Supplementary Note 19-2, wherein the terminal connecting step connects the power terminals by laser welding or ultrasonic bonding.Supplementary Note 20. The semiconductor device according to Supplementary Note 1, wherein the first semiconductor element (21) has an element back surface (21b) facing the substrate main surface (11a) in the thickness direction (z) and a back surface electrode (211) formed on the element back surface (21b), and the first conductor portion (121) is mounted on the first semiconductor element (21) and is electrically connected to the back surface electrode (212).

[0177] A10 to A13, A20 to A22, A30: semiconductor device 10: supporting substrate 109: bonding layer 11: insulating substrate 11a: substrate main surface 11b: substrate back surface 12: main surface metal layer 121: conductor portion 121a: conductor main surface 121b: exposed area 122: conductor portion 122a: conductor main surface 122b: exposed area 1221, 1222: partition portion 123: conductor portion 123a: conductor main surface 123b: exposed area 120: metal block 13: back surface metal layer 15: power terminal 151: bonding portion 152: suspension portion 153: extension portion 154: extension portion 16: power terminal 161: bonding portion 162: suspension portion 17: power terminal 171: bonding portion 172: suspension portion 174: Extension portion 19, 191 to 194, 196, 197: Signal terminal 190: Tip portion 190A: Bulging portion 21: Semiconductor element 21a: Element main surface 21b: Element back surface 211: Back electrode 212, 213, 214: Principal surface electrode 219: Conductive bonding layer 22: Semiconductor element 22a: Element main surface 22b: Element back surface 221: Back electrode 222, 223, 224: Principal surface electrode 229: Conductive bonding layer 23: Thermistor 31: Conductive member 311: Main body portion 311a: Through hole 312: Bonding portion 313: Bonding portion 32: Conductive member 321: Main body portion 322: Bonding portion 323: Intermediate portion 323a: Through hole 324: Bonding portion 33, 34, 35: Conductive bonding layer 41 to 45: Connection member 50: Sealing resin 51: Resin main surface 52: Resin back surface 521: Recess 522: Protrusion 531 to 534: Resin side surface 56: Main surface opening 561, 562, 563: Opening 571, 572: Recess 573, 574: Protrusion 601, 602: Signal substrate 61: Insulating layer 62: Wiring layer 621 to 624: Wiring portion 63: Metal layer 64: Sleeve 71: Main body portion 71a: Main body main surface 71b: Main body back surface 711: Protrusion 712: Recess 73: Heat dissipation portion 91: Base material 911: Through hole 92: Main portion wiring 93: Back portion wiring 94: Internal wiring 96: Interconnect wiring 97: Positioning pin B10, B11: Semiconductor package C10: Heat dissipation member E1: Control board E11,E12: Circuit board F1: Vehicle F11: On-board charger F12: Storage battery F13: Drive system F131: Inverter F132: Drive source S101: Board preparation process S102: Board bonding process S103: Element bonding process S104: Signal board bonding process S105: Conductive member bonding process S106: Sleeve bonding process S107: Thermistor bonding process S108: Wire bonding process S109: Molding process S110: Terminal connection process U10, U11: Power conversion unit,

Claims

1. A semiconductor device comprising: a first semiconductor element; an insulating substrate having a substrate principal surface facing the first semiconductor element in a thickness direction of the first semiconductor element and supporting the first semiconductor element; a first conductor portion bonded to the substrate principal surface; and a sealing resin covering the first semiconductor element, a portion of the first conductor portion, and the insulating substrate, wherein the first conductor portion has a first conductor principal surface facing the same direction as the substrate principal surface in the thickness direction and is conductive to the first semiconductor element; the insulating substrate is located inward from the periphery of the sealing resin as viewed in the thickness direction; the sealing resin has a resin principal surface facing the same direction as the substrate principal surface and a principal surface opening formed in the resin principal surface, and the principal surface opening includes a first opening exposing a portion of the first conductor principal surface from the resin principal surface.

2. The semiconductor device according to claim 1, further comprising a first power terminal inserted into the first opening, the first conductor main surface including a first exposed region exposed from the first opening, and the first power terminal including a first joint portion joined to the first exposed region.

3. The semiconductor device according to claim 2, wherein the first opening is rectangular when viewed in the thickness direction.

4. The semiconductor device described in claim 3, wherein the first power terminal includes a first suspension portion extending from the first joint portion when viewed in the thickness direction, and the first opening has a short side in the direction in which the first suspension portion extends from the first joint portion when viewed in the thickness direction.

5. A semiconductor device according to any one of claims 2 to 4, further comprising a second conductor bonded to the substrate main surface and spaced apart from the first conductor, wherein the first semiconductor element has an element main surface facing in the same direction as the substrate main surface in the thickness direction and a main surface electrode formed on the element main surface, the first semiconductor element being mounted on the second conductor, and the first conductor being electrically connected to the main surface electrode.

6. The semiconductor device according to claim 5, further comprising a conductive member that electrically connects said first conductor portion and said main surface electrode, said conductive member being covered with said sealing resin.

7. A semiconductor device according to claim 5 or claim 6, wherein the second conductor portion has a second conductor main surface facing in the same direction as the substrate main surface in the thickness direction, and the main surface opening includes a second opening that exposes a portion of the second conductor main surface from the resin main surface.

8. The semiconductor device described in claim 7, further comprising a second power terminal inserted into the second opening, the second conductor main surface including a second exposed region exposed from the second opening, and the second power terminal including a second joint portion joined to the second exposed region.

9. The semiconductor device according to any one of claims 4 to 8, further comprising: a second semiconductor element covered with the sealing resin; and a third conductor portion bonded to the main surface of the substrate and on which the second semiconductor element is mounted.

10. The semiconductor device described in claim 9, wherein the third conductor portion has a third conductor main surface facing in the same direction as the substrate main surface in the thickness direction, and the main surface opening includes a third opening that exposes a portion of the third conductor main surface from the resin main surface.

11. The semiconductor device described in claim 10, further comprising a third power terminal inserted into the third opening, the third conductor main surface including a third exposed region exposed from the third opening, and the third power terminal including a third bonding portion bonded to the third exposed region.

12. The semiconductor device described in claim 11, further comprising an additional first conductor portion, wherein the main surface opening includes an additional first opening that exposes the additional first conductor portion from the resin main surface, thereby including two first openings, wherein the two first openings are arranged along a first direction perpendicular to the thickness direction, and the third opening is located between the two first openings in the first direction.

13. The semiconductor device described in claim 12, wherein the main surface opening includes an additional third opening that exposes a portion of the third conductor main surface from the resin main surface, thereby including two third openings, and the two third openings are aligned in the first direction between the two first openings.

14. The semiconductor device according to claim 13, wherein a portion of the first power terminal and a portion of the third power terminal overlap each other when viewed in the thickness direction.

15. The semiconductor device according to any one of claims 1 to 14, further comprising a heat dissipation member located on the insulating substrate on the opposite side to the first semiconductor element in the thickness direction.

16. The semiconductor device according to claim 15, wherein the sealing resin is formed on the heat dissipation member and is located inward from the periphery of the heat dissipation member when viewed in the thickness direction.

17. The semiconductor device according to any one of claims 1 to 16, further comprising a signal terminal protruding from the main surface of the resin.

18. The semiconductor device according to claim 17, wherein the resin main surface has a recess located between the signal terminal and the main surface opening.

19. A method for manufacturing a semiconductor device, comprising: a substrate bonding step of bonding an insulating substrate and a substrate including a conductor portion to a heat dissipation member; a molding step of forming a sealing resin covering the substrate on the heat dissipation member; and a terminal connection step of connecting a power terminal conductive to the conductor portion, wherein the method further comprises an element bonding step of mounting a semiconductor element on the substrate before the molding step, wherein the insulating substrate has a substrate main surface facing the semiconductor element in a thickness direction of the semiconductor element, the sealing resin has a resin main surface facing in the same direction as the substrate main surface in the thickness direction, and the conductor portion has a conductor main surface facing in the same direction as the substrate main surface in the thickness direction, wherein the molding step forms a main surface opening in the resin main surface to expose a portion of the conductor main surface, and the terminal connection step connects the power terminal to the portion of the conductor main surface through the main surface opening.

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