Semiconductor device

Abstract

This semiconductor device comprises: a first semiconductor element that has an element main surface and a main surface electrode formed on the element main surface; an insulating substrate that has a substrate main surface facing the first semiconductor element and supports the first semiconductor element; a first conductor part that is joined to the substrate main surface and on which the first semiconductor element is mounted; a second conductor part that is joined to the substrate main surface and is separate from the first conductor part; a conduction member that is joined to the main surface electrode; and a first power terminal that is electrically connected to the main surface electrode via the conduction member. The second conductor part supports the first power terminal and the conduction member.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices incorporating semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) have been widely known. Patent Document 1 (PTL 1) discloses an example of a conventional semiconductor device (semiconductor module). The semiconductor module described in Patent Document 1 includes a first semiconductor element, a second semiconductor element, a first conductive portion, a second conductive portion, a first conductive member, a second conductive member, and a plurality of input terminals. The first semiconductor element is bonded to the first conductive portion, and the second semiconductor element is bonded to the second conductive portion. The first semiconductor element and the second semiconductor element are electrically connected via the first conductive member and the second conductive portion. The first semiconductor element is electrically connected to one of the plurality of input terminals via the first conductive portion. The second semiconductor element is electrically connected to another of the plurality of input terminals via the second conductive member.

[0003] When the semiconductor module disclosed in Patent Document 1 is in use, heat is generated from each semiconductor element. This heat increases the temperature of the conductive members bonded to each semiconductor element. For example, because the second conductive member is connected to the second semiconductor element, heat from the second semiconductor element is transferred to the second conductive member, potentially increasing the temperature of the second conductive member. Furthermore, the temperature of each conductive member may also increase due to self-heating caused by parasitic resistance (wiring resistance) when a current flows through it. As the temperature of each conductive member increases, the electrical resistance of the conductive member may also increase. In other words, heat accumulated in the conductive members may degrade the electrical performance of the semiconductor module. Therefore, dissipating heat from the conductive members is an important issue.

[0004] Japanese Patent Application Laid-Open No. 2023-181544

[0005] [Summary] An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that has improved heat dissipation properties.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises: a first semiconductor element having an element main surface facing one side in the thickness direction and a main surface electrode formed on the element main surface; an insulating substrate having a substrate main surface facing the first semiconductor element and supporting the first semiconductor element; a first conductor portion bonded to the substrate main surface and carrying the first semiconductor element; a second conductor portion bonded to the substrate main surface and spaced apart from the first conductor portion; a conductive member bonded to the main surface electrode; and a first power terminal electrically connected to the main surface electrode via the conductive member, wherein the second conductor portion supports the first power terminal and the conductive member.

[0007] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. FIG. 3 is a view showing the sealing resin in the plan view of FIG. 2 with imaginary lines. FIG. 4 is a view showing the plan view of FIG. 3 with one of two conductive members and the sealing resin omitted. FIG. 5 is a view showing the plan view of FIG. 4 with the other of the two conductive members, two first power terminals, two second power terminals, and a third power terminal omitted. FIG. 6 is a front view showing the semiconductor device according to the first embodiment. FIG. 7 is a bottom view showing the semiconductor device according to the first embodiment. FIG. 8 is a rear view showing the semiconductor device according to the first embodiment. FIG. 9 is a left side view showing the semiconductor device according to the first embodiment. FIG. 10 is a right side view showing the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 3. FIG. 12 is a partially enlarged view showing a portion (near the second semiconductor element) of FIG. 11. FIG. 13 is a partially enlarged view of a portion of FIG. 11 (near the first semiconductor element). FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 3. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 3. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 3. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 3. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 3. FIG. 19 is a plan view showing a power conversion unit including a semiconductor device according to the first embodiment. FIG. 20 is a view in which the wiring board is omitted from the plan view of FIG. 19. FIG. 21 is a left side view of the power conversion unit shown in FIG. 19. FIG. 22 is an enlarged cross-sectional view of a main portion of the power conversion unit shown in FIG. 19. FIG. 23 is a plan view showing a power conversion unit according to a first modified example, in which the wiring board is omitted. FIG. 24 is a left side view showing a power conversion unit according to a second modified example. Fig. 25 is a cross-sectional view showing another mounting example of the semiconductor device according to the first embodiment, and corresponds to the cross section of Fig. 14. Fig. 26 is a schematic diagram of a vehicle equipped with a power conversion unit including the semiconductor device according to the first embodiment. Fig. 27 is a cross-sectional view showing a semiconductor device according to a first modified example of the first embodiment, and corresponds to the cross section of Fig. 14. Fig. 28 is a cross-sectional view showing a semiconductor device according to a second modified example of the first embodiment, and corresponds to the cross section of Fig. 14.FIG. 29 is a cross-sectional view showing a semiconductor device according to a third modified example of the first embodiment, corresponding to the cross section of FIG. 14 . FIG. 30 is a cross-sectional view showing a semiconductor device according to a fourth modified example of the first embodiment, corresponding to the cross section of FIG. 14 . FIG. 31 is a plan view showing a semiconductor device according to a second embodiment, with the sealing resin indicated by imaginary lines. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII of FIG. 31 . FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII of FIG. 31 . FIG. 34 is a perspective view showing a semiconductor device according to a third embodiment. FIG. 35 is a plan view showing a semiconductor device according to the third embodiment. FIG. 36 is a view in which the first power terminal, the second power terminal, and the third power terminal are omitted from the plan view of FIG. 35 . FIG. 37 is a view in which the sealing resin is indicated by imaginary lines from the plan view of FIG. 36 . FIG. 38 is a perspective view showing a semiconductor device according to a modified example. FIG. 39 is a perspective view showing a semiconductor device according to another modified example.

[0008] DETAILED DESCRIPTION A preferred embodiment of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0009] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps part of object B." "Object A (or its material) contains material C" includes "object A (or its material) is made of material C" and "object A (or its material) is mainly composed of material C." "A surface A faces in direction B (one side or the other side of direction B)" does not necessarily mean that the angle between surface A and direction B is strictly 90°, but also includes the case where surface A is tilted with respect to direction B. "A surface A is perpendicular to surface B" does not necessarily mean that the angle between surface A and surface B is strictly 90°, but also includes the case where surface A is tilted with respect to surface B, unless otherwise specified. Unless otherwise specified, the phrase "an object A (surface A) is parallel to an object B (surface B)" is not limited to a strict definition, and includes cases where an object A (surface A) is tilted relative to an object B (surface B) (for example, a slight deviation due to a manufacturing error).

[0010] 1 to 18 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes a support substrate 10, two first power terminals 14, two second power terminals 15, a third power terminal 16, a plurality of signal terminals 171 to 174, 176, and 177, a plurality of first semiconductor elements 21, a plurality of second semiconductor elements 22, a thermistor 23, two conductive members 31 and 32, a plurality of connecting members 41 to 45, a sealing resin 50, and a pair of signal substrates 601 and 602. In the following description, the plurality of signal terminals 171 to 174, 176, and 177 will be referred to as a plurality of signal terminals 17 unless otherwise distinguished.

[0011] For ease of explanation, reference will be made to a thickness direction z, a first direction y, and a second direction x, which are perpendicular to each other. As an example, the thickness direction z corresponds to the thickness direction of the semiconductor device A10. "Planar view" refers to a view in the thickness direction z. The first direction y is perpendicular to the thickness direction z. The second direction x is perpendicular to the thickness direction z and the first direction y.

[0012] The semiconductor device A10 converts a DC power supply voltage applied to two first power terminals 14 and a third power terminal 16 into an AC voltage using a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22. The converted AC voltage is input from two second power terminals 15 to a power supply target such as a motor.

[0013] As shown in FIGS. 5 , 11 to 13 , 16 , and 17 , the support substrate 10 supports a plurality of first semiconductor elements 21 and second semiconductor elements 22 in the thickness direction z. The support substrate 10 is, for example, a DCB (Direct Copper Bonding) substrate. Alternatively, the support substrate 10 may be an AMB (Active Metal Brazing) substrate. The support substrate 10 includes an insulating substrate 11, a main surface wiring layer 12, and a back surface wiring layer 13. As shown in FIGS. 7 , 11 , and 14 to 18 , the support substrate 10 is covered with a sealing resin 50 except for a portion of the back surface wiring layer 13.

[0014] 11 and 14 to 18, the insulating substrate 11 is interposed between the main surface wiring layer 12 and the back surface wiring layer 13 in the thickness direction z. The insulating substrate 11 supports a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22 via the main surface wiring layer 12. The insulating substrate 11 includes a material with relatively high thermal conductivity. The insulating substrate 11 is made of ceramics including aluminum nitride (AlN), for example. The insulating substrate 11 may include an insulating resin sheet in addition to ceramics.

[0015] As shown in Figures 11 and 14, the insulating substrate 11 has a substrate main surface 11a and a substrate back surface 11b. The substrate main surface 11a and the substrate back surface 11b are spaced apart in the thickness direction z. The substrate main surface 11a and the substrate back surface 11b face opposite each other in the thickness direction z. The substrate main surface 11a faces upward in the thickness direction z, and the substrate back surface 11b faces downward in the thickness direction z. The substrate main surface 11a faces a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22.

[0016] As shown in Figures 11 and 14, the main surface wiring layer 12 is located above the insulating substrate 11 in the thickness direction z. The main surface wiring layer 12 is in contact with and bonded to the substrate main surface 11a. The main surface wiring layer 12 contains copper (Cu), but may contain other metals. In a plan view, the main surface wiring layer 12 is surrounded by the periphery of the insulating substrate 11. As shown in Figures 3 to 5 and 14, the main surface wiring layer 12 includes a first conductor portion 121, two second conductor portions 122, and a third conductor portion 123. The first conductor portion 121, the two second conductor portions 122, and the third conductor portion 123 are spaced apart from one another.

[0017] The first conductor portion 121 and the third conductor portion 123 are spaced apart in the first direction y. The first conductor portion 121 and the third conductor portion 123 are aligned in the first direction y. The two second conductor portions 122 are respectively arranged near two of the four corners of the support substrate 10 on one side in the first direction y (the y2 side) in the plan view. The two second conductor portions 122 are located on the opposite side of the first conductor portion 121 in the first direction y, with a portion of the third conductor portion 123 sandwiched between them. The dimension of the first conductor portion 121 in the thickness direction z, the dimensions of the two second conductor portions 122 in the thickness direction z, and the dimension of the third conductor portion 123 in the thickness direction z are all the same.

[0018] The first conductor portion 121 is located on the other side (y1 side) in the first direction y with respect to the third conductor portion 123. The first conductor portion 121 is located closer to the two second power terminals 15 than the third conductor portion 123 in the first direction y. The first conductor portion 121 has, for example, a rectangular shape in a plan view, but the shape in a plan view of the first conductor portion 121 is not limited in any way. A plurality of first semiconductor elements 21 and a signal substrate 601 are joined to the first conductor portion 121.

[0019] The first conductor portion 121 has a conductor principal surface 121a. The conductor principal surface 121a faces upward in the thickness direction z. The conductor principal surface 121a faces in the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 121a is flat and parallel to the substrate principal surface 11a.

[0020] The third conductor portion 123 is located on one side (y2 side) of the first conductor portion 121 in the first direction y. The third conductor portion 123 includes two partition portions 1231 and 1232. A plurality of second semiconductor elements 22 are bonded to the partition portion 1231, and a signal board 602 is bonded to the partition portion 1232. The partition portion 1232 is located on the opposite side of the first conductor portion 121 in the first direction y with respect to the partition portion 1231. The partition portion 1232 is located closer to the third power terminal 16 than the partition portion 1231. The partition portion 1232 is connected to one side (y2 side) of the partition portion 1231 in the first direction y. The dimension of the partition portion 1231 in the second direction x is the same as the dimension of the first conductor portion 121 in the second direction x. The dimension of the partition portion 1232 in the second direction x is smaller than the dimension of the partition portion 1231 in the second direction x.

[0021] The third conductor portion 123 has a conductor principal surface 123a. The conductor principal surface 123a faces upward in the thickness direction z. The conductor principal surface 123a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 123a is flat and parallel to the substrate principal surface 11a.

[0022] The two second conductors 122 are located on the opposite side of the first conductor 121 in the first direction y, with the partition 1231 as the reference. The two second conductors 122 are located closer to the two first power terminals 14 than the first conductor 121 in the first direction y. The two second conductors 122 are located on opposite sides of the partition 1232 in the second direction x. A corresponding one of the two second power terminals 15 and a conductive member 32 are respectively joined to the two second conductors 122.

[0023] Each of the two second conductor portions 122 has a conductor principal surface 122a. In each second conductor portion 122, the conductor principal surface 122a faces upward in the thickness direction z. In each second conductor portion 122, the conductor principal surface 122a faces the same direction as the substrate principal surface 11a. In the illustrated example, in each second conductor portion 122, the conductor principal surface 122a is flat and parallel to the substrate principal surface 11a.

[0024] In this embodiment, as shown in Figures 4 and 14, the conductor principal surface 121a of the first conductor portion 121 has multiple depressions 1219, the conductor principal surface 122a of each second conductor portion 122 has depressions 1229, and the conductor principal surface 123a of the third conductor portion 123 has multiple depressions 1239. These depressions 1219, 1229, and 1239 are each circular in plan view, but the planar shape of each depression 1219, 1229, and 1239 may also be elliptical, rectangular, polygonal, or annular. The multiple depressions 1219, 1229, and 1239 may be formed by pressing the support substrate 10 with a clamp member for fixing the support substrate 10 when the sealing resin 50 is formed. Therefore, the multiple depressions 1219, 1229, and 1239 are pressure marks caused by the clamp member. The pressing force of the clamping member does not leave any pressing marks, so it is not necessary to form the plurality of recesses 1219, 1229, 1239. The shape of the plurality of recesses 1219, 1229, 1239 in a plan view is the same as the shape of the tip of the clamping member.

[0025] As shown in FIGS. 11 and 14 to 18 , the back surface wiring layer 13 is located below (on the z1 side of) the insulating substrate 11 in the thickness direction z. The back surface wiring layer 13 is in contact with and bonded to the substrate back surface 11b. The composition of the back surface wiring layer 13 includes copper (Cu), similar to the main surface wiring layer 12, but may be other metals. Unlike this example, the composition of the back surface wiring layer 13 may be different from that of the main surface wiring layer 12. As shown in FIGS. 7 and 11 , the lower surface of the back surface wiring layer 13 (the surface facing downward in the thickness direction z) is exposed from the sealing resin 50 (the resin back surface 52 described below). In this example, a heat dissipation member (e.g., a heat sink) (not shown) may be bonded to the lower surface of the back surface wiring layer 13. In the illustrated example, the back surface wiring layer 13 is rectangular in plan view. The back surface wiring layer 13 is surrounded by the periphery of the insulating substrate 11 in plan view.

[0026] The main surface wiring layer 12 and the back surface wiring layer 13 are metal bodies individually bonded to both surfaces of the insulating substrate 11 in the thickness direction z. In the main surface wiring layer 12, the metal body is divided into a plurality of conductor portions (a first conductor portion 121, two second conductor portions 122, and a third conductor portion 123) by patterning. That is, the first conductor portion 121, the two second conductor portions 122, and the third conductor portion 123 are patterns of metal bodies formed on the substrate main surface 11a of the insulating substrate 11. In an example where the support substrate 10 is a DCB substrate, the main surface wiring layer 12 and the back surface wiring layer 13 are each bonded to the insulating substrate 11 by a direct bonding method. In contrast to this example, in an example where the support substrate 10 is an AMB substrate, the main surface wiring layer 12 and the back surface wiring layer 13 are each bonded by an active metal bonding method.

[0027] The plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 are each, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Alternatively, the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 may each be other transistors such as IGBTs (Insulated Gate Bipolar Transistors) and bipolar transistors, or diodes. In this embodiment, the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 are each n-channel MOSFETs with a vertical structure.

[0028] The first semiconductor elements 21 and the second semiconductor elements 22 each include a compound semiconductor substrate. The compound semiconductor substrate may be composed of silicon (Si), a wide bandgap semiconductor with a wider bandgap than Si, or an ultra-wide bandgap semiconductor with an even wider bandgap than the wide bandgap semiconductor. Examples of wide bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Examples of ultra-wide bandgap semiconductors include, but are not limited to, gallium oxide (GaO), diamond, and aluminum nitride (AlN). In this embodiment, the compound semiconductor substrates of the first semiconductor elements 21 and the second semiconductor elements 22 each include SiC. The types and compositions of the first semiconductor elements 21 and the second semiconductor elements 22 are not limited to being the same, and may be different.

[0029] 5, 17, etc., the plurality of first semiconductor elements 21 are mounted on the first conductor portion 121. The plurality of first semiconductor elements 21 are arranged along the second direction x.

[0030] 13 , each of the multiple first semiconductor elements 21 has an element main surface 21a and an element back surface 21b. The element main surface 21a and the element back surface 21b are spaced apart in the thickness direction z. The element main surface 21a and the element back surface 21b face opposite each other in the thickness direction z. The element main surface 21a faces upward in the thickness direction z, and the element back surface 21b faces downward in the thickness direction z. The element main surface 21a faces in the same direction as the substrate main surface 11a in the thickness direction z. The element back surface 21b faces the support substrate 10.

[0031] Each of the multiple first semiconductor elements 21 has a back surface electrode 211 and multiple main surface electrodes 212, 213, and 214. The back surface electrode 211 and multiple main surface electrodes 212, 213, and 214 described below are common to all first semiconductor elements 21 unless otherwise specified.

[0032] As shown in FIG. 13 , the back surface electrode 211 is disposed on the element back surface 21b and exposed thereon. As shown in FIGS. 5 and 13 , the plurality of principal surface electrodes 212, 213, and 214 are disposed on the element main surface 21a and exposed thereon. In the illustrated example, the principal surface electrode 212 is divided into two regions in a plan view. The two regions are aligned in the second direction x. Unlike this example, the principal surface electrode 212 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 213 in a plan view is smaller than the area of ​​the principal surface electrode 212 in a plan view. The two principal surface electrodes 214 are disposed on either side of the principal surface electrode 213 in the second direction x, sandwiching the principal surface electrode 213 therebetween. Unlike the illustrated example, each first semiconductor element 21 may include only one of the two principal surface electrodes 214 , or may include neither of the two principal surface electrodes 214 .

[0033] Each first semiconductor element 21 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 213. The operation of each first semiconductor element 21 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 211 and the principal surface electrode 212 are conductive, and in the OFF state, the back surface electrode 211 and the principal surface electrode 212 are non-conductive. In each first semiconductor element 21, the back surface electrode 211 and the principal surface electrode 212 are conductive in response to a drive signal input to the principal surface electrode 213. The two principal surface electrodes 214 are short-circuited to the principal surface electrode 212 inside each first semiconductor element 21. In this example, the potential of each of the two principal surface electrodes 214 is equal to the potential of the principal surface electrode 212. In an example where each first semiconductor element 21 is a MOSFET, the back surface electrode 211 is a drain electrode, the main surface electrode 212 is a source electrode, the main surface electrode 213 is a gate electrode, and each main surface electrode 214 is a source sense electrode.

[0034] The semiconductor device A10 further includes a plurality of conductive bonding layers 219. As shown in Fig. 13, each of the plurality of first semiconductor elements 21 is bonded to the first conductor 121 by a corresponding one of the plurality of conductive bonding layers 219. Each of the plurality of conductive bonding layers 219 is interposed between the back surface electrode 211 of the corresponding first semiconductor element 21 and the first conductor 121, and provides electrical continuity therebetween. Each conductive bonding layer 219 is, for example, solder. Alternatively, each conductive bonding layer 219 may include a sintered body of metal particles.

[0035] 5 and 16, the plurality of second semiconductor elements 22 are mounted on the partition portions 1231 of the third conductor portion 123. The plurality of second semiconductor elements 22 are arranged along the second direction x.

[0036] 12 , each of the multiple second semiconductor elements 22 has an element main surface 22a and an element back surface 22b. The element main surface 22a and the element back surface 22b are spaced apart in the thickness direction z. The element main surface 22a and the element back surface 22b face opposite each other in the thickness direction z. The element main surface 22a faces upward in the thickness direction z, and the element back surface 22b faces downward in the thickness direction z. The element main surface 22a faces in the same direction as the substrate main surface 11a in the thickness direction z. The element back surface 22b faces the support substrate 10.

[0037] Each of the second semiconductor elements 22 has a back surface electrode 221 and a plurality of main surface electrodes 222, 223, and 224. The back surface electrode 221 and the plurality of main surface electrodes 222, 223, and 224 described below are common to all second semiconductor elements 22 unless otherwise specified.

[0038] As shown in FIG. 12 , the back surface electrode 221 is disposed on the element back surface 22b and exposed thereon. As shown in FIGS. 5 and 12 , the plurality of principal surface electrodes 222, 223, and 224 are disposed on the element main surface 22a and exposed thereon. In the illustrated example, the principal surface electrode 222 is divided into two regions in a plan view. The two regions are aligned in the second direction x. Unlike this example, the principal surface electrode 222 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 223 in a plan view is smaller than the area of ​​the principal surface electrode 222 in a plan view. The two principal surface electrodes 224 are disposed on either side of the principal surface electrode 223 in the second direction x, sandwiching the principal surface electrode 223 therebetween. Unlike the illustrated example, each second semiconductor element 22 may include only one of the two main surface electrodes 224 or may include neither of the two main surface electrodes 224 .

[0039] Each second semiconductor element 22 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 223. The operation of each second semiconductor element 22 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 221 and the principal surface electrode 222 are conductive, and in the OFF state, the back surface electrode 221 and the principal surface electrode 222 are non-conductive. In each second semiconductor element 22, the back surface electrode 221 and the principal surface electrode 222 are conductive in response to a drive signal input to the principal surface electrode 223. The two principal surface electrodes 224 are short-circuited to the principal surface electrode 222 inside each second semiconductor element 22. In this example, the potential of each of the two principal surface electrodes 224 is equal to the potential of the principal surface electrode 222. In an example where each second semiconductor element 22 is a MOSFET, the back surface electrode 221 is a drain electrode, the main surface electrode 222 is a source electrode, the main surface electrode 223 is a gate electrode, and each main surface electrode 224 is a source sense electrode.

[0040] The semiconductor device A10 further includes a plurality of conductive bonding layers 229. As shown in FIG. 12 , each of the plurality of second semiconductor elements 22 is bonded to the third conductor 123 (partition portion 1231) by a corresponding one of the plurality of conductive bonding layers 229. Each of the plurality of conductive bonding layers 229 is interposed between the back surface electrode 221 of the corresponding second semiconductor element 22 and the third conductor 123, providing electrical continuity therebetween. Each conductive bonding layer 229 is, for example, solder. Alternatively, each conductive bonding layer 229 may include a sintered body of metal particles.

[0041] In the semiconductor device A10, the back electrodes 211 (drain electrodes) of the multiple first semiconductor elements 21 are electrically connected, and the main surface electrodes 212 (source electrodes) are electrically connected. That is, the multiple first semiconductor elements 21 are electrically connected in parallel with each other. The back electrodes 221 (drain electrodes) of the multiple second semiconductor elements 22 are electrically connected, and the main surface electrodes 222 (source electrodes) are electrically connected. That is, the multiple second semiconductor elements 22 are electrically connected in parallel with each other. In the semiconductor device A10, the back electrodes 211 (drain electrodes) of the multiple first semiconductor elements 21 are electrically connected to the main surface electrodes 222 (source electrodes) of the multiple second semiconductor elements 22. That is, the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 are connected in series. The semiconductor device A10 forms a half-bridge circuit in which the multiple second semiconductor elements 22 form an upper arm circuit and the multiple first semiconductor elements 21 form a lower arm circuit.

[0042] The two first power terminals 14, the two second power terminals 15, and the third power terminal 16 are each electrically connected to one of the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22. A current corresponding to the power before or after conversion by the switching operations of the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 flows through the two first power terminals 14, the two second power terminals 15, and the third power terminal 16. In the semiconductor device A10, the number of first power terminals 14, the number of second power terminals 15, and the number of third power terminals 16 are not limited to the example shown in the figure.

[0043] As shown in Figures 4 and 14, the two first power terminals 14 are joined to corresponding ones of the two second conductor portions 122. This joining is, for example, done using a conductive joining material (e.g., solder) not shown. Alternatively, joining by laser welding or crimping may be used. The two first power terminals 14 are supported by the corresponding second conductor portions 122. Each of the two first power terminals 14 is electrically connected to the main surface electrodes 212 (source electrodes of the lower arm circuits) of the multiple first semiconductor elements 21 via the corresponding second conductor portions 122 and the conductive members 32. The two first power terminals 14 are N-terminals (negative terminals) to which a DC power supply voltage to be converted is applied. The two first power terminals 14 are spaced apart from each other in the second direction x. A third power terminal 16 is located between the two first power terminals 14. 4 , the two first power terminals 14 are located on the same side of the support substrate 10 as the third power terminal 16 in the first direction y. Each of the two first power terminals 14 extends from the corresponding second conductor portion 122 to one side in the first direction y (y2 side) and protrudes from the sealing resin 50 to one side in the first direction y (y2 side). In the illustrated example, each first power terminal 14 is flat, but may include a bent portion.

[0044] As shown in Figure 3 and other figures, each of the two first power terminals 14 includes an exposed portion 141 and a covered portion 142. The exposed portion 141 is a portion of each first power terminal 14 that is exposed from the sealing resin 50. In each first power terminal 14, the exposed portion 141 is used as the aforementioned N terminal. The covered portion 142 is a portion of each first power terminal 14 that is covered with the sealing resin 50. In each first power terminal 14, the covered portion 142 is joined to the corresponding second conductor portion 122. In the illustrated example, a notch is provided at the tip (the edge farther from the sealing resin 50) of the exposed portion 141 in one of the two first power terminals 14, but this may not be necessary.

[0045] The two second power terminals 15 are each joined to the first conductor portion 121. This joining is not limited in any way and may be done using a conductive joining material (e.g., solder or sintered metal, not shown), laser welding, or crimping. The two second power terminals 15 are each supported by the first conductor portion 121. Each of the two second power terminals 15 is electrically connected to the back surface electrodes 211 (drain electrodes of the lower arm circuit) of the multiple first semiconductor elements 21 via the first conductor portion 121, and is also electrically connected to the main surface electrodes 222 (source electrodes of the upper arm circuit) of the multiple second semiconductor elements 22 via the first conductor portion 121 and the conductive member 31. AC power converted by the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 is output from the two second power terminals 15. In other words, each of the two second power terminals 15 is an output terminal for the AC power. The two second power terminals 15 are spaced apart from each other in the second direction x. As shown in FIG. 4 and other figures, the two second power terminals 15 are located on opposite sides of the first conductor portion 121 from the third conductor portion 123 in the first direction y. Each of the two second power terminals 15 extends from the first conductor portion 121 to the other side (y1 side) in the first direction y and protrudes from the sealing resin 50 to the other side (y1 side) in the first direction y. In the illustrated example, each second power terminal 15 is flat, but may include a bent portion.

[0046] As shown in Figure 3 and other figures, each of the two second power terminals 15 includes an exposed portion 151 and a covered portion 152. The exposed portion 151 is a portion of each second power terminal 15 that is exposed from the sealing resin 50. In each second power terminal 15, the exposed portion 151 is used as the output terminal described above. The covered portion 152 is a portion of each second power terminal 15 that is covered with the sealing resin 50. In each second power terminal 15, the covered portion 152 is joined to the first conductor portion 121. In the illustrated example, a notch is provided at the tip (the edge farther from the sealing resin 50) of the exposed portion 151 in one of the two second power terminals 15, but this is not necessary.

[0047] The third power terminal 16 is joined to the third conductor portion 123 (partition portion 1232). This joining is not limited in any way and may be done using a conductive joining material (e.g., solder or sintered metal, etc.) not shown, laser welding, or crimping. The third power terminal 16 is supported by the third conductor portion 123. The third power terminal 16 is electrically connected to the back electrodes 221 (drain electrodes of the upper arm circuits) of the multiple second semiconductor elements 22 via the third conductor portion 123. The third power terminal 16 is a P terminal (positive terminal) to which a DC power supply voltage to be converted is applied. As shown in FIG. 4 and other figures, the third power terminal 16 is located on the opposite side of the first conductor portion 121 in the first direction y, with the third conductor portion 123 sandwiched therebetween. The third power terminal 16 is located between the two first power terminals 14 in the second direction x. The third power terminal 16 extends from the third conductor portion 123 to one side in the first direction y (the y2 side) and protrudes to the one side in the first direction y (the y2 side) from the sealing resin 50. In the illustrated example, the third power terminal 16 is flat, but may include a bent portion.

[0048] As shown in Figure 3 and other figures, the third power terminal 16 includes an exposed portion 161 and a covered portion 162. The exposed portion 161 is a portion of the third power terminal 16 that is exposed from the sealing resin 50. In the third power terminal 16, the exposed portion 161 is used as the P terminal described above. The covered portion 162 is a portion of the third power terminal 16 that is covered with the sealing resin 50. In the third power terminal 16, the covered portion 162 is joined to the third conductor portion 123.

[0049] The pair of signal boards 601, 602 constitute part of the conductive paths between the multiple signal terminals 17 and the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22. As shown in FIGS. 4 and 11 , the signal board 601 is located between the multiple first semiconductor elements 21 and the two second power terminals 15 in the first direction y. The signal board 601 is bonded to the first conductor portion 121 as shown in FIG. 11 . As shown in FIGS. 4 and 11 , the signal board 602 is located between the multiple second semiconductor elements 22 and the two first power terminals 14 and the second power terminals 15 in the first direction y. The signal board 602 is bonded to the third conductor portion 123 (partition portion 1232) as shown in FIG. 11 . Each of the pair of signal boards 601, 602 is, for example, a DCB board or an AMB board. Unlike this example, each of the pair of signal boards 601, 602 may be a printed circuit board.

[0050] Each of the pair of signal substrates 601, 602 has an insulating layer 61, a wiring layer 62, a metal layer 63, and a plurality of sleeves 64. Each of the pair of signal substrates 601, 602 is covered with a sealing resin 50 except for a portion of each of the plurality of sleeves 64. Unless otherwise specified, the insulating layer 61, the wiring layer 62, the metal layer 63, and the plurality of sleeves 64 described below are common to each of the pair of signal substrates 601, 602.

[0051] The insulating layer 61 is interposed between the wiring layer 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 may be made of, for example, ceramics. Alternatively, the insulating layer 61 may be made of an insulating resin sheet.

[0052] 11 , 15 , and 18 , the wiring layer 62 is located above the insulating layer 61 in the thickness direction z. The composition of the wiring layer 62 is not limited in any way, but may include copper. As shown in FIG. 5 , the wiring layer 62 includes a plurality of wiring portions 621 to 624. The plurality of wiring portions 621 to 624 are spaced apart from one another. The planar shape, arrangement, size, and the like of each of the wiring portions 621 to 624 are not limited to the examples shown in the drawings.

[0053] 11 , 15 , and 18 , the metal layer 63 is located on the opposite side of the wiring layer 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The composition of the metal layer 63 is not limited in any way, but may include copper. The metal layer 63 of the signal substrate 601 is bonded to the first conductor 121 by an adhesive layer (not shown). The metal layer 63 of the signal substrate 602 is bonded to the third conductor 123 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. These adhesive layers are, for example, solder.

[0054] As shown in FIGS. 11 , 15 , and 18 , each of the multiple sleeves 64 is bonded to one of the multiple wiring layers 62 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z1 side in the thickness direction z) is conductively bonded to one of the multiple wiring layers 62. As shown in FIGS. 11 , 15 , and 18 , the other end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z2 side in the thickness direction z) is exposed from the sealing resin 50.

[0055] 5, the thermistor 23 is conductively connected across the wiring portion 623 of the signal substrate 601 and the wiring portion 624 of the signal substrate 601. The thermistor 23 is, for example, an NTC (Negative Temperature Coefficient) thermistor. An NTC thermistor has the characteristic that its resistance decreases gradually with increasing temperature. The thermistor 23 is used as a temperature detection sensor for the semiconductor device A10.

[0056] Each of the signal terminals 17 (signal terminals 171 to 174, 176, and 177) is formed by a metal pin and extends in the thickness direction z, as shown in FIG. 1 and other figures. The signal terminals 17 protrude from the sealing resin 50 (a resin main surface 51, which will be described later). The signal terminals 17 (signal terminals 171 to 174, 176, and 177) are individually press-fitted into the sleeves 64 of the pair of signal boards 601 and 602. As a result, each of the signal terminals 17 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62 of the pair of signal boards 601 and 602. The signal terminals 171 to 174 and 176 are electrically connected to one of the first semiconductor elements 21 and the second semiconductor elements 22. The two signal terminals 177 are not electrically connected (non-conductive) to either the plurality of first semiconductor elements 21 or the plurality of second semiconductor elements 22 , but are electrically connected to the thermistor 23 .

[0057] 5 , the signal terminal 171 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 171 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal substrate 601. The signal terminal 171 is electrically connected to each of the main surface electrodes 213 of the multiple first semiconductor elements 21. A drive signal for driving each of the first semiconductor elements 21 is input to the signal terminal 171 (a gate voltage is applied).

[0058] 5 , the signal terminal 172 is press-fitted into a sleeve 64 joined to the wiring portion 621 of the signal substrate 602. As a result, the signal terminal 172 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal substrate 602. The signal terminal 172 is electrically connected to each of the main surface electrodes 223 of the multiple second semiconductor elements 22. A drive signal for driving each second semiconductor element 22 is input to the signal terminal 172 (a gate voltage is applied).

[0059] As shown in Fig. 5 , the signal terminal 173 is located adjacent to the signal terminal 171 in the second direction x. As shown in Fig. 5 , the signal terminal 173 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 601. As a result, the signal terminal 173 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 601. The signal terminal 173 is electrically connected to the main surface electrodes 214 of the multiple first semiconductor elements 21. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 214 of the multiple first semiconductor elements 21 is applied to the signal terminal 173.

[0060] As shown in Fig. 5 , the signal terminal 174 is located next to the signal terminal 172 in the second direction x. As shown in Fig. 5 , the signal terminal 174 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 602. As a result, the signal terminal 174 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 602. The signal terminal 174 is electrically connected to the main surface electrodes 224 of the multiple second semiconductor elements 22. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 224 of the multiple second semiconductor elements 22 is applied to the signal terminal 174.

[0061] As shown in Fig. 5 , the signal terminal 176 is located on the opposite side of the signal terminal 172 in the second direction x, with the signal terminal 174 sandwiched therebetween. As shown in Fig. 5 , the signal terminal 176 is press-fitted into a sleeve 64 joined to the wiring portion 623 of the signal board 602. As a result, the signal terminal 176 is supported by the sleeve 64 and is electrically connected to the wiring portion 623 of the signal board 602. The signal terminal 176 is electrically connected to the third conductor portion 123. A voltage equivalent to the DC power input to the third power terminal 16 is applied to the signal terminal 176.

[0062] As shown in Fig. 5 , the pair of signal terminals 177 are located on the opposite side of the signal terminal 171 in the second direction x with the signal terminal 173 sandwiched therebetween, and the pair of signal terminals 177 are adjacent to each other in the second direction x. As shown in Fig. 5 , the pair of signal terminals 177 are individually press-fitted into a pair of sleeves 64 joined to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601, respectively. As a result, the pair of signal terminals 177 are individually supported by the pair of sleeves 64 and are individually conducted to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601. The pair of signal terminals 177 are conducted to the thermistor 23.

[0063] Each of the plurality of connection members 41 to 45 electrically connects portions spaced apart from one another. Each of the plurality of connection members 41 to 45 is, for example, a bonding wire. Unlike this example, each of the plurality of connection members 41 to 45 may be a metal plate material. Each of the plurality of connection members 41 to 45 contains gold (Au). Each of the plurality of connection members 41 to 45 may contain copper or aluminum. The plurality of connection members 41 to 45 are omitted from FIGS. 11, 15, and 18.

[0064] 5 , each of the plurality of connection members 41 is conductively joined to the corresponding main surface electrode 213 of the first semiconductor element 21 and the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 171 is conductively connected to the main surface electrodes 213 of the plurality of first semiconductor elements 21.

[0065] 5 , each of the plurality of connection members 42 is conductively joined to the corresponding main surface electrode 223 of the second semiconductor element 22 and the wiring portion 621 of the signal substrate 602. As a result, the signal terminal 172 is conductively connected to the main surface electrodes 223 of the plurality of second semiconductor elements 22.

[0066] 5 , each of the plurality of connection members 43 is conductively joined to the corresponding main surface electrode 214 of the first semiconductor element 21 and to the wiring portion 622 of the signal substrate 601. This allows the signal terminal 173 to be conductively connected to the main surface electrodes 214 of the plurality of first semiconductor elements 21. When each first semiconductor element 21 does not include either of the two main surface electrodes 214, each of the plurality of connection members 43 is joined to the main surface electrode 212 of the corresponding first semiconductor element 21.

[0067] 5 , each of the plurality of connection members 44 is conductively joined to the corresponding main surface electrode 224 of the second semiconductor element 22 and the wiring portion 622 of the signal substrate 602. This allows the signal terminal 174 to be conductively connected to the main surface electrodes 224 of the plurality of second semiconductor elements 22. When each second semiconductor element 22 does not include either of the two main surface electrodes 224, each of the plurality of connection members 44 is joined to the corresponding main surface electrode 222 of the second semiconductor element 22.

[0068] 5 , the connection member 45 is electrically connected to the wiring portion 623 of the signal substrate 602 and the third conductor portion 123 (partition portion 1232). As a result, the signal terminal 176 is electrically connected to the back surface electrodes 221 of the plurality of second semiconductor elements 22 via the third conductor portion 123.

[0069] As shown in FIG. 4 and other figures, the conductive member 31 is bonded to the main surface electrodes 222 of the plurality of second semiconductor elements 22 and the first conductor portion 121 of the support substrate 10. The main surface electrodes 222 of the plurality of second semiconductor elements 22 are electrically connected to the first conductor portion 121 via the conductive member 31. The conductive member 31 may contain copper. The conductive member 31 is a metal clip. As shown in FIGS. 4 and 11 and other figures, the conductive member 31 has a main body portion 311 and a plurality of joint portions 312, 313.

[0070] The main body portion 311 forms a main part of the conductive member 31. As shown in FIG. 4 , the main body portion 311 extends in the second direction x. As shown in FIGS. 4 and 11 , the main body portion 311 straddles the first conductor portion 121 and the third conductor portion 123. As shown in FIG. 4 , a plurality of through holes 311 a are formed in the main body portion 311. The plurality of through holes 311 a penetrate the main body portion 311 in the thickness direction z. The plurality of through holes 311 a overlap between the first conductor portion 121 and the third conductor portion 123 in a plan view. This allows the sealing resin 50 to flow smoothly downward in the thickness direction z of the main body portion 311 when forming the sealing resin 50.

[0071] As shown in FIGS. 4 and 12 , the multiple bonding portions 312 are individually bonded to the principal surface electrodes 222 of the multiple second semiconductor elements 22. Each of the multiple bonding portions 312 faces one of the principal surface electrodes 222 of the multiple second semiconductor elements 22. In a plan view, each bonding portion 312 extends from the main body portion 311 toward the y2 side in the first direction y. In the illustrated example, the multiple bonding portions 312 are bifurcated from the main body portion 311, but they do not have to be bifurcated. The tip of each bonding portion 312 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 312 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each bonding portion 312, which is located at a different position in the thickness direction z, to the main body portion 311.

[0072] 4 and 11 , the multiple joints 313 are joined to the first conductor 121. The multiple joints 313 face the first conductor 121. In a plan view, each joint 313 extends from the main body 311 to the y1 side in the first direction y. The tip of each joint 313 (the end opposite to the side connected to the main body 311) is located below the main body 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each joint 313 (the end connected to the main body 311) is bent in the thickness direction z so as to connect the tip of each joint 313, which is located at a different position in the thickness direction z, to the main body 311.

[0073] 12 , the semiconductor device A10 further includes a conductive bonding layer 33. The conductive bonding layer 33 is interposed between the main surface electrodes 222 of the plurality of second semiconductor elements 22 and the plurality of bonding portions 312. The conductive bonding layer 33 conductively bonds the main surface electrodes 222 of the plurality of second semiconductor elements 22 to the plurality of bonding portions 312. The conductive bonding layer 33 is, for example, solder. Alternatively, the conductive bonding layer 33 may include a sintered body of metal particles.

[0074] 11 , the semiconductor device A10 further includes a conductive bonding layer 34. The conductive bonding layer 34 is interposed between the first conductor portion 121 and the bonding portion 313. The conductive bonding layer 34 conductively bonds the first conductor portion 121 and the bonding portion 313. The conductive bonding layer 34 is, for example, solder. Alternatively, the conductive bonding layer 34 may include a sintered body of metal particles.

[0075] As shown in FIG. 3 , the conductive member 32 is conductively bonded to the principal surface electrodes 212 of the plurality of first semiconductor elements 21 and the two second conductor portions 122 of the support substrate 10. As a result, the principal surface electrodes 212 of the plurality of first semiconductor elements 21 are electrically connected to each of the two second conductor portions 122 via the conductive member 32. As described above, each of the two first power terminals 14 is bonded to one of the two second conductor portions 122, and therefore the principal surface electrodes 212 of the plurality of first semiconductor elements 21 are electrically connected to each of the two first power terminals 14. The composition of the conductive member 32 may include copper, for example. The conductive member 32 is a metal clip. As shown in FIGS. 3 and 11 , the conductive member 32 includes two main body portions 321, a plurality of joint portions 322, a plurality of joint portions 324, a plurality of intermediate portions 326, and a cross beam portion 327.

[0076] As shown in FIG. 3 , the two main bodies 321 are spaced apart from each other in the second direction x. The two main bodies 321 extend in the first direction y. As shown in FIGS. 14 and 16 , the two main bodies 321 are arranged parallel to the conductor principal surface 121 a of the first conductor portion 121, the conductor principal surface 122 a of the second conductor portion 122, and the conductor principal surface 123 a of the third conductor portion 123. In the thickness direction z, the two main bodies 321 are farther from the main-surface wiring layer 12 (the first conductor portion 121, the two second conductor portions 122, and the third conductor portion 123) than the main body portion 311 of the conductive member 31. Each of the two main bodies 321 intersects the third conductor portion 123 (the partition portion 1231) in a plan view. That is, each of the two main bodies 321 extends from one edge to the other edge in the first direction y of the partition portion 1231 of the third conductor 123 in a plan view.

[0077] 3 , a plurality of notches 3211 are formed in the two main body portions 321. Each notch 3211 is recessed in the second direction x from an edge of one of the two main body portions 321 that faces each other in the second direction x. The plurality of notches 3211 are provided to prevent a clamp member for fixing the support substrate 10 from contacting the conductive member 32 when forming the sealing resin 50. Each of the plurality of notches 3211 overlaps one of the plurality of recesses 1219, 1239 in a plan view.

[0078] 3 , the intermediate portions 326 are spaced apart from one another in the second direction x and are located between the two main body portions 321 in the second direction x. The intermediate portions 326 extend in the first direction y. The dimension of each of the intermediate portions 326 in the first direction y is smaller than the dimension of each of the two main body portions 321 in the first direction y.

[0079] As shown in FIG. 3 , the multiple bonding portions 322 are individually bonded to the principal surface electrodes 212 of the multiple first semiconductor elements 21. Each of the multiple bonding portions 322 faces one of the principal surface electrodes 212 of the multiple first semiconductor elements 21. In a plan view, the multiple bonding portions 322 extend in the second direction x from the multiple intermediate portions 326. The tip of each bonding portion 322 (the end opposite to the side connected to the intermediate portion 326) is located lower in the thickness direction z than the intermediate portion 326 (on the z1 side in the thickness direction z). The base end of each bonding portion 322 (the end connected to the intermediate portion 326) is bent in the thickness direction z so as to connect the tip of each bonding portion 322 and each intermediate portion 326, which are located at different positions in the thickness direction z.

[0080] As shown in FIGS. 3 and 14 , the pair of joints 324 are individually joined to the two second conductors 122. The joining may be, for example, soldering. Alternatively, joining may be performed using a joining material containing a sintered body of metal particles. Each of the pair of joints 324 faces a corresponding one of the two second conductors 122. Each of the pair of joints 324 is joined to a portion of the corresponding second conductor 122 on the other side (y2 side) in the first direction y, at a fixed distance from the portion to which the covering 142 (first power terminal 14) is joined. Unlike this example, the pair of joints 324 and the pair of coverings 142 may be joined side by side in the first direction y so as to contact each other in the first direction y. In this embodiment, as can be seen from FIG. 3 , a portion of each second conductor 122 does not overlap the joint 324 or the covering 142 in a plan view. The above-mentioned recess 1229 is formed on the conductor main surface 122a in this non-overlapping region.

[0081] 3 and 16 , the cross beam portion 327 is located between the two main body portions 321 in the second direction x. The cross beam portion 327 extends in the second direction x from each of the two main body portions 321. As can be seen from FIG. 3 , the cross beam portion 327 overlaps with the multiple joint portions 312 of the conductive member 31 in a plan view. The multiple intermediate portions 326 each extend from the cross beam portion 327 toward the other side (y1 side) in the first direction y.

[0082] 13 , the semiconductor device A10 further includes a conductive bonding layer 35. The conductive bonding layer 35 is interposed between the main surface electrodes 212 of the plurality of first semiconductor elements 21 and the plurality of bonding portions 322. The conductive bonding layer 35 conductively bonds the main surface electrodes 212 of the first semiconductor elements 21 to the plurality of bonding portions 322. The conductive bonding layer 35 is, for example, solder. Alternatively, the conductive bonding layer 35 may include a sintered body of metal particles.

[0083] As shown in FIGS. 1 to 3 and 6 to 18 , the sealing resin 50 covers the multiple first semiconductor elements 21 and the insulating substrate 11. Furthermore, the sealing resin 50 covers the multiple second semiconductor elements 22, the two conductive members 31 and 32, and the multiple connecting members 41 to 45. Furthermore, the sealing resin 50 covers a portion of the insulating substrate 11, a portion of each of the two first power terminals 14, a portion of each of the two second power terminals 15, a portion of the third power terminal 16, and a portion of each of the multiple signal terminals 17 (171 to 174, 176, 177). The sealing resin 50 has electrical insulation properties. The sealing resin 50 contains, for example, a black epoxy resin. The sealing resin 50 is formed, for example, by molding. The sealing resin 50 has a resin main surface 51, a resin back surface 52, multiple resin side surfaces 531 to 534, and two recesses 55.

[0084] As shown in FIGS. 6 , 8 to 11 , and 14 to 18 , the resin main surface 51 and the resin back surface 52 are spaced apart in the thickness direction z. The resin main surface 51 and the resin back surface 52 face opposite each other in the thickness direction z. The resin main surface 51 faces upward in the thickness direction z, and the resin back surface 52 faces downward in the thickness direction z. The resin main surface 51 faces the same direction in the thickness direction z as the substrate main surface 11 a, the element main surface 21 a, and the element main surface 22 a. Each of the multiple signal terminals 17 protrudes upward in the thickness direction z from the resin main surface 51. As shown in FIGS. 7 , 11 , and 14 to 18 , the back wiring layer 13 of the support substrate 10 is exposed from the resin back surface 52.

[0085] In this embodiment, as shown in FIGS. 1 , 2 , and 11 , the resin main surface 51 has a plurality of recesses 511. The recesses 511 are, for example, circular in plan view; however, the planar shape of each recess 511 may also be elliptical, rectangular, or polygonal. In plan view, one of the recesses 511 overlaps with one of the notches 3211 in one of the two main body portions 321. In plan view, each of the recesses 511 overlaps with one of the recesses 1219, 1229, or 1239. The recesses 511 may be formed by holding the support substrate 10 with a clamp member for fixing the support substrate 10 during the formation of the sealing resin 50. For example, the formation of the sealing resin 50 may be started with the support substrate 10 fixed with the clamp member, and then the clamp member may gradually release the support substrate 10 from the fixation by the clamp member (by pulling up the clamp member), thereby forming each recess 511. Each of the plurality of recesses 511 may be filled with a resin of the same material as the sealing resin 50 or a resin different from the sealing resin 50. The resin main surface 51 does not necessarily have to have the plurality of recesses 511.

[0086] Each of the multiple resin side surfaces 531 to 534 is connected to the resin main surface 51. As shown in FIGS. 2 and 3 , the pair of resin side surfaces 531, 532 are spaced apart in the first direction y. The resin side surface 531 faces one side of the first direction y (the y2 side), and the resin side surface 532 faces the other side of the first direction y (the y1 side). The pair of resin side surfaces 531, 532 each extend in the second direction x. The two first power terminals 14 and the two third power terminals 16 each protrude from the resin side surface 531. The two second power terminals 15 each protrude from the resin side surface 532. As shown in FIGS. 2 and 3 , the pair of resin side surfaces 533, 534 are spaced apart in the second direction x. The resin side surface 533 faces one side of the second direction x (the x2 side), and the resin side surface 534 faces the other side of the second direction x (the x1 side). 15 to 17, each of the pair of resin side surfaces 533 and 534 is connected to the resin main surface 51 as well as the resin rear surface 52.

[0087] As shown in FIGS. 2 and 3 , the two recesses 55 are recessed from the resin side surface 531 in the first direction y. The two recesses 55 extend from the resin main surface 51 to the resin back surface 52 in the thickness direction z. As shown in FIGS. 2 , 3 , and 8 , the two recesses 55 are located on both sides of the third power terminal 16 in the second direction x, and are individually disposed between the third power terminal 16 and the two first power terminals 14. The two recesses 55 increase the creepage distance along the sealing resin 50 between each of the first power terminals 14 and the third power terminal 16, thereby improving the dielectric strength between each of the first power terminals 14 and the third power terminal 16. The sealing resin 50 does not necessarily have to have two recesses 55.

[0088] First Embodiment: Power Conversion Unit: Next, a power conversion unit B10 including a semiconductor device A10 will be described with reference to FIGS. 19 to 22. In the example shown in FIGS. 19 to 22, the power conversion unit B10 includes three semiconductor devices A10. The power conversion unit B10 includes three semiconductor devices A10, a heat dissipation member C1, an attachment member D1, and a control board E1. In the following description, an example is given in which three semiconductor devices A10 are attached to the heat dissipation member C1. However, the attachment object of each semiconductor device A10 may not be the heat dissipation member C1, but may be a housing (frame, etc.) of an electronic device, an electric vehicle, or the like. The power conversion unit B10 is not limited to one including three semiconductor devices A10, and may include one, two, four or more semiconductor devices A10.

[0089] The heat dissipation member C1 supports the three semiconductor devices A10. Most of the heat dissipation member C1 is located below the three semiconductor devices A10 in the thickness direction z (on the z1 side). Therefore, most of the heat dissipation member C1 is located on the opposite side of the insulating substrate 11 from the side on which the first semiconductor elements 21 and the second semiconductor elements 22 are located in the thickness direction z. In this embodiment, the heat dissipation member C1 is a heat sink. The material of the heat dissipation member C1 includes, for example, aluminum. The material is not limited to aluminum, and may be other metal materials or resin materials (preferably those with good thermal conductivity). The three semiconductor devices A10 are arranged in the second direction x on the heat dissipation member C1. The heat dissipation member C1 includes a main body 71, multiple pedestals 72, and multiple positioning members 73.

[0090] The main body 71 is a plate material. The three semiconductor devices A10 are mounted on the main body 71. As shown in FIGS. 20 and 21 , the three semiconductor devices A10 are arranged on the main body 71 in the second direction x. The main body 71 faces the lower surface (resin back surface 52) of each sealing resin 50 of the three semiconductor devices A10. The main body 71 contacts the back surface wiring layer 13 of each semiconductor device A10. The main body 71 is, for example, rectangular in plan view.

[0091] 21 , each of the plurality of pedestals 72 protrudes upward in the thickness direction z from the main body 71. In the illustrated example, the plurality of pedestals 72 are formed integrally with the main body 71, but they may be attached to the main body 71 as separate bodies. The dimension of each pedestal 72 in the thickness direction z is greater than the dimension of the sealing resin 50 of each semiconductor device A10 in the thickness direction z. The control substrate E1 is supported by the plurality of pedestals 72 and is disposed at a fixed interval from the upper surface of the main body 71.

[0092] As can be seen from Figures 19 and 20, each of the positioning portions 73 protrudes upward in the thickness direction z from the main body portion 71. For example, each of the positioning portions 73 is attached to the main body portion 71 as a separate body. Unlike this example, each positioning portion 73 may be formed integrally with the main body portion 71. For example, each positioning portion 73 is press-fitted into a through-hole formed in the main body portion 71. Each positioning portion 73 is cylindrical and has a tapered tip on the z2 side in the thickness direction z. In the illustrated example, the diameter of each positioning portion 73 in a plan view is smaller than the diameter of each base portion 72 in a plan view.

[0093] The mounting member D1 secures the three semiconductor devices A10 to the heat dissipation member C1. The mounting member D1 is, for example, a leaf spring. The elastic force of the mounting member D1 presses the three semiconductor devices A10 against the heat dissipation member C1 (main body 71). The material of the mounting member D1 is not limited, but may be, for example, copper, iron, titanium, or an alloy containing any of these (including, for example, stainless steel). As shown in FIGS. 20 and 21 , the mounting member D1 includes a plurality of pressing portions 81 and a plurality of fixing portions 82.

[0094] The pressing portions 81 are provided individually for the three semiconductor devices A10. Each pressing portion 81 contacts the sealing resin 50 (resin main surface 51) of the corresponding semiconductor device A10. Each pressing portion 81 presses the semiconductor device A10 it contacts against the main body 71 of the heat dissipation member C1.

[0095] Each of the multiple fixing portions 82 is fixed to the heat dissipation member C1, and in this embodiment, is fixed to the main body portion 71. Each of the multiple fixing portions 82 is, for example, in the shape of a flat plate parallel to the xy plane. A through hole is formed in each of the multiple fixing portions 82. A fastener 89 (a hexagonal bolt in the illustrated example) is inserted into the through hole. The fastener 89 fixes the fixing portion 82 to the main body portion 71. The multiple fixing portions 82 include those arranged on both sides of the three semiconductor devices A10 in the first direction y, and those sandwiched between two of the three semiconductor devices A10.

[0096] As shown in FIGS. 19 and 21 , the control board E1 is provided in common for the three semiconductor devices A10. Alternatively, multiple control boards E1 may be provided individually for each of the three semiconductor devices A10. As can be seen from FIGS. 19 and 21 , the signal terminals 17 of the three semiconductor devices A10 are inserted into the control board E1. The control board E1 is electrically connected to each of the signal terminals 17. The control board E1 includes, for example, a control circuit that controls the driving of the first semiconductor elements 21 and the second semiconductor elements 22 of the three semiconductor devices A10. In an example in which the first semiconductor elements 21 and the second semiconductor elements 22 are MOSFETs or IGBTs, the control board E1 is a gate driver. The control board E1 faces the upper surface (resin main surface 51) of the sealing resin 50 of each of the three semiconductor devices A10. The control board E1 is located on the opposite side of the three semiconductor devices A10 from the main body 71 of the heat dissipation member C1. In a plan view, the control substrate E1 overlaps the sealing resin 50 of each of the three semiconductor devices A10. The control substrate E1 is held by a plurality of pedestals 72 at a fixed distance in the thickness direction z.

[0097] As shown in FIG. 22 , the control board E1 has a base material 91, main wiring 92, back wiring 93, and internal wiring 94. The base material 91 has a plurality of through holes 911 that penetrate in the thickness direction z. The main wiring 92 is formed on the upper surface of the base material 91 (the surface facing the z1 side in the thickness direction z). The back wiring 93 is formed on the lower surface of the base material 91 (the surface facing the z2 side in the thickness direction z). The internal wiring 94 is disposed on the inner surfaces of the plurality of through holes 911. The internal wiring 94 is connected to the main wiring 92 and the back wiring 93. The main wiring 92 forms a path for mutual conduction between the back wiring 93 and the internal wiring 94 and circuits provided on the control board E1.

[0098] Each signal terminal 17 of the three semiconductor devices A10 is inserted into a corresponding one of the plurality of through holes 911 of the control board E1. Fig. 22 shows a state in which any signal terminal 17 of the plurality of semiconductor devices A10 is inserted into the through hole 911 of the base material 91. All signal terminals 17 of the three semiconductor devices A10 are inserted into the through hole 911 of the base material 91, as shown in Fig. 22.

[0099] 22 , each signal terminal 17 includes a tip portion 170. The tip portion 170 is an end portion of each signal terminal 17 that is far from the sealing resin 50. The tip portion 170 has a bulging portion 170A. As shown in FIG. 22 , the bulging portion 170A bulges out of the signal terminal 17 in a direction perpendicular to the thickness direction z.

[0100] As shown in FIG. 22 , the bulging portion 170A of each signal terminal 17 is press-fitted into one of the through-holes 911 of the control board E1. As a result, the internal wiring 94 arranged in one of the through-holes 911 is pressed against the bulging portion 170A of the signal terminal 17 inserted into the corresponding through-hole 911. Therefore, each signal terminal 17 is press-fitted into the through-hole 911 in the thickness direction z, thereby providing electrical continuity with the control board E1 (its control circuit). The control board E1 is supported by each signal terminal 17 by press-fitting each signal terminal 17 into a corresponding one of the through-holes 911. As can be seen from this configuration, the control board E1 is attached to the tip portion 170 of each signal terminal 17. Alternatively, each signal terminal 17 may not include the bulging portion 170A. That is, each signal terminal 17 may be a straight pin with no change in thickness. In this case, each signal terminal 17 is inserted into a through-hole 911 and then soldered to the control board E1.

[0101] As shown in FIG. 19, a plurality of mounting holes 951 and a plurality of positioning holes 952 are formed in the control board E1.

[0102] 19 , a plurality of pedestals 72 are individually inserted into the plurality of mounting holes 951. Each mounting hole 951 is formed, for example, in a perfect circle in plan view. The control board E1 is sandwiched between the plurality of pedestals 72 with a portion of the corresponding mounting hole 951 inserted therethrough.

[0103] As shown in FIG. 19 , a plurality of positioning portions 73 are individually inserted into the plurality of positioning holes 952. In the illustrated example, two positioning holes 952 are formed in the control board E1. One of the two positioning holes 952 (the positioning hole 952 located on the x2 side in the second direction x) is formed as a perfect circle, and the other of the two positioning holes 952 (the positioning hole 952 located on the x1 side in the second direction x) is formed as an elongated hole. This facilitates positioning of the control board E1 relative to the heat dissipation member C1. In this case, by forming one of the two positioning holes 952 as an elongated hole, slight misalignment between the heat dissipation member C1 and the control board E1 due to manufacturing errors can be suppressed.

[0104] The configuration of the power conversion unit B10 is not limited to the examples shown in FIGS. 19 to 22. FIG. 23 shows a power conversion unit B11 according to a first modified example. The power conversion unit B11 includes a plurality of mounting members D1. In the power conversion unit B11, three semiconductor devices A10 are individually attached using a plurality of mounting members D1. This distinguishes the power conversion unit B11 from the power conversion unit B10. FIG. 24 shows a power conversion unit B12 according to a second modified example. In the power conversion unit B12, the control board E1 includes two circuit boards E11 and E12. The two circuit boards E11 and E12 are spaced apart in the thickness direction z. The control board E1 of the power conversion unit B12 includes a plurality of interconnecting wires 96. The two circuit boards E11 and E12 are electrically connected to each other via the plurality of interconnecting wires 96. The configuration of the plurality of interconnecting wires 96 is not limited in any way, but may be configured, for example, as follows. Each interconnection wiring 96 includes a plurality of connection pins provided on the circuit board E11 and a connector provided on the circuit board E12. In each interconnection wiring 96, the plurality of connection pins are connected to the connector, thereby providing electrical continuity between the circuit board E11 and the circuit board E12. The power conversion unit B12 includes a plurality of positioning pins 97. Each positioning pin 97 is interposed between the two circuit boards E11 and E12. Each positioning pin 97 is used to determine the position of the circuit board E12 relative to the circuit board E11 and to support the circuit board E12.

[0105] In the above-described power conversion units B10 to B12, an example has been shown in which each semiconductor device A10 is fixed to the heat dissipation member C1 by the mounting member D1. Alternatively, each semiconductor device A10 may be fixed to the heat dissipation member C1 by a bonding layer 80, as shown in FIG.

[0106] First Embodiment: Vehicle F1: Next, a vehicle F1 equipped with a semiconductor device A10 will be described with reference to Fig. 26. The vehicle F1 is, for example, an electric vehicle (EV). In Fig. 26, the semiconductor device A10 is described as being equipped in the vehicle F1 as the power conversion unit B10, but one or more semiconductor devices A10 may be individually equipped in the vehicle F1.

[0107] As shown in Fig. 26, the vehicle F1 includes an on-board charger F11, a storage battery F12, and a drive system F13. The on-board charger F11 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger F11 via a wired connection. The on-board charger F11 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger F11 is stepped up by the converter and then supplied to the storage battery F12. The stepped-up voltage is, for example, 600 V.

[0108] The drive system F13 drives the vehicle F1. The drive system F13 includes an inverter F131 and a drive source F132. The power conversion unit B10 (semiconductor device A10) constitutes part of the inverter F131. Power stored in the storage battery F12 is supplied to the inverter F131. The power supplied from the storage battery F12 to the inverter F131 is DC power. Alternatively, unlike the power system shown in FIG. 26 , a step-up DC-DC converter may be further provided between the storage battery F12 and the inverter F131. The inverter F131 converts DC power into AC power. The inverter F131, including the power conversion unit B10 (semiconductor device A10), is electrically connected to the drive source F132. The drive source F132 includes an AC motor and a transmission. When AC power converted by the inverter F131 is supplied to the drive source F132, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of the vehicle F1. This drives the vehicle F1. To drive the vehicle F1, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the power conversion unit B10 (semiconductor device A10) in the inverter F131 is necessary to output AC power whose frequency is appropriately changed to correspond to the required rotational speed of the AC motor.

[0109] The semiconductor device A10 has the following functions and effects.

[0110] The semiconductor device A10 includes an insulating substrate 11, a first conductor 121, a second conductor 122, and a conductive member 32. The first conductor 121 and the second conductor 122 are bonded to the substrate main surface 11a of the insulating substrate 11. The first semiconductor element 21 is mounted on the first conductor 121. The second conductor 122 is spaced apart from the first conductor 121. The conductive member 32 is bonded to a main surface electrode 212 of the first semiconductor element 21. The conductive member 32 is electrically connected to the second conductor 122 and is supported by the second conductor 122. With this configuration, heat generated by the first semiconductor element 21 is transferred to the conductive member 32. Furthermore, the conductive member 32 generates heat due to parasitic resistance (wiring resistance) when a current flows through it. The heat transferred to or generated by the conductive member 32 is then transferred to the second conductor 122 and dissipated to the outside of the semiconductor device A10 via the insulating substrate 11. Therefore, the semiconductor device A10 can dissipate heat that may accumulate in the conductive member 32 more effectively than the semiconductor module described in Patent Document 1, due to heat dissipation via the second conductor 122. In other words, the semiconductor device A10 can improve heat dissipation performance.

[0111] In the semiconductor device A10, the conductive member 32 forms a path through which a main current flows. The main current refers to a current corresponding to power before or after conversion by the switching operations of the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22. In this configuration, a large current flows through the conductive member 32, which can lead to increased heat generation due to the parasitic resistance (wiring resistance) of the conductive member 32. This means that the amount of heat that can accumulate in the conductive member 32 can be large. In other words, improving the heat dissipation performance of the semiconductor device A10 is important. In particular, the main body 321 of the conductive member 32 is strip-shaped extending in the first direction y and has a small cross-sectional area relative to the main current. This increases the parasitic resistance of the main body 321, which can lead to increased self-heat generation in the main body 321. In other words, improving the heat dissipation performance of the conductive member 32 is particularly important in the semiconductor device A10. Therefore, in the semiconductor device A10, as described above, the heat dissipation properties of the conductive member 32 are improved by connecting the conductive member 32 to the second conductor portion 122. In other words, the semiconductor device A10 has a preferable structure for improving the heat dissipation properties of the semiconductor device A10.

[0112] In the semiconductor device A10, each first power terminal 14 and the conductive member 32 are electrically connected via the corresponding second conductor portion 122. This configuration ensures electrical connection between each first power terminal 14 and the conductive member 32. Furthermore, in the semiconductor device A10, because the conductive member 32 is joined to the second conductor portion 122, the distance of the main body portion 321 (conductive member 32) can be made shorter than in a configuration in which the conductive member 32 is directly joined to the first power terminal 14 (for example, the semiconductor module described in Patent Document 1). This reduces the parasitic resistance of the conductive member 32, making it possible to reduce self-heating of the conductive member 32.

[0113] In the semiconductor device A10, each first power terminal 14 and the conductive member 32 are configured as separate bodies. Each first power terminal 14 and conductive member 32 is joined to the corresponding second conductor portion 122 at a distance in the first direction y from the corresponding second conductor portion 122. This configuration allows the clamp member to press the second conductor portion 122 when forming the sealing resin 50. This allows the semiconductor device A10 to stably fix the support substrate 10. Furthermore, this configuration allows the clamp member to press the second conductor portion 122 without providing a through-hole or the like in each main body portion 321, thereby improving the thermal conductivity and electrical conductivity of the conductive member 32.

[0114] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0115] 27 to 30 show modified examples of the semiconductor device A10 according to the first embodiment. Each of Fig. 27 to 30 corresponds to the cross section shown in Fig. 14. In each of the modified examples shown in Fig. 27 to 30, the plurality of recesses 1219, 1229, and 1239 are not formed, but these recesses 1219, 1229, and 1239 may be formed as in the semiconductor device A10.

[0116] 27 shows a semiconductor device A11 according to a first modified example of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: the two second conductors 122 are not part of the main surface wiring layer 12 of the support substrate 10, but are formed of metal blocks separate from the main surface wiring layer 12.

[0117] In this modified example, each second conductor 122 is individually bonded to the substrate main surface 11a of the insulating substrate 11. The two second conductors 122 in this embodiment are positioned at the same positions as the two second conductors 122 in the semiconductor device A10. Each second conductor 122 made of a metal block is bonded to the substrate main surface 11a of the insulating substrate 11 with an adhesive (not shown). The adhesive may be conductive or non-conductive, and may be, for example, a brazing material or solder. In an example where the insulating substrate 11 is made of ceramic, the adhesive is preferably a brazing material in consideration of adhesion to the insulating substrate 11. The adhesive preferably has high thermal conductivity. The two joints 324 of the conductive member 32 and the coverings 142 of the two first power terminals 14 are electrically connected via the second conductors 122 made of a metal block. In the illustrated example, the dimension in the thickness direction z of each second conductor portion 122 in this modified example is the same as the dimension in the thickness direction z of each second conductor portion 122 in the semiconductor device A10, but may be different.

[0118] Each second conductor portion 122 in this modification includes a first joint portion 1221 and a second joint portion 1222. The first joint portion 1221 is a portion of the corresponding second conductor portion 122 to which the first power terminal 14 (coating portion 142) is joined. The second joint portion 1222 is a portion of the corresponding second conductor portion 122 to which the conductive member 32 (joint portion 324) is joined. In the semiconductor device A11, the thickness (dimension in the thickness direction z) of the first joint portion 1221 and the thickness (dimension in the thickness direction z) of the second joint portion 1222 are the same.

[0119] FIG. 28 illustrates a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A11 in the following respect: the thickness of the second bonding portion 1222 is greater than the thickness of the first bonding portion 1221. In the semiconductor device A11, each second conductor portion 122 is formed of a metal block. This makes it easier to process the second conductor portion 122 than when it is part of the main surface wiring layer 12 (part of a DCB substrate or an AMB substrate). Therefore, it is easy to change the thickness of the first bonding portion 1221 and the second bonding portion 1222. Unlike the semiconductor device A12, the semiconductor device of the present disclosure may have the thickness of the first bonding portion 1221 greater than the thickness of the second bonding portion 1222.

[0120] 29 shows a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respect: the semiconductor device A13 further includes two metal blocks 120.

[0121] The two metal blocks 120 are each provided on a corresponding one of the two second conductors 122. The two metal blocks 120 are joined to the conductor main surfaces 122a of the corresponding second conductors 122. The joining may be performed using a conductive joining material (e.g., solder or a sintered body of metal particles), laser joining, or crimping. Each metal block 120 faces one of the two joining portions 324 (conductive members 32). Each joining portion 324 (conductive members 32) is joined to the corresponding metal block 120 and is electrically connected to the second conductors 122 via the metal block 120.

[0122] 30 shows a semiconductor device A14 according to a fourth modification of the first embodiment. The semiconductor device A14 differs from the semiconductor device A10 in the following respect: the conductive member 32 and each of the first power terminals 14 are integrally formed. That is, in the semiconductor device A14, the conductive member 32 and each of the first power terminals 14 are formed as a single continuous unit.

[0123] In the semiconductor device A14, the two first power terminals 14 extend individually from two joints 324 of the conductive member 32. The boundaries between the two first power terminals 14 and the conductive member 32 are located on the two second conductor portions 122, respectively.

[0124] The semiconductor devices A11 to A14 according to these modifications also achieve the same effects as the semiconductor device A10. Furthermore, as can be seen from the semiconductor devices A11 and A12, the second conductor portion 122 may not be part of the main surface wiring layer 12 but may be formed as a metal block separate from the main surface wiring layer 12. In the semiconductor devices A12 and A13, there is no need to bend the end portion of each main body portion 321 that connects to the joint portion 324. In the semiconductor device A14, the conductive member 32 and each first power terminal 14 are integrally formed. Therefore, compared to the semiconductor device A10, electrical conductivity from the conductive member 32 to each first power terminal 14 is improved, while a heat dissipation path for the conductive member 32 via each second conductor portion 122 can be ensured.

[0125] 31 to 33 show a semiconductor device A20 according to a second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respect: the first power terminal 14 and the conductive member 32 (joint 324) are joined in an overlapping manner on the second conductor portion 122.

[0126] As shown in FIGS. 31 to 33 , in the semiconductor device A20, the first power terminal 14 (covering 142) is joined to the conductor principal surface 122a of the second conductor portion 122, and a joint 324 (conductive member 32) is joined onto the first power terminal 14 (covering 142). Thus, in a plan view, a portion of the covering 142 of the first power terminal 14, a portion of the joint 324 of the conductive member 32, and the second conductor portion 122 overlap one another. In the overlapping region where these overlap, the first power terminal 14 is interposed between the second conductor portion 122 and the conductive member 32 in the thickness direction z. Unlike the example described above, the joint 324 (conductive member 32) may be joined to the conductor principal surface 122a of the second conductor portion 122, and the first power terminal 14 (covering 142) may be joined onto the joint 324.

[0127] In the illustrated example, a through hole connecting the conductive member 32 (joint portion 324) to the first power terminal 14 is formed in the overlapping region. Specifically, the joint portion 324 of the conductive member 32 includes a through hole 3241, and the covering portion 142 of the first power terminal 14 includes a through hole 1421. The through hole 3241 and the through hole 1421 overlap each other in a planar view. In the illustrated example, the center of the through hole 3241 in a planar view overlaps with the center of the through hole 1421 in a planar view, and the diameter of the through hole 3241 is larger than the diameter of the through hole 1421. The relationship between the diameter of the through hole 3241 and the diameter of the through hole 1421 is not limited to this.

[0128] The functions and effects of the semiconductor device A20 are as follows.

[0129] In the semiconductor device A20, similar to the semiconductor device A10, heat transferred from the first semiconductor element 21 to the conductive member 32 is transferred to the second conductor portion 122 and dissipated to the outside of the semiconductor device A20 via the insulating substrate 11. Therefore, the semiconductor device A20 can improve heat dissipation performance similar to the semiconductor device A10. In addition, the semiconductor device A20 achieves the same effects as the semiconductor device A10 by virtue of the configuration common to the semiconductor device A10.

[0130] In the semiconductor device A20, the first power terminals 14 and the conductive members 32 are overlapped and joined on each second conductor portion 122. This configuration makes it possible to reduce the dimension of the second conductor portion 122 in the first direction y. In other words, the semiconductor device A20 can be made smaller in size than the semiconductor device A10 because it can reduce the dimension in the first direction y.

[0131] In the semiconductor device A20, through holes 3241 and 1421 are formed connecting the conductive member 32 (joint 324) to the first power terminal 14. In contrast to this configuration, if the through holes 3241 and 1421 were not formed, the clamping member used to form the sealing resin 50 would sandwich the conductive member 32 (joint 324) and the first power terminal 14 (coating 142) and press against the second conductor 122. Therefore, in order to transmit the pressing force to the second conductor 122, the pressing force of the clamping member must be increased. However, increasing the pressing force of the clamping member may cause bond breakdown between the conductive member 32, the first power terminal 14, and the second conductor 122. In contrast, in the semiconductor device A20, the clamping member can directly press against the second conductor 122, thereby reducing the bond breakdown. Even when the through holes 3241, 1421 are provided, the conductive member 32, the first power terminals 14, and the second conductors 122 can ensure electrical conduction and heat transfer paths in the thickness direction z. If the bonding strength between the conductive member 32, the first power terminals 14, and the second conductors 122 can be sufficiently ensured against the pressing force of the clamping member, in a configuration different from that of the semiconductor device A20, the joint 324 of the conductive member 32 may not include the through hole 3241, and the covering 142 of the first power terminal 14 may not include the through hole 1421. Alternatively, in the semiconductor device A20, the joint 324 of the conductive member 32 may not include the through hole 3241. If the covering 142 of the first power terminal 14 is bonded onto the joint 324 of the conductive member 32, the covering 142 of the first power terminal 14 may not include the through hole 1421.

[0132] 33 to 36 show a semiconductor device A30 according to a third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respects. First, the semiconductor device A30 has a plurality of openings 514, 515, and 516 formed in the main resin surface 51 of the sealing resin 50. Second, the configurations of the first power terminal 14, the second power terminal 15, and the third power terminal 16 are different.

[0133] Each of the two openings 514 has a rectangular shape in a plan view. A portion of the conductor principal surface 122a of each of the two second conductor portions 122 is exposed from each of the two openings 514. A portion of the first power terminal 14 is inserted into each of the two openings 514, and the first power terminal 14 is joined to the second conductor portion 122 exposed from each opening 514.

[0134] The first power terminal 14 includes two joint portions 143 and a connecting portion 144. The two joint portions 143 are individually inserted into two openings 514 and conductively connected to the second conductor portion 122 exposed through the openings 514. The joint portions 143 and the second conductor portion 122 are connected to each other by a conductive bonding material (e.g., solder or a sintered body of metal particles) or by laser welding, but this is not limited to this. The connecting portion 144 connects the two joint portions 143. In the illustrated example, the end of the connecting portion 144 connected to each joint portion 143 is bent downward in the thickness direction z. The connecting portion 144 extends in the second direction x from one joint portion 143 to the other joint portion 143. The shape of the first power terminal 14 is not limited to the illustrated example.

[0135] Each of the two openings 515 has a rectangular shape in a plan view. A portion of the conductor principal surface 121 a of the first conductor portion 121 is exposed from each of the two openings 515. A portion of the second power terminal 15 is inserted into the two openings 515, and the second power terminal 15 is joined to the first conductor portion 121 exposed from each opening 515.

[0136] The second power terminal 15 includes two joint portions 153 and a connecting portion 154. The two joint portions 153 are individually inserted into two openings 515 and are conductively connected to the first conductor portion 121 exposed through the openings 515. The joint portions 153 and the first conductor portion 121 are connected to each other using a conductive bonding material (e.g., solder or a sintered body of metal particles) or by laser welding, but this is not limited to this. The connecting portion 154 connects the two joint portions 153. In the illustrated example, the end of the connecting portion 154 connected to each joint portion 153 is bent downward in the thickness direction z. The connecting portions 154 extend from each joint portion 143 in the first direction y and then bend toward each other in the second direction x. Most of the connecting portion 154 extends in the second direction x. The shape of the second power terminal 15 is not limited to the illustrated example.

[0137] Each of the two openings 516 has a rectangular shape in a plan view. A portion of the conductor main surface 123a of the third conductor portion 123 is exposed from each of the two openings 516. A portion of the third power terminal 16 is inserted into the two openings 516, and the third power terminal 16 is joined to the third conductor portion 123 exposed from each opening 516.

[0138] The third power terminal 16 includes two joint portions 163, a connecting portion 164, and an extending portion 165. The two joint portions 163 are individually inserted into the two openings 516 and are conductively connected to the third conductor portion 123 exposed through the openings 516. The joint portions 163 and the third conductor portion 123 are connected to each other by, but not limited to, a conductive bonding material (e.g., solder or a sintered body of metal particles) or by laser welding. The connecting portion 164 connects the two joint portions 163. In the illustrated example, the end of the connecting portion 164 connected to each joint portion 163 is bent downward in the thickness direction z. In a plan view, the connecting portion 164 overlaps the connecting portion 144 of the first power terminal 14. The extending portion 165 is connected to the connecting portion 164 and extends from the connecting portion 164 in the first direction y. The extending portion 165 causes a portion of the third power terminal 16 to protrude from the first power terminal 14 in a plan view. The shape of the third power terminal 16 is not limited to the example shown in the drawings.

[0139] The functions and effects of the semiconductor device A30 are as follows.

[0140] In the semiconductor device A30, similar to the semiconductor devices A10 and A20, heat transferred from the first semiconductor element 21 to the conductive member 32 is transferred to the second conductor portion 122 and dissipated to the outside of the semiconductor device A30 via the insulating substrate 11. Therefore, similar to the semiconductor devices A10 and A20, the semiconductor device A30 can improve heat dissipation. In addition, the semiconductor device A30 has a common configuration with the semiconductor devices A10 and A20, and thereby achieves the same effects as the semiconductor devices A10 and A20.

[0141] As can be understood from semiconductor device A30, the semiconductor devices disclosed herein are not limited to those in which the first power terminal 14, the second power terminal 15, and the third power terminal 16 protrude from the side of the sealing resin 50 (resin side surface 531 or resin side surface 532) as in each of semiconductor devices A10 and A20.

[0142] In the first to third embodiments (including their modified examples), the arrangement of the multiple signal terminals 17 is not limited to the illustrated example. For example, the multiple signal terminals 17 may be arranged closer to either the side where the first power terminal 14 and the third power terminal 16 are arranged or the side where the second power terminal 15 is arranged in the first direction y. FIG. 38 shows an example in which the multiple signal terminals 17 are arranged closer to the second power terminal 15 in the first direction y. In the semiconductor device shown in FIG. 38 , the multiple signal terminals 17 are aligned in a single row along the second direction x. Unlike this example, the multiple signal terminals 17 may be arranged in multiple rows closer to the second power terminal 15. For example, the multiple signal terminals 17 are divided into those electrically connected to the multiple first semiconductor elements 21 and those electrically connected to the multiple second semiconductor elements 22, with their centers (extension line L1 in FIG. 38 ) sandwiched between them in the second direction x, but this is not limiting. Such a configuration may also be applied to the semiconductor device A30 according to the third embodiment. For example, FIG. 39 illustrates an example of a semiconductor device having a configuration equivalent to that of semiconductor device A30, in which multiple signal terminals 17 are arranged closer to the second power terminal 15 in the first direction y. In the semiconductor device illustrated in FIG. 39 , the multiple signal terminals 17 include multiple signal terminals 171 to 174, which are arranged in a line along the second direction x. The multiple signal terminals 17 may include other signal terminals 176 and 177 instead of or in addition to at least one of the multiple signal terminals 171 to 174. In the example illustrated in FIG. 39 , signal terminals 171 and 173 electrically connected to multiple first semiconductor elements 21 and signal terminals 172 and 174 electrically connected to multiple second semiconductor elements 22 are arranged on opposite sides of the center of the sealing resin 50 in the second direction x. However, the order of the multiple signal terminals 17 along the second direction x is not limited to this. As can be understood from the semiconductor devices illustrated in FIGS. 38 and 39 , the arrangement of the multiple signal terminals 17 of the present disclosure is not limited in any way. In the modifications shown in FIGS. 38 and 39, the layout, number, size, shape, etc. of each component of the semiconductor device can be changed as appropriate in accordance with the layout of the plurality of signal terminals 17.

[0143] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways. The semiconductor device according to the present disclosure includes the embodiments described in the following appendices. As an example, the semiconductor device according to the present disclosure is provided in the power conversion unit and vehicle described in the following appendices. Appendix 1. a first semiconductor element (21) having an element main surface (21a) facing one side in a thickness direction (z) and a main surface electrode (212) formed on the element main surface (21a); ​​an insulating substrate (11) having a substrate main surface (11a) facing the first semiconductor element (21) and supporting the first semiconductor element (21); a first conductor portion (121) bonded to the substrate main surface (11a) and on which the first semiconductor element (21) is mounted; a second conductor portion (122) bonded to the substrate main surface (11a) and spaced apart from the first conductor portion (121); a conductive member (32) bonded to the main surface electrode (212); and a first power terminal (14) electrically connected to the main surface electrode (212) via the conductive member (32), The semiconductor device (A10-A14, A20, A30) in which the second conductor portion (122) supports the first power terminal (14) and the conductive member (32). Appendix 2. The semiconductor device (A10-A13, A20, A30) in which the first power terminal (14) and the conductive member (32) are separate bodies, and the first power terminal (14) and the conductive member (32) are electrically connected via the second conductor portion (122). Appendix 3. The semiconductor device (A11) in which the first power terminal (14) and the conductive member (32) are each joined to the second conductor portion (122), and the second conductor portion (122) includes a first joint portion (1221) to which the first power terminal (14) is joined and a second joint portion (1222) to which the conductive member (32) is joined. Supplementary Note 4: The semiconductor device (A12) according to Supplementary Note 3, wherein the dimension of the first joint (1221) in the thickness direction is different from the dimension of the second joint (1222) in the thickness direction. Supplementary Note 5: The semiconductor device (A20) according to Supplementary Note 2, wherein the first power terminal (14) and the conductive member (32) overlap on the second conductor portion (122).Supplementary Note 6. The semiconductor device (A20) according to Supplementary Note 5, wherein in an overlapping region where the first power terminal (14), the conductive member (32), and the second conductor portion (122) overlap one another in the thickness direction (z), the first power terminal (14) is interposed between the second conductor portion (122) and the conductive member (32) in the thickness direction (z). Supplementary Note 7. The semiconductor device (A20) according to Supplementary Note 6, wherein a through hole (3241, 1421) connecting the conductive member (32) to the first power terminal (14) is formed in the overlapping region. Supplementary Note 8. The semiconductor device (A14) according to Supplementary Note 1, wherein the first power terminal (14) and the conductive member (32) are integrally formed. Supplementary Note 9. The semiconductor device (A10, A13, A14, A20, A30) according to any one of Supplementary Notes 1 to 8, wherein the first conductor portion (121) and the second conductor portion (122) are patterns of metal bodies formed on the substrate main surface (11a). Supplementary Note 10. The semiconductor device (A10 to A14, A20, A30) according to any one of Supplementary Notes 1 to 9, further comprising a sealing resin (50) that covers the first semiconductor element (21) and the insulating substrate (11). Supplementary Note 11. The semiconductor device (A10 to A14, A20) according to Supplementary Note 10, wherein the sealing resin (50) has a first resin side surface (531) facing one side of a first direction (y) perpendicular to the thickness direction (z), and the first power terminal (14) protrudes from the first resin side surface (531). Supplementary Note 12. The semiconductor device (A10 to A14, A20, A30) according to Appendix 11 further comprises: a second semiconductor element (22) covered with the sealing resin (50); and a third conductor portion (123) bonded to the substrate main surface (11a) and on which the second semiconductor element (22) is mounted. Appendix 13. The semiconductor device (A10 to A14, A20, A30) according to Appendix 12, wherein the first conductor portion (121) is located on the opposite side of the third conductor portion (123) from the first resin side surface (531) in the first direction (y). Appendix 13-1. The semiconductor device (A10 to A14, A20, A30) according to Appendix 13, wherein the conductive member (32) intersects the first conductor portion (121) when viewed in the thickness direction (z).Appendix 14. The semiconductor device (A10 to A14, A20, A30) according to any one of Appendix 12, Appendix 13, and Appendix 13-1, further comprising: a second power terminal (15) joined to the first conductor portion (121); and a third power terminal (16) joined to the third conductor portion (123). Appendix 15. The semiconductor device (A10 to A14, A20) according to Appendix 14, wherein the sealing resin (50) has a second resin side surface (532) facing opposite to the first resin side surface (531) in the first direction (x), the second power terminal (15) protrudes from the second resin side surface (531), and the third power terminal (16) protrudes from the first resin side surface (531) together with the first power terminal (14). Appendix 16. The semiconductor device (A10 to A14, A20, A30) according to any one of Supplementary Notes 10 to 15 and Supplementary Note 13-1, further comprising at least one signal terminal (17) electrically connected to the first semiconductor element (21), the sealing resin (50) having a resin main surface (51) facing in the same direction as the element main surface (21a) in the thickness direction (z), and the at least one signal terminal (17) protruding from the resin main surface (51). The semiconductor device (A10) according to any one of Supplementary Notes 1 to 16 and Supplementary Note 13-1, wherein the second conductor portion (122) has a conductor main surface (122a) facing the same direction as the element main surface (21a), and the conductor main surface (122a) includes a depression (1229) recessed in the thickness direction (z) in a non-bonding region that does not overlap with either the first power terminal (14) or the conductive member (32) when viewed in the thickness direction (z). Supplementary Note 18. The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the first semiconductor element (21) includes a semiconductor substrate. Supplementary Note 18-1. The semiconductor device according to Supplementary Note 18, wherein the semiconductor substrate includes any one of silicon, a wide bandgap semiconductor (e.g., silicon carbide or gallium nitride) having a bandgap wider than that of silicon, or an ultra-wide bandgap semiconductor (e.g., gallium oxide, diamond, or aluminum nitride) having a bandgap wider than that of a wide bandgap semiconductor.Supplementary Note 19. The semiconductor device according to any one of Supplementary Notes 1 to 18, Supplementary Note 13-1, and Supplementary Note 18-1, wherein the first semiconductor element (21) is a MOSFET. Supplementary Note 20. A power conversion unit (B10 to B12) further comprising: the semiconductor device (A10 to A14, A20, A30) according to any one of Supplementary Notes 1 to 19, and Supplementary Note 18-1; and a heat dissipation member (C1) arranged on the insulating substrate (11) on the opposite side of the thickness direction (z) to the side on which the first semiconductor element (21) is located. Supplementary Note 20-1. The power conversion unit (B10 to B12) according to Supplementary Note 20, wherein the heat dissipation member (C1) overlaps the second conductor portion (122) as seen in the thickness direction (z). Supplementary Note 20-2. A power conversion unit (B10 to B12) according to Supplementary Note 20 or Supplementary Note 20-1, further comprising a control board (E1) for driving the first semiconductor element (21).Supplementary Note 21. A vehicle (F1) comprising: a semiconductor device (A10 to A14, A20, A30) according to any one of Supplements 1 to 19 and 18-1; and a drive source (F132), wherein the semiconductor device (A10 to A14, A20, A30) is electrically connected to the drive source (F132).Supplementary Note 22. A vehicle (C1) comprising: a power conversion unit (B10 to B12) according to any one of Supplementary Note 20, Supplementary Note 20-1 and Supplementary Note 20-2; and a drive source (F132), wherein the power conversion unit (B10 to B12) is electrically connected to the drive source (F132).

[0144] A10 to A14, A20, A30: semiconductor device 10: supporting substrate 11: insulating substrate 11a: substrate main surface 11b: substrate back surface 12: main surface wiring layer 120: metal block 121: first conductor portion 121a: conductor main surface 1219: recess 122: second conductor portion 122a: conductor main surface 1221: first joint portion 1222: second joint portion 1229: recess 123: third conductor portion 123a: conductor main surface 1231: partition portion 1232: partition portion 1239: recess 13: back surface wiring layer 14: first power terminal 141: exposed portion 142: coated portion 1421: through hole 143: joint portion 144: connecting portion 15: second power terminal 151: exposed portion 152: Covering portion 153: Joint portion 154: Linking portion 16: Third power terminal 161: Exposed portion 162: Covering portion 163: Joint portion 164: Linking portion 165: Extension portion 17: Signal terminal 170: Tip portion 170A: Bulging portion 171 to 174, 176, 177: Signal terminal 21: First semiconductor element 21a: Element main surface 21b: Element back surface 211: Back electrode 212, 213, 214: Principal surface electrode 219: Conductive bonding layer 22: Second semiconductor element 22a: Element main surface 22b: Element back surface 221: Back electrode 222, 223, 224: Principal surface electrode 229: Conductive bonding layer 23: Thermistor 31: Conductive member 311: Main body portion 311a: Through hole 312: Joint portion 313: Joint portion 32: Conductive member 321: Main body portion 3211: Notch 322: Joint portion 324: Joint portion 3241: Through hole 326: Middle portion 327: Cross beam portion 33, 34, 35: Conductive joining layer 41 to 45: Connection member 50: Sealing resin 51: Main resin surface 511: Recess 514, 515, 516: Opening 52: Back resin surface 531 to 534: Side resin surface 55: Recess 601, 602: Signal board 61: Insulating layer 62: Wiring layer 621 to 624: Wiring portion 63: Metal layer 64: Sleeve B10, B11, B12: Power conversion unit C1: Heat dissipation member D1: Mounting member E1: Control board E11,E12: Circuit board F1: Vehicle F11: On-board charger F12: Storage battery F13: Drive system F131: Inverter F132: Drive source 71: Main body 72: Base 73: Positioning part 80: Bonding layer 81: Pressing part 82: Fixing part 89: Fastener 91: Base material 911: Through hole 92: Main wiring 93: Back wiring 94: Internal wiring 951: Mounting hole 952: Positioning hole 96: Connecting wiring 97: Positioning pin,

Claims

1. A semiconductor device comprising: a first semiconductor element having an element principal surface facing one side in the thickness direction and a principal surface electrode formed on the element principal surface; an insulating substrate having a substrate principal surface facing the first semiconductor element and supporting the first semiconductor element; a first conductor portion bonded to the substrate principal surface and carrying the first semiconductor element; a second conductor portion bonded to the substrate principal surface and spaced apart from the first conductor portion; a conductive member bonded to the principal surface electrode; and a first power terminal electrically connected to the principal surface electrode via the conductive member, wherein the second conductor portion supports the first power terminal and the conductive member.

2. The semiconductor device according to claim 1, wherein the first power terminal and the conductive member are separate bodies, and the first power terminal and the conductive member are electrically connected via the second conductor portion.

3. The semiconductor device described in claim 2, wherein each of the first power terminal and the conductive member is joined to the second conductor portion, and the second conductor portion includes a first joint portion to which the first power terminal is joined and a second joint portion to which the conductive member is joined.

4. The semiconductor device according to claim 3, wherein the dimension of the first bonding portion in the thickness direction is different from the dimension of the second bonding portion in the thickness direction.

5. The semiconductor device according to claim 2, wherein the first power terminal and the conductive member overlap the second conductor portion.

6. A semiconductor device as described in claim 5, wherein in an overlapping region where the first power terminal, the conductive member, and the second conductor portion overlap each other when viewed in the thickness direction, the first power terminal is interposed between the second conductor portion and the conductive member in the thickness direction.

7. The semiconductor device according to claim 6, wherein a through hole is formed in the overlapping region, connecting the conductive member to the first power terminal.

8. The semiconductor device according to claim 1, wherein the first power terminal and the conductive member are integrally formed.

9. The semiconductor device according to any one of claims 1 to 8, wherein the first conductor portion and the second conductor portion are patterns of metal bodies formed on the main surface of the substrate.

10. The semiconductor device according to any one of claims 1 to 9, further comprising a sealing resin that covers said first semiconductor element and said insulating substrate.

11. The semiconductor device according to claim 10, wherein the sealing resin has a first resin side surface facing one side of a first direction perpendicular to the thickness direction, and the first power terminal protrudes from the first resin side surface.

12. The semiconductor device according to claim 11, further comprising: a second semiconductor element covered with said sealing resin; and a third conductor portion bonded to said substrate main surface and on which said second semiconductor element is mounted.

13. The semiconductor device according to claim 12, wherein the first conductor portion is located on the opposite side of the third conductor portion from the first resin side surface in the first direction.

14. The semiconductor device according to claim 12 or 13, further comprising: a second power terminal joined to said first conductor portion; and a third power terminal joined to said third conductor portion.

15. The semiconductor device described in claim 14, wherein the sealing resin has a second resin side surface facing opposite to the first resin side surface in the first direction, the second power terminal protrudes from the second resin side surface, and the third power terminal protrudes from the first resin side surface together with the first power terminal.

16. A semiconductor device as described in any one of claims 10 to 15, further comprising at least one signal terminal electrically connected to the first semiconductor element, the sealing resin having a resin main surface facing in the same direction as the element main surface in the thickness direction, and the at least one signal terminal protruding from the resin main surface.

17. A semiconductor device as described in any one of claims 1 to 16, wherein the second conductor portion has a conductor main surface facing in the same direction as the element main surface, and the conductor main surface includes a recess recessed in the thickness direction in a non-bonding region that does not overlap with either the first power terminal or the conductive member when viewed in the thickness direction.

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