Memory array and semiconductor memory system

Abstract

A memory array according to the present invention comprises: a preceding-stage bit line which is connected to a sense amplifier 3; a preceding-stage block unit which includes at least one memory cell connected to the preceding-stage bit line; a switching element which is connected to an end of the preceding-stage bit line that is opposite from an end to which the sense amplifier is connected; a subsequent-stage bit line which is connected to the switching element; and a subsequent-stage block unit which includes at least one memory cell connected to the subsequent-stage bit line. The switching element switches between a first circuit configuration in which the preceding-stage block unit and the subsequent-stage block unit are connected to the sense amplifier and a second circuit configuration in which only the preceding-stage block unit is connected to the sense amplifier.

Description

MEMORY ARRAY AND SEMICONDUCTOR MEMORY SYSTEM

[0001] The present invention relates to memory arrays and semiconductor memory systems.

[0002] NAND flash memory can perform read and write operations faster than hard disks. Because NAND flash memory consumes less power than hard disks, its market is expanding in data centers. Data centers consume a small percentage of the world's total power. It is estimated that approximately 20% of data center power consumption is consumed by memory. Therefore, technologies that reduce power consumption while maintaining memory performance are becoming increasingly important.

[0003] 3D NAND flash memory achieves high bit density by increasing the number of word line stacks. However, increasing the number of word line stacks increases the number of series transistors, which reduces cell current and results in longer bit line access times, which has been pointed out as a technical issue.

[0004] International Publication No. 2022-264903

[0005] In view of the above circumstances, the inventors of the present application have come up with the technology described in Patent Document 1. The technology described in Patent Document 1 uses a power supply that outputs a lower voltage than the power supply for the peripheral circuitry as the power supply used for charging the bit lines, rather than the power supply for the peripheral circuitry. This technology can reduce the power required for read operations by about 30% while maintaining memory performance.

[0006] However, in the technical field of semiconductor memory systems, there is a demand for further power saving and faster operation.

[0007] An object of the present invention is to provide a memory array and a semiconductor memory system that are capable of further reducing power consumption and increasing the operation speed.

[0008] One aspect of the present invention is a memory array in which data is written and / or read via an amplifier circuit. The memory array includes a first bit line connected to the amplifier circuit, a first block unit including at least one memory cell connected to the first bit line, a first switching element connected to an end of the first bit line opposite to the end connected to the amplifier circuit, a second bit line connected to the first switching element, and a second block unit including at least one memory cell connected to the second bit line. The first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the amplifier circuit and a second circuit configuration in which only the first block unit is connected to the amplifier circuit.

[0009] The switching element of this memory array alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the amplifier circuit and a second circuit configuration in which only the first block unit is connected to the amplifier circuit. The parasitic capacitance and parasitic resistance in the second circuit configuration are smaller than those in the first circuit configuration. As a result, when reading data from a memory cell belonging to the first block unit, the time required to charge the bit line can be shortened compared to when reading data from a memory cell belonging to the second block unit. The shorter charging time contributes to faster read operations. When reading data from a memory cell belonging to the first block unit, the energy required to charge the bit line is reduced compared to when reading data from a memory cell belonging to the second block unit. The reduced energy required for charging contributes to power savings in read operations.

[0010] Another aspect of the present invention is a memory array in which data is written via a circuit switching element. The memory array includes a first bit line connected to the circuit switching element, a first block unit including at least one memory cell connected to the first bit line, a first switching element connected to an end of the first bit line opposite to the end connected to the circuit switching element, a second bit line connected to the first switching element, and a second block unit including at least one memory cell connected to the second bit line. The circuit switching element outputs a voltage corresponding to data to be written to the first bit line. The first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the circuit switching element and a second circuit configuration in which only the first block unit is connected to the circuit switching element.

[0011] In this memory array, when writing data to a memory cell belonging to the first block unit, the time required to charge the bit line can be made shorter than when writing data to a memory cell belonging to the second block unit. The shorter charging time contributes to faster write operations. Furthermore, when writing data to a memory cell belonging to the first block unit, the energy required to charge the bit line is reduced compared to when writing data to a memory cell belonging to the second block unit. The reduced energy required for charging contributes to power savings in write operations.

[0012] In the memory array, the number of memory cells included in the first block unit may be equal to the number of memory cells included in the second block unit. In the memory array, the length of the first bit line may be equal to the length of the second bit line. These configurations enable a circuit configuration that emphasizes reducing the energy required for charging.

[0013] In the memory array, the number of memory cells included in the first block unit may be different from the number of memory cells included in the second block unit. In the memory array, the length of the first bit line may be different from the length of the second bit line. These configurations enable a circuit configuration that emphasizes shortening the time required for charging.

[0014] The memory array further includes an n+1th switching element connected to an end of the nth bit line opposite to the end to which the nth block unit (n is an integer between 2 and N) is connected, an n+1th bit line connected to the n+1th switching element, and an n+1th block unit including at least one memory cell connected to the n+1th bit line. The nth switching element may alternate between a connection configuration in which the nth block unit is connected to the n-1th block unit and a disconnection configuration in which only the nth block unit is disconnected from the n-1th block unit. This configuration enables further power savings and faster operation in read and / or write operations in a memory array including multiple block units.

[0015] According to another aspect of the present invention, a semiconductor memory system includes a memory array including a plurality of memory cells from which data is to be read, an amplifier circuit connected to the memory array and used to read data stored in the memory cells, and a control module for providing control signals to the memory array and the amplifier circuit. The memory array includes a first bit line connected to the amplifier circuit, a first block unit including at least one memory cell connected to the first bit line, a first switching element connected to an end of the first bit line opposite to the end connected to the amplifier circuit, a second bit line connected to the first switching element, and a second block unit including at least one memory cell connected to the second bit line. The first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the amplifier circuit and a second circuit configuration in which only the first block unit is connected to the amplifier circuit.

[0016] This semiconductor memory system includes the memory array described above, and therefore is capable of further reducing power consumption and increasing the operation speed of read operations.

[0017]

[0009] Another aspect of the present invention provides a semiconductor memory system comprising: a memory array including a plurality of memory cells to which data is to be written; a circuit switching element connected to the memory array and used for writing data stored in the memory cells; and a control module for providing control signals to the memory array and the circuit switching element. The memory array includes a first bit line connected to the circuit switching element, a first block unit including at least one memory cell connected to the first bit line, a first switching element connected to an end of the first bit line opposite to the end connected to the circuit switching element, a second bit line connected to the first switching element, and a second block unit including at least one memory cell connected to the second bit line. The circuit switching element outputs a voltage corresponding to data to be written to the first bit line. The first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the circuit switching element and a second circuit configuration in which only the first block unit is connected to the circuit switching element.

[0018] This semiconductor memory system includes the memory array described above, and therefore is capable of further reducing power consumption and increasing the operation speed of write operations.

[0019] In the semiconductor memory system, the control module may select the first circuit configuration when a target memory cell selected as a target of operation belongs to the second block unit, and may select the second circuit configuration when the target memory cell belongs to the first block unit. With this configuration, one of the first circuit configuration and the second circuit configuration can be selected depending on the position of the memory cell that is the target of operation.

[0020] In the semiconductor memory system described above, the control module may be configured to, when a target memory cell selected as a target for operation belongs to a second block unit, start charging the first bit line and the second bit line, and perform an operation targeting data from the target memory cell after a first charging time has elapsed since the time when charging started, and, when a target memory cell selected as a target for operation belongs to the first block unit, start charging the first bit line, and perform an operation targeting data from the target memory cell after a second charging time has elapsed since the time when charging started, the second charging time may be shorter than the first charging time. With this configuration, when a memory cell to be read or written belongs to the first block unit, it is possible to further shorten the time required for reading or writing.

[0021] According to the present invention, it is possible to provide a memory array and a semiconductor memory system that can further reduce power consumption and increase the operation speed.

[0022] FIG. 1 is a diagram showing the configuration of a semiconductor memory system according to a first embodiment. FIG. 2 is a functional block diagram of the control module shown in FIG. 1. FIG. 3 is a circuit diagram of the memory array and sense amplifier shown in FIG. 1. FIG. 4 is a circuit diagram showing a specific example of the memory array shown in FIG. 2. FIG. 5 is a flowchart showing a read operation performed by the semiconductor memory system according to the first embodiment. FIGS. 6(a), 6(b), 6(c), 6(d), 6(e), 6(f), 6(g), 6(h), 6(i), 6(j), and 6(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is subjected to a read operation under a first condition. FIGS. 7(a), 7(b), 7(c), 7(d), 7(e), 7(f), 7(g), 7(h), 7(i), 7(j), and 7(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is subjected to a read operation under a second condition. Figures 8(a), 8(b), 8(c), 8(d), 8(e), 8(f), 8(g), 8(h), 8(i), 8(j), and 8(k) are timing charts showing changes in control signals and voltages related to the memory array when a read operation is performed on the semiconductor memory system under the third condition. Figures 9(a), 9(b), 9(c), 9(d), 9(e), 9(f), 9(g), 9(h), 9(i), 9(j), and 9(k) are timing charts showing changes in control signals and voltages related to the memory array when a read operation is performed on the semiconductor memory system under the fourth condition. Figures 10(a) and 10(b) are conceptual diagrams for explaining power consumption related to a read operation. Figure 10(c) is a conceptual diagram for explaining charging time related to a read operation. Figure 11 is a flowchart showing a write operation performed by the semiconductor memory system of the first embodiment. Figures 12(a), 12(b), 12(c), 12(d), 12(e), 12(f), 12(g), 12(h), 12(i), 12(j), and 12(k) are timing charts showing changes in control signals and voltages related to the memory array when a write operation is performed on the semiconductor memory system under the fifth condition.Figures 13(a), 13(b), 13(c), 13(d), 13(e), 13(f), 13(g), 13(h), 13(i), 13(j), and 13(k) are timing charts showing changes in control signals and voltages related to the memory array when a write operation is performed on the semiconductor memory system under condition 6. Figures 14(a), 14(b), 14(c), 14(d), 14(e), 14(f), 14(g), 14(h), 14(i), 14(j), and 14(k) are timing charts showing changes in control signals and voltages related to the memory array when a write operation is performed on the semiconductor memory system under condition 7. 15(a), 15(b), 15(c), 15(d), 15(e), 15(f), 15(g), 15(h), 15(i), 15(j), and 15(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is operated under the eighth condition. FIG. 16 is a diagram showing the configuration of a semiconductor memory system of a second embodiment. FIG. 17 is a circuit diagram of the switching circuit shown in FIG. 16. FIG. 18 is a functional block diagram of the control module shown in FIG. 16. FIG. 19 is a flowchart showing the operation of the semiconductor memory system of the second embodiment. FIGS. 20(a), 20(b), 20(c), 20(d), 20(e), 20(f), 20(g), 20(h), 20(i), 20(j), and 20(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is operated under the first condition. Figures 21(a), 21(b), 21(c), 21(d), 21(e), 21(f), 21(g), 21(h), 21(i), 21(j), and 21(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is operated under condition 2. Figures 22(a), 22(b), 22(c), 22(d), 22(e), 22(f), 22(g), 22(h), 22(i), 22(j), and 22(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is operated under condition 3.23(a), 23(b), 23(c), 23(d), 23(e), 23(f), 23(g), 23(h), 23(i), 23(j), and 23(k) are timing charts showing changes in control signals and voltages related to the memory array when the semiconductor memory system is operated under the fourth condition. FIGS. 24(a), 24(b), and 24(c) are timing charts showing control signals for the switching circuit shown in FIG. 17. FIG. 25 is a circuit diagram showing a specific example of a memory cell included in the semiconductor memory system of the first modified example. FIG. 26 is a circuit diagram showing a specific example of a memory cell included in the semiconductor memory system of the second modified example. FIG. 27 is a circuit diagram showing a specific example of a memory cell included in the semiconductor memory system of the third modified example. FIG. 28(a) is a graph showing the results of a first example confirming the effect of shortening charging time. FIG. 28(b) is a graph showing the results of a second example confirming the effect of reducing the energy required for charging. Fig. 29 is a graph showing the results of Example 3 in which the expected value of the effect of shortening the charging time and the expected value of the effect of reducing the energy required for charging were confirmed. Fig. 30 is a diagram showing the circuit configuration that is the premise of Example 4.

[0023] Hereinafter, preferred embodiments of the memory system according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are designated by the same reference numerals, and duplicated explanations will be omitted.

[0024] 1 stores data in combination with a memory controller 100. The semiconductor memory system 1 executes data read operations and data write operations in accordance with the control of the memory controller 100.

[0025] The semiconductor memory system 1 is configured with a plurality of transistors (MOSFETs: Metal Oxide Semiconductor Field Effect Transistors) mounted on a semiconductor chip. The semiconductor memory system 1 has a memory array 2, a circuit module 5, and a control module 6. The memory array 2, the circuit module 5, and the control module 6 may be formed on the same semiconductor chip.

[0026] The memory array 2 includes a plurality of memory cells 21 configured with transistors (MOSFETs). The memory cells 21 are arranged in a two-dimensional array. The memory cells 21 store binary data such as "0" or "1." Specifically, the memory cells 21 are set to either a high or low threshold voltage state by a write operation by the circuit module 5. The memory array 2 includes a plurality of subarrays. The number of subarrays may be, for example, approximately 128,000. Each subarray includes a plurality of memory cells 21 arranged one-dimensionally (linearly). The number of memory cells 21 may be, for example, 1,024.

[0027] The circuit module 5 has a function of reading data from the memory array 2 and a function of writing data to the memory array 2. The circuit module 5 includes a sense amplifier 3 (amplification circuit) that executes data read and write operations.

[0028] The control module 6 has a function of relaying control signals and data between the memory controller 100 and the circuit module 5. The control module 6 transmits and receives control signals and data from the bus line 101 via the input / output port 15a and the wiring 16a. That is, the control module 6 relays control signals for controlling data reading and data writing, which are transmitted from the memory controller 100, to the circuit module 5. The control module 6 relays data output from the circuit module 5 during a data read operation to the memory controller 100. The control module 6 receives data to be written to the memory array 2 from the memory controller 100 and relays the received data to the circuit module 5.

[0029] The semiconductor memory system 1 includes four power supply terminals 11a, 11b, 13a, and 13b. The power supply terminals 11a, 11b, 13a, and 13b receive various voltages from a regulator 110. For example, the regulator 110 receives a voltage V ＤＤ a power supply line 111 that outputs a voltage V ＳＳ a power supply line 112 that outputs a voltage V ＤＤＱ a power supply line 113 that outputs a voltage V ＳＳＱ and a power supply line 114 that outputs

[0030] The power supply terminal 11a is connected to the power supply line 111. The power supply terminal 11a supplies a voltage V ＤＤ Voltage V ＤＤ may be any value. ＤＤ The power supply terminal 11b is connected to the power supply line 112. ... ＳＳ Voltage V ＳＳ is 0V as a reference voltage. ＤＤ is the voltage V ＳＳ is the potential difference based on

[0031] The power supply terminal 13a is connected to the power supply line 113. The power supply terminal 13a supplies a voltage V ＤＤＱ Voltage V ＤＤＱ may be any value. ＤＤＱThe power supply terminal 13b is connected to the power supply line 114. ... ＳＳＱ Voltage V ＳＳＱ is 0V as a reference voltage. ＤＤＱ is the voltage V ＳＳＱ is the potential difference based on

[0032] The power supply terminals 11a and 11b are electrically connected to the circuit module 5 via wiring 12a and 12b, respectively. The power supply terminals 11a and 11b transmit power supplied from the power supply 102 to the circuit module 5. The power supply terminal 13a is electrically connected to the control module 6 via wiring 14a. The power supply terminal 13b is electrically connected to the control module 6 via wiring 14b.

[0033] The control module 6 incorporates transistors that have a lower drive voltage and faster operation speed than the circuit module 5. As a result, it can operate with power supplied from a relatively low-voltage power supply 103. In contrast, the circuit module 5 operates while receiving power from a relatively high-voltage power supply 102 in order to maintain the reliability of the data read operation from the memory array 2.

[0034] <Control Module 6> The control module 6 outputs several control signals for operating the memory array 2 and the sense amplifiers 3. The control module 6 outputs information to be written to the memory cells 21. The control module 6 receives information read from the memory cells 21.

[0035] More specifically, the control module 6 outputs control signals PASS, PREB, and SNS to the sense amplifier 3 based on a write command or a read command received from the bus line 101. The control module 6 also receives address information from the bus line 101 that identifies the memory cell 21 that is the target of reading or writing. Based on the write command or the read command, the control module 6 outputs the control signal V ＷＬ, SW to the memory array 2. As shown in Fig. 2, the control module 6 is composed of several functional blocks. These functional blocks may be physical circuits built into a semiconductor chip.

[0036] The control module 6 includes an input buffer 61 , a row address decoder 62 , a word line decoder 63 , a controller 64 , a column address decoder 65 , and an output buffer 66 .

[0037] The input buffer 61 is connected to the bus line 101. The input buffer 61 receives address information that identifies the memory cell 21 to be read or written from the bus line 101. The input buffer 61 passes the address information to a row address decoder 62 and a column address decoder 65.

[0038] The output buffer 66 is connected to the bus line 101. The output buffer 66 receives the data signal D output from the sense amplifier 3. ＯＵＴ The output buffer 66 receives the data signal D ＯＵＴ is output to the bus line 101.

[0039] The row address decoder 62 receives address information from the input buffer 61. The row address decoder 62 generates row address information from the address information. The row address decoder 62 passes the row address information to the word line decoder 63 and the controller 64.

[0040] The word line decoder 63 receives row address information from the row address decoder 62. The word line decoder 63 receives predetermined information from the controller 64. The word line decoder 63 generates a control signal V ＷＬ A sub-block BK is selected for applying a control signal V to the word line WL connected to the selected sub-block BK. ＷＬ Give.

[0041] The column address decoder 65 receives address information from the input buffer 61. The column address decoder 65 generates column address information from the address information. The column address decoder 65 passes the column address information to the sense amplifier 3.

[0042] The controller 64 receives a command from the bus line 101. The controller 64 generates control signals PASS, PREB, and SNS based on the command. The controller 64 outputs the generated control signals PASS, PREB, and SNS to the sense amplifier 3.

[0043] The controller 64 receives row address information from the row address decoder 62. The controller 64 generates a control signal SW based on the row address information. Specifically, the controller 64 first determines whether or not the sub-block BK specified by the row address information is included in the subsequent block unit BU2. When the controller 64 determines that the sub-block BK is included in the subsequent block unit BU2, it generates a control signal SW[1(H)] that turns on the switching element 20. When the controller 64 determines that the sub-block BK is not included in the subsequent block unit BU2, it generates a control signal SW[0(L)] that turns off the switching element 20. The controller 64 outputs the control signal SW to the memory array 2 at a predetermined timing.

[0044] The detailed configuration of the main parts of the semiconductor memory system 1 will be described with reference to FIGS.

[0045] 3, the memory array 2 has a plurality of memory cells 21, a plurality of bit lines BL, and a plurality of word lines WL. These memory cells 21, bit lines BL, and word lines WL are formed on a semiconductor chip. The bit lines BL have a parasitic capacitance C ＢＬＦ , C ＢＬＮThe bit lines BL read information stored in the memory cells 21. The bit lines BL write predetermined information to the memory cells 21. The word lines WL select the memory cells 21 from which information is to be read or written. The word lines WL carry a positive voltage control signal V to select one memory cell 21 in each sub-array 25 during a data read operation. ＷＬ Information is written and / or read via the bit line BL to the memory cell 21 selected by the signal via the word line WL.

[0046] For example, it is assumed that the memory cell 21 has a bit line port 211 connected to the bit line BL, a word line port 212 connected to the word line WL, and a ground port 213. The bit line port 211, word line port 212, and ground port 213 are used for convenience of explanation and do not necessarily exist physically.

[0047] A plurality of memory cells 21 are connected to one bit line BL. A plurality of memory cells 21 connected to one bit line BL is called a subarray 20S. A plurality of memory cells 21 belonging to different subarrays 20S are connected to one word line WL. A plurality of memory cells 21 belonging to different subarrays 20S connected to one word line WL is called a subblock BK. With this connection configuration, the plurality of memory cells 21 are arranged two-dimensionally.

[0048] The memory cell 21 can employ various circuit configurations that can write and read binary information.

[0049] An example of the memory cell 21 is a memory cell transistor 21a shown in Figure 4. The memory cell transistor 21a has a so-called floating gate. When the memory cell 21 stores data "0", electrons are injected into the floating gate of the memory cell transistor 21a. When the memory cell 21 stores data "1", electrons are not injected into the floating gate of the memory cell transistor 21a.

[0050] The source of the memory cell transistor 21a is connected to the bit line BL via a bit line port 211. The drain of the memory cell transistor 21a is connected to a ground voltage point via a ground port 213. The control gate of the memory cell transistor 21a is connected to the word line WL via a word line port 212. A semiconductor memory system 1 having such a connection configuration is known as a NOR flash type.

[0051] The type of the semiconductor memory system is not limited to the NOR flash type. The type of the semiconductor memory system may be a NAND flash type, SRAM, DRAM, ReRAM, MRAM, Cross-Point MEMORY, ROM, etc. Some specific examples of these will be described later as modified examples.

[0052] The memory array 2 has a front-stage block unit BU1 (first block unit) including a plurality of sub-blocks BK, a rear-stage block unit BU2 (second block unit), and a switching element 20 (first switching element). With this configuration, the memory array 2 can select a first circuit configuration or a second circuit configuration.

[0053] The first circuit configuration indicates that the preceding block unit BU1 is connected to the sense amplifier 3 and the following block unit BU2 is disconnected from the sense amplifier 3. The first circuit configuration is realized by turning off the switching element 20. The first circuit configuration is selected when the sub-block BK selected for reading or writing is included in the preceding block unit BU1.

[0054] The second circuit configuration indicates that the preceding block unit BU1 is connected to the sense amplifier 3, and the succeeding block unit BU2 is also connected to the sense amplifier 3. The second circuit configuration is realized by turning on the switching element 20. The second circuit configuration is selected when the sub-block BK selected for reading or writing is included in the succeeding block unit BU2.

[0055] The preceding block unit BU1 and the following block unit BU2 can be defined by the switching element 20. The preceding block unit BU1 is composed of a plurality of sub-blocks BK connected to the bit line BL between the switching element 20 and the sense amplifier 3. For example, the portion of the bit line BL included in the preceding block unit BU1 is referred to as the preceding bit line BL1 (first bit line). In other words, the preceding block unit BU1 has a plurality of sub-blocks BK and a plurality of preceding bit lines BL1.

[0056] The subsequent block unit BU2 is composed of a plurality of sub-blocks BK connected between the switching element 20 and the end of the bit line BL. The distance from the subsequent block unit BU2 to the sense amplifier 3 is longer than the distance from the previous block unit BU1 to the sense amplifier 3. For example, the portion of the bit line BL included in the subsequent block unit BU2 is referred to as the subsequent bit line BL2 (second bit line).

[0057] The switching element 20 is an N-channel MOSFET. The source of the switching element 20 is connected to the subsequent block unit BU2. The source of the switching element 20 is connected to the subsequent bit line BL2. The drain of the switching element 20 is connected to the previous block unit BU1. The drain of the switching element 20 is connected to the previous bit line BL1. The gate of the switching element 20 is connected to a control signal line SL. The gate of the switching element 20 receives a control signal SW via the control signal line SL. A plurality of switching elements 20 are connected to one control signal line SL.

[0058] With this configuration, it is possible to reduce the power required for writing or reading data to or from the memory cells 21 belonging to the preceding block unit BU1 and shorten the time required for the operation, thereby increasing the speed of writing or reading data.

[0059] 3, the sense amplifier 3 has a function of writing information to a selected memory cell 21 and a function of reading information from a selected memory cell 21. The sense amplifier 3 has a plurality of sub-circuits 3S. One sub-circuit 3S is connected to an end of one bit line BL. The number of sub-circuits 3S included in the sense amplifier 3 may be the same as the number of bit lines BL included in the memory array 2.

[0060] The sub-circuit 3S includes a read / write line RL, which is a line-shaped wiring portion, an amplifier portion 31, an inverter 32, and an inverter 33. The read / write line RL is formed on the semiconductor chip in the same manner as the bit line BL, and inevitably has a finite parasitic capacitance C ＳＮ Since the length of the read / write line RL is shorter than that of the bit line BL, the parasitic capacitance C ＳＮ The magnitude of the parasitic capacitance C ＢＬＦ , C ＢＬＮ is much smaller than the magnitude of the

[0061] The amplifier unit 31 includes a switching element 311 (circuit switching element) and a switching element 312 .

[0062] The switching element 311 is an N-channel MOSFET. The source of the switching element 311 is connected to the bit line BL via the read / write line RL. The drain of the switching element 311 is connected to a sense node SN on the read / write line RL. The gate of the switching element 311 receives a control signal PASS. The gate of the switching element 311 is connected to a control signal line PL. The gates of multiple switching elements 311 are connected to one control signal line PL. The multiple switching elements 311 can receive the control signal PASS substantially simultaneously.

[0063] A positive voltage control signal PASS is applied to the gate of the switching element 311 during a data read operation. The switching element 311 turns on or off depending on the voltage of the bit line BL. Here, "on or off of the switching element 311" means the following in more detail: "on" means that the switching element 311 flows a current I ＢＬ１ "OFF" indicates a state in which the switching element 311 flows a current I when the memory cell 21 with data "0" is connected to the bit line BL. ＢＬ０ Indicates the state in which water is flowing.

[0064] Here, the current I ＢＬ１ is the current I ＢＬ０ Current I ＢＬ１ is the current I that flows through the memory cell 21 with data "1" when the voltages of the word line WL, bit line BL, and read / write line RL reach a steady state. ｃｅｌｌ１ Current I ＢＬ０ is the current I that flows through the memory cell 21 with data "0" when the voltages of the word line WL, bit line BL, and read / write line RL reach a steady state. ｃｅｌｌ０ where the current I ｃｅｌｌ１ is the current I ｃｅｌｌ０ The switching element 312 is configured so that a control signal PREB is applied to its gate during a data read operation. The switching element 312 operates to turn on or off the connection between the power supply 103 or 102 and the read / write line RL.

[0065] The switching element 312 is a P-channel MOSFET. The drain of the switching element 312 is connected to a sense node SN on the read / write line RL. The drain of the switching element 312 is connected to the drain of the switching element 311 via the sense node SN. The source of the switching element 312 is connected to a power supply. The source of the switching element 312 receives a voltage output by the power supply 102. The source of the switching element 312 is electrically connected to a power supply selected from the power supplies 102 and 103 via the switching circuit 4.

[0066] <Charging Function and Amplification Function of Sense Amplifier> First, the charging function is performed by the functions of the switching elements 311 and 312. According to the charging function of the sense amplifier 3, the control signal PASS is set to a positive voltage after the start of a data read operation. Next, when the control signal PREB is set to a low voltage lower than the source voltage of the switching element 312, the switching elements 311 and 312 are turned on. Then, a charging current is supplied to the read / write line RL and bit line BL via the switching element 312, the read / write line RL, and the switching element 311.

[0067] The switching elements 311 and 312 perform a charging function, and then an amplifying function. The amplifying function of the sense amplifier 3 maintains the control signal PASS at a positive voltage. Next, when the control signal PREB is set to a high voltage close to the source voltage of the switching element 312, the switching element 312 is turned off. Then, the voltage (electrical signal) of the bit line BL is amplified at the sense node SN on the read / write line RL. In other words, the amplifier 31 amplifies the current I according to the data of the memory cell 21 flowing through the bit line BL. ＢＬ１ Or current I ＢＬ０ It has the function of amplifying (electrical signals).

[0068] Specifically, the threshold voltage and the voltage of the control signal PASS are set so that the switching element 311 turns on or off depending on the voltage of the bit line BL, which changes in response to the storage state of the data in the memory cell 21 connected to the bit line BL.

[0069] For example, when data "0" is stored in the selected memory cell 21 and the selected memory cell 21 is turned off, the switching element 311 operates as a source follower. Next, the switching element 311 turns on until the bit line BL reaches a voltage (e.g., 0.5 V) obtained by subtracting the threshold voltage from the control signal PASS due to charging. Then, the switching element 311 turns off at the timing when the bit line BL reaches that voltage. As a result, the voltage V of the bit line BL ＢＬ is stabilized at a voltage obtained by subtracting the threshold voltage from the control signal PASS.

[0070] For example, when the selected memory cell 21 stores data "1" and the selected memory cell 21 is turned on, a charging current flows through the memory cell 21, causing the voltage V ＢＬ is stabilized at a voltage (for example, 0.4 V) equal to or lower than the voltage obtained by subtracting the threshold voltage from the control signal PASS. As a result, the switching element 311 remains in the on state.

[0071] When the control signal PREB is set to a high voltage at the timing when the voltage of the bit line BL is stabilized at two different voltages by the above function, the switching elements 311 and 312 change the voltage V of the bit line BL. ＢＬ The voltage V of the bit line BL is amplified. ＢＬ When the voltage is stabilized at a high voltage, the switching elements 311 and 312 are turned off. As a result, the parasitic capacitance C ＳＮ Therefore, the charge stored in the sense node SN is maintained. ＳＮ is maintained at a high voltage (e.g., 2 V). ＢＬ When the voltage Vcc stabilizes at a low voltage, the switching element 311 is turned on and the switching element 312 is turned off. As a result, the parasitic capacitance C ＳＮ The charge stored in the sense node SN is discharged through the bit line BL. ＳＮ drops to a low voltage (eg, 0.4V).

[0072] The other end of the read / write line RL is connected to the input of the inverter 32. The inverter 32 detects the voltage V ＳＮ Next, the inverter 32 detects the detected voltage V ＳＮ is compared with a predetermined threshold voltage. As a result, the data stored in the memory cell 21 connected to the bit line BL corresponding to the sub-circuit 3S to which the inverter 32 belongs is determined. The inverter 32 outputs a data signal D ＯＵＴ The inverter 32 outputs the voltage V ＳＮis high (for example, 2 V), it is determined that the voltage is higher than a predetermined threshold voltage (for example, 1.2 V). ＯＵＴ The inverter 32 outputs the voltage V ＳＮ is low (for example, 0.4 V), it is determined that the voltage is lower than a predetermined threshold voltage (for example, 1.2 V). Then, the inverter 32 outputs a high-level (for example, 2 V) data signal D ＯＵＴ At this time, the inverter 32 starts the above-mentioned determination operation at the timing when the input control signal SNS is set to a high level indicating an enable state. Specifically, the inverter 32 starts the determination operation at the timing after the control signal PREB is set to a high voltage and the switching element 312 is turned off.

[0073] The input of the inverter 33 is connected to, for example, the input / output port 15a. The inverter 33 receives a voltage (2V) representing data "1" or a voltage (0V) representing data "0". The output of the inverter 33 is connected to the other end of the read / write line RL. The inverter 33 compares the voltage applied to its input with a predetermined threshold voltage. When the voltage applied to its input is 2V ("1"), the inverter 33 generates an output voltage of 2V. When the voltage applied to its input is 0V ("0"), the inverter 33 generates an output voltage of 1V. The voltage generated by the inverter 33 is applied to the sense node SN via the read / write line RL in accordance with the control signal PGM. Specifically, when the control signal PGM is set to a high voltage, the inverter 33 applies an output voltage (2V or 1V) to the sense node SN.

[0074] <Read Operation> Next, the operation of the semiconductor memory system 1 will be described using a read operation as an example. Fig. 5 is a flowchart showing the main steps of the read operation.

[0075] 6, 7, 8 and 9 are timing charts showing changes in voltages and control signals in the memory array 2 and the sense amplifier 3 during a data read operation. ＤＤＢＬ 6(b), 7(b), 8(b) and 9(b) show the time variation of the control signal V ＷＬ 6(c), 7(c), 8(c), and 9(c) show the time changes of the control signal SW. FIGS. 6(d), 7(d), 8(d), and 9(d) show the time changes of the control signal PASS. FIGS. 6(e), 7(e), 8(e), and 9(e) show the time changes of the control signal PREB. FIGS. 6(f), 7(f), 8(f), and 9(f) show the time changes of the voltage V ＢＬ 6(g), 7(g), 8(g), and 9(g) show the time variation of the voltage V ＳＮ 6(h), 7(h), 8(h) and 9(h) show the time changes of the control signal SNS. 6(i), 7(i), 8(i) and 9(i) show the time changes of the data signal D ＯＵＴ 6(j), 7(j), 8(j) and 9(j) show the time changes of the control signal PGM. 6(k), 7(k), 8(k) and 9(k) show the time changes of the data signal D ｉｎ The time change of is shown.

[0076] First, the control module 6 executes a read preparation operation (S1). First, the control module 6 determines the sub-block BK to be read (S11). Next, the control module 6 determines whether the sub-block BK to be read is included in the subsequent block unit BU2 (S12). If the control module 6 determines that the sub-block BK to be read is included in the subsequent block unit BU2 (S12: YES), the control module 6 selects subsequent read operation conditions (S13A). The subsequent read operation conditions include a setting to turn on the switching element 20 and a setting to set the charging time to a first time. If the control module 6 determines that the sub-block BK to be read is not included in the subsequent block unit BU1 (S12: NO), the control module 6 selects previous read operation conditions (S13B). The previous read operation conditions include a setting to turn off the switching element 20 and a setting to set the charging time to a second time. Here, the second time is shorter than the first time. The charging time will be described in detail later.

[0077] The read preparation operation (S1) also includes an operation of putting the sub-circuit 3S into a state in which it can perform the read operation. The operation of putting the sub-circuit 3S into a state in which it can perform the read operation is to output a control signal PGM(0) to the inverter 33 used for writing. During the period in which the read operation (S1, S2) is being performed, the control signal PGM(0) is always applied to the inverter 33. Note that during the period in which the read operation (S1, S2) is being performed, the data signal D received by the inverter 33 is ｉｎ The value of the data signal D may be a voltage indicating data "0" or a voltage indicating data "1." In the following description, as an example, the data signal D received by the inverter 33 during the period when the read operation (S1, S2) is being performed is ｉｎ The value of is a voltage that indicates data "0".

[0078] After the read preparation operation (S1) is completed, the control module 6 executes the read operation (S2).

[0079] Here, the four conditions shown in Table 1 are assumed for the read operation (S2).

[0080] First, the control module 6 applies a voltage V ＤＤＢＬ More specifically, the control module 6 starts the operation (S21) of applying (2V). ０ From time T ＷＬ The control module 6 applies the voltages and control signals shown in Table 2 to the circuit module 5 and the memory array 2 during the period from time T ０ From time T ＷＬ During the period up to , the voltages shown in Table 2 are generated at the sense node SN.

[0081] Next, the control module 6 outputs a control signal V ＷＬ Then, the operation of giving the control signal V ＷＬ rises to 1 V over time. More specifically, the control module 6 ＷＬ From time T ＳＷ The control module 6 applies the voltages and control signals shown in Table 3 to the circuit module 5 and the memory array 2 during the period from time T ＷＬ From time T ＳＷ During the period up to , the voltages shown in Table 3 are generated at the sense node SN.

[0082] Next, the control module 6 outputs a control signal SW (S23). As shown in Table 4, when the sub-block BK to be read belongs to the previous block unit BU1 (when the previous stage read operation condition is selected), the control module 6 outputs a control signal SW that is "0 (L)". When the sub-block BK to be read belongs to the next block unit BU2 (when the next stage read operation condition is selected), the control module 6 outputs a control signal SW that is "1 (H)". More specifically, the control module 6 outputs a control signal SW that is "1 (H)" for a time T ＳＷ From time T ＰＡＳＳ The control module 6 applies the voltages and control signals shown in Table 4 to the circuit module 5 and the memory array 2 during the period from time T ＳＷ From time T ＰＡＳＳDuring the period up to , the voltages shown in Table 4 are generated at the sense node SN.

[0083] Next, the control module 6 enables the charging function of the sense amplifier 3 (S24). Specifically, the control module 6 outputs a control signal PASS[1(H)]. More specifically, the control module 6 ＰＡＳＳ From time T ＰＲＥＢ The control module 6 applies the voltages and control signals shown in Table 5 to the circuit module 5 and the memory array 2 during the period from time T ＰＡＳＳ From time T ＰＲＥＢ During the period up to the time when the voltage V ＢＬ rises to a voltage corresponding to the stored state of the data in the selected memory cell 21. For example, when the data stored in the memory cell 21 is "1", the voltage V ＢＬ For example, when the data stored in the memory cell 21 is "0", the voltage V of the bit line BL rises to 0.4V (first condition, third condition). ＢＬ rises to 0.5 V (second and fourth conditions).

[0084] Here, the voltage V when the first condition and the second condition are met is ＢＬ and the voltage V when the third and fourth conditions are met. ＢＬ 10(a) and 10(b) show the distribution of the voltage V ＢＬ 10(a) shows the distribution of the voltage V ＢＬ 10(b) shows the distribution of the voltage V ＢＬ10(a), under the first and second conditions, the switching element 20 is in a connected state, and a predetermined voltage is generated at all connection points between the memory cells 21 and the bit lines BL. On the other hand, as shown in FIG. 10(b), under the third and fourth conditions, the switching element 20 is in a disconnected state, and a predetermined voltage is generated at the connection points between the memory cells 21 belonging to the preceding block unit BU1 and the bit lines BL. In contrast, the voltage at the connection points between the memory cells 21 belonging to the succeeding block unit BU2 and the bit lines BL is 0V. Under the third and fourth conditions, the succeeding bit line BL2 to which the succeeding block unit BU2 is connected is not charged. Therefore, the power required for the charging operation can be reduced.

[0085] As shown in FIG. 10(c), the voltage V ＢＬ The time change (G10a) of the voltage V ＢＬ Specifically, the time required for the voltage to converge to a predetermined value differs. The convergence time T Ｆ is the convergence time T when the first and second conditions are met. Ｂ The convergence time T Ｆ , T Ｂ is the parasitic capacitance C included in the bit line BL ＢＬＦ , C ＢＬＮ The parasitic capacitance C included in the bit line BL is affected by the magnitude of ＢＬＦ , C ＢＬＮ The larger the convergence time T Ｆ , T Ｂ The parasitic capacitance C included in the bit line BL becomes longer. ＢＬＦ , C ＢＬＮ The smaller the convergence time T Ｆ , T Ｂ When the first and second conditions are met, the bit lines BL connected to the sense amplifier 3 include the preceding bit line BL1 and the succeeding bit line BL2. Therefore, the parasitic capacitance C ＢＬ is the parasitic capacitance C of the previous bit line BL1 ＢＬＮ and the parasitic capacitance C of the subsequent bit line BL2 ＢＬＦ Includes:

[0086] On the other hand, under the third and fourth conditions, the only bit line BL connected to the sense amplifier 3 is the preceding bit line BL1. Therefore, under the third and fourth conditions, the parasitic capacitance C ＢＬ is the parasitic capacitance C of the previous bit line BL1 ＢＬＮ Therefore, the parasitic capacitance C ＢＬ is the parasitic capacitance C when the first and second conditions are met. ＢＬ As a result, the convergence time T Ｆ is the convergence time T when the first and second conditions are met. Ｂ will be shorter than

[0087] Therefore, the control module 6 may set the timing for enabling the amplification function of the sense amplifier 3 next when the third and fourth conditions are met to be earlier than the timing for enabling the amplification function of the sense amplifier 3 when the first and second conditions are met. Specifically, when the third and fourth conditions are met, the time T ＰＡＳＳ The time T at which the control signal PREB is output ＰＲＥＢ The time T ＰＡＳＳ The time T at which the control signal PREB is output ＰＲＥＢ The time until this is the "charging time" mentioned above.

[0088] Next, the control module 6 enables the amplification function of the sense amplifier 3 (S26). Specifically, the control module 6 outputs a control signal PREB[1(H)]. More specifically, the control module 6 enables the amplification function of the sense amplifier 3 (S26). ＰＲＥＢ From time T ＳＮＳ The control module 6 applies the voltages and control signals shown in Table 6 to the circuit module 5 and the memory array 2 during the period from time T ＰＲＥＢ From time T ＳＮＳ During the period up to , the voltages shown in Table 6 are generated at the sense node SN. As a result of outputting the control signal PREB [1(H)], the voltage V ＳＮis the voltage V of the bit line BL ＢＬ For example, the voltage V of the bit line BL ＢＬ When is "0.4", the voltage V of the sense node SN ＳＮ For example, the voltage V of the bit line BL changes from 2 V to 0.4 V. ＢＬ When is "0.5", the voltage V of the sense node SN ＳＮ maintains 2V.

[0089] That is, the voltage V ＢＬ The difference ΔV ＢＬ (0.1V in this embodiment) is the difference ΔV between the two voltages VSN at the sense node SN due to the amplification function of the sense amplifier 3. ＳＮ (1.6V in this embodiment). As a result, the sense margin becomes larger. However, the sense amplifier 3 is amplified to ΔV ＢＬ <ΔV ＳＮ It is sufficient that the amplifier is configured to have an amplification function that satisfies the relationship.

[0090] Next, the control module 6 outputs a data signal D ＯＵＴ (S27). Specifically, the control module 6 outputs the control signal SNS[1(H)]. More specifically, the control module 6 outputs the control signal SNS[1(H)] at the time T ＳＮＳ At a later time period, the control module 6 applies the voltages and control signals shown in Table 7 to the circuit module 5 and the memory array 2. ＳＮＳ In the later period, the inverter 32 generates the voltage shown in Table 7 at the sense node SN. When the voltage VSN at the sense node SN is "0.4" as a result of outputting the control signal SNS[1(H)], the inverter 32 generates the voltage shown in Table 7 at the data signal D ＯＵＴ [1(H)] is output. The voltage V of the sense node SN ＳＮ is "2V", the inverter 32 outputs the data signal D ＯＵＴ Output [0(L)].

[0091] <Write Operation> Next, the operation of the semiconductor memory system 1 will be described using write as an example. Figure 11 is a flowchart showing the main steps of the write operation.

[0092] 12, 13, 14, and 15 are timing charts showing changes in voltages and control signals in the memory array 2 and the sense amplifier 3 during a data write operation. ＤＤＢＬ 12(b), 13(b), 14(b) and 15(b) show the time variation of the control signal V ＷＬ 12(c), 13(c), 14(c), and 15(c) show the time changes of the control signal SW. FIGS. 12(d), 13(d), 14(d), and 15(d) show the time changes of the control signal PASS. FIGS. 12(e), 13(e), 14(e), and 15(e) show the time changes of the control signal PREB. FIGS. 12(f), 13(f), 14(f), and 15(f) show the time changes of the voltage V ＢＬ 12(g), 13(g), 14(g), and 15(g) show the time variation of the voltage V ＳＮ 12(h), 13(h), 14(h), and 15(h) show the time changes of the control signal SNS. 12(i), 13(i), 14(i), and 15(i) show the time changes of the data signal D ＯＵＴ 12(j), 13(j), 14(j), and 15(j) show the time changes of the control signal PGM. 12(k), 13(k), 14(k), and 15(k) show the time changes of the data signal D ｉｎ The time change of is shown.

[0093] First, the control module 6 executes a write preparation operation (S3). Similar to the read preparation operation (S1), the write preparation operation (S3) includes steps S31 to S33a and S33b. Details of these steps S31 to S33a and S33b can be easily understood by substituting "write" for "read" in the description of the read preparation operation (S1).

[0094] After the write preparation operation (S3) is completed, the control module 6 executes the write operation (S4).

[0095] Here, the four conditions shown in Table 8 are assumed for the write operation (S4).

[0096] First, the control module 6 applies a voltage V ＤＤＢＬ More specifically, the control module 6 starts the operation of applying (2V) (S41) for the time T ０ From time T ＰＧＭ１ During the period from 0 to 1000 s, the voltages and control signals shown in Table 9 are applied to the circuit module 5 and the memory array 2.

[0097] Next, the control module 6 outputs the control signal SN and the control signal PGM (S42). This operation switches the sub-circuit 3S to a state in which it can perform the write operation. Specifically, the control signal SN (0V ("0")) is output to the inverter 32 used for reading, and the control signal PGM ("1") is output to the inverter 33 used for writing. The control module 6 outputs the control signal SN (0V ("0")) to the inverter 32 used for reading, and the control signal PGM ("1") to the inverter 33 used for writing. The control module 6 outputs the control signal SN and the control signal PGM ("1") to the inverter 33 used for writing, for a time T ＰＧＭ１ From time T ＰＡＳＳ１ During the period from 0 to 1000 s, the voltages and control signals shown in Table 10 are applied to the circuit module 5 and the memory array 2.

[0098] Next, the control module 6 outputs a control signal SW (S43). If the sub-block BK to be written belongs to the subsequent block unit BU2 (if the subsequent write operation condition is selected, the fifth and sixth conditions in Table 8), the control module 6 outputs a control signal SW that is "1". If the sub-block BK to be written belongs to the previous block unit BU1 (if the previous write operation condition is selected, the seventh and eighth conditions in Table 8), the control module 6 outputs a control signal SW that is "0". Furthermore, the control module 6 outputs a control signal PASS (3V ("1")) in parallel with the operation of outputting the control signal SW (S43). This operation enables the charging function of the sense amplifier 3. More specifically, the control module 6 outputs a control signal PASS (3V ("1")) in parallel with the operation of outputting the control signal SW for a time T ＰＡＳＳ１ From time T ＷＬ１ During the period from 0 to 1000 s, the voltages and control signals shown in Table 11 are applied to the circuit module 5 and the memory array 2.

[0099] As a result of outputting the control signal PASS (3V ("1")), the voltage V ＢＬ is the time T ＰＡＳＳ１ From time T ＢＬ For example, if the information to be written in the memory cell 21 is "1", the voltage V of the bit line BL is ＢＬ is determined to be 0 V (fifth and seventh conditions). For example, when the data to be written to the memory cell 21 is "0", the voltage V ＢＬ rises to 2 V (sixth and eighth conditions).

[0100] As in the read operation, the convergence time T Ｆ is the convergence time T when the fifth and sixth conditions are met. Ｂ For example, the convergence time TB (see FIG. 15(e)) when writing "0" to the memory cell 21 belonging to the preceding block unit BU2 is shorter than the convergence time TF (see FIG. 13(e)) when writing "0" to the memory cell 21 belonging to the succeeding block unit BU2.

[0101] Next, the control module 6 outputs a control signal V ＷＬ Then, the operation of applying (10V) to the control signal V ＷＬ rises to 10 V over time. More specifically, the control module 6 ＷＬ１ From time T ＷＬ２ During the period up to , the voltages and control signals shown in Table 12 are applied to the circuit module 5 and the memory array 2. The control signal V ＷＬ The action of applying the voltage V ＢＬ is determined (time TBL).

[0102] A control signal V ＷＬ As a result of the operation of applying (S44), predetermined information is written in the memory cell 21.

[0103] Next, the control module 6 outputs a control signal V ＷＬ In more detail, the control module 6 starts the operation of applying (0V) to the power supply 14 (S45) for the time T ＷＬ２ From time T ＰＡＳＳ２ During the period up to , the voltages and control signals shown in Table 13 are applied to the circuit module 5 and the memory array 2. ＷＬ (0V) is the control signal V ＷＬ Based on the time TWL1 when the power supply voltage (10V) is output, ＷＬ１ The output may be made after a predetermined time has elapsed.

[0104] Next, the control module 6 generates a control signal V ＰＡＳＳ In more detail, the control module 6 starts the operation of applying 0V ("0") to the voltage Vcc (S46). ＰＡＳＳ２ From time T ＰＧＭ２ During the period up to , the voltages and control signals shown in Table 14 are applied to the circuit module 5 and the memory array 2. ＰＡＳＳ (0V("0")) is the control signal V ＰＡＳＳ Time T when (3V("1")) is output ＰＡＳＳ１ Based on this, time T ＰＡＳＳ１The signal is output after a predetermined time has elapsed.

[0105] Then, the control module 6 starts the operation of giving the control signal PGM("0"s) to the inverter 33 (S47). More specifically, the control module 6 starts the operation of giving the control signal PGM("0"s) to the inverter 33 (S47). ＰＡＳＳ２ From time T ＰＧＭ２ During the period up to , the voltages and control signals shown in Table 15 are applied to the circuit module 5 and the memory array 2 .

[0106] <Effects> The semiconductor memory system 1 comprises a memory array 2 including a plurality of memory cells 21, a sense amplifier 3 that reads data stored in the memory cells 21, and a control module 6 that provides control signals to the memory array 2 and the sense amplifier 3.

[0107] The memory array 2 is a memory array 2 from which data is read via a sense amplifier 3, and includes a preceding bit line BL1 connected to the sense amplifier 3, a preceding block unit BU1 including at least one memory cell 21 connected to the preceding bit line BL1, a switching element 20 connected to an end of the preceding bit line BL1 opposite to the end connected to the sense amplifier 3, a following bit line BL2 connected to the switching element 20, and a following block unit BU2 including at least one memory cell 21 connected to the following bit line BL2. The switching element 20 alternately switches between a first circuit configuration in which the preceding block unit BU1 and the following block unit BU2 are connected to the sense amplifier 3, and a second circuit configuration in which only the preceding block unit BU1 is connected to the sense amplifier 3.

[0108] The switching element 20 of the memory array 2 alternately switches between a first circuit configuration in which the preceding block unit BU1 and the succeeding block unit BU2 are connected to the sense amplifier 3, and a second circuit configuration in which only the preceding block unit BU1 is connected to the sense amplifier 3. The parasitic capacitance and parasitic resistance in the second circuit configuration are smaller than those in the first circuit configuration. As a result, when reading data from a memory cell 21 belonging to the preceding block unit BU1, the charging time of the bit line BL can be shortened compared to when reading data from a memory cell 21 belonging to the succeeding block unit BU2. The shorter charging time contributes to faster read operations. Furthermore, when reading data from a memory cell 21 belonging to the preceding block unit BU1, the energy required to charge the bit line is reduced compared to when reading data from a memory cell 21 belonging to the succeeding block unit BU2. The reduced energy required for charging contributes to power savings in read operations.

[0109] The number of memory cells 21 included in the preceding block unit BU1 may be equal to the number of memory cells 21 included in the succeeding block unit BU2. In the memory array 2, the length of the preceding bit line BL1 may be equal to the length of the succeeding bit line BL2. This configuration allows for a circuit configuration that emphasizes reducing the energy required for charging.

[0110] The number of memory cells 21 included in the preceding block unit BU1 may be different from the number of memory cells 21 included in the succeeding block unit BU2. In the memory array 2, the length of the preceding bit line BL1 may be different from the length of the succeeding bit line BL2. This configuration allows for a circuit configuration that prioritizes shortening the time required for charging.

[0111] The control module 6 selects the first circuit configuration when the memory cell 21 selected as the read target belongs to the subsequent block unit BU2, and selects the second circuit configuration when the memory cell 21 selected as the read target belongs to the previous block unit BU1. With this configuration, it is possible to select either the first circuit configuration or the second circuit configuration depending on the position of the memory cell 21 to be read.

[0112] When the memory cell 21 selected as the read target belongs to the subsequent block unit BU2, the control module 6 starts charging the previous bit line BL1 and the subsequent bit line BL2, and performs an operation of reading data from the memory cell 21 after a first charging time has elapsed since the time when charging started, and when the memory cell 21 selected as the read target belongs to the previous block unit BU1, the control module 6 starts charging the previous bit line BL1, and performs an operation of reading data from the memory cell 21 after a second charging time has elapsed since the time when charging started, the second charging time being shorter than the first charging time. With this configuration, when the memory cell 21 selected as the read target belongs to the previous block unit BU1, it is possible to further shorten the time required for reading.

[0113] Second Embodiment A semiconductor memory system 1A according to a second embodiment will be described. The semiconductor memory system 1A according to the second embodiment has a configuration that can further reduce the power required for read and write operations compared to the semiconductor memory system 1 according to the first embodiment.

[0114] The semiconductor memory system 1A of the second embodiment differs from the semiconductor memory system 1 of the first embodiment in the voltage used during the charging operation. As shown in FIG. 19A, the semiconductor memory system 1A of the second embodiment has a charging period (time T ＰＡＳＳ ~Time T ＰＲＥＢ ) at voltage V ＤＤＱ is applied to the sense amplifier 3. This voltage V ＤＤＱ On the other hand, in the semiconductor memory system 1 of the first embodiment, the period during which the charging operation is performed (time T ＰＡＳＳ~Time T ＰＲＥＢ ) at voltage V ＤＤＲ is applied to the sense amplifier 3. This voltage V ＤＤＲ is, for example, 2.0 V. That is, in the semiconductor memory system 1A of the second embodiment, the charging operation is performed during a period (time T ＰＡＳＳ ~Time T ＰＲＥＢ ) is applied to the sense amplifier 3 is lower than that in the semiconductor memory system 1 of the first embodiment. As a result, the power required for the charging operation is reduced, and the power required for the read operation and the write operation can be further reduced.

[0115] The semiconductor memory system 1A of the second embodiment will be described in detail with reference to Figures 16 to 24. In this description, explanations of configurations and operations that overlap with those of the semiconductor memory system 1 of the first embodiment will be omitted as appropriate. For example, since the memory array 2 of the second embodiment is the same as the memory array 2 of the first embodiment, explanations of the memory array 2 of the second embodiment will be omitted.

[0116] 16, in the semiconductor memory system 1A, a branch wiring 14a1 is provided on the wiring 14a that connects the power supply terminal 13a to the control module 6. One end of the branch wiring 14a1 is connected to the wiring 14a. The other end of the branch wiring 14a1 is connected to the circuit module 5A. The branch wiring 14a1 allows the voltage received by the power supply terminal 13a to be supplied to the circuit module 5A.

[0117] The circuit module 5A includes a switching circuit 4 in addition to the sense amplifier 3. The switching circuit 4 supplies a voltage V ＤＤＲ and voltage V ＤＤＱ Either one of the above is output to the sense amplifier 3.

[0118] 17 is a circuit diagram showing the switching circuit 4. The switching circuit 4 selects and connects one of the power supplies 103 and 102 to the sense amplifier 3. The power supplies 103 and 102 supply a voltage V ＤＤＢＬThe switching circuit 4 switches one of the power supplies 103 and 102 connected to the sense amplifier 3 to the other of the power supplies 103 and 102.

[0119] The switching circuit 4 includes a power supply line PL1, a power supply line PL2, a linear regulator 41, and a switching circuit 42. The power supply line PL1 is electrically connected to the source of the switching element 312 (see FIG. 3 ). The power supply line PL2 supplies power to elements of the circuit module 5A other than the switching element 312. The linear regulator 41 is electrically connected to the power supply 102 via a power supply terminal 11a and converts a voltage to a predetermined voltage for output. The switching circuit 42 is electrically connected to the power supply 103 via a power supply terminal 13a and switches the connection between the output of the power supply 103, the output of the linear regulator 41, and the power supply line PL1.

[0120] The linear regulator 41 receives the voltage V ＤＤ The circuit includes an input terminal 411 to which an error signal V is supplied, an error amplifier 412, a control transistor 413, and resistor elements R1 and R2. The control transistor 413 is a P-channel MOSFET. The source of the control transistor 413 is connected to the input terminal 411. The gate of the control transistor 413 is connected to the output of the error amplifier 412. The drain of the control transistor 413 is the output terminal of the linear regulator 41. The resistor elements R1 and R2 are connected in series between the drain of the control transistor 413 and the ground. The resistor elements R1 and R2 generate a voltage obtained by dividing the output voltage of the linear regulator 41. The error amplifier 412 is a differential amplifier. A preset reference voltage V is supplied to the inverting input of the error amplifier 412. ｒｅｆ The non-inverting input of the error amplifier 412 is connected to a node 41N between the two resistor elements R1 and R2. The error amplifier 412 receives the voltage V ＤＤＲ is the reference voltage V ｒｅｆThe on-resistance of the control transistor 413 is controlled so that the voltage becomes a predetermined voltage (for example, 2.0 V) set by the linear regulator 41. The output of the linear regulator 41 is electrically connected to the power supply line PL2. The output of the linear regulator 41 is electrically connected to the power supply line PL1 via the switching circuit 42.

[0121] The switching circuit 42 receives the voltage V ＤＤＱ The linear regulator 41 includes an input terminal 421 to which a voltage is supplied, and switching elements 422 and 423 which are N-channel MOSFETs. The switching element 422 has a function of turning on or off the connection between the input terminal 421 and the power feed line PL1 in response to a control signal φ2. The drain of the switching element 422 is electrically connected to the input terminal 421. The source of the switching element 422 is electrically connected to the power feed line PL1. The control signal φ2 is applied to the gate of the switching element 422. The switching element 423 has a function of turning on or off the connection between the output of the linear regulator 41 and the power feed line PL1 in response to a control signal φ1. The drain of the switching element 423 is electrically connected to the output of the linear regulator 41. As a result, the source of the switching element 423 is electrically connected to the power feed line PL1, and therefore the control signal φ1 is applied to the gate of the switching element 423.

[0122] 18 is a functional block diagram of a control module 6A included in the semiconductor memory system 1A of the second embodiment. The difference from the control module 6 of the first embodiment is that a controller 64 generates control signals φ1 and φ2 for the switching circuit 4 and outputs the control signals φ1 and φ2 to the switching circuit 4.

[0123] <Read Operation> The read operation of the semiconductor memory system 1A of the second embodiment will be described with reference to the flowchart of Fig. 19 and the timing charts of Fig. 20, Fig. 21, Fig. 22, Fig. 23, and Fig. 24. The read operation of the semiconductor memory system 1A of the second embodiment differs from that of the first embodiment in that it includes a step (S25) of switching the voltage supplied from the switching circuit 4 to the sense amplifier 3.

[0124] As shown in FIG. 19, in the second embodiment, in step (S25), the voltage V ＤＤＱ More specifically, after the step of outputting the control signal PASS (S24) and before the step of outputting the control signal PREB (S25), the voltage V ＤＤＱ voltage V ＤＤＲ The step of switching to (S25) is included.

[0125] First, the control module 6A executes a read preparation operation (S1). The read preparation operation is the same as that in the first embodiment, so a detailed description will be omitted. After the read preparation operation (S1) is completed, the control module 6A executes a read operation (S2A).

[0126] The control module 6A supplies a voltage V ＤＤＢＬ An operation (S21) of applying (1.2 V) is started at time T ０ From time T ＷＬ Table 16 shows the voltages and control signals output to the circuit module 5A and the memory array 2 during the period from time T ０ From time T ＷＬ Table 16 shows the voltage generated at the sense node SN during the period from Next, the control module 6A starts the operation of applying the control signal VWL to the word line WL (S22). ＷＬ From time T ＳＷ Table 17 shows the voltages and control signals output to the circuit module 5A and the memory array 2 during the period from time T ＷＬ From time T ＳＷ Table 17 shows the voltage generated at the sense node SN during the period from

[0127] Next, the control module 6A outputs the control signal SW (S23). ＳＷ From time T ＰＡＳＳ Table 18 shows the voltages and control signals output to the circuit module 5A and the memory array 2 during the period from time T ＳＷ From time T ＰＡＳＳTable 18 shows the voltage generated at the sense node SN during the period from

[0128] Next, the control module 6A outputs the control signal PASS (S24). ＰＡＳＳ From time T ＶＤＤ Table 19 shows the voltages and control signals output to the circuit module 5A and the memory array 2 during the period from time T ＰＡＳＳ From time T ＶＤＤ Table 19 shows the voltage generated at the sense node SN during the period from

[0129] Next, the control module 6A controls the voltage V ＤＤＱ voltage V ＤＤＲ (S25). Time T ＶＤＤ From time T ＰＲＥＢ Table 20 shows the voltages and control signals output to the circuit module 5A and the memory array 2 during the period from time T ＶＤＤ From time T ＰＲＥＢ Table 20 shows the voltage generated at the sense node SN during the period from

[0130] Voltage V ＤＤＱ voltage V ＤＤＲ The operation of switching to is realized by a control signal φ1 (see FIG. 24(a)) and a control signal φ2 (see FIG. 24(b)) shown in FIG. 24. According to these control signals φ1 and φ2, the voltage VDDBL applied to the switching element 312 is as shown in FIG. 24(c).

[0131] Next, the control module 6A enables the amplification function of the sense amplifier 3 (S26). Specifically, the control module 6A outputs the control signal PREB(1). At time T ＰＲＥＢ From time T ＳＮＳ Table 21 shows the voltages and control signals output to the circuit module 5 and the memory array 2 during the period from time T ＰＲＥＢ From time T ＳＮＳ Table 21 shows the voltage generated at the sense node SN during the period from

[0132] Next, the control module 6A outputs a data signal D ＯＵＴ (S27). Specifically, the control module 6A outputs the control signal SNS(1). ＳＮＳ In the later period, the voltages and control signals output to the circuit module 5A and the memory array 2 are shown in Table 22. ＳＮＳ At a later time period, the voltage appearing at the sense node SN is shown in Table 22.

[0133] <Write Operation> The semiconductor memory system 1A of the second embodiment can also perform a write operation in the same manner as the semiconductor memory system 1 of the first embodiment. The write operation of the semiconductor memory system 1A of the second embodiment can also be performed using the voltage V ＢＬ This can provide the effect of shortening the convergence time.

[0134] <Operation and Effect> According to the circuit module 5A, when data is read from a memory cell 21 selected from among the plurality of memory cells 21 electrically connected to the bit line BL, the amplifier 31 amplifies the voltage V ＤＤＱ The bit line BL is first charged via the read / write line RL based on the power supply from the power supply 103 having a voltage V ＤＤ Based on the power supply from the power supply 102 having a voltage V ＢＬ is amplified at the sense node SN on the read / write line RL. Furthermore, the inverter 32 amplifies the voltage V ＳＮ The data stored in the selected memory cell 21 is determined based on the data signal D ＯＵＴ is output as

[0135] This reduces the power consumption required to charge the bit line BL until the data storage state of the memory cell 21 can be determined. ＢＬThe voltage V of the sense node SN can be amplified by a sufficient driving voltage. As a result, the data read operation can be stabilized. ＳＮ into two voltages with a large voltage difference according to the data storage state, the determination operation using the threshold value by the inverter 32 based on the amplified voltage is stabilized. As a result, the reliability of the data read operation from the memory cell 21 can be improved while the power consumption in the read operation can be efficiently reduced.

[0136] Parasitic capacitance C of the read / write line RL ＳＮ is the parasitic capacitance C of the bit line BL ＢＬ In this case, the power consumption when charging the bit line BL in the circuit module 5A is set to the voltage V ＤＤＱ As a result, the power consumption during the data read operation of the circuit module 5A can be reduced more efficiently.

[0137] The amplifier 31 includes a switching element 311 and a switching element 312. The inverter 32 detects the voltage V of the sense node SN at the timing after the switching element 311 is turned off. ＳＮ According to this configuration, the amplifier 31 operates to sense the voltage V of the bit line BL when the bit line BL is charged. ＢＬ The inverter 32 can be operated to charge the sense node SN until the voltage V ＳＮ As a result, the bit line BL can be charged to a state where the data storage state of the memory cell 21 can be determined. As a result, the voltage of the bit line BL is amplified and the voltage V ＳＮ Based on this, the data in the memory cell 21 can be determined stably.

[0138] The switching element 311 is turned on / off in response to the voltage of the bit line BL, which changes in response to the data storage state of the memory cell 21 connected to the bit line BL when the amplifier 31 charges the bit line BL. During a data read operation, a voltage equal to the voltage at which the bit line BL is charged plus a threshold voltage is applied to the gate of the switching element 311. This configuration allows the bit line BL to be charged to a state where the data storage state of the memory cell 21 can be determined. Furthermore, the voltage of the bit line BL can be amplified at the sense node SN on the read / write line RL. As a result, the data read operation can be stabilized.

[0139] The circuit module 5A further includes a switching circuit 4 that switches the connection between the power supply line PL1 connected to the amplifier unit 31 and the power supply 103 or 102. In this case, the power supply that supplies power to the amplifier unit 31 can be switched between the power supply 103 and the power supply 102 using the switching circuit 4. As a result, the power consumption during the data read operation of the circuit module 5A can be reduced with a simple circuit configuration.

[0140] The switching circuit 4 is connected to a power supply 102 and supplies a voltage V ＤＤ at a predetermined voltage V ＤＤＲ and outputs the converted voltage V of the power supply 102, and switching elements 422 and 423 that switch the connection between the output of the power supply 103, the output of the linear regulator 41, and the power supply line PL1. With this configuration, the power supply that supplies power to the amplifier 31 can be switched between the power supply 103 and the power supply 102 using the switching circuit 4. Furthermore, the voltage V of the power supply 102 ＤＤ at a predetermined voltage V ＤＤＲ As a result, it is possible to reduce the power consumption in the data read operation of the circuit module 5A with a simple circuit configuration, and it is also possible to stabilize the data read operation.

[0141] [Modifications] The present invention is not limited to the above-described embodiment, and the configuration of the above-described embodiment may be modified in various ways.

[0142] [First Modification] In the first embodiment, a NOR flash type memory cell 21 is exemplified as a specific example of the memory cell 21. As shown in FIG. 25 , a NAND flash type memory cell 21B may be employed. The NAND flash memory cell 21B has a string 21S in which a plurality of transistors 21b, 21c, and 21d are connected in series to one another by a local bit line LBL. Each of the plurality of strings 21S is connected to a global bit line GBL. The string 21S includes a transistor 21b having a floating gate for storing data and a transistor 21c provided at a connection portion with the global bit line GBL. The end of the string 21S is connected to a reference voltage point via the transistor 21d. Even with this configuration, the same effects as those of the semiconductor memory system 1 of the first embodiment can be obtained.

[0143] [Second Modification] As shown in FIG. 26 , the memory cell 21C may be a dynamic random access memory (DRAM). The memory cell 21C, which is a DRAM, includes a transistor 21e and a capacitor 21f. The gate of the transistor 21e is connected to a word line WL. The source of the transistor 21e is connected to a bit line BL. The drain of the transistor 21e is connected to the capacitor 21f. With this circuit, data is stored as a state (1) in which charge is stored in the capacitor 21f and a state (0) in which no charge is stored in the capacitor 21f. Even with this configuration, the same effects as those of the semiconductor memory system 1 of the first embodiment can be obtained.

[0144] 27, the memory cell 21D may be a static random access memory (SRAM). The memory cell 21D, which is an SRAM, includes a flip-flop circuit 21g and switching elements 21h and 21i. The gates of the switching elements 21h and 21i are connected to the word line WL. The sources of the switching elements 21h and 21i are connected to the bit lines BL and BLB. The drains of the switching elements 21h and 21i are connected to the flip-flop circuit 21g. Even with this configuration, the same effects as those of the semiconductor memory system 1 of the first embodiment can be obtained.

[0145] [Other Modifications] In the first and second embodiments, only one switching element 20 is provided for one bit line BL. The number of switching elements 20 provided for one bit line BL is not limited to one. The number of switching elements 20 provided for one bit line BL may be two or more.

[0146] The memory cell 21 is not limited to storing binary (1-bit) data, but may store multi-level (2-bit or more) data.

[0147] Regarding the steady-state current, the memory cell 21 has a current I ｃｅｌｌ１ The memory cell 21 is configured so that the current I is larger than the current Icell0 when data is "0". ｃｅｌｌ１ is the current I ｃｅｌｌ０ It may be configured to be smaller.

[0148] Instead of the power supply 103 shared with the control module 6, the circuit module 5 of the semiconductor memory system 1 may be separately connected to a power supply having a voltage lower than the voltage VDD and higher than the voltage at which the data on the bit line BL can be determined (0.5 V in this embodiment).

[0149] In the semiconductor memory system 1A of the second embodiment, the voltage V ＤＤＢＬ Voltage V ＤＤＱ to voltage V ＤＤＲThe switching to the current state may be performed at a timing before the charging of the bit line BL is completed.

[0150] The circuit modules 5 and 5A may also perform the above-described data read operation during a data write operation. The circuit modules 5 and 5A may also perform an operation similar to the above-described data read operation as a verify read operation for verifying the write operation after the completion of the data write operation to the memory cells 21. In this case, it is possible to further reduce power consumption in the circuit modules 5 and 5A.

[0151] [First Example] In the first example, the charging time (time T ＰＡＳＳ ~Time T ＢＬ ) was confirmed to have the effect of shortening the charging time. The probability that the memory cell 21 selected as the read target, among the multiple memory cells 21 connected to a certain bit line BL, belongs to the preceding block unit BU1 is set to "x". x is a value between 0 and 1. Then, the probability that the memory cell 21 selected as the read target belongs to the succeeding block unit BU2 is "1-x". With this setting, the average charging time can be defined by equation (1). T ＢＬ＿ＡＶＧ : Average charging time T ＢＬ＿ｎｅａｒ : charging time when the selected memory cell 21 belongs to the preceding block unit BU1 ＢＬ＿ｆａｒ : Charging time when the selected memory cell 21 belongs to the subsequent block unit BU2

[0152] The charging time is determined by the parasitic capacitance C ＢＬ and parasitic resistance R ＢＬ (see FIG. 4). For example, when the selected memory cell 21 belongs to the subsequent block unit BU2, the charging time (T ＢＬ＿ｆａｒ ) is assumed to be "1", the charging time (T ＢＬ＿ｎｅａｒ ) is "x ２ "

[0153] The above charging time (T ＢＬ＿ｆａｒ = 1, T ＢＬ＿ｎｅａｒ = x ２) into equation (1), we obtain equation (2).

[0154] According to equation (2), the average charging time (T ＢＬ＿ＡＶＧ ) is the minimum value (T ＢＬ＿ＡＶＧ = 1 / √3 = 0.62). This is also clear from the graph G28a shown in FIG. 28(a). The graph G28a in FIG. 28(a) is a plot of the formula (2). The graph G28b in FIG. 28(a) is a calculation result obtained using a circuit simulator.

[0155] The probability that the selected memory cell 21 belongs to the preceding block unit BU1 is "x" when, for example, N memory cells 21 are connected to one bit line BL and the number of memory cells 21 belonging to the preceding block unit BU1 is k, and k / N=x holds. If it is assumed that the lengths of the bit lines BL connecting adjacent memory cells 21 are the same, the number of memory cells 21 belonging to the preceding block unit BU1 corresponds to the length of the preceding bit line BL1. According to this assumption, the probability that the selected memory cell 21 belongs to the preceding block unit BU1 is "x" when, for example, the length of one bit line BL is L ＢＬ and the length of the preceding bit line BL1 is L ＢＬ１ When it is assumed that ＢＬ１ / L ＢＬ = x.

[0156] In this case, when the switching element 20 is placed at a position where the ratio of the length of the preceding bit line BL1 to the length of the succeeding bit line BL2 is approximately 4:6, the average charging time (T ＢＬ＿ＡＶＧ ) was found to be approximately 0.62. ＢＬ＿ＡＶＧ ) can be reduced by approximately 40%.

[0157] Second Example In the second example, the effect of reducing the energy required for charging was confirmed. The energy required for charging may be interpreted as the power required for charging. As in the first example, the probability that the selected memory cell 21 belongs to the preceding block unit BU1 is set to "x," and the probability that the selected memory cell 21 belongs to the succeeding block unit BU2 is set to "1-x." With this setting, the energy required for charging can be defined by equation (3). E ＢＬ＿ＡＶＧ : Average energy required for charging E ＢＬ＿ｎｅａｒ : Energy required for charging when the selected memory cell 21 belongs to the preceding block unit BU1 ＢＬ＿ｆａｒ : Energy required for charging when the selected memory cell 21 belongs to the subsequent block unit BU2

[0158] The energy required for charging is defined by equation (4).

[0159] For example, the energy required for charging when the memory cell 21 belongs to the subsequent block unit BU2 (E ＢＬ＿ｆａｒ ) is assumed to be "1", the energy (E ＢＬ＿ｎｅａｒ ) is "x".

[0160] The energy required for charging (E ＢＬ＿ｆａｒ = 1, E ＢＬ＿ｎｅａｒ = x) into equation (4), we obtain equation (5).

[0161] According to equation (5), the average energy required for charging (E ＢＬ＿ＡＶＧ ) reaches the minimum value (E ＢＬ＿ＡＶＧ It can be seen that the equation (0.5) = 0.75 is obtained. This is also clear from the graph G28c shown in FIG. 28(b). The graph G28c in FIG. 28(b) is a plot of the equation (5). The graph G28d in FIG. 28(b) is a calculation result obtained using a circuit simulator.

[0162] When the switching element 20 is placed at a position where the length of the preceding bit line BL1 and the length of the succeeding bit line BL2 are equal, the average energy required for charging (E ＢＬ＿ＡＶＧ In other words, the average energy required for charging (E ＢＬ＿ＡＶＧ ) can be reduced by approximately 25%.

[0163] Third Example In the third example, the effects of the charging time and the energy required for charging on the write operation were confirmed.

[0164] In the third embodiment, an operation is set in which data is written sequentially from the memory cell 21 closest to the sense amplifier 3 to the memory cell 21 farthest from the sense amplifier 3. Furthermore, the switching element 20 is set to be provided in the center of the bit line BL. N memory cells 21 are connected to the bit line BL, and the memory cell 21 closest to the sense amplifier 3 is set to n=1, and the memory cell 21 farthest from the sense amplifier 3 is set to n=N. Then, the write operation from the first memory cell 21 closest to the sense amplifier 3 to the N / 2th memory cell 21 is performed with the switching element 20 disconnected. Then, the write operation from the N / 2+1th memory cell 21 to the Nth memory cell 21 is performed with the switching element 20 connected.

[0165] 29 is a graph showing the data write rate and expected value. The data write rate is the ratio (n / N) of the number of memory cells 21 (n) to the number of memory cells 21 to which data has been written out of N memory cells 21. For example, a data write rate of 0.5 indicates that writing to N / 2 memory cells 21 out of N memory cells 21 has been completed. For example, a data write rate of 1 indicates that writing to N memory cells 21 out of N memory cells 21 has been completed. In other words, this indicates that writing to all memory cells 21 has been completed.

[0166] Now, assume that the switching elements 20 are arranged at positions where the number of memory cells 21 belonging to the preceding block unit BU1 is equal to the number of memory cells 21 belonging to the succeeding block unit BU2. In this case, a data write rate of 0 to 0.5 means writing to the memory cells 21 belonging to the preceding block unit BU1. A data write rate of 0.5 to 1 means writing to the memory cells 21 belonging to the succeeding block unit BU2.

[0167] The expected values ​​G29a and G29b indicate the charging time (G29a) and the energy required for charging (G29b) that can be expected by providing the switching element 20. In other words, the expected values ​​indicate the charging time and power required for charging that can be achieved by providing the switching element 20, assuming that the case where the switching element 20 is not provided is 1. For example, an expected value of 0.5 means that the charging time is halved and the power required for charging is also halved.

[0168] Focus on the range of data write rates from 0 to 0.5. As mentioned above, the range of data write rates from 0 to 0.5 means writing to the memory cells 21 belonging to the preceding block unit BU1. Therefore, in operation when the data write rate is in the range of 0 to 0.5, the switching element 20 is in a disconnected state. In this case, the expected value of the reduction in charging time is 25% (0.25), and the expected value of the reduction in energy required for charging is 50% (0.5). In other words, compared to when the switching element 20 is not provided, the charging time is 1 / 4 and the energy required for charging is 75%.

[0169] Focus on the range of the data write rate from 0.5 to 1. As mentioned above, the range of the data write rate from 0.5 to 1 means writing to the memory cells 21 belonging to the subsequent block unit BU2. Therefore, in the operation when the data write rate is in the range from 0.5 to 1, the switching element 20 is in the connected state. In this case, the charging time and the energy required for charging are the same (1) as when the switching element 20 is not provided. Therefore, as the write operation progresses, the average of the expected values ​​gradually increases. As a result, as the number of memory cells 21 to which data is written increases, the respective expected values ​​G29a, G29b become closer to the average values ​​(T ＢＬ＿ＡＶＧ = 0.62, E ＢＬ＿ＡＶＧ = 0.75).

[0170] 30, the effect of providing two switching elements 20A, 20B for one bit line BL was confirmed. A front-stage block unit BU1 including at least one memory cell 21 was arranged between the sense amplifier 3 and the first switching element 20A. A middle-stage block unit BU2 including at least one memory cell 21 was arranged between the first switching element 20A and the second switching element 20B. A rear-stage block unit BU3 including at least one memory cell 21 was arranged between the second switching element 20B and the end of the bit line BL.

[0171] The length of one bit line BL is set to "1." The position where the first switching element 20A is arranged is set to "x," and the position where the second switching element 20B is arranged is set to "y." These "x" and "y" are each values ​​greater than or equal to 0 and less than 1, and have the relationship "x<y."

[0172] Average charging time (T ＢＬ＿ＡＶＧ ) can be defined by equation (6). When the equation (6) is partially differentiated with respect to the variables x and y, if the first switching element 20A and the second switching element 20B are arranged at positions where (x, y)≈(0.43, 0.74), the average value of the charging time (T ＢＬ＿ＡＶＧ ) was found to be 0.51.

[0173] The average energy required for charging (E ＢＬ＿ＡＶＧ ) can be defined by equation (7). By partially differentiating equation (7) with respect to the variables x and y, it was found that when the first switching element 20A and the second switching element 20B are placed at positions where (x, y) ≈ 1 / 3, 2 / 3), respectively, the average energy required for charging becomes 2 / 3.

[0174] Therefore, it was found that the more the number of switching elements 20A, 20B provided on the bit line BL is increased, the more the average charging time can be shortened and the more the average energy required for charging can be reduced.

[0175] 1, 1A... semiconductor memory system, ... memory array, 6, 6A... control module, 20, 31, 51, 53, 311, 312... switching element, 21, 21A, 21B, MC... memory cell, BL1... previous stage bit line (first bit line), BL2... subsequent stage bit line (second bit line), BU1... previous stage block unit, BU2... subsequent stage block unit, PASS, PREB, SNS, SW, T ＰＡＳＳ , φ1, φ2...control signals.

Claims

1. A memory array in which data is read via an amplifier circuit, comprising: a first bit line connected to the amplifier circuit; a first block unit including at least one memory cell connected to the first bit line; a first switching element connected to an end of the first bit line opposite to the end connected to the amplifier circuit; a second bit line connected to the first switching element; and a second block unit including at least one memory cell connected to the second bit line, wherein the first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the amplifier circuit, and a second circuit configuration in which only the first block unit is connected to the amplifier circuit.

2. A memory array in which data is written via a circuit switching element, comprising: a first bit line connected to the circuit switching element; a first block unit including at least one memory cell connected to the first bit line; a first switching element connected to an end of the first bit line opposite to the end to which the circuit switching element is connected; a second bit line connected to the first switching element; and a second block unit including at least one memory cell connected to the second bit line, wherein the circuit switching element outputs a voltage corresponding to the data to be written to the first bit line, and the first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the circuit switching element, and a second circuit configuration in which only the first block unit is connected to the circuit switching element.

3. The memory array according to claim 1 or 2, wherein the number of said memory cells included in said first block unit is equal to the number of said memory cells included in said second block unit.

4. The memory array of claim 1 or 2, wherein the length of said first bit lines is equal to the length of said second bit lines.

5. The memory array according to claim 1 or 2, wherein the number of said memory cells included in said first block unit is different from the number of said memory cells included in said second block unit.

6. The memory array of claim 1 or 2, wherein the length of said first bit lines is different from the length of said second bit lines.

7. The memory array of claim 1 or 2, further comprising: an n+1th switching element connected to an end of the nth bit line opposite to the end to which the nth block unit (n is an integer between 2 and N) is connected; an n+1th bit line connected to the n+1th switching element; and an n+1th block unit including at least one memory cell connected to the n+1th bit line, wherein the nth switching element alternately switches between a connection configuration in which the nth block unit is connected to the n-1th block unit and a disconnection configuration in which only the nth block unit is disconnected from the n-1th block unit.

8. The memory array of claim 1, wherein, when a target memory cell selected as a target for a read operation belongs to the second block unit, the first switching element switches to the first circuit configuration, charging of the first bit line and the second bit line in the first circuit configuration begins, and a read operation is performed on the target memory cell after a first charging time has elapsed since the time when the charging began; when a target memory cell selected as a target for a read operation belongs to the first block unit, the first switching element switches to the second circuit configuration, charging of the first bit line in the second circuit configuration begins, and a read operation is performed on the target memory cell after a second charging time has elapsed since the time when the charging began; and the second charging time is shorter than the first charging time.

9. The memory array of claim 2, wherein, when a target memory cell selected as a target for a write operation belongs to the second block unit, the first switching element switches to the first circuit configuration, charging of the first bit line and the second bit line in the first circuit configuration begins, and a write operation is performed on the target memory cell after a first charging time has elapsed since the time when the charging began; when a target memory cell selected as a target for a write operation belongs to the first block unit, the first switching element switches to the second circuit configuration, charging of the first bit line in the second circuit configuration begins, and a write operation is performed on the target memory cell after a second charging time has elapsed since the time when the charging began; and the second charging time is shorter than the first charging time.

10. A semiconductor memory system comprising: a memory array including a plurality of memory cells from which data is to be read; an amplifier circuit connected to the memory array and used to read the data stored in the memory cells; and a control module that provides control signals to the memory array and the amplifier circuit, wherein the memory array has: a first bit line connected to the amplifier circuit; a first block unit including at least one memory cell connected to the first bit line; a first switching element connected to an end of the first bit line opposite to the end connected to the amplifier circuit; a second bit line connected to the first switching element; and a second block unit including at least one memory cell connected to the second bit line, wherein the first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the amplifier circuit, and a second circuit configuration in which only the first block unit is connected to the amplifier circuit.

11. A semiconductor memory system comprising: a memory array including a plurality of memory cells to which data is to be written; a circuit switching element connected to the memory array and used for writing the data stored in the memory cells; and a control module for supplying control signals to the memory array and the circuit switching element, wherein the memory array has: a first bit line connected to the circuit switching element; a first block unit including at least one memory cell connected to the first bit line; a first switching element connected to an end of the first bit line opposite to the end to which the circuit switching element is connected; a second bit line connected to the first switching element; and a second block unit including at least one memory cell connected to the second bit line, wherein the circuit switching element outputs a voltage corresponding to the data to be written to the first bit line, and the first switching element alternately switches between a first circuit configuration in which the first block unit and the second block unit are connected to the circuit switching element and a second circuit configuration in which only the first block unit is connected to the circuit switching element.

12. A semiconductor memory system as described in claim 10 or 11, wherein the control module selects the first circuit configuration when a target memory cell selected as the target of operation belongs to the second block unit, and selects the second circuit configuration when the target memory cell belongs to the first block unit.

13. The semiconductor memory system of claim 10 or 11, wherein the control module, when a target memory cell selected as the target of operation belongs to the second block unit, starts charging the first bit line and the second bit line, and performs an operation on the target memory cell after a first charging time has elapsed since the time when the charging started, when the target memory cell selected as the target of operation belongs to the first block unit, starts charging the first bit line, and performs an operation on the target memory cell after a second charging time has elapsed since the time when the charging started, and the second charging time is shorter than the first charging time.

Images