Ceramic circuit board and semiconductor device using same

Abstract

Provided is a ceramic circuit board with improved long-term reliability. A ceramic circuit board according to an embodiment comprises a ceramic substrate and a metal part bonded to the ceramic substrate. An AC voltage of 50 Hz or 60 Hz is applied between a front surface and a back surface of the ceramic circuit board at a ramp-up rate of 200 V / s, an arc discharge voltage A (kV) is measured when arc discharge is detected, and when an insulation breakdown voltage B (kV) between the front surface and the back surface is measured in accordance with IEC 672-2, the ratio A / B is 0.10 or more. The ratio A / B is preferably in the range of 0.10-0.50. The metal part is bonded to the ceramic substrate via a bonding layer, and preferably the total area ratio of voids in an arbitrary cross section of the bonding layer is in the range of 0-1%. The metal part is a metal plate having a thickness of 0.2 mm or more, and preferably an upper end portion of at least a part of a side surface of the metal plate has a radiused shape.

Description

Ceramic circuit board and semiconductor device using the same

[0001] The embodiments described below generally relate to a ceramic circuit substrate and a semiconductor device using the same.

[0002] Ceramic circuit boards are used as semiconductor devices by mounting semiconductor elements on them. In recent years, the guaranteed operating temperature of semiconductor elements has increased with the increasing performance of semiconductor elements. As a result, the thermal cycle test characteristics (TCT characteristics) required of ceramic circuit boards have also become more stringent.

[0003] For example, Japanese Patent No. 6906662 (Patent Document 1) discloses a ceramic circuit board in which the size and hardness of the protruding portion of the bonding layer are controlled. Japanese Patent No. 7010950 (Patent Document 2) discloses a ceramic circuit board having a bonding layer with a void rate of 1% or less. Japanese Patent No. 7332588 (Patent Document 3) discloses a ceramic circuit board in which the shape of the copper plate side surface is controlled. The ceramic circuit boards of Patent Documents 1 to 3 had excellent TCT characteristics.

[0004] Patent No. 6906662 Patent No. 7010950 Patent No. 7332588 Patent No. 6293772

[0005] Japanese Patent No. 6293772 (Patent Document 4) discloses a silicon nitride substrate having a dielectric strength of 20 kV / mm or more. A silicon nitride circuit board using a silicon nitride substrate having a high dielectric strength has a high dielectric strength.

[0006] Semiconductor devices are obtained by mounting semiconductor elements on ceramic circuit substrates. Despite their high dielectric strength, ceramic circuit substrates have sometimes been found to lack long-term reliability. Investigation into the cause of this problem revealed that dielectric strength tests use test conditions that deviate significantly from practical electric fields, and therefore dielectric strength is not an optimal indicator of long-term reliability. For example, the practical voltage of semiconductor devices is approximately 1 kV. In contrast, in tests, a large voltage of approximately 9 kV is applied to measure the dielectric breakdown voltage.

[0007] The embodiments are intended to address such issues, and have an object to provide a ceramic circuit board with improved long-term reliability of insulation, and a semiconductor device using the same.

[0008] A ceramic circuit substrate according to an embodiment includes a ceramic substrate and a metal part bonded to the ceramic substrate. When an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces of the ceramic circuit substrate at a voltage increase rate of 200 V / s, an arc discharge voltage A (kV) is measured when an arc discharge is detected, and a breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2. The ratio A / B is 0.10 or greater.

[0009] 1 is a diagram showing an example of a ceramic circuit substrate according to an embodiment; FIG. 2 is a diagram showing another example of a ceramic circuit substrate according to an embodiment; FIG. 3 is a diagram showing an example of a cross-sectional structure of a ceramic substrate; FIG. 4 is a diagram showing an example of a semiconductor device according to an embodiment;

[0010] A ceramic circuit substrate according to an embodiment includes a ceramic substrate and a metal part bonded to the ceramic substrate. When an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces of the ceramic circuit substrate at a voltage increase rate of 200 V / s, an arc discharge voltage A (kV) is measured when an arc discharge is detected, and a breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2. The ratio A / B is 0.10 or greater.

[0011] 1 and 2 are side views showing an example of a ceramic circuit board according to an embodiment, in which reference numeral 1 denotes a ceramic circuit board, reference numeral 2 denotes a ceramic substrate, reference numeral 3 denotes a metal portion (metal plate), reference numeral 4 denotes a bonding layer, and reference numeral 5 denotes an upper end portion of a side surface of the metal plate.

[0012] The ceramic substrate 2 may have a variety of shapes in plan view, such as a rectangle, square, circle, oval, triangle, or pentagon. Screw holes may be provided in the ceramic substrate 2 as needed. The ceramic substrate 2 may be, for example, a silicon nitride substrate, an aluminum nitride substrate, an aluminum oxide substrate, or a zirconium oxide substrate. The thermal conductivity of the silicon nitride substrate is 40 W / m·K or more, and can be 80 W / m·K or more. The three-point bending strength of the silicon nitride substrate is 600 MPa or more, and can be 700 MPa or more.

[0013] The thermal conductivity of aluminum nitride substrates is 160 W / m·K or higher, and can be 200 W / m·K or higher. The three-point bending strength of aluminum nitride substrates is approximately 300 to 450 MPa. The three-point bending strength of aluminum oxide substrates is approximately 300 to 450 MPa, but aluminum oxide substrates are less expensive than other substrates. The thermal conductivity of aluminum oxide substrates is approximately 20 to 30 W / m·K. The three-point bending strength of zirconium oxide substrates is high, approximately 550 MPa, but their thermal conductivity is approximately 30 to 50 W / m·K.

[0014] The metal portion 3 is, for example, a metal plate, a metallized layer, a thin film, etc. In the example shown in Figures 1 and 2, the metal portion 3 is a metal plate, and the metal portion 3 is bonded to the ceramic substrate 2 via a bonding layer 4.

[0015] The metal plate is, for example, a copper plate, a copper alloy plate, an aluminum plate, or an aluminum alloy plate. When a plurality of metal portions 3 are provided on the ceramic circuit board 1, only one selected from copper plates, copper alloy plates, aluminum plates, and aluminum alloy plates may be used. Alternatively, some of the metal portions 3 may be any one selected from copper plates, copper alloy plates, aluminum plates, and aluminum alloy plates, and the other metal portions 3 may be any one selected from copper plates, copper alloy plates, aluminum plates, and aluminum alloy plates.

[0016] The metal plate is preferably a copper plate. Furthermore, it is preferable to use an oxygen-free copper plate as the copper plate. Oxygen-free copper has a copper purity of 99.96 wt% or more, as specified in JIS-H-3100 (2018). JIS-H-3100 corresponds to ISO 197 and other standards.

[0017] The thermal conductivity of copper is approximately 400 W / m·K, while that of aluminum is approximately 240 W / m·K. Compared to aluminum, copper has a higher thermal conductivity. Therefore, using a copper plate as the metal plate improves heat dissipation.

[0018] When an aluminum plate is used, it is preferable that the aluminum plate be made of substantially pure aluminum. Pure aluminum is specified in JIS-H-4000 (2022). JIS-H-4000 corresponds to ISO 6361.

[0019] The thickness of the metal plate is preferably 0.2 mm or more, and more preferably 0.3 mm or more. By increasing the thickness of the metal plate, the heat dissipation property can be improved. The current carrying capacity of the metal part 3 can also be improved. For this reason, the thickness of the metal plate is preferably 0.3 mm or more, and more preferably 0.6 mm or more. There is no particular upper limit to the thickness of the metal plate, but it is preferably 5 mm or less. If the thickness exceeds 5 mm, it may be difficult to control the inclined shape of the side surface of the metal plate.

[0020] From the viewpoint of heat dissipation, the metal portion 3 is preferably a copper plate having a thickness of 0.6 mm or more. More preferably, copper plates having a thickness of 0.6 mm or more are provided on both the front and back surfaces of the ceramic substrate 2.

[0021] The ceramic substrate 2 and the metal portion 3 are preferably bonded via a bonding layer 4. The bonding layer 4 is preferably formed using an active metal bonding method. In the active metal bonding method, bonding is performed using an active metal brazing material. The main component of the active metal brazing material is copper (Cu) or silver (Ag). The active metal brazing material contains one or more active metals selected from Ti (titanium), Zr (zirconium), and Hf (hafnium). The "main component" refers to the component that is contained in the largest amount among the metal components of the brazing material.

[0022] The active metal brazing material contains 0% by mass or more and 60% by mass or less of Ag (silver), 15% by mass or more and 70% by mass or less of Cu (copper), and Ti (titanium) or TiH ２ It is preferable that the titanium hydride is contained in an amount of 1 mass % or more and 15 mass % or less. ２ When both Ag and Cu are used, their total content is preferably in the range of 1% by mass to 15% by mass. When both Ag and Cu are used, Ag is preferably in the range of 20% by mass to 60% by mass and Cu is preferably in the range of 15% by mass to 40% by mass. If necessary, one or both of Sn (tin) and In (indium) may be contained in an amount of 1% by mass to 50% by mass. If necessary, C (carbon) may be contained in an amount of 0.1% by mass to 2% by mass.

[0023] The composition ratio of each component in the active metal brazing material is calculated assuming that the total of the mixed raw materials is 100 mass %. For example, if the active metal brazing material is composed of three elements, Ag, Cu, and Ti, the total of Ag, Cu, and Ti is 100 mass %. ２ When the alloy is composed of four elements, Ag, Cu, TiH, and In, ２ In the case where the active metal brazing material is composed of five elements, Ag, Cu, Ti, Sn, and C, the total of Ag, Cu, Ti, Sn, and C is taken as 100 mass %.

[0024] Ag or Cu is a component that serves as the base material of the brazing filler metal. Sn or In has the effect of lowering the melting point of the brazing filler metal. Adding carbon (C) makes it easier to control the fluidity of the brazing filler metal and to control the structure of the joining layer by reacting with other components. For this reason, the components of the brazing filler metal are preferably, for example, Ag-Cu-Ti, Ag-Cu-Sn-Ti, Ag-Cu-Ti-C, Ag-Cu-Sn-Ti-C, Ag-Ti, Cu-Ti, Ag-Sn-Ti, Cu-Sn-Ti, Ag-Ti-C, Cu-Ti-C, Ag-Sn-Ti-C, or Cu-Sn-Ti-C. In may be used instead of Sn. Both Sn and In may be used. The active metal brazing material may also contain one or more elements selected from tungsten (W), molybdenum (Mo), and rhenium (Re) in an amount of 0.1% by mass to 10% by mass. The addition of tungsten, molybdenum, or rhenium makes it easier to control the fluidity of the active metal brazing material. The active metal brazing material may also contain magnesium (Mg). The amount of magnesium added may also be in an amount of 0.1% by mass to 10% by mass.

[0025] When the metal part 3 is an aluminum plate, it is preferable to use an Al-Si or Al-Mg brazing filler metal as the active metal brazing filler metal. The content of one or both of Si and Mg contained in the active metal brazing filler metal is preferably within the range of 0.1 mass % to 20 mass %.

[0026] The ceramic circuit board 1 preferably has a shape in which the bonding layer 4 protrudes from the side surface of the metal part 3. The protruding part of the bonding layer 4 is also called a bonding layer protrusion part. By providing a bonding layer protrusion part, the TCT characteristics of the ceramic copper circuit board can be improved.

[0027] The metal portion 3 may be a thin film or a metallized layer. The thin film is a conductive film formed by sputtering or plating. The metallized layer is a conductive layer formed by applying a metal powder paste to the ceramic substrate 2 and firing it.

[0028] The metal portion 3 may be provided on each of both surfaces of the ceramic substrate 2. The metal portion 3 on the front surface (first metal portion) can be used as a member on which a semiconductor element is mounted. The metal portion 3 on the back surface (second metal portion) can be used as a heat dissipation portion. Alternatively, the metal portions 3 on both surfaces may be used as members on which a semiconductor element is mounted.

[0029] As shown in Fig. 1, one metal portion 3 may be provided on the front surface of the ceramic substrate 2. As shown in Fig. 2, multiple metal portions 3 may be provided, or three or more metal portions 3 may be provided. When multiple metal portions 3 are provided, each metal portion 3 can be used as a member on which a semiconductor element is mounted. When a semiconductor element is also mounted on the metal portion 3 on the back surface, multiple metal portions 3 may be provided on the back surface.

[0030] In the embodiment, when the arc discharge voltage A (kV) of the ceramic circuit board 1 is measured and the breakdown voltage B (kV) is measured, the ratio A / B is 0.10 or more.

[0031] Here, the method for measuring the arc discharge voltage and the breakdown voltage will be described.

[0032] First, a method for measuring the arc discharge voltage will be described. A pair of electrodes is placed on the metal portion 3 on the front surface of the ceramic circuit substrate 1 and on the metal portion 3 on the back surface of the ceramic circuit substrate 1, respectively, and the ceramic circuit substrate 1 is sandwiched between the pair of electrodes. The pair of electrodes is arranged to face each other in a direction perpendicular to the surface of the ceramic substrate 2. If the metal portion 3 is provided only on the front surface of the ceramic substrate 2, one electrode is placed on the metal portion 3 on the front surface, and the other electrode is placed on the back surface of the ceramic substrate 2. If multiple metal portions 3 are provided on one surface of the ceramic substrate 2, an electrode is placed on any one of the metal portions 3. In this state, an AC voltage of 50 Hz or 60 Hz is applied between the electrodes. The initial voltage value is set to 0 V, and the voltage is increased at a rate of 200 V / s. The voltage when an arc discharge is detected between the electrodes is measured as the arc discharge voltage (kV). Once the arc discharge voltage is measured, the voltage application is stopped without further increase.

[0033] For example, a spherical electrode with a tip diameter of 10 mm, as specified in JIS-C-2110-1 (2013), is used. JIS-C-2110-1 corresponds to IEC 60243-1. The measurement environment is set to a temperature of 10 to 25°C and a humidity of 30 to 60%, and the measurement is performed in the atmosphere.

[0034] The arc discharge voltage is measured at three arbitrary locations on one ceramic circuit board, and the average value is recorded as the arc discharge voltage A (kV). The three arbitrary locations are selected so that they do not overlap with each other. For example, if three or more metal portions 3 are provided on the surface of the ceramic substrate 2, three metal portions 3 are selected in descending order of area. Electrodes are sequentially placed on the three selected metal portions 3, and the arc discharge voltage is measured for each. If one metal portion 3 is provided on the surface of the metal portion 3, the arc discharge voltage is measured by changing the position of the electrode on the same metal portion 3. If two metal portions 3 are provided on the surface of the metal portion 3, the arc discharge voltage is measured twice by changing the position of the electrode on one metal portion 3, and the arc discharge voltage is measured once on the other metal portion 3.

[0035] The maximum voltage when measuring the arc discharge voltage is 20 kV. The ceramic circuit board 1 is housed in a container and managed so that the measurement is not affected by air currents. It is preferable to use an AC withstand voltage tester -7473 manufactured by Keisoku Giken Kenkyusho as the measuring device. Alternatively, a device with an equivalent or better arc discharge detection function may be used. The unit of arc discharge voltage A can be "kV / mm", which is the voltage divided by the thickness of the ceramic substrate.

[0036] The breakdown voltage is measured in accordance with the dielectric breakdown strength test of JIS-C-2141 (1992). JIS-C-2141 corresponds to IEC672-2. The test is performed using the two-terminal method. A pair of electrodes is placed on the metal part 3 on the front surface of the ceramic circuit board 1 and on the metal part 3 on the back surface, respectively, and the ceramic circuit board 1 is sandwiched between the pair of electrodes. In this state, an AC voltage of 50 Hz or 60 Hz is applied between the electrodes. The initial value of the voltage is set to 0 V, and the voltage is increased at a rate of 200 V / s. The voltage at which the ceramic circuit board 1 experiences dielectric breakdown is measured as the breakdown voltage B (kV).

[0037] For example, a spherical electrode with a tip diameter of 10 mm, as specified in JIS-C-2110-1 (2013), is used as the electrode. The electrode conditions when measuring breakdown voltage B are the same as the electrode conditions when measuring arc discharge voltage A. The maximum voltage is 20 kV. The unit of breakdown voltage B can be "kV / mm", which is the voltage divided by the thickness of the ceramic circuit substrate 1. The units of arc discharge voltage and breakdown voltage are unified to either "kV" or "kV / mm".

[0038] The electrodes, voltage rise rate, and measurement environment when measuring the breakdown voltage are the same as those when measuring the arc discharge voltage. Furthermore, when the size of the ceramic circuit board is small, a catalog value measured in accordance with IEC 672-2 may be used as the breakdown voltage of the ceramic circuit board 1. As a guideline for size, when one side is less than 5 mm, it is preferable to use the catalog value. The catalog value is a representative value listed by a manufacturer or seller in a product catalog, specification, etc., to indicate the performance or specifications of the product.

[0039] After measuring the arc discharge voltage, the breakdown voltage is measured. In measuring the breakdown voltage, the ceramic circuit substrate 1 is subjected to dielectric breakdown. Therefore, while the arc discharge voltage is measured three times, the breakdown voltage is measured only once. In measuring the breakdown voltage, if multiple metal portions 3 are provided on the surface of the ceramic substrate 2, one electrode is placed on the metal portion 3 with the largest area. The other electrode is placed on the metal portion 3 on the back surface so as to face that electrode.

[0040] In the embodiment, when the arc discharge voltage A (kV) and the breakdown voltage B (kV) of the ceramic circuit board 1 are measured, the ratio A / B is 0.10 or more.

[0041] Arc discharge is detected as a pulse current that occurs periodically when an AC electric field of a constant frequency is applied to the ceramic circuit board 1. Arc discharge is likely to occur in a structure where electric field concentration can occur. For example, arc discharge can be caused by voids in the bonding layer 4 or voids in the ceramic substrate 2. The shape of the upper end of the side surface of the metal part 3 can also cause arc discharge.

[0042] Arc discharge occurs in voids and other areas inside the ceramic substrate 2. When a voltage is applied to the ceramic circuit substrate 1, a shared voltage is applied to the voids. In the ceramic substrate 2, the ceramic portion and the void portion have different electrical resistance values, which creates a voltage gradient. In the void portion, the magnitude of the shared voltage varies depending on the size or shape. When this shared voltage reaches the discharge voltage in the void, a partial discharge occurs, which is the source of the arc discharge. The occurrence of an arc discharge is determined when a periodic pulse current of 10 kHz or more appears due to this partial discharge. The voltage at which the arc discharge begins is detected and measured as the arc discharge voltage.

[0043] In measuring the breakdown voltage, the voltage is measured when a large current is detected between the front and back surfaces of the ceramic circuit substrate 1. When breakdown occurs in the ceramic circuit substrate 1 and the structure of the ceramic circuit substrate 1 is destroyed, a short circuit occurs between the electrodes, and a much larger current than before is detected. The voltage at this time is measured as the breakdown voltage B.

[0044] In recent years, the switching frequency of semiconductor elements has increased with the increasing performance of semiconductor elements. Power semiconductor elements can be Si elements, SiC elements, GaN elements, and the like. Their switching frequencies vary from several tens of Hz to several hundreds of kHz. Recently, semiconductor elements with switching frequencies of approximately 1 GHz have also become available. In semiconductor elements, current is repeatedly turned on and off depending on the switching frequency. When the current is repeatedly turned on and off and an AC voltage is applied to the ceramic circuit substrate 1, arc discharge may occur in the ceramic circuit substrate 1. The lower the arc discharge voltage of the ceramic circuit substrate 1, the more likely arc discharge occurs in the ceramic circuit substrate 1 when the current is repeatedly turned on and off. Repeated arc discharges deteriorate the insulation of the ceramic circuit substrate 1. As a result, the insulation of the ceramic circuit substrate 1 cannot be maintained for a long period of time. In other words, the insulation of the ceramic circuit substrate 1 deteriorates even before the breakdown voltage is reached.

[0045] Generally, the switching frequency of a Si-IGBT element, which is a type of Si element, is about 100 Hz to 50 kHz. The switching frequency of a SiC-MOS element is about 8 kHz to 1 MHz. As the switching frequency increases, the output power and power density also increase. For example, a Si-IGBT element with a switching frequency of 25 kHz has an output power of 3.3 kW and a power density of 0.3 W / cm. ３ For a SiC-MOS device with a switching frequency of 160 kHz, the output power is 5 kW and the power density is 1.8 W / cm. ３For GaAs-Metal Semiconductor Field Effect Transistors (MESFETs) and High Electron Mobility Transistors (HEMTs), the switching operating frequency may be 1 GHz to 10 GHz. An increase in the switching frequency leads to an increase in the output voltage or power density.

[0046] The ceramic circuit board 1 according to the embodiment exhibits excellent insulation properties even when a semiconductor element having a switching frequency of 8 kHz or more is mounted thereon. Furthermore, the ceramic circuit board 1 according to the embodiment can be used with an output power of 1 kW or more or a power density of 1 W / cm. ３ Even when the above semiconductor elements are mounted, the ceramic circuit board exhibits excellent insulation properties. For ceramic circuit boards on which high-performance semiconductor elements are mounted, the insulation properties cannot be appropriately evaluated by the breakdown voltage alone. According to the embodiment, by controlling the ratio of the arc discharge voltage to the breakdown voltage, a ceramic circuit board 1 having insulation properties suitable for semiconductor devices is provided.

[0047] In the ceramic circuit board 1 according to the embodiment, when the arc discharge voltage A (kV) and the breakdown voltage B (kV) are measured, the ratio A / B is 0.10 or more. This indicates that the arc discharge voltage A is 0.10 times or more the breakdown voltage B. On the other hand, a ratio A / B of less than 0.10 indicates that the arc discharge voltage A is lower than 0.10 times the breakdown voltage B. When the ratio A / B of the ceramic circuit board 1 is less than 0.10, insulation failure of the ceramic circuit board 1 may occur when a semiconductor element with a high switching frequency is mounted and used, despite the high breakdown voltage. In other words, a ceramic circuit board 1 with a ratio A / B of less than 0.10 may lack long-term reliability.

[0048] Arc discharge is detected as a pulse current that periodically occurs when an AC electric field of a constant frequency is applied between electrodes. Initial arc discharge phenomena occur in voids in the bonding layer 4 or in the ceramic substrate 2. Repeated arc discharges lead to a phenomenon known as arc degradation. As arc degradation progresses, dielectric breakdown occurs. Arc discharges can also be considered a precursor to dielectric breakdown. Therefore, measuring the voltage at which arc discharge occurs can confirm the long-term reliability of the ceramic circuit substrate 1. In other words, the higher the ratio of arc discharge voltage to breakdown voltage and the less likely arc discharge occurs, the less likely arc degradation progresses in the ceramic circuit substrate 1. As a result, even when a semiconductor device including the ceramic circuit substrate 1 is used for a long period of time, dielectric breakdown in the ceramic circuit substrate 1 can be suppressed. As described above, the dielectric breakdown voltage of the ceramic substrate 2 is designed to be higher than the practical voltage. The larger the ratio A / B, the closer the voltage at which arc discharge voltage occurs to the dielectric breakdown voltage. In other words, the larger the ratio A / B, the less likely arc discharge voltage occurs at the practical voltage or the higher the practical voltage. Therefore, the larger the ratio A / B, the more the arc deterioration in the ceramic circuit board 1 can be suppressed.

[0049] Furthermore, measurement of the arc discharge voltage is a non-destructive test, while measurement of the dielectric strength voltage is a destructive test. By using a catalog value for the dielectric strength voltage, it is also possible to confirm the long-term reliability of the ceramic circuit board 1 by non-destructive testing.

[0050] In particular, as the switching frequency of the semiconductor element increases, the number of periodically generated pulse currents increases. As the output voltage and power density increase, arc discharge becomes more likely to occur inside the ceramic circuit substrate 1. Therefore, the higher the switching frequency, output voltage, and power density, the more likely the insulation inside the ceramic circuit substrate 1 is to be degraded by arc discharge, even if the ceramic circuit substrate 1 does not suffer from dielectric breakdown. As a result, long-term reliability problems may arise.

[0051] A ratio A / B of 0.10 or more indicates that the ratio of arc discharge voltage A to breakdown voltage B is higher than that of conventional ceramic circuit boards. Therefore, arc discharge is less likely to occur even when the output voltage and power density of the semiconductor element are high. By suppressing the occurrence of arc discharge, the number of arc discharge occurrences can be reduced even when the switching frequency of the mounted semiconductor element is high. In other words, suppressing the occurrence of arc discharge leads to improved reliability of semiconductor devices including semiconductor elements with high switching frequencies.

[0052] The upper limit of the ratio A / B is 1.0. A ratio A / B=1.0 indicates a state in which the arc discharge voltage and the breakdown voltage are substantially the same, or a state in which substantially no arc discharge is observed. A ratio A / B=1.0 indicates that the ceramic circuit substrate 1 does not have a structure that generates a periodic pulse current even when an AC electric field of a constant frequency is applied between the electrodes.

[0053] For example, in the ceramic circuit substrate 1, there are cases where voids are substantially absent in the ceramic substrate 2 or the bonding layer 4, and cases where voids are present but arc discharge is undetectable (including below the detection limit). The ceramic circuit substrate 1 includes a metal portion 3, and when measuring the arc discharge voltage, the metal portion 3 electrically connected to the electrode essentially functions as an electrode for the ceramic substrate 2 and the bonding layer 4. Therefore, the arc discharge voltage of the ceramic circuit substrate 1 can be measured more easily than when measuring the arc discharge voltage of the ceramic substrate 2 alone. Therefore, in practice, a state in which voids are present but arc discharge is undetectable is unlikely to occur. Furthermore, producing a ceramic substrate 2 and a bonding layer 4 that are free of voids increases costs. From these perspectives, the ratio A / B is preferably in the range of 0.10 to 0.50, more preferably in the range of 0.20 to 0.45. In other words, according to the embodiment, even if voids are present in the ceramic substrate 2 or the bonding layer 4, a ceramic circuit substrate with long-term reliability can be provided.

[0054] The metal part 3 is bonded to the ceramic substrate 2 via the bonding layer 4, and the total area ratio of voids (air pores) in the bonding layer 4 is preferably in the range of 0% to 1%. As mentioned above, voids in the bonding layer 4 can cause arc discharge. Therefore, it is preferable that the number of voids in the bonding layer 4 is as small as possible.

[0055] To measure the total area ratio of voids in the bonding layer 4, an arbitrary cross section of the bonding layer 4 is observed with a scanning electron microscope (SEM). A cross section perpendicular to the surface of the ceramic substrate 2 is used for the observation. The magnification of the SEM photograph is set to 1000x. An area of ​​the bonding layer 4 with a width of 100 μm and the thickness of the bonding layer is observed. The total area of ​​the voids is calculated, and this total area is divided by the area of ​​the observed area to calculate the total area ratio (%). In the cross-sectional SEM photograph, there is a large contrast between the voids and other parts. The voids appear black compared to other parts, making them easy to identify. In particular, in bonding layers 4 whose main components are Ag, Cu, or Al, there is a large contrast, and a large difference in brightness between the voids and other parts.

[0056] The metal portion 3 is preferably a metal plate, and as shown in FIG. 2, it is preferable that the upper end 5 of at least a portion of the side surface of the metal plate has an R-shape. The upper end 5 is the uppermost portion of the side surface of the metal plate. Preferably, the upper end 5 of the entire side surface of the metal plate has an R-shape. When multiple metal plates are provided on one surface of the ceramic substrate 2, two adjacent metal plates have side surfaces facing each other. In this case, it is preferable that the upper end 5 of each side surface has an R-shape. More preferably, the upper end 5 of the entire side surface of each metal plate has an R-shape.

[0057] The R-shape refers to a curved surface between the side and top surfaces of a metal plate, with a radius of curvature greater than zero. The R-shape is measured using a three-dimensional shape measuring instrument. Electric field concentration is likely to occur at the upper end 5 (edge ​​portion). This is particularly true when the metal portion 3 is a metal plate. Because a metal plate has a thickness of, for example, 0.2 mm or more, when a circuit shape is imparted to the metal plate, the upper end of the metal plate side surface is likely to become a right angle or acute angle and sharp. For example, if the upper end of the metal plate side surface is sharp, discharge phenomena are likely to occur between the upper ends of the opposing metal plate side surfaces. For this reason, it is preferable to impart an R-shape to the upper end of the metal plate side surface. On the other hand, sputtered films and metallized layers are thin films, making discharge phenomena less likely to occur. For this reason, it is preferable to impart an R-shape to the upper end of the metal plate side surface in a ceramic circuit board to which a metal plate with a thickness of 0.2 mm or more is bonded.

[0058] An example of a metal plate having a non-rounded upper end 5 is one in which the angle of the upper end 5 (the angle between the side surface and the top surface) is 90° or less. When the angle of the upper end 5 is 90° or less, the upper end 5 of the metal plate has a pointed shape. When the upper end 5 has a pointed shape, discharge is likely to occur between the upper ends 5 of opposing metal plates. In particular, when the distance between the upper ends 5 of adjacent metal plates is 3 mm or less, discharge may occur, resulting in electric field concentration. In other words, when there is a location between adjacent metal plates where the distance between the upper ends 5 is 3 mm or less, it is preferable that the upper end 5 has an R-shape. Furthermore, by imparting an inclined shape to the side surface of the metal plate, the upper end 5 can be imparted with an angle exceeding 90°. When the angle of the upper end 5 exceeds 90° and the upper end 5 is imparted with an R-shape, electric field concentration can be further suppressed.

[0059] When a metal plate is used for the metal portion 3, the metal portion 3 can be made thicker than when a metallized layer or a conductive thin film is used for the metal portion 3. Therefore, in order to improve the current-carrying capacity of the metal portion 3, it is preferable to use a metal plate for the metal portion 3. Furthermore, by providing an R-shape to the upper end 5 of the side surface of the metal plate, the occurrence of arc discharge can be suppressed.

[0060] The upper limit of the radius of curvature of the R-shape of the upper end 5 is not particularly limited, but is preferably 300 μm or less. If the radius of curvature exceeds 300 μm, the area of ​​the flat portion on the upper surface of the metal part 3 will be small. The area on which the semiconductor element is mounted is preferably flat. If the radius of curvature exceeds 300 μm, the area available for mounting the semiconductor element may be small. For this reason, the radius of curvature of the R-shape of the upper end 5 is preferably greater than 0 μm and less than 300 μm, and more preferably in the range of 5 μm to 200 μm.

[0061] The bonding area of ​​the metal portion 3 bonded to one surface of the ceramic substrate 2 is, for example, 40% or more of the area of ​​the one surface of the ceramic substrate 2. When a plurality of metal portions 3 are provided on one surface of the ceramic substrate 2, the total bonding area of ​​the plurality of metal portions 3 is 40% or more of the area of ​​the one surface. When a plurality of metal portions 3 are provided on each of the front and back surfaces of the ceramic substrate 2, the proportion of the bonding area on each of the front and back surfaces may be 40% or more.

[0062] As described above, electric field concentration is likely to occur at the upper end 5 of the metal portion 3. When multiple metal portions 3 are provided, the area of ​​the upper end 5 increases compared to when a single metal portion 3 is provided. The increase in the area of ​​the upper end 5 of the metal portion 3 can cause arc discharge to occur more easily. Furthermore, when the upper end portions 5 of the metal portions 3 face each other, arc discharge can also occur more easily between those upper end portions 5. In particular, when multiple metal portions 3 are provided and the proportion of their joint area is 40% or more, the area of ​​the upper end portions 5 facing each other increases, and the distance between the upper end portions 5 also becomes shorter. As a result, arc discharge becomes more likely to occur between the upper end portions 5.

[0063] In the ceramic circuit board 1 according to the embodiment, the ratio A / B is controlled to 0.10 or greater. In other words, according to the embodiment, even if the bonding area of ​​the metal portion 3 increases, the ratio A / B is controlled to 0.10 or greater, and arc discharge is suppressed. For example, according to the embodiment, even if a plurality of metal portions 3 are provided on one of the front and back surfaces of the ceramic substrate 2 and the proportion of the bonding area on that one surface is 40% or greater, the ratio A / B is controlled to 0.10 or greater, and arc discharge is suppressed on that one surface. Even if a plurality of metal portions 3 are provided on each of the front and back surfaces of the ceramic substrate 2 and the proportion of the bonding area on each of the front and back surfaces is 40% or greater, the ratio A / B is controlled to 0.10 or greater, and arc discharge is suppressed on both surfaces.

[0064] In order to control the ratio A / B, it is also effective to control voids in the ceramic substrate 2. Fig. 3 is a schematic diagram showing a cross section of the ceramic substrate. In Fig. 3, reference numeral 6 denotes a cross section of the ceramic substrate, and reference numeral 7 denotes a void having an area of ​​1 µm ２ The above voids, reference numeral 8, have an area of ​​1 μm ２ Voids less than 1 μm in area. ２ The above voids 7 are sometimes called large voids (secondary voids). Area 1 μm ２ Voids 8 smaller than this size are sometimes called small voids (first voids).

[0065] Any cross section of the ceramic substrate 2 has an area of ​​1 μm ２ The number of small voids less than 30 to 500, and the area is less than 1 μm ２ It is preferable that there is a 90 μm × 120 μm region in which the number of large voids 7 is 0 to 30 or less. Large voids 7 are likely to cause arc discharge. For this reason, in a 90 μm × 120 μm region, the number of large voids 7 is preferably in the range of 0 to 30, and more preferably in the range of 0 to 20. Small voids 8 are unlikely to cause arc discharge, but if there are too many of them, they can affect the arc discharge voltage. Furthermore, reducing the number of small voids 8 to zero is costly. For this reason, the number of small voids 8 is preferably in the range of 30 to 500, and more preferably in the range of 40 to 400.

[0066] The method for measuring voids will be described. First, a cross section perpendicular to the surface of the ceramic substrate 2 is prepared. A polished surface with a surface roughness Ra of 1 μm or less is used as the cross section. The cross section is observed with an SEM, and a 1000x magnification photograph is taken. The SEM used is a JEOL JCM-7000, JSM-7200F, or an instrument with equivalent or better performance. An area of ​​180 μm x 430 μm on the cross section is observed with the SEM. Within the 180 μm x 430 μm area, three non-overlapping regions of 90 μm x 120 μm are set. The voids present in each region are observed. Of the three regions, the 90 μm x 120 μm region in which the most voids are observed is selected.

[0067] In the 90 μm × 120 μm region where the most voids were observed among the three regions, the numbers of large voids 7 and small voids 8 may be within the above ranges, and in the unselected regions, the numbers of large voids 7 and small voids 8 may be below the above ranges. In other words, according to the embodiment, even in the 90 μm × 120 μm region with the most voids in the cross section of the ceramic substrate 2, the number of large voids 7 is controlled to be 0 to 20, and the number of small voids 8 is controlled to be 30 to 500.

[0068] If it is not possible to observe a 180 μm × 430 μm area in a single field of view, the 180 μm × 430 μm area may be observed multiple times. In this case, the minimum size of the observed area is set to 90 μm × 120 μm. The orientation of the sample relative to the 180 μm × 430 μm observation area and the 90 μm × 120 μm region is arbitrary. The orientation of the 180 μm × 430 μm observation area and the 90 μm × 120 μm region may be adjusted so that the most voids are observed in any cross section.

[0069] Area of ​​1 μm in a 90 μm × 120 μm area ２ The total area ratio of the small voids 8 less than 1 μm in an area of ​​90 μm×120 μm is preferably in the range of 0.01% to 0.8%. ２The total area ratio of the large voids 7 is preferably within the range of 0% to 0.6%. Controlling the total area ratio of the small voids 8 and the total area ratio of the large voids 7 is effective in suppressing the occurrence of arc discharge.

[0070] In a 90 μm × 120 μm area, the maximum diameter of the voids is preferably 15 μm or less. After the 90 μm × 120 μm area with the most voids is selected, the longest diameter of each void in that area is measured. The "longest diameter" is the distance between the two most distant points on the outer edge of the void. The largest value among the longest diameters of multiple voids is defined as the "maximum diameter." By making the maximum diameter of the voids 15 μm or less, it is possible to suppress a decrease in the insulation properties of the ceramic circuit board 1 due to large voids 7.

[0071] Furthermore, in a 90 μm × 120 μm area, the number of sets of large voids 7 where the distance between them is 5 μm or less is preferably 0 to 3. If the distance between one large void 7 and another large void 7 is 5 μm or less, those large voids 7 are counted as one set. If two large voids 7 exist within a 5 μm range from a reference large void 7, the reference large void 7 and each of the two large voids 7 are counted as two sets. If three or more large voids 7 exist within a 5 μm range from a reference large void 7, those large voids 7 are counted as three or more sets. For example, if three large voids 7 are distributed in a triangular shape with a distance of 5 μm or less between them, those large voids 7 are counted as three sets.

[0072] The distance is measured using an enlarged photograph of the observed cross section. A 5 μm range is set around each observed large void 7, and if another large void 7 exists within that range, the number of pairs of voids is counted. When a 5 μm range is then set around another large void 7, the pairs that have already been counted are not counted again.

[0073] If the large voids 7 are close to each other, they may function similarly to larger voids. For example, if the number of pairs of large voids 7 that are 5 μm or less apart exceeds three, the arc discharge voltage and breakdown voltage may decrease, and the insulating properties of the ceramic circuit board 1 may deteriorate. For this reason, the number of pairs of large voids 7 that are 5 μm or less apart is preferably in the range of 0 to 3, and more preferably in the range of 0 to 1. Note that even if small voids 8 exist near a large void 7, the pair of a large void 7 and a small void 8 is not counted. This is because the adverse effect on insulating properties is small even if the large voids 7 and the small voids 8 are close to each other. Here, only pairs of large voids 7 that are 5 μm or less apart are counted.

[0074] If the ceramic substrate 2 has controlled voids, the ratio of the arc discharge voltage to the breakdown voltage of the ceramic substrate 2 itself can be made 0.3 or more. To make the ratio A / B of the ceramic circuit substrate 1 0.10 or more, it is also effective to use a ceramic substrate 2 in which the ratio of the arc discharge voltage to the breakdown voltage is 0.3 or more. It is particularly preferable to use a ceramic substrate 2 having a thickness of 0.2 mm to 3 mm and in which the ratio of the arc discharge voltage to the breakdown voltage is 0.3 or more. The method for measuring the arc discharge voltage and breakdown voltage of the ceramic substrate 2 is the same as the method for measuring the arc discharge voltage and breakdown voltage of the ceramic circuit substrate 1. Furthermore, the value of the breakdown voltage of the ceramic substrate 2 may be a catalog value measured in accordance with JIS-C-2141 (1992).

[0075] To observe voids, SEM photographs are analyzed using image analysis software. Image J or equivalent software is used as the image analysis software. In cross-sectional SEM photographs, contrast occurs between voids and other parts. For example, the color of voids appears darker and deeper than the color of parts other than voids. By utilizing this contrast and binarizing the SEM photograph, it is possible to distinguish between voids and other parts. Note that small voids are defined as those with a size of 0.01 μm or more. ２ Voids with an area of ​​0.01 μm or more are counted.２ This is because voids smaller than this size are difficult to distinguish in a 1000x magnification photograph.

[0076] The threshold value for binarization is determined by the "mode method" or "discriminant analysis binarization method." If the image analysis software has the function of discriminant analysis binarization, the discriminant analysis binarization method of that image analysis software is used. With discriminant analysis binarization, the threshold value is uniquely determined by the analysis software. This makes it easy to identify voids. For example, in an SEM photograph, the white area around a void is the boundary between the void and the silicon nitride sintered body. Therefore, the white area around the void should not be counted as a void. Furthermore, in an SEM photograph, the silicon nitride sintered body is gray. By using the threshold value obtained by the "mode method" or "discriminant analysis binarization method," voids can be displayed in black, and the white area around the void and the silicon nitride sintered body can be displayed in white. Using the binarized image, it is possible to distinguish between voids and other areas in the SEM photograph.

[0077] The ceramic circuit substrate 1 according to the embodiment can be used in a semiconductor device. A semiconductor device is obtained by mounting a semiconductor element on the ceramic circuit substrate 1. Fig. 4 is a side view showing an example of a semiconductor device according to the embodiment. In Fig. 4, reference numeral 1 denotes a ceramic circuit substrate, reference numeral 9 denotes a semiconductor element, and reference numeral 10 denotes a semiconductor device.

[0078] As shown in Fig. 4, a semiconductor device 10 can be fabricated by mounting a semiconductor element 9 on at least one of the metal portions 3 of a ceramic circuit substrate 1. In the example shown in Fig. 4, one semiconductor element 9 is mounted on one metal portion 3. Multiple semiconductor elements 9 may be mounted on multiple metal portions 3, respectively. Multiple semiconductor elements 9 may be mounted on one metal portion 3. In addition to the semiconductor element 9, a lead frame, wire bonding, or the like may be bonded to the metal portion 3. By improving the arc discharge voltage of the ceramic circuit substrate 1, it is possible to ensure the long-term reliability of the insulation of the semiconductor device 10, even when a semiconductor element 9 with a high switching frequency is mounted.

[0079] Next, a method for manufacturing the ceramic circuit board 1 according to the embodiment will be described. As long as the ceramic circuit board 1 according to the embodiment has the above-described configuration, the manufacturing method is not particularly limited. Here, an example of a method for obtaining the ceramic circuit board 1 with a high yield will be described. Below, an example of a method for manufacturing a ceramic circuit board in which metal plates are bonded using an active metal brazing material will be described.

[0080] First, a ceramic substrate 2 is prepared. The ceramic substrate 2 may be one selected from a silicon nitride substrate, an aluminum nitride substrate, an aluminum oxide substrate, and a zirconium oxide substrate. As described above, it is preferable to use a ceramic substrate 2 in which voids are controlled. It is also preferable to use a ceramic substrate 2 in which the ratio of arc discharge voltage to breakdown voltage is 0.3 or more.

[0081] Next, a metal plate is prepared. The metal plate is preferably a copper plate, a copper alloy plate, an aluminum plate, or an aluminum plate. When multiple metal plates are used, two or more types selected from the copper plate, the copper alloy plate, the aluminum plate, and the aluminum plate may be used.

[0082] Next, an active metal brazing filler metal is prepared. When the metal plate is a copper plate (including a copper alloy plate), an active metal brazing filler metal containing Ag or Cu as the main component is used. When the metal plate is an aluminum plate (including an aluminum alloy plate), an active metal brazing filler metal containing Al as the main component is used. The preferred composition of the active metal brazing filler metal is as described above.

[0083] The active metal brazing material is made into a paste and applied to the surface of the ceramic substrate 2, and a metal plate is placed on top of it. When joining metal plates to both sides of the ceramic substrate 2, the active metal brazing material paste is also applied to the back surface, and the metal plate is then placed on it. Through the above steps, a laminate having a layered structure of a metal plate, an active metal brazing material layer, and the ceramic substrate 2 can be produced.

[0084] Next, the laminate is heated and bonded. The heating temperature is preferably in the range of 600°C to 950°C. In the heat bonding process, the temperature of the laminate is raised to the heating temperature and then maintained at the heating temperature for a certain period of time. The laminate is then cooled to room temperature. A batch furnace, a continuous furnace, a hot press, or the like can be used for the heat bonding process. In the heat bonding process, the active metal brazing material melts and then solidifies, forming a bonding layer 4.

[0085] In order to reduce the total area ratio of voids in the bonding layer 4 to 1% or less, it is effective to extend the bonding time. Methods for extending the bonding time include increasing the time held at the heating temperature and slowing the cooling rate after holding at the heating temperature. The time held at the heating temperature is preferably 30 minutes or more, and more preferably in the range of 1 hour to 5 hours. Furthermore, the cooling rate after holding at the heating temperature is preferably 100°C / hour or less, and more preferably 50°C / hour or less.

[0086] By extending the bonding time, the active metal brazing material melts sufficiently and fills the voids in the bonding layer 4. Also, slowing down the cooling rate is effective in filling the voids before the bonding layer 4 solidifies. Increasing the degree of vacuum in the bonding atmosphere is also effective. By increasing the degree of vacuum in the bonding atmosphere, oxidation of the active metal brazing material can be suppressed. This can suppress the occurrence of voids. The degree of vacuum is 10 －２ It is preferable that the viscosity is 10 Pa or less. －３ It is more preferable that the bonding pressure is 100 Pa or less. The method of extending the bonding time, the method of slowing down the cooling rate, and the method of increasing the degree of vacuum in the bonding atmosphere may be used alone or in combination. A bonded body can be obtained by performing the heat bonding step.

[0087] Next, the resulting bonded body is subjected to an etching process to impart a circuit shape to the metal plate. The etching process may be performed to control the side shape of the metal plate or the size of the protruding portion of the bonding layer.

[0088] The etching step is preferably carried out so as to impart an R-shape to the upper end 5 of the side surface of the metal plate. In order to impart an R-shape to the upper end 5, it is effective to etch the upper end 5. For example, the R-shape can be imparted to the upper end 5 by masking the area other than the upper end 5 and etching only the upper end 5. Alternatively, instead of the etching step, a metal plate whose upper end 5 has already been imparted with an R-shape may be bonded to the ceramic substrate 2.

[0089] The ceramic circuit board 1 according to the embodiment can be fabricated by the above steps. Furthermore, by mounting a semiconductor element 9 on the ceramic circuit board 1, a semiconductor device 10 can be fabricated.

[0090] (Examples 1 to 5, Comparative Examples 1 to 4) Silicon nitride substrates and aluminum nitride substrates were prepared as ceramic substrates. The silicon nitride substrates had a thermal conductivity of 90 W / m·K or more and a three-point bending strength of 600 MPa or more. The aluminum nitride substrates had a thermal conductivity of 180 W / m·K or more and a three-point bending strength of 400 MPa or more.

[0091] The thickness, arc discharge voltage / dielectric strength voltage, and void distribution of each ceramic substrate are shown in Tables 1 and 2. The arc discharge voltage, dielectric strength voltage, and void distribution were measured according to the measurement methods described above. Regarding the void distribution, three 90 μm × 120 μm regions were observed from an area of ​​180 μm × 430 μm, and the distribution in the region with the largest number of voids was shown in Table 2.

[0092]

[0093]

[0094] As can be seen from Table 2, in the examples, the distribution of voids in the ceramic substrate was controlled within a preferred range. In contrast, in the comparative examples, the distribution of voids in the ceramic substrate was outside the preferred range. In addition, in all of the examples, the ratio of arc discharge voltage / dielectric breakdown voltage of the ceramic substrate was 0.3 or more. On the other hand, in some of the comparative examples, the ratio of arc discharge voltage / dielectric breakdown voltage of the ceramic substrate was less than 0.3.

[0095] Next, a metal plate was bonded to the ceramic substrate using an active brazing material. The metal plate was a copper plate. The active brazing material was Ag—Cu—Sn—TiH. ２ Brazing filler metal or Cu-Sn-TiH ２ The heating temperature was set to a range of 750°C to 850°C. －３ The bonding was performed in a vacuum of 100 Pa or less, and the bonding time was set to 1 hour or more. Using this active metal bonding method, metal plates were bonded to both sides of the ceramic substrate.

[0096] The resulting bonded body was subjected to an etching process to impart a circuit pattern to the metal plate on the front surface. This process formed multiple metal parts on the front surface of the ceramic substrate. The metal plate on the back surface was not imparted with a circuit pattern and was used as a heat sink. In addition, an inclined shape was imparted to the side surfaces of the metal plates on the front and back surfaces, and a bonding layer protrusion was formed on the bonding layer 4.

[0097] Ceramic circuit boards according to the examples and comparative examples were fabricated using the above steps. The bonding area of ​​the metal plate in the ceramic circuit board, the total area ratio of voids in the bonding layer, and the R shape of the upper end of the metal plate are shown in Table 3. The methods for measuring the bonding area of ​​the metal plate, the total area ratio of voids, and the R shape (radius of curvature) of the upper end of the metal plate were as described above. In Table 3, the copper plate bonded to the front surface of the ceramic substrate is referred to as the "front copper plate," and the copper plate bonded to the back surface of the ceramic substrate is referred to as the "back copper plate."

[0098]

[0099] In the ceramic circuit boards according to the examples and comparative examples, multiple patterns (metal portions) are provided on the surface copper plate. In the examples, the total area ratio of voids in the bonding layer is 1% or less (including 0%), and an R-shape is provided on the upper end of the metal plate. In the comparative examples, the total area ratio of voids in the bonding layer is 3% or more, and no R-shape is provided on the upper end of the metal plate.

[0100] Next, the arc discharge voltage A and the breakdown voltage B of each of the ceramic circuit boards according to the examples and comparative examples were measured. The methods for measuring each voltage were as described above. The results are shown in Table 4.

[0101]

[0102] As can be seen from Table 4, in the examples, the ratio of arc discharge voltage A / breakdown voltage B was 0.2 or more. Therefore, it can be seen that the ratio of arc discharge voltage / breakdown voltage of the ceramic substrate, void control, the total area ratio of voids in the bonding layer, and the R-shape of the upper end of the metal plate are effective in controlling the ratio of arc discharge voltage A / breakdown voltage B of the ceramic circuit substrate. In contrast, in the comparative example, although the breakdown voltage of the ceramic circuit substrate was equivalent to that of the examples, the arc discharge voltage was lowered. As a result, the ratio of arc discharge voltage to breakdown voltage was below 0.1. Therefore, it can be seen that the ceramic circuit substrates according to the examples have excellent long-term reliability.

[0103] Embodiments of the present invention include the following features. (Feature 1) A ceramic circuit board comprising: a ceramic substrate; and a metal part bonded to the ceramic substrate, wherein when an AC voltage of 50 Hz or 60 Hz is applied between a front surface and a back surface of the ceramic circuit board at a voltage increase rate of 200 V / s, an arc discharge voltage A (kV) is measured when an arc discharge is detected, and a breakdown voltage B (kV) between the front surface and the back surface is measured in accordance with IEC 672-2, the ratio A / B is 0.10 or more. (Feature 2) The ceramic circuit board according to Feature 1, wherein the ratio A / B is within a range of 0.10 or more and 0.50 or less. (Feature 3) The ceramic circuit board according to Feature 1 or Feature 2, wherein the metal part is bonded to the ceramic substrate via a bonding layer, and a total area ratio of voids in any cross section of the bonding layer is within a range of 0% or more and 1% or less. (Feature 4) The ceramic circuit board according to any one of Features 1 to 3, wherein the metal portion is a metal plate having a thickness of 0.2 mm or more, and at least a part of the upper end of a side surface of the metal plate has an R-shape. (Feature 5) The ceramic circuit board according to any one of Features 1 to 4, wherein the metal portion is a copper plate having a thickness of 0.6 mm or more. (Feature 6) The ceramic circuit board according to any one of Features 1 to 5, wherein the thickness of the ceramic substrate is in the range of 0.2 mm to 3 mm. (Feature 7) Any cross section of the ceramic substrate has a surface area of ​​1 μm ２ The number of first voids that are less than 1 μm is in the range of 30 to 500, and the area is less than 1 μm ２Feature 6: The ceramic circuit board according to Feature 6, wherein there is a 90 μm × 120 μm region in which the number of second voids having a distance of 0 to 30 is within the range of 0 to 30. (Feature 8): The ceramic circuit board according to Feature 7, wherein in the 90 μm × 120 μm region, the total area ratio of the first voids is within the range of 0.01% to 0.8%. (Feature 9): The ceramic circuit board according to Feature 8, wherein in the 90 μm × 120 μm region, the total area ratio of the second voids is within the range of 0% to 0.6%. (Feature 10): The ceramic circuit board according to Feature 9, wherein in the 90 μm × 120 μm region, the maximum diameter of the voids is 15 μm or less. (Feature 11): The ceramic circuit board according to Feature 10, wherein in the 90 μm × 120 μm region, the number of sets of second voids whose distance is 5 μm or less is 3 or less. (Feature 12) The ceramic circuit board according to any one of Features 7 to 11, wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.2 mm to 3 mm. (Feature 13) A semiconductor device comprising: the ceramic circuit board according to any one of Features 1 to 12; and a semiconductor element mounted on the ceramic circuit board.

[0104] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0105] REFERENCE SIGNS LIST 1... ceramic circuit board 2... ceramic substrate 3... metal part (metal plate) 4... bonding layer 5... upper end of metal plate 6... cross section of ceramic substrate 7... area 1 μm ２ Voids 8 or more...area 1 μm ２ Voids less than 9... Semiconductor element 10... Semiconductor device

Claims

1. A ceramic circuit board comprising a ceramic substrate and a metal part bonded to the ceramic substrate, wherein an AC voltage of 50 Hz or 60 Hz is applied between the front and back surfaces of the ceramic circuit board at a voltage increase rate of 200 V / s, the arc discharge voltage A (kV) when an arc discharge is detected is measured, and when the breakdown voltage B (kV) between the front and back surfaces is measured in accordance with IEC 672-2, the ratio A / B is 0.10 or greater.

2. The ceramic circuit board according to claim 1, wherein the ratio A / B is within the range of 0.10 to 0.

50.

3. A ceramic circuit board according to claim 1 or 2, wherein the metal part is bonded to the ceramic substrate via a bonding layer, and the total area ratio of voids in any cross section of the bonding layer is within the range of 0% to 1%.

4. A ceramic circuit board according to any one of claims 1 to 3, wherein the metal portion is a metal plate having a thickness of 0.2 mm or more, and at least a part of the upper end of the side surface of the metal plate has an R-shape.

5. A ceramic circuit board according to any one of claims 1 to 4, wherein the metal portion is a copper plate having a thickness of 0.6 mm or more.

6. The ceramic circuit board according to any one of claims 1 to 5, wherein the thickness of the ceramic substrate is within the range of 0.2 mm to 3 mm.

7. Any cross section of the ceramic substrate has an area of ​​1 μm ２ The number of first voids that are less than 1 μm is in the range of 30 to 500, and the area is less than 1 μm ２ The ceramic circuit board according to claim 6, wherein there is a 90 μm×120 μm region in which the number of second voids is in the range of 0 to 30.

8. A ceramic circuit board according to claim 7, wherein the total area ratio of the first voids in the 90 μm×120 μm region is in the range of 0.01% or more and 0.8% or less.

9. A ceramic circuit board according to claim 8, wherein the total area ratio of the second voids in the 90 μm×120 μm region is within the range of 0% to 0.6%.

10. A ceramic circuit board according to claim 9, wherein the maximum diameter of voids in said 90 μm×120 μm region is 15 μm or less.

11. The ceramic circuit board according to claim 10, wherein the number of sets of second voids with a distance of 5 μm or less in the 90 μm×120 μm region is 3 or less.

12. The ceramic circuit board according to any one of claims 7 to 11, wherein the ceramic substrate is a silicon nitride substrate having a thickness of 0.2 mm to 3 mm.

13. A semiconductor device comprising: a ceramic circuit board according to any one of claims 1 to 12; and a semiconductor element mounted on said ceramic circuit board.

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