Nitride semiconductor device

Abstract

A nitride semiconductor device (1) comprises: a substrate (10); an n-type drift layer (12); a p-type block layer (14); a diffusion suppression layer (16); a side surface (20b) and a bottom surface (20a) of a gate opening (20), and an electron transport layer (22) and an electron supply layer (24); a gate electrode (32); a source electrode (34); and a drain electrode (36).

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors have a larger band gap, a higher breakdown field, and a higher saturated drift velocity than compound semiconductor materials such as Si semiconductors or GaAs, and are therefore used in electronic devices such as high-voltage power devices and high-speed, high-power transistors.

[0003] Electronic device structures formed using nitride semiconductors can be divided into lateral structures, in which current flows laterally, and vertical structures, in which current flows vertically. Lateral structures include an AlGaN / GaN heterostructure formed on a heterogeneous substrate, such as a sapphire substrate, SiC substrate, or Si substrate. Low-cost, high-speed devices have been realized by passing current through a two-dimensional electron gas layer generated near the AlGaN / GaN heterointerface. On the other hand, vertical structures can handle larger currents than lateral structures because they allow current to flow throughout the entire device. However, because vertical structures pass current parallel to crystal defects such as dislocations, they require significantly reduced defect density compared to lateral structures. To reduce defect density, vertical structures are typically fabricated on GaN substrates.

[0004] Patent Documents 1 and 2 and Non-Patent Document 1 disclose vertical FETs (Field Effect Transistors) formed using GaN-based semiconductor materials. In the vertical FETs disclosed in Patent Documents 1 and 2, a transistor operation is achieved by opening and closing a channel made of a two-dimensional electron gas layer generated at an AlGaN / GaN heterointerface using a gate voltage.

[0005] Patent No. 6511645 Patent No. 6755892

[0006] Zhu et al., “Vertical GaN Power Transistor With Intrinsic Reverse Conduction and Low Gate Charge for High-Performance Power Conversion”, IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 7, No. 3, September 2019

[0007] There is room for improvement in reducing the on-resistance compared to conventional nitride semiconductor devices.

[0008] Therefore, the present disclosure provides a nitride semiconductor device with low on-resistance.

[0009] a first n-type nitride semiconductor layer provided above the substrate; a first p-type nitride semiconductor layer provided above the first n-type nitride semiconductor layer; a first nitride semiconductor layer provided above the first p-type nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from below so as to cover a side surface and a bottom surface of a first opening that penetrates the first p-type nitride semiconductor layer and an upper surface of the first nitride semiconductor layer; a gate electrode provided above the electron supply layer; a source electrode provided at a position separated from the gate electrode in a plan view of the substrate; and a drain electrode provided below the substrate, wherein the first nitride semiconductor layer contains indium.

[0010] According to the present disclosure, it is possible to provide a nitride semiconductor device with low on-resistance.

[0011] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment of the present disclosure. FIG. 2A is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the first embodiment of the present disclosure. FIG. 2B is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the first embodiment of the present disclosure. FIG. 2C is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the first embodiment of the present disclosure. FIG. 2D is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a second modification of the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a third modification of the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a second embodiment of the present disclosure. FIG. 7A is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the second embodiment of the present disclosure. FIG. 7B is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the second embodiment of the present disclosure. FIG. 7C is a cross-sectional view for illustrating a step included in a method for manufacturing a nitride semiconductor device according to the second embodiment of the present disclosure. 7D is a cross-sectional view illustrating a step included in a method for manufacturing a nitride semiconductor device according to a second embodiment of the present disclosure. FIG. 8 is a cross-sectional view of a nitride semiconductor device according to a first modification of the second embodiment of the present disclosure. FIG. 9 is a cross-sectional view of a nitride semiconductor device according to a second modification of the second embodiment of the present disclosure. FIG. 10 is a cross-sectional view of a nitride semiconductor device according to a third modification of the second embodiment of the present disclosure. FIG. 11 is a cross-sectional view of a nitride semiconductor device according to a fourth modification of the first embodiment of the present disclosure. FIG. 12 is a cross-sectional view of a nitride semiconductor device according to a fifth modification of the first embodiment of the present disclosure.

[0012] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the conventional nitride semiconductor devices described in the "Background Art" section have the following problems.

[0013] The vertical FETs disclosed in Patent Documents 1 and 2 and Non-Patent Document 1 utilize two-dimensional electron gas generated near the AlGaN / GaN heterojunction interface as a channel. By utilizing two-dimensional electron gas with a high carrier concentration for connection to the source electrode, it is expected that a low on-resistance can be achieved.

[0014] However, the inventors analyzed the cross-sectional carrier concentration of a conventional vertical FET and found that the desired high-carrier-concentration two-dimensional electron gas was not generated. In other words, the conventional vertical FET has a problem in that it is not possible to achieve low on-resistance.

[0015] In order to solve the above problems, a nitride semiconductor device according to a first aspect of the present disclosure includes: a substrate; a first n-type nitride semiconductor layer provided above the substrate; a first p-type nitride semiconductor layer provided above the first n-type nitride semiconductor layer; a first nitride semiconductor layer provided above the first p-type nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from below so as to cover a side surface and a bottom surface of a first opening that penetrates the first p-type nitride semiconductor layer and an upper surface of the first nitride semiconductor layer; a gate electrode provided above the electron supply layer; a source electrode provided at a position separated from the gate electrode in a plan view of the substrate; and a drain electrode provided below the substrate, wherein the first nitride semiconductor layer contains indium.

[0016] As a result, the first nitride semiconductor layer containing indium can suppress the diffusion of p-type impurities contained in the first p-type nitride semiconductor layer into the electron transit layer, and the reduction in the carrier concentration of the two-dimensional electron gas generated at the interface between the electron supply layer and the electron transit layer can be suppressed, thereby reducing the on-resistance of the nitride semiconductor device.

[0017] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the first nitride semiconductor layer covers the side and bottom surfaces of the first opening.

[0018] This allows the first nitride semiconductor layer to cover the top and side surfaces of the first p-type nitride semiconductor layer, thereby enhancing the effect of suppressing the diffusion of p-type impurities contained in the first p-type nitride semiconductor layer, thereby further reducing the on-resistance of the nitride semiconductor device.

[0019] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the first opening further penetrates the first nitride semiconductor layer.

[0020] This allows, for example, the first nitride semiconductor layer to contact and cover the upper surface of the first p-type nitride semiconductor layer, thereby enhancing the effect of suppressing the diffusion of p-type impurities contained in the first p-type nitride semiconductor layer, and thus further reducing the on-resistance of the nitride semiconductor device.

[0021] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to the third aspect, further comprising a second nitride semiconductor layer provided between the first nitride semiconductor layer and the electron transit layer, and the first opening further penetrates the second nitride semiconductor layer.

[0022] This allows the second nitride semiconductor layer to suppress the desorption of indium from the first nitride semiconductor layer and the surface roughening of the first nitride semiconductor layer, thereby enhancing the effect of the first nitride semiconductor layer in suppressing the diffusion of p-type impurities, and thereby reducing the on-resistance of the nitride semiconductor device.

[0023] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fourth aspects, further comprising a second p-type nitride semiconductor layer provided between the electron supply layer and the gate electrode.

[0024] This reduces the carrier concentration directly below the gate electrode, shifting the threshold voltage of the transistor to the positive side, and thus the nitride semiconductor device according to this embodiment can be easily realized as a normally-off FET.

[0025] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to the fifth aspect, further comprising a third nitride semiconductor layer provided between the electron supply layer and the second p-type nitride semiconductor layer, wherein the third nitride semiconductor layer contains indium.

[0026] As a result, the third nitride semiconductor layer containing indium can suppress the diffusion of p-type impurities contained in the second p-type nitride semiconductor layer into the electron transit layer, and the reduction in the carrier concentration of the two-dimensional electron gas generated at the interface between the electron supply layer and the electron transit layer can be suppressed, thereby reducing the on-resistance of the nitride semiconductor device.

[0027] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to the sixth aspect, wherein the third nitride semiconductor layer includes a plurality of stacked layers, and at least one of the plurality of layers includes indium.

[0028] This allows a quantum well structure to be formed using multiple stacked layers, and the on-resistance can be further reduced by the photon recycling effect, which effectively utilizes the light generated when a voltage is applied to the gate electrode.

[0029] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to seventh aspects, further comprising a fourth nitride semiconductor layer provided between the first n-type nitride semiconductor layer and the first p-type nitride semiconductor layer, wherein the fourth nitride semiconductor layer contains indium.

[0030] This allows the fourth nitride semiconductor layer to absorb light generated when a voltage is applied to the gate electrode, and increases the carrier concentration through photoelectric conversion in the fourth nitride semiconductor layer, thereby further reducing the on-resistance.

[0031] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0032] It should be noted that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement positions, and connection configurations shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, the embodiments of the present disclosure are not limited to the current independent claims, but may be expressed by other independent claims. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0033] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0034] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0035] In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0036] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided is considered to be "upper" or "upper side", and the side of the substrate on which the drain electrode is provided is considered to be "lower" or "lower side".

[0037] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0038] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0039] In addition, in this specification, "A and B overlap in a plan view" means that at least a part of A overlaps with at least a part of B. In other words, this includes cases where only a part of A overlaps with only a part of B, where all of A overlaps with B, where all of B overlaps with A, and where A and B completely overlap with each other.

[0040] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0041] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN, where x, 1-xy, and y represent the composition ratios of Al, Ga, and In, respectively.

[0042] First Embodiment [Configuration] First, the configuration of a nitride semiconductor device according to a first embodiment will be described with reference to FIG.

[0043] 1 is a cross-sectional view of a nitride semiconductor device 1 according to a first embodiment. In FIG. 1, each component, such as a semiconductor layer and an electrode, is shaded with diagonal lines to indicate a cross section. However, the diagonal lines indicating a cross section have been omitted from the electron transit layer 22 and the electron supply layer 24 to make it easier to see the two-dimensional electron gas 26, which is represented by a dashed line.

[0044] The nitride semiconductor device 1 according to this embodiment is a normally-off FET. In the nitride semiconductor device 1, for example, the source electrode 34 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 36. The potential applied to the drain electrode 36 is, for example, not limited to, 100 V or more and 1200 V or less. When the nitride semiconductor device 1 is in an off state, 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32. When the nitride semiconductor device 1 is in an on state, a positive potential (e.g., +5 V) is applied to the gate electrode 32. Note that the nitride semiconductor device 1 may be a normally-on FET.

[0045] 1 , the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a block layer 14, a diffusion suppression layer 16, an intermediate layer 18, a gate opening 20, an electron transit layer 22, an electron supply layer 24, a threshold adjustment layer 28, a source opening 30, a gate electrode 32, a source electrode 34, and a drain electrode 36. At the interface between the electron transit layer 22 and the electron supply layer 24, a two-dimensional electron gas (2DEG) 26 that functions as a channel is generated.

[0046] Each of the components included in the nitride semiconductor device 1 will be described in detail below.

[0047] The substrate 10 is made of a nitride semiconductor and has a rectangular shape in plan view, for example, but is not limited to this.

[0048] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 １８ cm －３n ＋ The substrate is made of n-type GaN. Note that n-type and p-type indicate the conductivity type of the semiconductor. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor. － The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., a so-called lightly doped state. ＋ Type and n － Both types are examples of n-type, and may be referred to as n-type without distinction. ＋ Type and p － The same is true for types.

[0049] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0050] The drift layer 12 is an example of a first n-type nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, an n-type nitride semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The donor concentration of the drift layer 12 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ As an example, １６ cm －３ The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 １５ cm －３ 2 x 10 or more １７ cm －３ The drift layer 12 is provided in contact with, for example, the upper surface (main surface) of the substrate 10 .

[0051] The block layer 14 is an example of a first p-type nitride semiconductor layer provided above the drift layer 12. The block layer 14 has a thickness of 300 nm and a carrier concentration of 1×10 １７ cm －３The block layer 14 is a film made of p-type GaN, where p-type GaN is a p-type GaN film. The block layer 14 is provided in contact with the upper surface of the drift layer 12. The block layer 14 is formed on the drift layer 12 by crystal growth using, for example, MOVPE, HVPE, or the like.

[0052] Although the block layer 14 is formed by crystal growth, it may be formed, for example, by implanting magnesium (Mg) into the formed i-GaN. Furthermore, the block layer 14 may be an insulating layer obtained by implanting iron (Fe) or boron (B) instead of a p-type nitride semiconductor layer.

[0053] In this embodiment, as shown in FIG. 1 , the block layer 14 is in contact with the source electrode 34. Therefore, the block layer 14 is fixed to the source potential applied to the source electrode 34. This achieves a high breakdown voltage for the nitride semiconductor device 1. For example, when a reverse voltage is applied to the pn junction formed between the block layer 14 and the drift layer 12, specifically, when the drain electrode 36 has a higher potential than the source electrode 34, a depletion layer extends to the drift layer 12, thereby enabling a high breakdown voltage for the nitride semiconductor device 1. In this embodiment, the drain electrode 36 has a higher potential than the source electrode 34 in both the off state and the on state, except in the case of reverse conduction. This achieves a high breakdown voltage for the nitride semiconductor device 1.

[0054] The diffusion suppression layer 16 is an example of a first nitride semiconductor layer provided above the block layer 14. In the present embodiment, the diffusion suppression layer 16 is provided between the block layer 14 and the intermediate layer 18 in contact with each other. In a plan view of the substrate 10, a portion of the diffusion suppression layer 16 overlaps the source electrode 34, and another portion of the diffusion suppression layer 16 overlaps the gate electrode 32 or the threshold adjustment layer 28. In a plan view, the diffusion suppression layer 16 overlaps a portion of the two-dimensional electron gas 26 that is generated above the block layer 14 and parallel to the substrate 10, i.e., a portion through which the drain current flows laterally.

[0055] The diffusion suppression layer 16 contains indium (In). For example, the diffusion suppression layer 16 is a film made of undoped InGaN with a thickness of 5 nm. The composition ratio of In contained in the diffusion suppression layer 16 is, for example, 10%. The diffusion suppression layer 16 suppresses the upward diffusion of p-type impurities (specifically, Mg) contained in the block layer 14.

[0056] The diffusion suppression layer 16 may further contain Al. ｘ Al ｙ Ga １－ｘ－ｙ Alternatively, the diffusion suppression layer 16 may be a layer made of N. Note that as the Al composition ratio y increases and the In composition ratio x decreases, the lattice constant of the diffusion suppression layer 16 decreases. If the lattice constant of the diffusion suppression layer 16 is smaller than that of the block layer 14, piezoelectric charges are generated at the interface between the block layer 14 and the diffusion suppression layer 16 due to the piezoelectric effect, which causes an increase in leakage current and threshold voltage. For this reason, the lattice constant of the diffusion suppression layer 16 is required to be larger than that of GaN. Specifically, by making y<3x, the lattice constant of the diffusion suppression layer 16 can be made larger than that of GaN, thereby suppressing increases in leakage current and threshold voltage. Note that by making y<x, the effect of suppressing increases in leakage current and threshold voltage can be further enhanced.

[0057] The intermediate layer 18 is an example of a second nitride semiconductor layer provided between the diffusion suppression layer 16 and the electron transit layer 22. The intermediate layer 18 is a high-resistance layer having a higher resistance than the block layer 14. The intermediate layer 18 is, for example, a film made of undoped GaN (i-GaN) with a thickness of 150 nm. The intermediate layer 18 is provided in contact with both the diffusion suppression layer 16 and the electron transit layer 22. The intermediate layer 18 can suppress the separation of In contained in the diffusion suppression layer 16 and the surface roughness of the diffusion suppression layer 16.

[0058] The gate opening 20 is an example of a first opening that penetrates the block layer 14. Specifically, the gate opening 20 penetrates the intermediate layer 18, the diffusion suppression layer 16, and the block layer 14, and reaches the drift layer 12. A bottom surface 20a of the gate opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the block layer 14. The lower surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the main surface of the substrate 10. When the nitride semiconductor device 1 is on, a drain current flows between the drain electrode 36 and the source electrode 34 through the bottom surface 20a of the gate opening 20.

[0059] In this embodiment, the gate opening 20 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 20b of the gate opening 20 is inclined obliquely. As shown in FIG. 1 , the cross-sectional shape of the gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0060] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 90°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, which improves the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more likely it is that the gate opening 20 will not become too large, thereby enabling the nitride semiconductor device 1 to be miniaturized.

[0061] The electron transit layer 22 is an example of a first regrowth layer provided to cover the side surface 20 b and bottom surface 20 a of the gate opening 20 and the upper surface of the diffusion suppression layer 16. Specifically, a portion of the electron transit layer 22 is provided along the bottom surface 20 a and side surface 20 b of the gate opening 20, and another portion of the electron transit layer 22 is provided above the diffusion suppression layer 16 and on the upper surface of the intermediate layer 18. The electron transit layer 22 is, for example, a 150 nm-thick film made of undoped GaN. Note that although the electron transit layer 22 is assumed to be undoped, it may be partially made n-type by, for example, doping with Si.

[0062] The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20 a and the side surface 20 b of the gate opening 20. The electron transit layer 22 is in contact with each of the block layer 14, the diffusion suppression layer 16, and the intermediate layer 18 at the side surface 20 b of the gate opening 20. Furthermore, the electron transit layer 22 is in contact with the top surface of the intermediate layer 18.

[0063] The electron transit layer 22 has a channel region. Specifically, a two-dimensional electron gas 26 that serves as a channel is generated near the interface between the electron transit layer 22 and the electron supply layer 24. In FIG. 1 , the two-dimensional electron gas 26 is schematically illustrated by a dashed line. The two-dimensional electron gas 26 bends along the interface between the electron transit layer 22 and the electron supply layer 24, i.e., along the inner surface of the gate opening 20.

[0064] 1, an AlN layer with a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 24. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0065] The electron supply layer 24 is an example of a third regrowth layer provided to cover the side surface 20 b and bottom surface 20 a of the gate opening 20 and the upper surface of the diffusion suppression layer 16. The electron transit layer 22 and the electron supply layer 24 are provided in this order from the substrate 10 side. The electron supply layer 24 is, for example, a film made of undoped AlGaN with a thickness of 20 nm. The electron supply layer 24 is formed to a shape that conforms to the upper surface of the electron transit layer 22 and has a substantially uniform thickness.

[0066] The electron supply layer 24 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 24 and the electron transit layer 22. The electron supply layer 24 supplies electrons to a channel region (two-dimensional electron gas 26) formed in the electron transit layer 22.

[0067] The threshold adjustment layer 28 is an example of a second p-type nitride semiconductor layer provided between the electron supply layer 24 and the gate electrode 32. Specifically, the threshold adjustment layer 28 is disposed so as to be in direct contact with the upper surface of the electron supply layer 24 at a position overlapping the gate opening 20 in a plan view of the substrate 10. The threshold adjustment layer 28 and the source electrode 34 are disposed at a distance from each other and are electrically isolated from each other.

[0068] The threshold adjustment layer 28 has a thickness of 230 nm and a carrier concentration of 1×10 １９ cm －３ The thickness and carrier concentration of the threshold adjustment layer 28 are merely examples and can be changed as appropriate.

[0069] The provision of the threshold adjustment layer 28 raises the potential of the conduction band edge in the channel portion. This reduces the carrier concentration directly below the gate electrode 32, shifting the threshold voltage of the transistor to the positive side. This makes it easy to realize the nitride semiconductor device 1 as a normally-off FET. The threshold adjustment layer 28 may be a film made of p-type AlGaN.

[0070] The threshold adjustment layer 28 may not be provided, and the gate electrode 32 may be provided in contact with the upper surface of the electron supply layer 24. Alternatively, instead of the threshold adjustment layer 28, an insulating film such as a silicon nitride film, a silicon oxide film, or an aluminum oxide film may be provided between the gate electrode 32 and the electron supply layer 24.

[0071] The source opening 30 is an example of a second opening that penetrates the electron supply layer 24 and the electron transit layer 22 at a position away from the gate electrode 32 in a plan view of the substrate 10, and reaches the block layer 14. Specifically, the source opening 30 penetrates not only the electron supply layer 24 and the electron transit layer 22, but also the intermediate layer 18 and the diffusion suppression layer 16. In the present embodiment, the source opening 30 is provided at a position away from both the gate electrode 32 and the threshold adjustment layer 28 in a plan view of the substrate 10.

[0072] 1, the bottom surface 30a may be located lower than the lower surface of the diffusion suppression layer 16. The lower surface of the diffusion suppression layer 16 corresponds to the interface between the diffusion suppression layer 16 and the block layer 14. The bottom surface 30a is parallel to the main surface of the substrate 10, for example.

[0073] 1, the source opening 30 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 is perpendicular to the bottom surface 30a. In other words, the cross-sectional shape of the source opening 30 is rectangular.

[0074] Alternatively, the source opening 30 may be formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 may be obliquely inclined. For example, the cross-sectional shape of the source opening 30 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30b relative to the bottom surface 30a may be, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30b increases the contact area between the source electrode 34 and the electron transit layer 22 (two-dimensional electron gas 26), making it easier to achieve ohmic contact. The two-dimensional electron gas 26 is exposed at the side surface 30b of the source opening 30 and connected to the source electrode 34 at the exposed portion.

[0075] The provision of the source opening 30 reduces the ohmic contact resistance between the two-dimensional electron gas 26 functioning as a channel and the source electrode 34. That is, the on-resistance of the nitride semiconductor device 1 can be reduced. Furthermore, since the block layer 14 and the source electrode 34 can be electrically connected, the potential of the block layer 14 can be stabilized, thereby achieving effects such as improved breakdown voltage. Note that the source opening 30 may not be provided, and the source electrode 34 may be provided in contact with the upper surface of the electron supply layer 24 at a position away from the threshold adjustment layer 28.

[0076] The gate electrode 32 is provided above the electron supply layer 24. Specifically, the gate electrode 32 is provided in contact with the upper surface of the electron supply layer 24 at a position overlapping the gate opening 20 in a plan view of the substrate 10. The gate electrode 32 is provided at a position overlapping the bottom surface 20 a of the gate opening 20 in a plan view.

[0077] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 may be made of a material that forms ohmic contact with the p-type GaN layer, but is not limited thereto. A material that forms Schottky contact with the p-type GaN layer may also be used. For example, palladium (Pd), nickel (Ni)-based material, tungsten silicide (WSi), gold (Au), etc. may be used.

[0078] The source electrode 34 is provided to cover the source opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30. The source electrode 34 is electrically connected to the block layer 14 exposed at the bottom surface 30a of the source opening 30.

[0079] The source electrode 34 is in direct contact with the two-dimensional electron gas 26 at the side surface 30b of the source opening 30. This reduces the contact resistance between the source electrode 34 and the two-dimensional electron gas 26, thereby reducing the on-resistance of the nitride semiconductor device 1.

[0080] The source electrode 34 is formed using a conductive material such as a metal, and may be made of a material that can be ohmically connected to the n-type GaN layer by heat treatment, such as Ti / Al (a laminated structure of a Ti layer and an Al layer).

[0081] The drain electrode 36 is provided below the substrate 10. Specifically, the drain electrode 36 is provided in contact with the lower surface of the substrate 10.

[0082] The drain electrode 36 is formed using a conductive material such as a metal. As with the material of the source electrode 34, the material of the drain electrode 36 may be a material that makes ohmic contact with n-type GaN, such as Ti / Al.

[0083] As described above, in the nitride semiconductor device 1 according to this embodiment, the diffusion suppression layer 16 containing indium is provided between the p-type block layer 14 and the electron transit layer 22. The diffusion suppression layer 16 can suppress the diffusion of Mg from the block layer 14 to the electron transit layer 22, thereby suppressing a decrease in the carrier concentration of the two-dimensional electron gas 26. This allows for good contact between the source electrode 34 and the two-dimensional electron gas 26, thereby achieving a nitride semiconductor device 1 with low on-resistance.

[0084] In the first embodiment, the nitride semiconductor device 1 has been described as shown in Fig. 1, but the present invention is not limited to this. In the nitride semiconductor device 1 shown in Fig. 11, the diffusion suppression layer 16 is disposed between the intermediate layer 18 and the block layer 14 in the same manner as in the first embodiment.

[0085] 11 , the threshold adjustment layer 28 and the gate electrode 32 are provided at positions overlapping the side surface 20b of the gate opening 20 in a plan view, but this is not limiting. The threshold adjustment layer 28 and the gate electrode 32 may be provided so as not to overlap the gate opening 20 in a plan view. Specifically, the threshold adjustment layer 28 and the gate electrode 32 may be provided at positions overlapping the upper surface of the intermediate layer 18 outside the gate opening 20 in a plan view. The threshold adjustment layer 28 and the gate electrode 32 may be arranged on both sides of the gate opening 20 so as to sandwich the gate opening 20 therebetween in a plan view, like the source electrode 34. The threshold adjustment layer 28 does not have to be provided.

[0086] In this case, the electron supply layer 24 may be provided with a gate recess at a position overlapping the gate electrode 32 in a plan view. The gate recess is a recess provided in the upper surface of the electron supply layer 24. Since the thickness of the electron supply layer 24 is smaller at the bottom of the gate recess, it becomes easier to suppress the generation of 2DEG during the off state, and a normally-off state can be easily achieved. A threshold adjustment layer 28 is provided to cover the gate recess. If the threshold adjustment layer 28 is not provided, the gate electrode 32 is provided to cover the gate recess.

[0087] In this case, a first electrode 134 electrically isolated from the threshold adjustment layer 28 and the gate electrode 32 may be provided above the electron supply layer 24 at a position overlapping the bottom surface 20 a of the gate opening 20 in a plan view. The first electrode 134 is supplied with, for example, the same potential as that applied to the source electrode 34. For example, a through-hole may be provided in an insulating layer covering the first electrode 134, and a conductive via may be provided to electrically connect the first electrode 134 to a source wiring connecting the source electrode 34. A p-type nitride semiconductor layer 126 may be provided between the first electrode 134 and the electron supply layer 24. The p-type nitride semiconductor layer 126 is electrically isolated from the threshold adjustment layer 28 and the gate electrode 32. For example, the first electrode 134 and the p-type nitride semiconductor layer 126 are ohmically connected.

[0088] With this configuration, the electric field lines extending from the drain electrode 36 can be terminated at the first electrode 134 and the p-type nitride semiconductor layer 126, thereby reducing the parasitic capacitance Cgd between the gate and the drain. This shortens the rise and fall times of the voltage and current, thereby reducing switching loss. Furthermore, a nitride semiconductor device capable of high-speed operation can be realized. Since total loss is suppressed even during high-speed operation, a low-loss power device can be realized.

[0089] In the nitride semiconductor device 406 shown in FIG. 12, the diffusion suppressing layer 16 is disposed between the intermediate layer 18 and the blocking layer 14, similar to the first embodiment.

[0090] A gate recess structure is provided in the nitride semiconductor device 406. Specifically, the nitride semiconductor device 406 includes a threshold adjustment layer 928. Furthermore, a recess 924 is provided in the electron supply layer 24.

[0091] The recess 924 is provided at a position overlapping the gate electrode 432 in a plan view of the substrate 10. The recess 924 is formed, for example, by removing a part of the electron supply layer 24 by dry etching or the like.

[0092] The threshold adjustment layer 928 is provided so as to cover the recess 924. The threshold adjustment layer 928 contacts and covers the bottom and side surfaces of the recess 924. Note that the threshold adjustment layer 928 may not be provided, and the gate electrode 432 may be in contact with the bottom and side surfaces of the recess 924. Alternatively, an insulating film may be provided instead of the threshold adjustment layer 928.

[0093] The recess 924 is provided in an area narrower than the threshold adjustment layer 928 in a plan view. Specifically, the entire recess 924 is covered by the threshold adjustment layer 928, and the threshold adjustment layer 928 is in contact with a region of the electron supply layer 24 outside the recess 924. The recess 924 may be formed larger than the threshold adjustment layer 928 and the gate electrode 432 in a plan view. For example, the threshold adjustment layer 928 and the gate electrode 432 may cover the bottom surface of the recess 924 but not the side surface of the recess 924.

[0094] According to the above configuration, the carrier concentration directly below the gate electrode 432 can be reduced, and the threshold voltage of the transistor can be further shifted to the positive side. Therefore, the nitride semiconductor device 406 can be easily realized as a normally-off type FET.

[0095] Alternatively, instead of providing the recess 924, the electron supply layer 24 may be thickened in a portion other than the portion directly below the threshold adjustment layer 928 and the gate electrode 432. This makes it possible to reduce the on-resistance while achieving a threshold voltage equivalent to that of the nitride semiconductor device 401.

[0096] The recess 924 is formed by successively depositing nitride semiconductor films for the electron transit layer 22 and the electron supply layer 24 by a crystal regrowth process, followed by patterning into a predetermined shape. Specifically, an undoped GaN film serving as the base of the electron transit layer 22 and an undoped AlGaN film serving as the base of the electron supply layer 24 are successively deposited by MOVPE, HVPE, or the like. After deposition, a portion of the undoped AlGaN film is removed by etching to form the recess 924. Thereafter, a p-type AlGaN layer serving as the base of the threshold adjustment layer 928 and the p-type semiconductor layer 426 is deposited by MOVPE, HVPE, or the like. After deposition, a portion of the p-type AlGaN film is removed by etching to separate the threshold adjustment layer 928 and the p-type semiconductor layer 426. In other words, the nitride semiconductor device 406 can be fabricated by adding one additional regrowth process compared to conventional methods.

[0097] The bottom of the recess 924 is provided above the upper surface of the electron transit layer 22, but may penetrate the electron supply layer 24 and reach the electron transit layer 22. In this case, an undoped AlGaN film and a p-type AlGaN film are formed again in the subsequent crystal growth step, thereby forming a structure similar to that described above.

[0098] An electrode 434 is formed on the p-type semiconductor layer 426 and is electrically connected to the source electrode 34 .

[0099] Generally, InGaN crystals are characterized by the fact that InN is H ２ The etching reaction by the gas is large, which tends to cause non-uniformity in the In composition. ２The need to lower the ratio results in an increase in crystal defects. Therefore, it is considered difficult to utilize this in vertically structured devices that pass a large current in the vertical direction. In particular, forming an electron transit region above the InGaN layer and passing a current in the vertical direction parallel to the crystal defects increases resistance and leakage current during off-state operation. In contrast, in the nitride semiconductor device 1 according to this embodiment, a lateral current path is formed by the two-dimensional electron gas 26 above the diffusion suppression layer 16 made of InGaN. Therefore, a reduction in on-resistance can be achieved without being affected by non-uniform In composition and crystal defects.

[0100] [Manufacturing Method] Next, a manufacturing method of the nitride semiconductor device 1 according to this embodiment will be described with reference to Figures 2A to 2D. Figures 2A to 2D are cross-sectional views illustrating one step of the manufacturing method of the nitride semiconductor device 1 according to this embodiment.

[0101] 2A , an n-type GaN film 11, a p-type GaN film 13, an undoped InGaN film 15, and an undoped GaN film 17 are formed in this order by crystal growth using metal organic chemical vapor deposition (MOCVD) on a substrate 10. The n-type GaN film 11, the p-type GaN film 13, the undoped InGaN film 15, and the undoped GaN film 17 correspond to the drift layer 12, the block layer 14, the diffusion suppression layer 16, and the intermediate layer 18, respectively, and are nitride semiconductor films that form the basis of the corresponding layers.

[0102] Next, as shown in FIG. 2B , a gate opening 20 is formed. The gate opening 20 is formed into a predetermined shape by, for example, patterning using photolithography and dry etching. Specifically, the n-type GaN film 11 is partially exposed by removing a portion of each of the GaN film 17, the InGaN film 15, and the p-type GaN film 13 by etching. By performing etching to remove a portion of the n-type GaN film 11, it is possible to prevent the p-type GaN film 13 from remaining on the bottom surface 20 a of the gate opening 20. The n-type GaN film 11 from which a portion has been removed is the drift layer 12.

[0103] Next, as shown in FIG. 2C , an undoped GaN film 21, an undoped AlGaN film 23, and a p-type GaN film 27 are formed in this order by crystal regrowth using MOCVD. The GaN film 21, the AlGaN film 23, and the p-type GaN film 27 are formed in a curved shape along the bottom surface 20 a and the side surface 20 b of the gate opening 20. The GaN film 21, the AlGaN film 23, and the p-type GaN film 27 correspond to the electron transit layer 22, the electron supply layer 24, and the threshold adjustment layer 28, respectively, and are nitride semiconductor films that form the basis of the corresponding layers. Two-dimensional electron gas 26 is generated near the interface between the GaN film 21 and the AlGaN film 23. The two-dimensional electron gas 26 is formed as a channel layer in a curved shape along the bottom surface 20 a and the side surface 20 b of the gate opening 20. In this embodiment, the provision of InGaN film 15 can suppress upward diffusion of p-type impurities from p-type GaN film 13 during the regrowth process. Furthermore, the provision of GaN film 17 can suppress separation of In from InGaN film 15 and surface roughening of InGaN film 15 during temperature rise during the regrowth process.

[0104] 2D , the p-type GaN film 27 is etched away to leave a gate region, thereby forming a threshold adjustment layer 28. The gate region is a portion that overlaps with the gate opening 20 in a plan view of the substrate 10.

[0105] 1, the gate electrode 32, the source electrode 34, and the drain electrode 36 are each formed by depositing a conductive film by, for example, sputtering or vapor deposition, and then patterning the deposited conductive film.

[0106] The source electrode 34 is formed to cover the source opening 30 after the source opening 30 is formed. Like the gate opening 20, the source opening 30 is formed into a predetermined shape by, for example, photolithographic patterning and dry etching. Specifically, the AlGaN film 23, the GaN film 21, the GaN film 17, and the InGaN film 15 are removed by etching to partially expose the p-type GaN film 13. By performing etching to remove a portion of the p-type GaN film 13, it is possible to prevent the InGaN film 15 from remaining on the bottom surface 30 a of the source opening 30. By forming the gate opening 20 and the source opening 30, the AlGaN film 23, the GaN film 21, the GaN film 17, the InGaN film 15, and the p-type GaN film 13 become the electron supply layer 24, the electron transit layer 22, the intermediate layer 18, the diffusion suppression layer 16, and the block layer 14, respectively.

[0107] Through the above steps, the nitride semiconductor device 1 shown in Fig. 1 is manufactured. The above-described method for manufacturing the nitride semiconductor device 1 is merely an example, and may be modified as appropriate.

[0108] [Modifications] Next, a description will be given of several modifications of embodiment 1. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0109] <Modification 1> First, a description will be given of Modification 1. Modification 1 differs from Embodiment 1 mainly in that a diffusion suppressing layer is further provided between the electron supply layer 24 and the threshold adjustment layer 28.

[0110] 3 is a cross-sectional view of a nitride semiconductor device 2 according to a first modification of the first embodiment. As shown in Fig. 3, the nitride semiconductor device 2 includes a diffusion suppression layer 40 in addition to the configuration of the nitride semiconductor device 1 according to the first embodiment.

[0111] The diffusion suppression layer 40 is an example of a third nitride semiconductor layer provided between the electron supply layer 24 and the threshold adjustment layer 28. The diffusion suppression layer 40 contains indium (In). For example, the diffusion suppression layer 40 is a 5-nm-thick film made of undoped InGaN. The In composition ratio of the diffusion suppression layer 40 is, for example, 10%, and the diffusion suppression layer 40 suppresses downward diffusion of p-type impurities (specifically, Mg) contained in the threshold adjustment layer 28. The diffusion suppression layer 40 may further contain Al. The thickness and In composition ratio of the diffusion suppression layer 40 are merely examples and are not particularly limited.

[0112] The diffusion suppression layer 40 is formed by depositing an undoped InGaN film by crystal growth using MOCVD and patterning the deposited InGaN film into a predetermined shape. As shown in FIG. 2C , the InGaN film that forms the diffusion suppression layer 40 can be formed continuously from the AlGaN film 23 that forms the electron supply layer 24, after the AlGaN film 23 has been formed, and before the p-type GaN film 27 that forms the threshold adjustment layer 28 has been formed. The InGaN film is patterned by etching the p-type GaN film 27 and then the p-type GaN film 27. This allows the threshold adjustment layer 28 and the diffusion suppression layer 40 to have substantially the same shape in plan view. The diffusion suppression layer 40 may be formed larger than the threshold adjustment layer 28 in plan view.

[0113] In the nitride semiconductor device 2 according to this modification, the diffusion suppression layer 40 containing indium is provided, which can suppress the diffusion of Mg from the threshold adjustment layer 28 to the electron supply layer 24. Therefore, in addition to the reduction in on-resistance due to the diffusion suppression layer 16, it is possible to stabilize the threshold voltage of the nitride semiconductor device 2 and reduce gate leakage.

[0114] Next, a description will be given of Modification 2. Modification 2 differs from Modification 1 mainly in that the diffusion suppressing layer provided between the electron supply layer 24 and the threshold adjustment layer 28 has a laminated structure.

[0115] 4 is a cross-sectional view of a nitride semiconductor device 3 according to Modification 2 of Embodiment 1. As shown in Fig. 4, nitride semiconductor device 3 includes a diffusion suppressing layer 50 instead of diffusion suppressing layer 40 according to Modification 1.

[0116] The diffusion suppression layer 50 includes multiple stacked layers 51, 52, 53, 54, and 55. The multiple layers 51, 52, 53, 54, and 55 are stacked in this order from bottom to top. At least one of the multiple layers 51, 52, 53, 54, and 55 contains indium. Specifically, the diffusion suppression layer 50 has a quantum well structure. For example, the band gap of each of the layers 52 and 54 is larger than the band gap of each of the layers 51, 53, and 55. As an example, the layers 52 and 54 are each undoped GaN films with a thickness of 10 nm. The layers 51, 53, and 55 are each InGaN films with a thickness of 5 nm and an In composition of 10%. Note that the thickness and composition of each layer are merely examples and are not particularly limited. For example, each layer may contain Al. Furthermore, the number of layers included in the diffusion suppression layer 50 is not limited to five, but may be four or less, or six or more.

[0117] The diffusion suppression layer 50 is formed by alternately depositing undoped GaN films and undoped InGaN films by crystal growth using MOCVD, and then patterning the deposited GaN and InGaN films into a predetermined shape. The stacked film of GaN and InGaN films that forms the diffusion suppression layer 50 can be formed consecutively with the AlGaN film 23 that forms the electron supply layer 24, as shown in FIG. 2C , after the AlGaN film 23 that forms the electron supply layer 24 has been formed, but before the p-type GaN film 27 that forms the threshold adjustment layer 28 has been formed. The GaN and InGaN films are patterned by sequential etching following the etching of the p-type GaN film 27. This allows the threshold adjustment layer 28 and the diffusion suppression layer 50 to have substantially the same planar shape. The diffusion suppression layer 50 may be formed larger than the threshold adjustment layer 28 in planar view.

[0118] In the nitride semiconductor device 3 according to this modification, the diffusion suppression layer 50 containing indium is provided, thereby suppressing the diffusion of Mg from the threshold adjustment layer 28 to the electron supply layer 24. Therefore, in addition to the reduction in on-resistance due to the diffusion suppression layer 16, it is possible to stabilize the threshold voltage of the nitride semiconductor device 3 and reduce gate leakage. Even when the nitride semiconductor device 3 is operated for a long period of time, the provision of the multiple layers 51, 53, and 55 containing indium makes it possible to maintain a high Mg diffusion suppression effect. Therefore, the long-term reliability of the nitride semiconductor device 3 can be improved.

[0119] Furthermore, because the diffusion suppression layer 50 has a quantum well structure, it is possible to increase the light emission efficiency in the diffusion suppression layer 50 when a voltage is applied to the gate electrode 32. This makes it possible to actively utilize the photon recycling effect. Specifically, light generated in the diffusion suppression layer 50 is absorbed by the electron transit layer 22, and electrons generated by photoelectric conversion can further reduce the on-resistance.

[0120] <Modification 3> Next, a description will be given of Modification 3. Modification 3 differs from Modification 2 mainly in that a nitride semiconductor layer containing indium is provided between the drift layer 12 and the block layer 14.

[0121] 5 is a cross-sectional view of a nitride semiconductor device 4 according to Modification 3 of Embodiment 1. As shown in Fig. 5, the nitride semiconductor device 4 includes a light absorption layer 60 in addition to the configuration of the nitride semiconductor device 3 according to Modification 2.

[0122] The light absorbing layer 60 is an example of a fourth nitride semiconductor layer provided between the drift layer 12 and the block layer 14. The light absorbing layer 60 contains indium (In). For example, the light absorbing layer 60 is a film made of n-type InGaN with a thickness of 10 nm. The composition ratio of In contained in the light absorbing layer 60 is, for example, 10%. The concentration of n-type impurities contained in the light absorbing layer 60 is, for example, the same as that of the drift layer 12.

[0123] The light absorption layer 60 has a smaller band gap than the drift layer 12 and the electron transit layer 22. This allows photoelectric conversion of low-energy light. The light absorption layer 60 may further contain Al. The thickness and In composition ratio of the light absorption layer 60 are merely examples and are not particularly limited. The light absorption layer 60 may also be an undoped nitride semiconductor layer.

[0124] The light absorption layer 60 is formed by depositing an n-type InGaN film by crystal growth using MOCVD and patterning the deposited InGaN film into a predetermined shape. As shown in FIG. 2A , the InGaN film that forms the light absorption layer 60 can be formed continuously from the n-type GaN film 11 that forms the drift layer 12, after the formation of the n-type GaN film 11, and before the formation of the p-type GaN film 13 that forms the block layer 14. The InGaN film is patterned when forming the gate opening 20. As shown in FIG. 5 , the gate opening 20 penetrates the light absorption layer 60. Note that the gate opening 20 does not have to penetrate the light absorption layer 60. That is, the bottom surface 20 a of the gate opening 20 may be the upper surface of the light absorption layer 60.

[0125] In the nitride semiconductor device 4 according to this modification, the light absorption layer 60 is provided, which can increase the efficiency of absorbing light generated in the diffusion suppression layer 50. In other words, the photon recycling effect can be promoted, which can further reduce the on-resistance.

[0126] Second Embodiment Next, a second embodiment will be described.

[0127] The main difference between the second embodiment and the first embodiment is that a diffusion suppression layer is provided along the inner surface of the gate opening. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0128] [Configuration] First, the configuration of a nitride semiconductor device according to the second embodiment will be described with reference to FIG.

[0129] 6 is a cross-sectional view of a nitride semiconductor device 101 according to the present embodiment. As shown in Fig. 6, the nitride semiconductor device 101 includes a diffusion suppression layer 116 instead of the diffusion suppression layer 16 of the nitride semiconductor device 1 according to the first embodiment. Furthermore, the nitride semiconductor device 101 does not include the intermediate layer 18 of the nitride semiconductor device 1 according to the first embodiment.

[0130] The diffusion suppressing layer 116 corresponds to the diffusion suppressing layer 16, but is provided at a different position. Specifically, the diffusion suppressing layer 116 covers the side surface 20b and bottom surface 20a of the gate opening 20. The thickness and In composition ratio of the diffusion suppressing layer 116 are the same as those of the diffusion suppressing layer 16. Furthermore, various modifications that can be applied to the diffusion suppressing layer 16 can also be applied to the diffusion suppressing layer 116.

[0131] As described above, the nitride semiconductor device 101 according to this embodiment has the diffusion suppression layer 116 containing indium provided between the p-type block layer 14 and the electron transit layer 22. The diffusion suppression layer 116 can suppress the diffusion of Mg from the block layer 14 to the electron transit layer 22, thereby suppressing a decrease in the carrier concentration of the two-dimensional electron gas 26. This allows for good contact between the source electrode 34 and the two-dimensional electron gas 26, thereby achieving a nitride semiconductor device 101 with low on-resistance. In this embodiment, the diffusion suppression layer 116 covers not only the top surface of the block layer 14 but also the side surfaces of the block layer 14. This enhances the Mg diffusion suppression effect, thereby enhancing the on-resistance reduction effect.

[0132] [Manufacturing Method] Next, a manufacturing method of nitride semiconductor device 101 according to this embodiment will be described with reference to Figures 7A to 7D. Figures 7A to 7D are cross-sectional views illustrating one step of the manufacturing method of nitride semiconductor device 101 according to this embodiment.

[0133] 7A , an n-type GaN film 11 and a p-type GaN film 13 are formed in this order by crystal growth using MOCVD on a substrate 10. The n-type GaN film 11 and the p-type GaN film 13 correspond to the drift layer 12 and the block layer 14, respectively, and are nitride semiconductor films that form the bases of the corresponding layers.

[0134] Next, as shown in FIG. 7B , a gate opening 20 is formed. The gate opening 20 is formed into a predetermined shape by, for example, patterning using photolithography and dry etching. Specifically, a portion of the p-type GaN film 13 is removed by etching to partially expose the n-type GaN film 11. By performing etching to remove a portion of the n-type GaN film 11, it is possible to prevent the p-type GaN film 13 from remaining on the bottom surface 20 a of the gate opening 20. The n-type GaN film 11 from which a portion has been removed is the drift layer 12.

[0135] Next, as shown in FIG. 7C , an undoped InGaN film 115, an undoped GaN film 21, an undoped AlGaN film 23, and a p-type GaN film 27 are formed in this order by crystal regrowth using MOCVD. The InGaN film 115, the GaN film 21, the AlGaN film 23, and the p-type GaN film 27 are formed in curved shapes along the bottom surface 20 a and the side surface 20 b of the gate opening 20. The InGaN film 115, the GaN film 21, the AlGaN film 23, and the p-type GaN film 27 correspond to the diffusion suppression layer 116, the electron transit layer 22, the electron supply layer 24, and the threshold adjustment layer 28, respectively, and are nitride semiconductor films that form the basis of the corresponding layers. In this embodiment, the diffusion suppression layer 116 is formed by crystal regrowth after the gate opening 20 is formed. Two-dimensional electron gas 26 is generated near the interface between the GaN film 21 and the AlGaN film 23. The two-dimensional electron gas 26 is formed as a channel layer in a curved shape along the bottom surface 20a and side surface 20b of the gate opening 20.

[0136] 7D , the p-type GaN film 27 is etched away to leave a gate region, thereby forming a threshold adjustment layer 28. The gate region is a portion that overlaps with the gate opening 20 in a plan view of the substrate 10.

[0137] 6, the gate electrode 32, the source electrode 34, and the drain electrode 36 are each formed by depositing a conductive film by, for example, sputtering or vapor deposition, and then patterning the deposited conductive film.

[0138] The source electrode 34 is formed to cover the source opening 30 after the source opening 30 is formed. Like the gate opening 20, the source opening 30 is formed into a predetermined shape by, for example, photolithographic patterning and dry etching. Specifically, the AlGaN film 23, the GaN film 21, and the InGaN film 115 are removed by etching to partially expose the p-type GaN film 13. By performing etching to remove a portion of the p-type GaN film 13, it is possible to prevent the InGaN film 115 from remaining on the bottom surface 30 a of the source opening 30. By forming the gate opening 20 and the source opening 30, the AlGaN film 23, the GaN film 21, the InGaN film 115, and the p-type GaN film 13 become the electron supply layer 24, the electron transit layer 22, the diffusion suppression layer 116, and the block layer 14, respectively.

[0139] Through the above steps, the nitride semiconductor device 101 shown in Fig. 6 is manufactured. The above-described method for manufacturing the nitride semiconductor device 101 is merely an example, and may be modified as appropriate.

[0140] [Modifications] Next, a description will be given of several modifications of embodiment 2. The following description will focus on the differences from embodiment 2, and the description of commonalities will be omitted or simplified.

[0141] <Modification 1> First, a description will be given of Modification 1. Modification 1 differs from Embodiment 2 mainly in that a diffusion suppressing layer is further provided between the electron supply layer 24 and the threshold adjustment layer 28.

[0142] 8 is a cross-sectional view of a nitride semiconductor device 102 according to a first modification of the second embodiment. As shown in Fig. 8, the nitride semiconductor device 102 includes a diffusion suppression layer 40 in addition to the configuration of the nitride semiconductor device 101 according to the second embodiment.

[0143] The diffusion suppression layer 40 is an example of a third nitride semiconductor layer provided between the electron supply layer 24 and the threshold adjustment layer 28. The diffusion suppression layer 40 is the same as the diffusion suppression layer 40 included in the nitride semiconductor device 2 according to the first modification of the first embodiment.

[0144] The nitride semiconductor device 102 according to this modification is provided with the diffusion suppression layer 40 containing indium, which can suppress the diffusion of Mg from the threshold adjustment layer 28 to the electron supply layer 24. Therefore, in addition to the reduction in on-resistance due to the diffusion suppression layer 116, it is possible to stabilize the threshold voltage of the nitride semiconductor device 102 and reduce gate leakage.

[0145] Next, a description will be given of Modification 2. Modification 2 differs from Modification 1 mainly in that the diffusion suppressing layer provided between the electron supply layer 24 and the threshold adjustment layer 28 has a laminated structure.

[0146] 9 is a cross-sectional view of a nitride semiconductor device 103 according to Modification 2 of Embodiment 2. As shown in Fig. 9, nitride semiconductor device 103 includes a diffusion suppressing layer 50 instead of diffusion suppressing layer 40 according to Modification 1.

[0147] Diffusion suppressing layer 50 includes a plurality of stacked layers 51, 52, 53, 54, and 55. At least one of layers 51, 52, 53, 54, and 55 contains indium. Diffusion suppressing layer 50 is the same as diffusion suppressing layer 50 according to the second modification of the first embodiment.

[0148] In the nitride semiconductor device 103 according to this modification, the diffusion suppression layer 50 containing indium is provided, thereby suppressing diffusion of Mg from the threshold adjustment layer 28 to the electron supply layer 24. Therefore, in addition to the reduction in on-resistance due to the diffusion suppression layer 116, it is possible to stabilize the threshold voltage of the nitride semiconductor device 103 and reduce gate leakage. Even when the nitride semiconductor device 103 is operated for a long period of time, the provision of the multiple layers 51, 53, and 55 containing indium makes it possible to maintain a high Mg diffusion suppression effect. Therefore, the long-term reliability of the nitride semiconductor device 103 can be improved.

[0149] Furthermore, because the diffusion suppression layer 50 has a quantum well structure, it is possible to increase the light emission efficiency in the diffusion suppression layer 50 when a voltage is applied to the gate electrode 32. This makes it possible to actively utilize the photon recycling effect. Specifically, light generated in the diffusion suppression layer 50 is absorbed by the electron transit layer 22, and electrons generated by photoelectric conversion can further reduce the on-resistance.

[0150] <Modification 3> Next, a description will be given of Modification 3. Modification 3 differs from Modification 2 mainly in that a nitride semiconductor layer containing indium is provided between the drift layer 12 and the block layer 14.

[0151] 10 is a cross-sectional view of a nitride semiconductor device 104 according to Modification 3 of Embodiment 2. As shown in Fig. 10, the nitride semiconductor device 104 includes a light absorption layer 60 in addition to the configuration of the nitride semiconductor device 103 according to Modification 2.

[0152] The light absorbing layer 60 is an example of a fourth nitride semiconductor layer provided between the drift layer 12 and the block layer 14. The light absorbing layer 60 is the same as the light absorbing layer 60 according to the third modification of the first embodiment.

[0153] In the nitride semiconductor device 104 according to this modification, the light absorption layer 60 is provided, which can increase the efficiency of absorbing light generated in the diffusion suppression layer 50. In other words, the photon recycling effect can be promoted, which can further reduce the on-resistance.

[0154] While nitride semiconductor devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0155] For example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) gradually decreases from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer may be two-layered, with a layer with a low donor concentration disposed below the block layer and a layer with a high donor concentration disposed on the substrate side. By providing a gate opening 20 that penetrates the layer with a low donor concentration, current flows through the layer with a high donor concentration through the gate opening 20 when the transistor is on, thereby reducing the on-resistance. Conversely, when the transistor is off, a high electric field is maintained by the layer with a low donor concentration, thereby achieving both low on-resistance and high breakdown voltage.

[0156] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0157] The nitride semiconductor device according to the present disclosure is useful, for example, as a power transistor used in a power supply circuit, an inverter circuit, or the like of an appliance.

[0158] 1, 2, 3, 4, 101, 102, 103, 104 Nitride semiconductor device 10 Substrate 11 n-type GaN film 12 Drift layer 13, 27 P-type GaN film 14 Block layer 15, 115 InGaN film 16, 40, 50, 116 Diffusion suppression layer 17, 21 GaN film 18 Intermediate layer 20 Gate opening 20a, 30a Bottom surface 20b, 30b Side surface 22 Electron transit layer 23 AlGaN film 24 Electron supply layer 26 Two-dimensional electron gas 28 Threshold adjustment layer 30 Source opening 32 Gate electrode 34 Source electrode 36 Drain electrode 51, 52, 53, 54, 55 Layer 60 Light absorption layer

Claims

1. A nitride semiconductor device comprising: a substrate; a first n-type nitride semiconductor layer provided above the substrate; a first p-type nitride semiconductor layer provided above the first n-type nitride semiconductor layer; a first nitride semiconductor layer provided above the first p-type nitride semiconductor layer; an electron transit layer and an electron supply layer provided in this order from below so as to cover the side and bottom surfaces of a first opening that penetrates the first p-type nitride semiconductor layer and an upper surface of the first nitride semiconductor layer; a gate electrode provided above the electron supply layer; a source electrode provided at a position separated from the gate electrode in a plan view of the substrate; and a drain electrode provided below the substrate, wherein the first nitride semiconductor layer contains indium.

2. The nitride semiconductor device according to claim 1, wherein said first nitride semiconductor layer covers the side and bottom surfaces of said first opening.

3. The nitride semiconductor device according to claim 1, wherein the first opening further penetrates through the first nitride semiconductor layer.

4. The nitride semiconductor device according to claim 3, further comprising a second nitride semiconductor layer provided between said first nitride semiconductor layer and said electron transit layer, and said first opening further penetrates said second nitride semiconductor layer.

5. The nitride semiconductor device according to claim 1, further comprising a second p-type nitride semiconductor layer provided between said electron supply layer and said gate electrode.

6. The nitride semiconductor device according to claim 5, further comprising a third nitride semiconductor layer provided between said electron supply layer and said second p-type nitride semiconductor layer, said third nitride semiconductor layer containing indium.

7. The nitride semiconductor device according to claim 6, wherein the third nitride semiconductor layer includes a plurality of stacked layers, and at least one of the plurality of layers includes indium.

8. The nitride semiconductor device according to any one of claims 1 to 4, further comprising a fourth nitride semiconductor layer provided between the first n-type nitride semiconductor layer and the first p-type nitride semiconductor layer, wherein the fourth nitride semiconductor layer contains indium.

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