Semiconductor apparatus

Abstract

This semiconductor apparatus includes: an active region provided on the main surface of an SiC chip; an outer peripheral region surrounding the periphery of the active region; a semiconductor region including a base region extending over the active region and the outer peripheral region, and a cap region that is formed in a surface layer part of the base region in at least the active region and that has a higher impurity concentration than the base region; a device structure that is formed in the active region, and that includes a body region of a second conductivity type formed in a surface layer part of the semiconductor region and includes a source region of a first conductivity type formed in a surface layer part of the body region; an outer well region of the second conductivity type formed in the surface layer part of the semiconductor region in the outer peripheral region; and a field stop region that is formed outward of the outer well region, has a higher impurity concentration than the base region, and has the same depth as the cap region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-025724 filed with the Japan Patent Office on February 22, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to SiC semiconductor devices.

[0003] Patent Document 1 (US2008 / 0277669A1) discloses a semiconductor device having a termination structure in the outer peripheral region of a drift layer.

[0004] US Patent Application Publication No. 2008 / 0277669

[0005] an outer well region of the second conductivity type formed in the outer periphery of the semiconductor region; and a field stop region formed outside the outer well region, the field stop region having a higher impurity concentration than the base region and having the same depth as the cap region.

[0006] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example of a chip layout. FIG. 4 is a perspective view showing an example of a chip layout. FIG. 5 is an enlarged plan view showing a main portion of a first main surface shown in FIG. 3 . FIG. 6 is an enlarged plan view showing a main portion of a first main surface shown in FIG. 3 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6 . FIG. 10 is a cross-sectional view showing a cross-sectional structure of the outer peripheral region taken along line XX in FIG. 1 . FIG. 11 is an enlarged cross-sectional view of a region shown in FIG. 10 . FIG. 12 is a graph showing an example of a concentration gradient of p-type impurities in a region taken along line XII-XII in FIG. 9 . FIG. 13 is a graph showing an example of a concentration gradient of p-type impurities in a region taken along line XIII-XIII in FIG. 11 . 14 is a graph showing an example of a concentration gradient of n-type impurities in a region along line XIV-XIV shown in FIG. 9 . FIG. 15 is a graph showing an example of a concentration gradient of n-type impurities in a region along line XV-XV shown in FIG. 11 . FIG. 16 is a cross-sectional view showing a field stop region according to a second embodiment. FIG. 17 is a cross-sectional view showing an outer well region according to a second embodiment. FIG. 18 is a cross-sectional view showing an outer well region according to a third embodiment. FIG. 19 is a cross-sectional view showing an outer well region according to a fourth embodiment. FIG. 20 is a cross-sectional view showing an outer well region according to a fifth embodiment. FIG. 21 is a graph showing a concentration gradient of an outer well region according to the second embodiment. FIG. 22 is a plan view showing an example of a chip layout of a semiconductor device according to a second embodiment of the present disclosure. FIG. 23 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 22 . FIG. 24 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 22 . FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 23 . Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 23. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 24. Fig. 28 is a cross-sectional view of a main portion of a semiconductor device according to a third embodiment of the present disclosure. Fig. 29 is a cross-sectional view of a main portion of a semiconductor device according to a fourth embodiment of the present disclosure.

[0007] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0012] 1 to 4, a semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0013] Semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0015] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0020] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0021] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0022] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0023] The semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "base region (layer)," a "semiconductor region (layer)," a "drain region (layer)," or the like.

[0024] The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0025] The first semiconductor region 6 may have a thickness T1 of 10 μm to 500 μm inclusive. The thickness T1 of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm to 50 μm inclusive, 50 μm to 100 μm inclusive, 100 μm to 150 μm inclusive, 150 μm to 200 μm inclusive, 200 μm to 300 μm inclusive, 300 μm to 400 μm inclusive, and 400 μm to 500 μm inclusive.

[0026] The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region closer to the first main surface 3 than the first semiconductor region 6 in a cross-sectional view, and is electrically connected to the first semiconductor region 6.

[0027] The second semiconductor region 7 extends in a layered form along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0028] The second semiconductor region 7 (epitaxial layer) has the aforementioned off direction and off angle. The second semiconductor region 7 preferably has a thickness T2 that is less than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be greater than the thickness T1 of the first semiconductor region 6.

[0029] The thickness T2 of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness T2 of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0030] The semiconductor device 1A includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0031] The active region 8 is set to a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0032] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in plan view. The peripheral region 9 extends in a strip shape along the active region 8 in plan view and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0033] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in the active region 8. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like.

[0034] The plurality of gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of gate structures 15 are arranged at intervals in a first direction X (= m-axis direction) in a plan view, and each extends in a band shape in a second direction Y (= a-axis direction). The plurality of gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0035] The semiconductor device 1A includes a p-type outer well region 40 formed in the peripheral region 9. The outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43.

[0036] 3 and 4 , the first outer well region 42 is a quadrangular ring-shaped region defined by a thick solid line and a thick dashed line. The first outer well region 42 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the first outer well region 42 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds a plurality of gate structures 15.

[0037] The first outer well region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). In this embodiment, the first outer well region 42 is formed in the peripheral region 9 and surrounds the active region 8.

[0038] 3 and 4 , each of the multiple second outer well regions 43 is indicated by a single solid line. Each of the multiple second outer well regions 43 has a portion extending in the first direction X and a portion extending in the second direction Y. In this embodiment, each second outer well region 43 is formed in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view, and surrounds the first outer well region 42.

[0039] Each of the plurality of second outer well regions 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). In this embodiment, the plurality of second outer well regions 43 are arranged in the outer periphery region 9 at intervals outward from the first outer well region 42.

[0040] The semiconductor device 1A includes an n-type field stop region 12 formed in the peripheral region 9. With reference to FIGS. 3 and 4 , the field stop region 12 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the field stop region 12 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the plurality of second outer well regions 43. The field stop region 12 is disposed spaced outward from the plurality of second outer well regions 43 and spaced inward from the end faces (first to fourth side faces 5A to 5D) of the chip 2.

[0041] The semiconductor device 1A includes a p-type voltage relaxation region 60 formed in the peripheral region 9. The voltage relaxation region 60 may also be referred to as an "edge voltage relaxation region." Referring to FIGS. 3 and 4 , the voltage relaxation region 60 has a portion extending in the first direction X and a portion extending in the second direction Y. In this embodiment, the voltage relaxation region 60 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the field stop region 12. The voltage relaxation region 60 is positioned outwardly and spaced apart from the field stop region 12 and is exposed from the edge faces (first to fourth side faces 5A to 5D) of the chip 2. The voltage relaxation region 60 is exposed from the edge faces of the chip 2 along its entire periphery. In this embodiment, the voltage relaxation region 60 is integrally exposed from both the first main surface 3 and the edge faces (first to fourth side faces 5A to 5D) at the peripheral corners on the first main surface 3 side of the chip 2.

[0042] The semiconductor device 1A includes an insulating interlayer film 47 formed on the first main surface 3. The interlayer film 47 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0043] The semiconductor device 1A includes a source electrode 51 disposed on the first main surface 3. The source electrode 51 is a terminal electrode to which a source potential is applied from the outside. The source electrode 51 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. The source electrode 51 is disposed on a portion of the interlayer film 47 that covers the active region 8.

[0044] In this embodiment, the source electrode 51 has a first pad portion 51 a, a second pad portion 51 b, and a third pad portion 51 c. The first pad portion 51 a has a relatively large planar area and forms the main body of the source electrode 51. In this embodiment, the first pad portion 51 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0045] The second pad portion 51b has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from one end of the first pad portion 51a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 51c has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from the other end of the first pad portion 51a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 51b in the second direction Y.

[0046] The plane area of ​​the third pad portion 51c may be approximately equal to the plane area of ​​the second pad portion 51b. The plane area of ​​the third pad portion 51c may be larger than the plane area of ​​the second pad portion 51b, or may be smaller than the plane area of ​​the second pad portion 51b. Either or both of the second pad portion 51b and the third pad portion 51c may be used as a terminal portion for monitoring current.

[0047] The source electrode 51 does not necessarily have to have both the second pad portion 51 b and the third pad portion 51 c at the same time. The source electrode 51 may have only one of the second pad portion 51 b and the third pad portion 51 c. The source electrode 51 may be composed of only the first pad portion 51 a, and may not have both the second pad portion 51 b and the third pad portion 51 c.

[0048] The semiconductor device 1A includes a source wiring 56 arranged around the source electrode 51 on the interlayer film 47. The same potential (source potential) as the potential (source potential) applied to the source electrode 51 is applied to the source wiring 56. The source wiring 56 may also be referred to as a "termination electrode (wiring)," "wiring," "first wiring," "finger electrode," "source finger," or the like.

[0049] The source wiring 56 has a wiring width less than the electrode width of the source electrode 51, and is selectively routed on the interlayer film 47. In this embodiment, the source wiring 56 is drawn from the source electrode 51 (first pad portion 51 a) to the fourth side surface 5D. The source wiring 56 is drawn from the active region 8 to the peripheral region 9.

[0050] The source wiring 56 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8). In this embodiment, the source wiring 56 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (the active region 8). The source wiring 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The source wiring 56 may be either ended or endless.

[0051] The semiconductor device 1A includes a gate electrode 57 disposed on the first main surface 3. The gate electrode 57 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 57 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like.

[0052] The gate electrode 57 is disposed on a portion of the interlayer film 47 that covers the active region 8, with a gap between it and the source electrode 51. In this embodiment, the gate electrode 57 is disposed in a region on the third side surface 5C side of the first pad portion 51a, and faces the first pad portion 51a in the first direction X. The gate electrode 57 is interposed in a region between the second pad portion 51b and the third pad portion 51c, and faces both the second pad portion 51b and the third pad portion 51c in the second direction Y.

[0053] The gate electrode 57 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 57 has a planar area less than the planar area of ​​the source electrode 51. The gate electrode 57 has a planar area less than the planar area of ​​the first pad portion 51a. The gate electrode 57 may also have a planar area less than the planar area of ​​the second pad portion 51b (third pad portion 51c).

[0054] The semiconductor device 1A includes a gate wiring 58 extending from the gate electrode 57 onto the first main surface 3. The gate wiring 58 may also be referred to as a "wiring," a "second wiring," a "finger electrode," a "gate finger," or the like. The gate wiring 58 transmits the gate potential applied to the gate electrode 57 to other regions.

[0055] The gate wiring 58 is drawn out from the gate electrode 57 onto the portion of the interlayer film 47 that covers the active region 8, and is routed to the region between the source electrode 51 and the source wiring 56 at a distance from the source electrode 51 and the source wiring 56.

[0056] The gate wiring 58 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y, and intersects (specifically, orthogonally) with ends (both ends in this embodiment) of the plurality of gate structures 15. In this embodiment, the gate wiring 58 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 51.

[0057] The semiconductor device 1A includes a drain electrode 59 covering the second main surface 4. The drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 59 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0058] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 59 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0059] A breakdown voltage that can be applied between source electrode 51 and drain electrode 59 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0060] FIG. 5 is an enlarged plan view showing a main portion of the first main surface 3 shown in FIG. 3 . FIG. 6 is an enlarged plan view showing a main portion of the first main surface 3 shown in FIG. 3 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6 . FIG. 10 is a cross-sectional view showing the cross-sectional structure of the peripheral region 9 taken along line XX in FIG. 1 . FIG. 11 is an enlarged cross-sectional view of a region shown in FIG. 10 . FIGS. 9 to 11 show the outer well region 40 according to a first embodiment of the semiconductor device 1A. In FIG. 11 , in order to clarify the structure of the peripheral portion of the chip 2, a portion between the active region 8 and the peripheral region 9 is omitted by a wavy line, and the peripheral portion of the chip 2 is shown enlarged.

[0061] The transistor structure Tr formed in the active region 8 of the semiconductor device 1A and the configuration within the peripheral region 9 will be described with reference to FIGS.

[0062] The semiconductor device 1A includes a p-type body region 10 formed in the active region 8 (inner portion of the first main surface 3) in a surface layer portion of the first main surface 3. The body region 10 may also be referred to as an "impurity region," a "channel region," or the like. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 10 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7. The body region 10 has a p-type impurity concentration of, for example, 1×10 １７ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0063] 10 , the body region 10 is formed in the inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. In this embodiment, the body region 10 is formed throughout the active region 8. The body region 10 is formed in the surface layer portion of the second semiconductor region 7, and extends in a layered form along the first main surface 3.

[0064] The body region 10 is formed at a distance from the bottom of the second semiconductor region 7 (first semiconductor region 6) toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 10 is formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0065] The body region 10 is formed in a region on the first main surface 3 side of the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7. The body region 10 forms a pn junction (body diode) with the second semiconductor region 7. The body region 10 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the body region 10 spreads in the horizontal direction and thickness direction within the second semiconductor region 7.

[0066] The semiconductor device 1A includes an n-type source region 11 formed in the active region 8 in a surface layer portion of the first main surface 3. A source potential is applied to the source region 11. The source region 11 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the source region 11 is higher than the p-type impurity concentration of the body region 10.

[0067] The source region 11 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. The source region 11 may be formed inwardly at a distance from the periphery of the body region 10. The source region 11 is formed in a surface layer portion of the body region 10, and extends in a layered form along the first main surface 3.

[0068] The source region 11 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the body region 10. The source region 11 is formed in a region on the first main surface 3 side of the body region 10 in a cross-sectional view, and is electrically connected to the body region 10.

[0069] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in an inner portion of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 15. The plurality of gate structures 15 controls inversion and non-inversion of the channel in the body region 10 in response to the gate potential.

[0070] The plurality of gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of gate structures 15 are arranged at intervals in a first direction X (= m-axis direction) in a plan view, and each extends in a band shape in a second direction Y (= a-axis direction). The plurality of gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0071] The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple gate structures 15 may be located in a region between the peripheral edge of the body region 10 and the peripheral edge of the source region 11. The multiple gate structures 15 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0072] The plurality of gate structures 15 penetrates the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0073] The plurality of gate structures 15 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The plurality of gate structures 15 are formed substantially perpendicular to the first main surface 3. The plurality of gate structures 15 may be formed in a shape that tapers toward the bottom of the second semiconductor region 7.

[0074] The side walls (long sides) of the plurality of gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 15 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The bottom walls of the plurality of gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the plurality of gate structures 15 extend substantially flat in the horizontal direction. The bottom walls of the plurality of gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0075] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0076] The gate structure 15 may have a width of 0.1 μm to 2 μm, and may have a width in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0077] The gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 is measured from the first main surface 3. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0078] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0079] Each of the plurality of gate structures 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0080] The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0081] The first insulating film 17 covers the wall surface of the first trench 16. The first insulating film 17 includes a first film portion and a second film portion. The first film portion covers the sidewall of the first trench 16 in a film-like manner. The second film portion covers the bottom wall of the first trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0082] The first insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0083] The first buried electrode 18 is buried in the first trench 16 with the first insulating film 17 sandwiched therebetween. The first buried electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the first insulating film 17 sandwiched therebetween.

[0084] The first buried electrode 18 has an electrode surface exposed from the first trench 16. The electrode surface is located closer to the bottom wall of the first trench 16 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the first trench 16.

[0085] The semiconductor device 1A includes gate well regions 25 formed in the chip 2 (second semiconductor region 7) in the active region 8 in regions below the plurality of gate structures 15. The gate well regions 25 may also be referred to as "first well regions" or the like.

[0086] A source potential is applied to the gate well region 25. The gate well region 25 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate well region 25 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10. The p-type impurity (trivalent element) of the gate well region 25 is preferably aluminum.

[0087] The multiple gate well regions 25 are formed in the second semiconductor region 7 in regions below (specifically, directly below) the multiple gate structures 15, spaced apart from one another in the horizontal direction (first direction X). The multiple gate well regions 25 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0088] The multiple gate well regions 25 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding gate structure 15. In other words, the multiple gate well regions 25 are arranged in stripes extending in the second direction Y in plan view.

[0089] The extension direction of the multiple gate well regions 25 coincides with the off-direction of the SiC single crystal. The multiple gate well regions 25 may extend in the first direction X according to the extension direction of the multiple gate structures 15. In this case, the multiple gate well regions 25 intersect (specifically, are perpendicular to) the off-direction.

[0090] The plurality of gate well regions 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of gate structures 15, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of gate well regions 25 each have an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4).

[0091] The upper ends of the plurality of gate well regions 25 are formed at intervals from the bottom of the body region 10 toward the bottom wall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may be connected to the bottom wall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may have portions that extend along the sidewall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may be formed at intervals from the bottom wall of the corresponding gate structure 15 toward the bottom of the second semiconductor region 7.

[0092] The bottoms of the multiple gate well regions 25 may be located on the bottom wall side of the multiple gate structures 15 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side toward the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0093] Each of the plurality of gate well regions 25 has a bulging portion 25 a. The bulging portion 25 a extends in an arc shape in the horizontal direction from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. Each of the plurality of gate well regions 25 is formed in a tapered shape from the bulging portion 25 a to the bottom.

[0094] The gate well region 25 may have a width greater than or less than the width of the gate structure 15. The width of the gate well region 25 may be 0.1 μm or more and 2 μm or less. The width of the gate well region 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0095] The gate well region 25 may have a thickness less than the depth of the gate structure 15, or may have a thickness greater than the depth of the gate structure 15. The thickness of the gate well region 25 is the depth of the gate well region 25 when the bottom wall of the gate structure 15 is used as the reference.

[0096] The thickness of the gate well region 25 may be greater than 0 μm and less than 5 μm. The thickness of the gate well region 25 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0097] The gate well region 25 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the gate well region 25 is the ratio of the thickness of the gate well region 25 to the width of the gate well region 25.

[0098] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0099] The gate well region 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the gate well region 25 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating from the gate well region 25 spreads in the horizontal and thickness directions, and reduces the electric field applied to the active region 8 (gate structure 15).

[0100] 5, 6, and 8, the semiconductor device 1A includes a plurality of gate contact regions 27 formed in the chip 2 (second semiconductor region 7) in the active region 8. The gate contact regions 27 may also be referred to as "first contact regions," etc. A source potential is applied to the gate contact regions 27.

[0101] The gate contact region 27 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the gate well region 25.

[0102] The plurality of gate contact regions 27 are formed at intervals in regions along the plurality of gate structures 15. The plurality of gate contact regions 27 are formed in a one-to-many correspondence with the plurality of gate structures 15. The plurality of gate contact regions 27 are formed at intervals in the second direction Y following the extension direction of the corresponding gate structures 15.

[0103] With respect to one and the other gate structures 15, the multiple gate contact regions 27 along one gate structure 15 face the multiple gate contact regions 27 along the other gate structure 15 in the first direction X in plan view. In other words, the multiple gate contact regions 27 are generally arranged in a matrix with gaps in the first direction X and the second direction Y in plan view.

[0104] In plan view, one of the plurality of gate contact regions 27 may face, in the first direction X, a region between the other of the plurality of gate contact regions 27. In other words, the plurality of gate contact regions 27 may be generally arranged in a staggered pattern at intervals in the first direction X and the second direction Y in plan view.

[0105] In this embodiment, the gate contact regions 27 extend in a strip shape along the gate structures 15 in a plan view. The lengths of the gate contact regions 27 in the second direction Y may be equal to or different from one another. The lengths of the gate contact regions 27 in the second direction Y are adjusted depending on the channel area to be formed.

[0106] The channel area is the total area of ​​the portions of the source region 11 exposed from the plurality of gate contact regions 27. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the plurality of gate contact regions 27. The total planar area of ​​the plurality of gate contact regions 27 is preferably less than the channel area.

[0107] That is, in the region between a pair of adjacent gate structures 15, the total planar area of ​​the multiple gate contact regions 27 is preferably less than the planar area of ​​the source region 11. With this configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0108] The length of the gate contact region 27 may be greater than or less than the width of the gate structure 15. The length of the gate contact region 27 may be greater than or less than the pitch of the gate structures 15. The length of the gate contact region 27 may be greater than or less than the pitch of two adjacent gate structures 15.

[0109] The interval between the multiple gate contact regions 27 may be greater than the width of the gate structures 15 or may be smaller than the width of the gate structures 15. The interval between the gate contact regions 27 may be greater than the pitch of the gate structures 15 or may be smaller than the pitch of the gate structures 15. The interval between the gate contact regions 27 may be greater than the pitch of two adjacent gate structures 15 or may be smaller than the pitch of two adjacent gate structures 15.

[0110] The plurality of gate contact regions 27 are respectively interposed in regions between the bottom walls of the plurality of gate structures 15 and the bottoms of the plurality of gate well regions 25. The plurality of gate contact regions 27 are connected to the bottom walls of the corresponding gate structures 15 and the corresponding gate well regions 25.

[0111] The plurality of gate contact regions 27 increase the p-type impurity concentration at the upper end of the corresponding gate well region 25. The gate contact regions 27 extend from the region directly below the gate structure 15 to both sides of the gate structure 15 and have extensions that extend along the sidewalls of the gate structure 15.

[0112] The thickness in the horizontal direction (first direction X) of the portion (extension) of the gate contact region 27 that runs along the side wall of the gate structure 15 may be less than the thickness in the vertical direction Z of the portion of the gate contact region 27 that runs along the bottom wall of the gate structure 15.

[0113] The extension of the gate contact region 27 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding gate well region 25 to the body region 10. This prevents the gate well region 25 from being electrically floating, and improves the electrical response characteristics of the gate well region 25.

[0114] The gate contact region 27 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the gate contact region 27 is exposed from the sidewall of the first trench 16 at the opening end of the first trench 16. The upper end of the gate contact region 27 may extend horizontally in the surface portion of the body region 10.

[0115] The second semiconductor region 7 of the semiconductor device 1A includes a stacked structure of a base region 71 and a cap region 72 .

[0116] The base region 71 is formed closer to the second main surface 4 than the gate well region 25 and away from the body region 10. The base region 71 is formed in a layer shape extending along the first main surface 3 at a position away from the body region 10 and the first trench 16 toward the second main surface 4. The base region 71 is formed over the entire surface layer portion of the second semiconductor region 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 71 forms a boundary surface between the second semiconductor region 7 and the first semiconductor region 6.

[0117] The thickness of the base region 71 may be, for example, not less than 0.5 μm and not more than 20 μm, and is preferably not less than 1 μm and not more than 10 μm.

[0118] The n-type impurity concentration of the base region 71 is preferably lower than the n-type impurity concentration of the first semiconductor region 6. The base region 71 has a dopant concentration of 1×10 １６ cm －３ 1x10 or more １７ cm －３The n-type impurity concentration of the base region 71 may have a peak value of the following: The n-type impurity concentration of the base region 71 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the base region 71 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0119] The cap region 72 is formed in at least the active region 8. The cap region 72 is formed on the base region 71. The cap region 72 is in contact with the body region 10 and the gate well region 25 and is formed in a layer shape extending along the first main surface 3. In this embodiment, the cap region 72 forms a boundary surface with the body region 10 in the second semiconductor region 7. The body region 10 is formed in a surface layer portion of the cap region 72. The body region 10 is physically separated from the base region 71 in the thickness direction of the chip 2 by the cap region 72 sandwiching the cap region 72 therebetween. The gate structure 15 penetrates the source region 11 and the body region 10 and has its bottom in the cap region 72.

[0120] The n-type impurity concentration of the cap region 72 is preferably higher than the n-type impurity concentration of the base region 71. The cap region 72 has a dopant concentration of 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the cap region 72 may have a peak value of the following: The n-type impurity concentration of the cap region 72 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the cap region 72 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0121] In this embodiment, the n-type impurity concentrations of the base region 71 and the cap region 72 are adjusted by nitrogen. The base region 71 and the cap region 72 may have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the base region 71 and the cap region 72 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0122] 9, the outermost gate structure 15 among the plurality of gate structures 15 is a terminal gate structure 15A. In this embodiment, the plurality of gate structures 15 arranged in stripes extending along the second direction Y have one terminal gate structure 15A formed at the end of each of both sides (the third side surface 5C side and the fourth side surface 5D side) in the first direction X (see also FIGS. 3 and 4). In FIG. 9, the terminal gate structure 15A on the fourth side surface 5D side is shown.

[0123] In this embodiment, the terminal gate structure 15A includes a terminal first trench 16A, a terminal first insulating film 17A, and a terminal first buried electrode 18A. The terminal first trench 16A is a boundary trench that forms a peripheral boundary 19, which is the boundary between the active region 8 and the peripheral region 9. The terminal gate structure 15A has the same structure as the remaining gate structures 15, except for its arrangement in stripes.

[0124] 6 and 9 to 11 , semiconductor device 1A includes a p-type outer well region 40 formed in a surface layer portion of first main surface 3 in peripheral region 9. A source potential is applied to outer well region 40. Outer well region 40 has a p-type impurity concentration higher than the n-type impurity concentration of second semiconductor region 7.

[0125] The p-type impurity concentration of the outer well region 40 is lower than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer well region 40 is lower than the p-type impurity concentration of the gate contact region 27.

[0126] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer well region 40 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25.

[0127] The p-type impurity concentration of the outer well region 40 may be approximately equal to the p-type impurity concentration of the body region 10. It may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0128] As described above, the outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43. The first outer well region 42 and the plurality of second outer well regions 43 may be referred to as a "termination region" and a "field region," respectively. The first outer well region 42 and the plurality of second outer well regions 43 may also be collectively referred to as an "outer well region." The first outer well region 42 may also be referred to as a "termination well region," a "Junction Termination Extension region (JTE region)," or the like. The second outer well region 43 may also be referred to as a "guard region," a "field limit region," or the like.

[0129] A source potential is applied to the first outer well region 42. The first outer well region 42 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0130] 9 and 10 , the first outer well region 42 is formed in a surface layer portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The first outer well region 42 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The first outer well region 42 is preferably formed at a distance from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0131] The first outer well region 42 is formed shallower than the gate well region 25 along the outer boundary 19. The depth D1 of the first outer well region 42 may be, for example, greater than 0 μm and equal to or less than 4 μm. The depth D1 of the first outer well region 42 may have a value belonging to at least one of the following ranges: greater than 0 μm and equal to or less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm.

[0132] When the first outer well region 42 is disposed at a distance from the first main surface 3 toward the bottom of the second semiconductor region 7 (when the first outer well region 42 is not exposed from the first main surface 3), the depth D1 of the first outer well region 42 may be referred to as the thickness of the first outer well region 42. Furthermore, the first outer well region 42 may have approximately the same depth as the gate well region 25.

[0133] In the horizontal direction along the first main surface 3, the first outer well region 42 at least partially covers the gate well region 25 of the terminal first trench 16A.

[0134] More specifically, the gate well region 25 includes a well side portion (in this embodiment, a bulging portion 25 a) extending in the thickness direction of the second semiconductor region 7, and a well bottom portion 25 b extending from the bulging portion 25 a in a direction along the first main surface 3. The first outer well region 42 selectively covers the bulging portion 25 a on the outer peripheral region 9 side (outside) of the gate well region 25 of the terminal first trench 16A. The bulging portion 25 a and the well bottom 25 b on the active region 8 side (inside) that are not covered by the first outer well region 42 are covered by the second semiconductor region 7 (in this embodiment, a cap region 72).

[0135] The first outer well region 42 has a first upper end 42a on the first main surface 3 side, a first lower end 42b on the opposite side, and a first main body portion 42c between the first lower end 42b and the first upper end 42a.

[0136] The first upper end 42a extends horizontally along the first main surface 3 and is exposed from the first main surface 3. The first upper end 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate structure 15. The first upper end 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25. The first upper end 42a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10. The first upper end 42a is located on the first main surface 3 side with respect to the depth position of a boundary 62 between the cap region 72 and the base region 71.

[0137] The first upper end 42a is formed in a shape that protrudes in an arc from the first body portion 42c toward the first main surface 3. The first upper end 42a includes a central portion 63 exposed from the first main surface 3, and an end 64 that is disposed at a position spaced from the first main surface 3 toward the bottom of the second semiconductor region 7.

[0138] A gap 65 is formed between an end 64 of the first upper end 42a and the first main surface 3. The gap 65 is a region defined between the flat first main surface 3 and the arc-shaped first upper end 42a. A part of the second semiconductor region 7 (in this embodiment, the base region 71) fits into the gap 65. This part of the second semiconductor region 7 is sandwiched between the first main surface 3 and the first upper end 42a.

[0139] The first lower end 42b extends horizontally along the first main surface 3 and forms a pn junction with the second semiconductor region 7. In this embodiment, the first lower end 42b forms a pn junction with the base region 71. The first lower end 42b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the gate structure 15. The first lower end 42b is located on the first main surface 3 side relative to the depth position of the bottom of the gate well region 25. The first lower end 42b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the body region 10. The first lower end 42b is located on the first main surface 3 side relative to the depth position of the boundary 62 between the cap region 72 and the base region 71.

[0140] The first lower end 42b is formed in a flat shape that is approximately parallel to the first main surface 3. The first lower end 42b may be formed in a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0141] The first body portion 42c is sandwiched between the first upper end portion 42a and the first lower end portion 42b. The first body portion 42c may be a portion of the first outer well region 42 that covers the gate structure 15 and the gate well region 25.

[0142] The first body portion 42c includes a first side portion 42d connecting the first upper end portion 42a and the first lower end portion 42b. In this embodiment, the first side portion 42d is inclined toward the active region 8 from the first upper end portion 42a toward the first lower end portion 42b. For example, the first outer well region 42 may be formed in a mesa shape in cross section, having the first side portion 42d inclined such that the width W1 narrows from the first upper end portion 42a toward the first lower end portion 42b.

[0143] The first outer well region 42 has a width W1 (for example, the width of the first lower end 42b) that is larger than the width of the gate structure 15. The width W1 of the first outer well region 42 is larger than the width of the terminal gate structure 15A. The width W1 of the first outer well region 42 may be larger than the total width of the multiple terminal gate structures 15A. The width W1 of the first outer well region 42 may be larger than the total width of the multiple gate well regions 25.

[0144] The width W1 of the first outer well region 42 may be greater than 0 μm and less than 300 μm. The width W1 of the first outer well region 42 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0145] When a reverse bias voltage is applied, the first outer well region 42 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating in the first outer well region 42 spreads in the horizontal and thickness directions, and relieves the electric field in the vicinity of the peripheral boundary 19 between the active region 8 and the peripheral region 9.

[0146] The semiconductor device 1A includes a p-type outer contact region 41 formed in the outer peripheral region 9 in a surface layer portion of the first main surface 3. A source potential is applied to the outer contact region 41. The outer contact region 41 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (cap region 72). The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentrations of the body region 10 and the first outer well region 42.

[0147] The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer contact region 41 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the outer contact region 41 may be lower than the p-type impurity concentration of the gate well region 25.

[0148] The p-type impurity concentration of the outer contact region 41 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the outer contact region 41 may be higher than the p-type impurity concentration of the gate contact region 27, or may be lower than the p-type impurity concentration of the gate contact region 27.

[0149] The outer contact region 41 is formed in the surface layer portion of the first outer well region 42. That is, the outer contact region 41 is formed in a thickness range between the first main surface 3 and the bottom of the first outer well region 42. In this embodiment, the outer contact region 41 is selectively formed in the first upper end portion 42a of the first outer well region 42. The p-type impurity concentration of the first outer well region 42 is increased, thereby improving the electrical response speed of the first outer well region 42.

[0150] The outer contact region 41 extends in a strip shape along the terminal gate structure 15A in the second direction Y. The outer contact region 41 extends in a strip shape across the plurality of gate structures 15 in the first direction X.

[0151] In this embodiment, the outer contact region 41 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The outer contact region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0152] A plurality of outer contact regions 41 may be formed at intervals along the direction in which the terminal gate structure 15A extends and the direction crossing the plurality of gate structures 15A.

[0153] The outer contact region 41 has a width less than that of the first outer well region 42, and is formed within the first outer well region 42. The outer contact region 41 has an inner edge portion on the inner side of the first main surface 3 (the active region 8 side) and an outer edge portion on the peripheral side of the first main surface 3.

[0154] In this embodiment, the inner edge of the outer contact region 41 is connected to the terminal gate structure 15A. In this embodiment, the inner edge of the outer contact region 41 is connected to the gate well region 25 of the terminal first trench 16A. The inner edge of the outer contact region 41 extends along the terminal gate structure 15A (peripheral boundary 19) in the thickness direction of the second semiconductor region 7 and is connected to the gate well region 25 of the terminal first trench 16A. The first outer well region 42 is electrically connected to the body region 10 via the gate well region 25 of the terminal first trench 16A. The first outer well region 42 may be formed at a distance from the terminal gate structure 15A.

[0155] The outer edge of the outer contact region 41 is formed at a distance from the outer edge of the first outer well region 42 toward the terminal gate structure 15A. The outer contact region 41 may have a portion that crosses the outer edge of the first outer well region 42 and is connected to the second semiconductor region 7.

[0156] The outer contact region 41 has a width greater than the width of the gate well region 25. The width of the outer contact region 41 is greater than the width of the terminal gate structure 15A. The width of the outer contact region 41 may be less than the width of the first outer well region 42. The width of the outer contact region 41 may be greater than the width of the first outer well region 42.

[0157] The width of the outer contact region 41 may be greater than 0 μm and less than 300 μm. The width of the outer contact region 41 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0158] The outer contact region 41 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the first outer well region 42. The upper end of the outer contact region 41 is exposed from the first main surface 3. The bottom of the outer contact region 41 is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25.

[0159] The bottom of the outer contact region 41 is located closer to the first main surface 3 than the depth position of the bottom of the first outer well region 42. The bottom of the outer contact region 41 may be located closer to the first main surface 3 than the depth position of the bottom of the body region 10, or may be located closer to the bottom of the first outer well region 42.

[0160] The depth (thickness) of the outer contact region 41 may be greater than 0 μm and less than or equal to 1 μm. The depth of the outer contact region 41 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm.

[0161] The second outer well region 43 is formed in an electrically floating state. A source potential may be applied to the second outer well region 43.

[0162] The number of second outer well regions 43 is arbitrary. The number of second outer well regions 43 may be 1 or more and 15 or less. The number of second outer well regions 43 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of second outer well regions 43 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1A includes three second outer well regions 43, as an example.

[0163] The second outer well region 43 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the second outer well region 43 may be approximately equal to the p-type impurity concentration of the first outer well region 42. The p-type impurity concentration of the second outer well region 43 may be higher than the p-type impurity concentration of the first outer well region 42, or may be lower than the p-type impurity concentration of the first outer well region 42.

[0164] The p-type impurity concentration of the second outer well region 43 may be lower than the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the second outer well region 43 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the second outer well region 43 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0165] In this embodiment, the p-type impurity concentrations of the second outer well regions 43 are approximately equal to each other. The p-type impurity concentrations of the second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations of the second outer well regions 43 may also be different from each other.

[0166] 10 and 11 , the plurality of second outer well regions 43 are formed in a surface layer portion of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The plurality of second outer well regions 43 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of second outer well regions 43 are preferably formed at intervals from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0167] The depth D2 of the second outer well region 43 may be approximately equal to the depth D1 of the first outer well region 42. The depth D2 of the second outer well region 43 may be deeper than the depth D1 of the first outer well region 42, or may be shallower than the depth D1 of the first outer well region 42.

[0168] The depth D2 of the second outer well region 43 may be, for example, greater than 0 μm and less than or equal to 4 μm. The depth D2 of the second outer well region 43 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, and 3.5 μm to 4 μm. When the second outer well region 43 is spaced apart from the first main surface 3 toward the bottom of the second semiconductor region 7 (when the second outer well region 43 is not exposed from the first main surface 3), the depth D2 of the second outer well region 43 may also be referred to as the thickness of the second outer well region 43.

[0169] In this embodiment, the depths D2 of the second outer well regions 43 are approximately equal to each other. The depths D2 of the second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The depths D2 of the second outer well regions 43 may also be different from each other.

[0170] The depth D2 of the multiple second outer well regions 43 may increase sequentially toward the peripheral edge of the first main surface 3. The depth D2 of the multiple second outer well regions 43 may increase toward the peripheral edge of the first main surface 3 in units of two or more groups, each group including two or more second outer well regions 43.

[0171] The depth D2 of the multiple second outer well regions 43 may decrease in order toward the peripheral edge of the first main surface 3. The depth D2 of the multiple second outer well regions 43 may decrease toward the peripheral edge of the first main surface 3 in units of two or more groups, each group including two or more second outer well regions 43.

[0172] The second outer well regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the terminal gate structure 15A (peripheral boundary portion 19). The second outer well regions 43 are formed at intervals in the region between the periphery of the first main surface 3 and the first outer well region 42.

[0173] The second outer well region 43 has a second upper end 43a on the first main surface 3 side, a second lower end 43b on the opposite side, and a second main body portion 43c between the second lower end 43b and the second upper end 43a.

[0174] The second upper end 43a extends horizontally along the first main surface 3 and is exposed from the first main surface 3. The second upper end 43a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate structure 15. The second upper end 43a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25. The second upper end 43a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10. The second upper end 43a is located on the first main surface 3 side with respect to the depth position of a boundary 62 between the cap region 72 and the base region 71.

[0175] The second upper end 43a is formed in a shape that protrudes in an arc from the second body portion 43c toward the first main surface 3. The second upper end 43a includes a central portion 66 exposed from the first main surface 3, and an end portion 67 that is disposed at a position spaced from the first main surface 3 toward the bottom of the second semiconductor region 7.

[0176] A gap 68 is formed between an end 67 of the second upper end 43a and the first main surface 3. The gap 68 is a region defined between the flat first main surface 3 and the arc-shaped second upper end 43a. A part of the second semiconductor region 7 (in this embodiment, the base region 71) fits into the gap 68. This part of the second semiconductor region 7 is sandwiched between the first main surface 3 and the second upper end 43a.

[0177] The second lower end 43b extends horizontally along the first main surface 3 and forms a pn junction with the second semiconductor region 7. In this embodiment, the second lower end 43b forms a pn junction with the base region 71. The second lower end 43b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the gate structure 15. The second lower end 43b is located on the first main surface 3 side relative to the depth position of the bottom of the gate well region 25. The second lower end 43b is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of the body region 10. The second lower end 43b is located on the first main surface 3 side relative to the depth position of the boundary 62 between the cap region 72 and the base region 71.

[0178] The second lower end 43b is formed in a flat shape that is approximately parallel to the first main surface 3. The second lower end 43b may be formed in a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0179] The second main body portion 43c is sandwiched between the second upper end portion 43a and the second lower end portion 43b. The second main body portion 43c includes a second side portion 43d connecting the second upper end portion 43a and the second lower end portion 43b. In this embodiment, the second side portion 43d is inclined from the second upper end portion 43a toward the second lower end portion 43b. For example, the second outer well region 43 may be formed in a mesa shape in cross section, having the second side portion 43d inclined such that the width W2 narrows from the second upper end portion 43a toward the second lower end portion 43b.

[0180] The plurality of second outer well regions 43 may have a width W2 that is less than the width W1 of the first outer well region 42. The width W2 of the plurality of second outer well regions 43 (for example, the width of the second lower end portion 43b) may be smaller than the width of the gate structure 15 or may be larger than the width of the gate structure 15. The width W2 of the second outer well region 43 may be smaller than the width of the gate well region 25 or may be larger than the width of the gate well region 25.

[0181] In this embodiment, the widths W2 of the second outer well regions 43 are approximately equal to each other. The widths W2 of the second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The widths W2 of the second outer well regions 43 may also be different from each other.

[0182] The widths W2 of the multiple second outer well regions 43 may increase sequentially toward the peripheral edge of the first main surface 3. The widths W2 of the multiple second outer well regions 43 may increase toward the peripheral edge of the first main surface 3 in units of two or more groups, each group including two or more second outer well regions 43.

[0183] The widths W2 of the multiple second outer well regions 43 may decrease in order toward the peripheral edge of the first main surface 3. The widths W2 of the multiple second outer well regions 43 may decrease toward the peripheral edge of the first main surface 3 in units of two or more groups, each group including two or more second outer well regions 43.

[0184] The width W2 of the second outer well region 43 is narrower than the width W1 of the first outer well region 42. The width W2 of the second outer well region 43 may be greater than 0 μm and less than 5 μm. The width W2 of the second outer well region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0185] The spacing between the multiple second outer well regions 43 may be equal to or less than the width W2 of the second outer well regions 43. The spacing between the multiple second outer well regions 43 is preferably less than the width W2 of the second outer well regions 43. The spacing between the multiple second outer well regions 43 may be greater than the width W2 of the second outer well regions 43.

[0186] In this embodiment, the intervals between the second outer well regions 43 are approximately equal to each other. The intervals between the second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The intervals between the second outer well regions 43 may also be different from each other.

[0187] The spacing between the multiple second outer well regions 43 may increase sequentially toward the peripheral edge of the first main surface 3. The spacing between the multiple second outer well regions 43 may increase toward the peripheral edge of the first main surface 3 in units of two or more groups, each group including two or more second outer well regions 43.

[0188] The intervals between the multiple second outer well regions 43 may decrease in order toward the periphery of the first main surface 3. The intervals between the multiple second outer well regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more second outer well regions 43.

[0189] The spacing between the second outer well regions 43 may be greater than 0 μm and less than 5 μm. The spacing may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0190] The ratio of the spacing of the second outer well region 43 to the width W2 of the second outer well region 43 (spacing ratio) may be 0.1 or more and 5 or less. The spacing ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, 2.5 or more and 3 or less, 3 or more and 3.5 or less, 3.5 or more and 4 or less, 4 or more and 4.5 or less, and 4.5 or more and 5 or less.

[0191] The second outer well regions 43 expand the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the second outer well regions 43 expands in the horizontal and thickness directions and merges with the depletion layer originating in the first outer well region 42. The second outer well regions 43 expand the depletion layer originating in the first outer well region 42 toward the periphery of the first main surface 3, thereby alleviating the electric field in the periphery (peripheral region 9) of the first main surface 3.

[0192] 10 and 11 , semiconductor device 1A includes n-type field stop region 12 formed in peripheral region 9 in a surface layer portion of first main surface 3. Field stop region 12 has the same depth as cap region 72. Field stop region 12 and cap region 72 may have their bottoms at the same depth position from first main surface 3.

[0193] Depth D3 of field stop region 12 and depth D4 of cap region 72 may be the distance from first major surface 3 to the bottom of field stop region 12 and the bottom of cap region 72, respectively. Depth D3 of field stop region 12 and depth D4 of cap region 72 may also be referred to as the "thickness of field stop region 12" and the "thickness of cap region 72," respectively.

[0194] The depth D3 of the field stop region 12 and the depth D4 of the cap region 72 may be, for example, not less than 0.1 μm and not more than 0.5 μm. The depth D3 of the field stop region 12 and the depth D4 of the cap region 72 are preferably not less than 0.15 μm and not more than 0.4 μm.

[0195] The field stop region 12 may be formed deeper than the outer well region 40. The bottom of the field stop region 12 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 40. The bottom of the field stop region 12 may be located closer to the bottom of the second semiconductor region 7 than the depth position of either the bottom of the first outer well region 42 or the bottom of the second outer well region 43. The bottom of the field stop region 12 may be located closer to the bottom of the second semiconductor region 7 than the depth positions of both the bottom of the first outer well region 42 and the bottom of the second outer well region 43. In other words, the depth D3 of the field stop region 12 may be greater than at least one of the depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43. The depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43 may be the distance from the first main surface 3 to the bottom of the first outer well region 42 and the bottom of the second outer well region 43, respectively.

[0196] The field stop region 12 may be formed deeper than the body region 10. The bottom of the field stop region 12 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10. In other words, the depth D3 of the field stop region 12 may be greater than the depth D5 of the body region 10.

[0197] The depth D5 of the body region 10 (the thickness of the body region 10) may be, for example, not less than 0.1 μm and not more than 3.0 μm. The depth D5 of the body region 10 is preferably not less than 0.5 μm and not more than 1.0 μm. The depth D5 of the body region 10 may be the distance from the first main surface 3 to the bottom of the body region 10.

[0198] The field stop region 12 may be formed deeper than the gate structure 15. The bottom of the field stop region 12 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the gate structure 15. In other words, the depth D3 of the field stop region 12 may be greater than the depth D6 of the gate structure 15.

[0199] As described above, the depth D6 of the gate structure 15 may be, for example, 0.1 μm or more and 3 μm or less. The depth D6 of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth D6 of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less. The depth D6 of the gate structure 15 may be the distance from the first main surface 3 to the bottom of the gate structure 15.

[0200] The field stop region 12 may be formed deeper than the gate well region 25. The bottom of the field stop region 12 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the gate well region 25. In other words, the depth D3 of the field stop region 12 may be greater than the depth D7 of the gate well region 25.

[0201] The depth D7 of the gate well region 25 may be, for example, not less than 0.1 μm and not more than 3.0 μm. The depth D7 of the gate well region 25 is preferably not less than 0.5 μm and not more than 2.0 μm. The depth D7 of the gate well region 25 may be the distance from the first main surface 3 to the bottom of the gate well region 25.

[0202] 11 , the first main surface 3 of the chip 2 is a continuous, flat surface without any steps from the active region 8 through the peripheral region 9 to the end faces (first to fourth side surfaces 5A to 5D) of the chip 2. The "no steps" of the first main surface 3 may be defined as a state in which, after the epitaxial growth of the second semiconductor region 7, a portion of the first main surface 3 is selectively removed by processing such as etching, and no recesses are formed.

[0203] As a result, the first main surface 3 of the active region 8 and the first main surface 3 of the peripheral region 9 may be flat surfaces. The thickness of the second semiconductor region 7 in the active region 8 may be the same as the thickness of the second semiconductor region 7 in the peripheral region 9. The distance from the interface between the second semiconductor region 7 and the first semiconductor region 6 in the active region 8 to the first main surface 3 may be the same as the distance from the interface between the second semiconductor region 7 and the first semiconductor region 6 in the peripheral region 9 to the first main surface 3.

[0204] In this embodiment, the field stop region 12 and the source region 11 each have an upper surface 12a exposed from the first main surface 3 of the peripheral region 9 and an upper surface 11a exposed from the first main surface 3 of the active region 8. The upper surface 12a of the field stop region 12 and the upper surface 11a of the source region 11 are located at the same height. In other words, there is no difference in height between the upper surface 12a and the upper surface 11a.

[0205] The field-stop region 12 includes a stacked structure of a first region 13 and a second region 14. The stacked structure may be a two-layer structure including a lower layer made of the first region 13 and an upper layer made of the second region 14. The first region 13 may be referred to as a "base region," "base layer," etc. The second region 14 may be referred to as a "high-concentration region," "high-concentration layer," etc.

[0206] Both the first region 13 and the second region 14 may have a higher impurity concentration than the base region 71. In comparison between the first region 13 and the second region 14, the second region 14 may have a higher impurity concentration than the first region 13.

[0207] The impurity concentration of the first region 13 may be the same as that of the cap region 72. The first region 13 has an impurity concentration of 1×10 １７ cm －３ 1x10 or more １８ cm －３ The second region 14 may have an n-type impurity concentration of 1×10 or less as a peak value. The impurity concentration of the second region 14 may be the same as that of the source region 11. １８ cm －３ 1x10 or more １９ cm －３The n-type impurity concentration may have the following peak value:

[0208] The thickness T3 of the first region 13 may be greater than the thickness T4 of the second region 14. The thickness T3 of the first region 13 may be greater than the depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43 by itself. The thickness T4 of the second region 14 may be smaller than the depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43 by itself.

[0209] A boundary 61 between the first region 13 and the second region 14 may be located at the same depth as the bottom of the source region 11. The boundary 61 may be located closer to the first main surface 3 than the depth of the bottom of the outer well region 40 (first outer well region 42 and second outer well region 43). The boundary 61 may be located closer to the first main surface 3 than the depth of the bottom of the body region 10. The boundary 61 may be located closer to the first main surface 3 than the depth of the bottom of the gate structure 15. The boundary 61 may be located closer to the first main surface 3 than the depth of the bottom of the gate well region 25.

[0210] 10 and 11 , semiconductor device 1A includes p-type voltage relaxation region 60 formed in peripheral region 9 in a surface layer portion of first main surface 3. Voltage relaxation region 60 has the same depth as body region 10. Voltage relaxation region 60 and body region 10 may have their bottoms at the same depth position from first main surface 3. In other words, depth D8 of voltage relaxation region 60 may be the same as depth D5 of body region 10.

[0211] The voltage relaxation region 60 has an upper surface 60a exposed from the first main surface 3 of the peripheral region 9 and side surfaces 60b exposed from the first to fourth side surfaces 5A to 5D. The upper surface 60a and side surfaces 60b are continuous at the peripheral corners on the first main surface 3 side of the chip 2. As a result, the voltage relaxation region 60 is exposed from two directions, from the first main surface 3 of the chip 2 and from the first to fourth side surfaces 5A to 5D.

[0212] The upper surface 60a of the voltage relaxation region 60 and the upper surface 11a of the source region 11 are disposed at the same height. In other words, there is no difference in height between the upper surface 60a and the upper surface 11a. Furthermore, the side surface 60b does not form a step on the first to fourth side surfaces 5A to 5D of the chip 2, and the first to fourth side surfaces 5A to 5D, including the side surface 60b, are continuous flat surfaces without any steps from the second main surface 4 to the first main surface 3.

[0213] The impurity concentration of the voltage relaxation region 60 may be the same as that of the body region 10. １７ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0214] The semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 45 preferably includes the same type of insulating material as the first insulating film 17. In this embodiment, the main surface insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of an oxide of the chip 2.

[0215] The main surface insulating film 45 is connected to the first insulating films 17 of the plurality of gate structures 15 in the active region 8 , and exposes the first buried electrodes 18 of the plurality of gate structures 15 .

[0216] The main surface insulating film 45 covers the second semiconductor region 7, the first outer well region 42, the outer contact region 41, the second outer well region 43, the field stop region 12, and the voltage relaxation region 60 in the peripheral region 9. In this embodiment, the main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D in the peripheral portion of the first main surface 3. The main surface insulating film 45 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0217] The semiconductor device 1A includes an insulating interlayer film 47 that selectively covers the first main surface 3 with the main surface insulating film 45 sandwiched therebetween. The interlayer film 47 may also be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0218] The interlayer film 47 covers the plurality of gate structures 15 (first buried electrodes 18) on the active region 8 side. The interlayer film 47 covers the second semiconductor region 7, the first outer well region 42, the outer contact region 41, the second outer well region 43, the field stop region 12, and the voltage relaxation region 60 on the peripheral region 9 side, with the main surface insulating film 45 sandwiched therebetween.

[0219] In this embodiment, the interlayer film 47 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the first main surface 3. The interlayer film 47 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0220] The interlayer film 47 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 47 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0221] The semiconductor device 1A includes a plurality of gate openings (not shown) formed in the interlayer film 47 in the active region 8. The plurality of gate openings are formed in a one-to-many correspondence with a corresponding one of the gate structures 15. In this embodiment, the plurality of gate openings penetrate the interlayer film 47 and expose one end or the other end of each of the plurality of gate structures 15 (first buried electrodes 18).

[0222] The plurality of gate openings may each have an opening end curved in an arc shape. The plurality of gate openings may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view. The plurality of gate openings may each have an opening end curved in an arc shape.

[0223] The semiconductor device 1A includes a plurality of source openings 49 formed in the interlayer film 47 in the active region 8. For clarity, the source openings 49 are omitted from FIG. 10 . The source openings 49 are formed in portions of the interlayer film 47 that cover the active region 8. In this embodiment, the source openings 49 are formed in regions between adjacent gate structures 15, respectively, and expose the source regions 11 and the gate contact regions 27, respectively.

[0224] The plurality of source openings 49 penetrate the main surface insulating film 45 and the interlayer film 47, and expose the corresponding plurality of source regions 11 and the corresponding plurality of gate contact regions 27. Each of the plurality of source openings 49 may have an opening end that is curved in an arc shape.

[0225] The source openings 49 may be formed in a one-to-many correspondence with the regions between adjacent gate structures 15. In this case, the source openings 49 may be formed at intervals along the regions between the corresponding gate structures 15. In this case, the source openings 49 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in plan view.

[0226] The semiconductor device 1A includes at least one outer opening 50 (one in this embodiment) formed in the interlayer film 47 in the peripheral region 9. The outer opening 50 penetrates the main surface insulating film 45 and the interlayer film 47 to expose the outer contact region 41. The outer opening 50 extends in a strip shape along the outer contact region 41 in a plan view.

[0227] In this embodiment, the outer opening 50 is formed in a polygonal ring shape (specifically, a square ring shape) in plan view that surrounds the inner portion (active region 8) of the first main surface 3 along the outer contact region 41. The outer opening 50 may have an opening end that is curved in an arc shape.

[0228] The semiconductor device 1A may have a plurality of outer openings 50. In this case, the plurality of outer openings 50 may be formed at intervals along the outer contact region 41 so as to surround the inner portion (active region 8) of the first main surface 3. In this case, the plurality of outer openings 50 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view.

[0229] The semiconductor device 1A includes a source electrode 51 disposed on the first main surface 3. The source electrode 51 extends from above the interlayer film 47 into the plurality of source openings 49, and is electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 within the plurality of source openings 49.

[0230] In this embodiment, the source electrode 51 has a layered structure including a lower electrode film 52 and a main electrode film 53, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 52 has a layered structure including a first electrode film and a second electrode film. In this embodiment, the first electrode film includes a Ti film, and the second electrode film includes a TiN film. The lower electrode film 52 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film (Ti film) or the second electrode film (TiN film).

[0231] The lower electrode film 52 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and extends into the plurality of source openings 49 from above the interlayer film 47. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 49 in a film-like manner, and a portion that covers the first main surface 3 in the plurality of source openings 49. The lower electrode film 52 is mechanically and electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 in the source openings 49.

[0232] The main electrode film 53 contains a different conductive material from that of the lower electrode film 52. The main electrode film 53 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 53 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. The thickness of the main electrode film 53 is preferably greater than the thickness of the interlayer film 47.

[0233] The thickness of the main electrode film 53 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 53 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0234] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and backfills the plurality of source openings 49.

[0235] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 49 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 52 sandwiched therebetween. The main electrode film 53 is electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 via the lower electrode film 52 within the plurality of source openings 49.

[0236] The semiconductor device 1A includes a source wiring 56 disposed on the interlayer film 47 around the source electrode 51 .

[0237] The source wiring 56 is drawn from the active region 8 to the peripheral region 9, and has a portion facing the outer contact region 41 across the interlayer film 47. The source wiring 56 enters the outer opening 50 from above the interlayer film 47, and is electrically connected to the outer contact region 41 within the outer opening 50. In other words, the source wiring 56 is electrically connected to the first outer well region 42 via the outer contact region 41.

[0238] The source wiring 56 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source wiring 56 is located within the active region 8 and faces one or more (multiple in this embodiment) gate structures 15 with the interlayer film 47 interposed therebetween. The inner edge portion of the source wiring 56 faces at least the terminal gate structure 15A with the interlayer film 47 interposed therebetween.

[0239] The outer edge of the source wiring 56 is formed at a distance inward (toward the active region 8) from the periphery of the first main surface 3. The outer edge of the source wiring 56 is formed at a distance inward from the innermost second outer well region 43 among the plurality of second outer well regions 43. In other words, the source wiring 56 does not face the plurality of second outer well regions 43, the field stop region 12, or the voltage relaxation region 60 across the interlayer film 47.

[0240] With this configuration, the electric field dispersion path is prevented from being blocked by the source wiring 56 in the region above the multiple second outer well regions 43, and the electric field (electric force lines) are appropriately dispersed by the multiple second outer well regions 43.

[0241] The source wiring 56 is not electrically or mechanically connected to the field stop region 12 and the voltage relaxation region 60. As a result, the field stop region 12 and the voltage relaxation region 60 are formed in an electrically floating state.

[0242] Like the source electrode 51, the source wiring 56 has a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side.

[0243] The lower electrode film 52 collectively covers the region of the interlayer film 47 where the outer opening 50 is formed, and extends into the outer opening 50 from above the interlayer film 47. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surface of the outer opening 50 in a film-like manner, and a portion that covers the first main surface 3 within the outer opening 50 in a film-like manner. The lower electrode film 52 is mechanically and electrically connected to the outer contact region 41 within the outer opening 50.

[0244] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 collectively covers the region of the interlayer film 47 where the outer opening 50 is formed, and backfills the outer opening 50.

[0245] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 in between, a portion that covers the wall surface of the outer opening 50 with the lower electrode film 52 in between, and a portion that covers the first main surface 3 with the lower electrode film 52 in between. The main electrode film 53 is electrically connected to the outer contact region 41 within the outer opening 50 via the lower electrode film 52.

[0246] Although the cross-sectional structure is omitted, the aforementioned gate electrode 57 and gate wiring 58 (see Figure 1) also have a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side, similar to the source electrode 51 and source wiring 56.

[0247] The concentration gradient of the n-type impurity concentration and the p-type impurity concentration in the impurity region in the chip 2 will be specifically described below.

[0248] The numerical values ​​of impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the outer contact region 41, first outer well region 42, second outer well region 43, source region 11, cap region 72, and field stop region 12 (second region 14 and first region 13) based on concentration gradients, and are not intended to uniquely limit the configuration of the outer contact region 41, first outer well region 42, second outer well region 43, source region 11, cap region 72, and field stop region 12 (second region 14 and first region 13). The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions (dose, implantation temperature, implantation energy, etc.) of the trivalent or pentavalent element. Furthermore, the term "concentration gradient" may be completely replaced with the term "concentration profile."

[0249] Fig. 12 is a graph showing an example of the concentration gradient of p-type impurities in the region along line XII-XII shown in Fig. 9. In Fig. 12, the vertical axis represents the p-type impurity concentration in the outer contact region 41 and the outer well region 40 (first outer well region 42), and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0250] 12, the outer contact region 41 has a concentration gradient specific to an impurity region formed by random implantation. Fig. 12 shows the concentration gradient of the outer contact region 41 when a predetermined trivalent element (here, aluminum) is introduced into the second semiconductor region 7 in a random direction with an implantation energy of 190 KeV. The random direction is a direction (for example, the vertical direction Z) that is not parallel (almost parallel) to the axial channel of the second semiconductor region 7. The depth (thickness) of the outer contact region 41 is about 0.5 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0251] The outer contact region 41 has a sudden increase portion 73, a peak portion 74 (peak value P1), and a sudden decrease portion 75 within a range of 0.5 μm.

[0252] The sudden increase portion 73 is a portion where the impurity concentration suddenly increases from the first main surface 3 toward the peak portion 74. The sudden decrease portion 75 is a portion where the impurity concentration suddenly decreases from the peak portion 74 toward the first lower end 42b of the first outer well region 42. For example, the depth position of the peak portion 74 is 0.2 μm or more and 0.3 μm or less. The outer contact region 41 may have the sudden increase portion 73 and the sudden decrease portion 75 in the range of 0.1 μm or more and 0.2 μm or less on the shallower and deeper sides of the peak portion 74, respectively.

[0253] The sudden increase portion 73 has a thickness of 0.1 μm or more and 0.2 μm or less, and has a density change rate of 100% or more within this thickness range.Similarly, the sudden decrease portion 75 has a thickness of 0.1 μm or more and 0.2 μm or less, and has a density change rate of 100% or more within this thickness range.

[0254] The first outer well region 42 has a concentration gradient specific to an impurity region formed by channeling implantation. Fig. 12 shows the concentration gradient of the first outer well region 42 when a predetermined trivalent element (here, aluminum) is introduced into the second semiconductor region 7 parallel or nearly parallel to the axial channel of the second semiconductor region 7 with an implantation energy of 650 KeV. The depth (thickness) of the first outer well region 42 is about 3 µm, and the dose of the trivalent element is 1 x 10 １３ cm －２ is.

[0255] The p-type impurity concentration of the first outer well region 42 has a concentration gradient from the first upper end 42a to the first lower end 42b, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. The gradually increasing portion 20 is a portion that forms the first upper end 42a of the first outer well region 42, and is a portion where the p-type impurity concentration gradually increases from the first upper end 42a toward the first lower end 42b to the peak portion 21 at a relatively steep rate of increase.

[0256] The peak portion 21 is a portion having a peak value P2 (maximum value) of the p-type impurity concentration. The peak portion 21 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The depth position of the peak portion 21 is 0.5 μm or more and 1 μm or less.

[0257] The gradual portion 22 is formed in a region closer to the first lower end 42b than the peak portion 21, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the gradual portion 22 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the main body of the first outer well region 42. The p-type impurity concentration of the gradual portion 22 gradually decreases within a concentration range that is less than the p-type impurity concentration of the peak portion 21.

[0258] The gradual portion 22 is defined as a portion having a concentration decrease rate of 50% or less in a thickness range of at least 1 μm. In this example, the gradual portion 22 has a thickness of 0.7 μm or more and 1.5 μm or less, and has a concentration decrease rate of 50% or less in this thickness range. In this example, the p-type impurity concentration of the gradual portion 22 is 4.5×10 １６ cm －３ 9 x 10 or more １６ cm －３ The concentration range is as follows:

[0259] The gradually decreasing portion 23 is a portion that forms the first lower end 42b of the first outer well region 42. The gradually decreasing portion 23 has a concentration decrease rate that is greater than that of the gradual portion 22, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 22 toward the first lower end 42b. The concentration decrease rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration decrease rate per unit thickness of the gradual portion 22. The p-type impurity concentration of the gradually decreasing portion 23 is 1×10 １５ cm －３ It is gradually decreasing to.

[0260] Fig. 13 is a graph showing an example of the concentration gradient in the region along line XIII-XIII shown in Fig. 11. In Fig. 13, the vertical axis represents the p-type impurity concentration in the outer well region 40 (second outer well region 43), and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0261] 13, the second outer well region 43 has a concentration gradient specific to an impurity region formed by channeling implantation. Fig. 13 shows the concentration gradient of the second outer well region 43 when a predetermined trivalent element (here, aluminum) is introduced into the second semiconductor region 7 parallel or nearly parallel to the axial channel of the second semiconductor region 7 with an implantation energy of 650 KeV. The depth (thickness) of the second outer well region 43 is about 3 μm, and the dose of the trivalent element is 1×10 １３ cm －２ is.

[0262] The p-type impurity concentration of the second outer well region 43 has a concentration gradient from the second upper end 43a to the second lower end 43b, including a gradually increasing portion 85, a peak portion 86, a gradual portion 87, and a gradually decreasing portion 88. The gradually increasing portion 85 is a portion that forms the second upper end 43a of the second outer well region 43, and is a portion where the p-type impurity concentration gradually increases from the second upper end 43a toward the second lower end 43b to the peak portion 86 at a relatively steep rate of increase.

[0263] The peak portion 86 is a portion having a peak value P3 (maximum value) of the p-type impurity concentration. The peak portion 86 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The depth position of the peak portion 86 is 0.5 μm or more and 1 μm or less.

[0264] The gradual portion 87 is formed in a region closer to the second lower end 43b than the peak portion 86, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the gradual portion 87 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the main body of the second outer well region 43. The p-type impurity concentration of the gradual portion 87 gradually decreases within a concentration range that is less than the p-type impurity concentration of the peak portion 86.

[0265] The gradual portion 87 is defined as a portion having a concentration drop rate of 50% or less in a thickness range of at least 1 μm. In this example, the gradual portion 87 has a thickness of 0.7 μm or more and 1.5 μm or less, and has a concentration drop rate of 50% or less in this thickness range. The p-type impurity concentration of the gradual portion 87 is 4.5×10 １６ cm －３ 9 x 10 or more １６ cm －３ The concentration range is as follows:

[0266] The gradually decreasing portion 88 is a portion that forms the second lower end 43b of the second outer well region 43. The gradually decreasing portion 88 has a concentration decrease rate that is greater than the concentration decrease rate in the gradual portion 87, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 87 toward the second lower end 43b. The concentration decrease rate per unit thickness of the gradually decreasing portion 88 is greater than the concentration decrease rate per unit thickness of the gradual portion 87. The p-type impurity concentration of the gradually decreasing portion 88 decreases from the gradual portion 87 by 1×10 １５ cm －３ It is gradually decreasing to.

[0267] Fig. 14 is a graph showing an example of the concentration gradient of n-type impurities in the regions along line XIV-XIV shown in Fig. 9. In Fig. 14, the vertical axis represents the n-type impurity concentration of the source region 11, the cap region 72, and the base region 71, and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0268] 14 , in the depth direction of the second semiconductor region 7, the second semiconductor region 7 has a first concentration gradient 76 based on the cap region 72 in a relatively shallow portion, and a second concentration gradient 77 based on the base region 71 in a portion relatively deeper than the first concentration gradient 76. The second semiconductor region 7 exhibits a two-stage concentration gradient including the first concentration gradient 76 and the second concentration gradient 77. In addition, in FIG. 14 , a source concentration gradient 78 is a concentration gradient based on the n-type source region 11.

[0269] The first concentration gradient 76 and the source concentration gradient 78 each have a peak portion 79 (peak value P4 (maximum value)) and a peak portion 80 (peak value P5 (maximum value)). The peak value P5 is higher than the peak value P4. For example, the peak value P4 is 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration is as follows: The peak value P5 is 1×10 １８ cm －３ 1x10 or more １９ cm －３ The n-type impurity concentrations are as follows:

[0270] First concentration gradient 76 has an increasing portion 81 and a decreasing portion 82 on the shallower and deeper sides of peak portion 79. The thickness range of increasing portion 81 may be, for example, 1 μm or more and 2 μm or less. The thickness range of decreasing portion 82 may be, for example, 1 μm or more and 2 μm or less.

[0271] The source concentration gradient 78 has an increasing portion 83 and a decreasing portion 84 on the shallower and deeper sides of the peak portion 80, respectively. The thickness of the increasing portion 83 may be in the range of 0.1 μm to 0.2 μm, for example. The thickness of the decreasing portion 84 may be in the range of 0.1 μm to 0.2 μm, for example.

[0272] Fig. 15 is a graph showing an example of the concentration gradient of n-type impurities in the region along line XV-XV shown in Fig. 11. In Fig. 15, the vertical axis represents the n-type impurity concentration of field stop region 12 (second region 14 and first region 13) and base region 71, and the horizontal axis represents the depth in the thickness direction of second semiconductor region 7, with the upper end (first main surface 3) of second semiconductor region 7 as the reference (zero point).

[0273] 15 , in the depth direction of second semiconductor region 7, field stop region 12 has a second concentration gradient 70 based on second region 14 in a relatively shallow portion, and a first concentration gradient 69 based on first region 13 in a portion relatively deeper than second concentration gradient 70. Field stop region 12 exhibits a two-stage concentration gradient including first concentration gradient 69 and second concentration gradient 70.

[0274] The first concentration gradient 69 and the second concentration gradient 70 each have a peak portion 94 (peak value P6 (maximum value)) and a peak portion 95 (peak value P7 (maximum value)). The peak value P7 is higher than the peak value P6. For example, the peak value P6 is 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration is as follows: The peak value P7 is 1×10 １８ cm －３ 1x10 or more １９ cm －３ The n-type impurity concentrations are as follows:

[0275] The first concentration gradient 69 has an increasing portion 96 and a decreasing portion 97 on the shallower and deeper sides of the peak portion 94. The thickness range of the increasing portion 96 may be, for example, 1 μm or more and 2 μm or less. The thickness range of the decreasing portion 97 may be, for example, 1 μm or more and 2 μm or less.

[0276] The second concentration gradient 70 has an increasing portion 98 and a decreasing portion 99 on the shallower and deeper sides of the peak portion 95. The thickness of the increasing portion 98 may be, for example, not less than 0.1 μm and not more than 0.2 μm. The thickness of the decreasing portion 99 may be, for example, not less than 0.1 μm and not more than 0.2 μm.

[0277] 14 and 15 , in the depth direction of the chip 2, the first concentration gradient 69 of the first region 13 shown in FIG. 15 is equal to the first concentration gradient 76 of the cap region 72 shown in FIG. 14 . Here, the term "equal concentration gradients" may be defined as, for example, showing approximately the same concentration profile when the impurity concentration in the depth direction of the chip 2 is analyzed by secondary ion mass spectrometry (SIMS). Also, in the depth direction of the chip 2, the second concentration gradient 70 of the second region 14 shown in FIG. 15 is equal to the source concentration gradient 78 of the source region 11 shown in FIG. 14 .

[0278] As described above, according to the semiconductor device 1A, as shown in FIGS. 10 and 11 , the n-type field stop region 12 is disposed outside the outer well region 40. This makes it possible to prevent the spread of the depletion layer from the outer well region 40 just before the end faces (first to fourth side faces 5A to 5D) of the chip 2. By designing the position of the field stop region 12 (for example, the distance from the end face of the chip 2 to the inside, etc.), it is possible to appropriately control the spread of the depletion layer. As a result, the size of the chip 2 can be reduced, thereby enabling the miniaturization of the semiconductor device 1A.

[0279] Furthermore, the field stop region 12 is formed deeper than the outer well region 40. This makes it difficult for the depletion layer that spreads in the horizontal direction along the first main surface 3 to extend beyond the field stop region 12, and the spread of the depletion layer can be effectively suppressed.

[0280] Furthermore, first concentration gradient 69 in first region 13 of field stop region 12 is equal to first concentration gradient 76 in cap region 72. In other words, first region 13 and cap region 72 can be formed in the same process, which makes it possible to suppress a decrease in manufacturing efficiency due to the addition of field stop region 12 (first region 13).

[0281] Furthermore, second concentration gradient 70 of second region 14 of field stop region 12 is equal to source concentration gradient 78 of source region 11. In other words, second region 14 and source region 11 can be formed in the same process, which makes it possible to suppress a decrease in manufacturing efficiency due to the addition of field stop region 12 (second region 14).

[0282] The p-type impurity concentration of the first outer well region 42 formed by channeling implantation has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23. The gradual portion 22 occupies a thickness range of at least one-quarter of the first outer well region 42 and is located within the second semiconductor region 7. Specifically, the proportion of the gradual portion 22 in the first outer well region 42 is at least one-third. The proportion of the gradual portion 22 in the first outer well region 42 is typically at most one-half (less than one-half). The proportion of the gradual portion 22 in the first outer well region 42 may be at least one-half.

[0283] On the other hand, if the outer contact region 41 is formed by random implantation, it is difficult to realize a concentration gradient similar to the concentration gradient having the gradually increasing portion 20, the peak portion 21, the gradual portion 22, and the gradually decreasing portion 23 described above.

[0284] Therefore, when forming the first outer well region 42 shown in FIG. 9 by the random implantation method, it is necessary to employ a multi-stage random implantation method. In the multi-stage random implantation method, a process of introducing a trivalent element into the second semiconductor region 7 at different depths using multiple implantation energies is performed. For example, the trivalent element is introduced into the second semiconductor region 7 using different implantation energies, such as three stages, five stages, and seven stages. In this process, the trivalent element can be introduced to the desired depth, but the thickness of the region into which the trivalent element can be introduced is narrow. Therefore, to implant the element deeper, the number of steps in the random implantation method must be increased, complicating the manufacturing process. As a result, the design of the first outer well region 42 becomes complicated, and the increased number of ion implantation steps also increases the burden on the device.

[0285] In contrast, with the channeling implantation method, a first outer well region 42 having a relatively thick gentle portion 22 can be formed by a single ion implantation process. The first outer well region 42 for improving the breakdown voltage can be formed with fewer steps than when the random implantation method is used. As a result, the design of the first outer well region 42 can be simplified, and the burden on the device can be reduced.

[0286] Similarly, the p-type impurity concentration of the second outer well region 43 also has a gradually increasing portion 85, a peak portion 86, a gradual portion 87, and a gradually decreasing portion 88. Therefore, the design of the second outer well region 43 can be simplified, and the load on the device can also be reduced.

[0287] 16 is a cross-sectional view showing a field stop region 12 according to a second embodiment. Referring to FIG. 16 (second embodiment), the field stop region 12 may be composed solely of the first region 13. Therefore, the upper surface of the first region 13 may be exposed from the first main surface 3 as the upper surface 12a of the field stop region 12.

[0288] 17 to 20 are cross-sectional views showing outer well regions 40 according to the second to fifth embodiments. The semiconductor device 1A may include at least one of the outer well regions 40 according to the first to fifth embodiments. The semiconductor device 1A may simultaneously include at least two of the outer well regions 40 according to the first to fifth embodiments in the same cross-sectional region or different cross-sectional regions.

[0289] 17 (second embodiment), the first lower end 42b of the first outer well region 42 of the semiconductor device 1A may be located closer to the bottom of the second semiconductor region 7 with respect to the depth position of the boundary 62 between the cap region 72 and the base region 71. The first lower end 42b may be a portion of the first outer well region 42 that protrudes further toward the bottom of the second semiconductor region 7 than the boundary 62 between the cap region 72 and the base region 71 in the thickness direction of the second semiconductor region 7. As a result, the inner end of the first outer well region 42 may cross the boundary 62 between the cap region 72 and the base region 71 in the thickness direction of the second semiconductor region 7 and be in contact with both side portions of the cap region 72 and the base region 71.

[0290] 18 (third embodiment), the first lower end 42b of the first outer well region 42 of the semiconductor device 1A may be located closer to the first main surface 3 than the depth position of the boundary 62 between the cap region 72 and the base region 71. The first lower end 42b may be spaced apart from the boundary 62 between the cap region 72 and the base region 71 toward the first main surface 3 in the thickness direction of the second semiconductor region 7. As a result, the cap region 72 may have an extension 29 that extends across the outer periphery boundary 19 into the outer periphery region 9 and covers the first lower end 42b of the first outer well region 42 from the second main surface 4 side. The extension 29 contacts the first lower end 42b of the first outer well region 42 along the first main surface 3, forming a flat boundary along the first main surface 3.

[0291] 19 (fourth embodiment), the semiconductor device 1A may include a first outer well region 42 having a first side portion 42d extending vertically from a first upper end portion 42a to a first lower end portion 42b. That is, the first side portion 42d does not have to be inclined with respect to the first main surface 3.

[0292] 20 (fifth embodiment), the semiconductor device 1A may include a second outer well region 43 having a second side portion 43 d extending vertically from a second upper end portion 43 a toward a second lower end portion 43 b. That is, the second side portion 43 d does not need to be inclined with respect to the first main surface 3.

[0293] Fig. 21 is a graph showing the concentration gradient of the outer well region 40 according to the second embodiment. In Fig. 21, the vertical axis represents the p-type impurity concentration of the outer well region 40 (first outer well region 42 and second outer well region 43), and the horizontal axis represents the depth in the thickness direction of the second semiconductor region 7, with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0294] 21 is a graph showing the concentration gradient of the outer well region 40 formed by random implantation. This graph shows the concentration gradient of the outer well region 40 when a predetermined trivalent element (aluminum in this case) is introduced into the second semiconductor region 7 in a random direction with implantation energies of 190 KeV, 380 KeV, 650 KeV, 960 KeV, or 2000 KeV. The random direction is a direction (for example, the vertical direction Z) that is not parallel (or substantially parallel) to the axial channel of the second semiconductor region 7.

[0295] Fig. 22 is a plan view showing an example of the layout of a chip of a semiconductor device 1B according to a second embodiment of the present disclosure. Fig. 23 is an enlarged plan view showing a main portion of the first main surface 3 shown in Fig. 22. Fig. 24 is an enlarged plan view showing a main portion of the first main surface 3 shown in Fig. 22. Fig. 25 is a cross-sectional view taken along line XXV-XXV shown in Fig. 23. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 23. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 24.

[0296] 22 to 27, semiconductor device 1B has a configuration in which a configuration of a plurality of source structures 90 and a configuration of a plurality of isolation structures 30 are introduced into semiconductor device 1B.

[0297] The semiconductor device 1B includes a plurality of trench-type (trench electrode-type) source structures 90 formed in an inner portion of the first main surface 3. The source structures 90 may be referred to as "first source structures," "source structures," "second trench structures," etc. A source potential is applied to the plurality of source structures 90.

[0298] The plurality of source structures 90 are formed in the inner part of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of source structures 90 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and each extends in a strip shape in the second direction Y (= a-axis direction).

[0299] The source structures 90 are arranged in regions between the gate structures 15 at intervals in the first direction X from the gate structures 15, and face the gate structures 15 in the first direction X. That is, the source structures 90 are arranged alternately with the gate structures 15 in the first direction X, and extend in a strip-like manner in the second direction Y. The source structures 90 are arranged in a strip-like manner extending in the second direction Y.

[0300] The extension direction of the source structures 90 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the source structures 90 may be located in a region between the periphery of the body region 10 and the periphery of the source region 11. The source structures 90 may be arranged at intervals in the second direction Y according to the extension direction of the gate structures 15, and may each extend in a strip shape in the first direction X.

[0301] The plurality of source structures 90 penetrate the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of source structures 90 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0302] The multiple source structures 90 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The multiple source structures 90 are formed substantially perpendicular to the first main surface 3. The multiple source structures 90 may be formed in a shape that tapers toward the bottom of the second semiconductor region 7.

[0303] The side walls of the plurality of source structures 90 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls of the plurality of source structures 90 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the source structures 90. The bottom walls of the plurality of source structures 90 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the plurality of source structures 90 extend substantially flat in the horizontal direction. The bottom walls of the plurality of source structures 90 may be curved in an arc shape toward the second main surface 4.

[0304] The inclination angle (absolute value) of the sidewall of the source structure 90 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0305] The source structure 90 has a width that is approximately equal to the width of the gate structure 15. The width of the source structure 90 may be greater than the width of the gate structure 15 or may be less than the width of the gate structure 15.

[0306] The width of the source structure 90 may be 0.1 μm to 2 μm, and may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0307] The source structure 90 has a depth approximately equal to the depth of the gate structure 15. The depth of the source structure 90 is measured from the first main surface 3. The depth of the source structure 90 may be greater than the depth of the gate structure 15 or may be less than the depth of the gate structure 15.

[0308] The ratio (depth ratio) of the depth of the source structure 90 to the depth of the gate structure 15 may be 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0309] The depth of the source structure 90 may be 0.1 μm or more and 3 μm or less. The depth of the source structure 90 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the source structure 90 is preferably 0.5 μm or more and 1.5 μm or less.

[0310] The source structure 90 may have an aspect ratio of 1 to 3, inclusive. The aspect ratio of the source structure 90 is the ratio of the depth of the source structure 90 to the width of the source structure 90. The aspect ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3, inclusive. Preferably, the aspect ratio is 1.5 to 2.5, inclusive.

[0311] The pitch between the central portions of the source structures 90 and the gate structures 15 may be 0.1 μm to 2.5 μm. The pitch may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0312] Each of the plurality of source structures 90 includes a second trench 91, a second insulating film 92, and a second buried electrode 93. The second trench 91 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the source structure 90.

[0313] The second insulating film 92 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 92 preferably includes the same insulating material as the insulating material of the first insulating film 17. In this embodiment, the second insulating film 92 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 92 includes a silicon oxide film made of an oxide of the chip 2.

[0314] The second insulating film 92 covers the wall surface of the second trench 91. The second insulating film 92 includes a first film portion and a second film portion. The first film portion covers the side wall of the second trench 91 in a film-like manner. The second film portion covers the bottom wall of the second trench 91 in a film-like manner and is continuous with the first film portion.

[0315] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the second insulating film 92 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the second insulating film 92 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0316] The second insulating film 92 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0317] The second buried electrode 93 is buried in the second trench 91 with the second insulating film 92 sandwiched therebetween. The second buried electrode 93 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The second buried electrode 93 preferably contains the same type of conductive material as the conductive material of the first buried electrode 18. The second buried electrode 93 faces the second semiconductor region 7, the body region 10, and the source region 11 with the second insulating film 92 sandwiched therebetween.

[0318] The second buried electrode 93 has an electrode surface exposed from the second trench 91. The electrode surface is located closer to the bottom wall of the second trench 91 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the second trench 91.

[0319] The semiconductor device 1B includes a plurality of source well regions 26 formed in regions below the plurality of source structures 90 within the chip 2 (second semiconductor region 7) of the active region 8. The source well regions 26 may also be referred to as "second well regions" or the like. A source potential is applied to the source well regions 26.

[0320] The source well region 26 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source well region 26 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0321] The p-type impurity concentration of the source well region 26 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the source well region 26 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25. The p-type impurity (trivalent element) of the source well region 26 is preferably aluminum.

[0322] The multiple source well regions 26 are formed in the second semiconductor region 7 in regions below (specifically, directly below) the multiple source structures 90, spaced apart in the horizontal direction (first direction X) from the multiple gate well regions 25. The multiple source well regions 26 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple source structures 90, and overlap the multiple source structures 90 in a one-to-one correspondence in the thickness direction.

[0323] The multiple source well regions 26 each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding source structure 90. In other words, the multiple source well regions 26 are arranged in stripes extending in the second direction Y in plan view.

[0324] The extension direction of the multiple source well regions 26 coincides with the off-direction of the SiC single crystal. The multiple source well regions 26 may extend in the first direction X according to the extension direction of the multiple source structures 90. In this case, the multiple source well regions 26 intersect (specifically, are perpendicular to) the off-direction.

[0325] The multiple source well regions 26 are formed at intervals inward from the periphery of the active region 8. In the second direction Y, both ends of the multiple source well regions 26 may be located inward of the multiple source structures 90 with respect to both ends of the multiple source structures 90, or may be located closer to the periphery of the active region 8 with respect to both ends of the multiple source structures 90.

[0326] The plurality of source well regions 26 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of source structures 90, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of source well regions 26 each have an upper end located on the bottom wall side of the corresponding source structure 90, and a bottom located on the bottom side of the second semiconductor region 7.

[0327] The upper ends of the plurality of source well regions 26 may be connected to the bottom walls of the corresponding source structures 90. The upper ends of the plurality of source well regions 26 may extend along the sidewalls of the corresponding source structures 90 and be connected to the body region 10. The upper ends of the plurality of source well regions 26 may be formed at intervals from the bottom walls of the corresponding source structures 90 toward the bottom of the second semiconductor region 7.

[0328] The bottoms of the multiple source well regions 26 may be located on the bottom wall side of the multiple source structures 90 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0329] Each of the plurality of source well regions 26 has a bulging portion 26 a. The bulging portion 26 a extends in an arc shape horizontally from a region directly below the corresponding source structure 90 to both sides of the corresponding source structure 90. Each of the plurality of source well regions 26 is formed in a tapered shape from the bulging portion 26 a to the bottom.

[0330] The source well region 26 may have a width approximately equal to the width of the gate well region 25. The width of the source well region 26 may be greater than the width of the gate well region 25 or less than the width of the gate well region 25. The width of the source well region 26 may be greater than the width of the source structure 90 or less than the width of the source structure 90.

[0331] The width of the source well region 26 may be 0.1 μm or more and 2 μm or less. The width of the source well region 26 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0332] The source well region 26 may have a depth approximately equal to that of the gate well region 25. That is, the bottom of the source well region 26 may be located at a depth approximately equal to that of the bottom of the gate well region 25. The depth of the source well region 26 is the depth of the source well region 26 when referenced to the bottom wall of the source structure 90. The depth of the source well region 26 may be greater than or less than the depth of the gate well region 25.

[0333] The depth of the source well region 26 may be greater than 0 μm and less than or equal to 5 μm. The depth of the source well region 26 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0334] The source well regions 26 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the source well regions 26 is the ratio of the depth of the source well regions 26 to the width of the source well regions 26.

[0335] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0336] The pitch between the centers of the source well regions 26 and the gate well regions 25 (the pitch of the source well regions 26) is approximately equal to the pitch of the source structures 90 and the gate structures 15. The pitch of the source well regions 26 may be 0.1 μm or more and 2.5 μm or less.

[0337] The pitch of the source well regions 26 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0338] The source well region 26 forms a pn junction with the second semiconductor region 7. The source well region 26 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the source well region 26 spreads in the horizontal and thickness directions, alleviating the electric field with respect to the active region 8 (source structure 90). The depletion layer originating from the source well region 26 merges with the depletion layer originating from the gate well region 25.

[0339] The semiconductor device 1B includes a plurality of source contact regions 28 formed in the chip 2 (second semiconductor region 7). The source contact regions 28 may also be referred to as "second contact regions," etc. A source potential is applied to the source contact regions 28.

[0340] The source contact region 28 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source contact region 28 is higher than the p-type impurity concentration of the body region 10.

[0341] The p-type impurity concentration of the source contact region 28 is higher than the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the source contact region 28 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the source contact region 28 may be higher than the p-type impurity concentration of the gate contact region 27 or may be lower than the p-type impurity concentration of the gate contact region 27.

[0342] The source contact regions 28 are formed in regions along the source structures 90, spaced apart from the gate structures 15. The source contact regions 28 have a planar layout that differs from the planar layout of the gate contact regions 27. In this embodiment, the source contact regions 28 are formed in a one-to-one correspondence with the source structures 90.

[0343] The source contact regions 28 extend in a strip-like shape in the second direction Y in accordance with the extension direction of the corresponding source structures 90. In other words, the source contact regions 28 are formed in a stripe shape extending along the source structures 90 in a plan view.

[0344] The source contact regions 28 have lengths in the second direction Y that are greater than the lengths of the gate contact regions 27 and cross the gate contact regions 27 in the second direction Y. The source contact regions 28 may have lengths in the second direction Y that are greater than the lengths of the source structures 90 or may have lengths that are less than the lengths of the source structures 90.

[0345] The plurality of source contact regions 28 preferably have a total planar area larger than the total planar area of ​​the plurality of gate contact regions 27. The total planar area of ​​the plurality of source contact regions 28 may be larger than the channel area or may be smaller than the channel area.

[0346] The source contact regions 28 may be formed in a one-to-many correspondence with the source structures 90, similar to the gate contact regions 27. In this case, with respect to one and the other source structures 90, the gate contact regions 27 along one source structure 90 may face the source contact regions 28 along the other source structure 90 in the first direction X in plan view.

[0347] That is, the multiple source contact regions 28 may be generally arranged in a matrix with gaps in the first direction X and the second direction Y in a plan view. One of the multiple source contact regions 28 may face a region between the other multiple source contact regions 28 in the first direction X in a plan view. That is, the multiple source contact regions 28 may be generally arranged in a staggered pattern with gaps in the first direction X and the second direction Y in a plan view.

[0348] The plurality of source contact regions 28 are respectively interposed in regions between the bottom wall of the corresponding source structure 90 and the bottom of the corresponding source well region 26. The plurality of source contact regions 28 are respectively connected to the bottom wall of the corresponding source structure 90 and the corresponding source well region 26.

[0349] The plurality of source contact regions 28 increase the p-type impurity concentration at the upper end of the corresponding source well region 26. The plurality of source contact regions 28 extend from the region directly below the source structure 90 to both sides of the source structure 90 and have extensions that extend along the sidewalls of the source structure 90.

[0350] The thickness in the horizontal direction (first direction X) of the portion (extension) of the source contact region 28 along the side wall of the source structure 90 may be less than the thickness in the vertical direction Z of the portion of the source contact region 28 along the bottom wall of the source structure 90.

[0351] The extension of the source contact region 28 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding source well region 26 to the body region 10. This prevents the source well region 26 from being electrically floating, and improves the electrical response characteristics of the source well region 26.

[0352] The source contact region 28 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the source contact region 28 is exposed from the sidewall of the second trench 91 at the opening end of the second trench 91. The upper end of the source contact region 28 may extend horizontally in the surface portion of the body region 10.

[0353] The upper end of the source contact region 28 is electrically connected to the upper end of the adjacent gate contact regions 27 in the body region 10. In this embodiment, the upper end of the source contact region 28 is integrally formed with the upper end of the gate contact region 27.

[0354] The semiconductor device 1B includes one or more (in this embodiment, multiple) trench-type (trench electrode-type) isolation structures 30 formed on the first main surface 3 in the active region 8. The isolation structures 30 may also be referred to as "trench structures," "third trench structures," "dummy structures," etc.

[0355] The number of isolation structures 30 is arbitrary. The number of isolation structures 30 may be 1 or more and 15 or less. The number of isolation structures 30 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of isolation structures 30 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1B includes five isolation structures 30, as an example.

[0356] At least one or all of the plurality of isolation structures 30 may be formed in an electrically floating state. A source potential may be applied to at least one or all of the plurality of isolation structures 30. The plurality of isolation structures 30 may include one or more isolation structures 30 formed in an electrically floating state and one or more isolation structures 30 to which a source potential is applied.

[0357] The plurality of isolation structures 30 are formed in the inner part of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The plurality of isolation structures 30 define an active region 8 on the inner side of the first main surface 3, and define an outer periphery region 9 on the peripheral side of the first main surface 3. The active region 8 is located inward of the outermost isolation structure 30A (terminal isolation structure 30A), and the outer periphery region 9 is located outward of the terminal isolation structure 30A.

[0358] The plurality of isolation structures 30 are arranged on the periphery of the active region 8 at intervals from the plurality of gate structures 15 and the plurality of source structures 90. The plurality of isolation structures 30 are arranged at intervals from one another and are adjacent to one another in the horizontal direction with part of the chip 2 sandwiched between them. The plurality of isolation structures 30 each extend in a strip shape along the periphery of the first main surface 3. The plurality of isolation structures 30 have a portion extending in the first direction X and a portion extending in the second direction Y.

[0359] That is, the plurality of isolation structures 30 have portions extending in the extension direction (second direction Y) of the plurality of gate structures 15 (plurality of source structures 90) and portions extending in a direction (first direction X) intersecting the extension direction of the plurality of gate structures 15 (plurality of source structures 90). The plurality of isolation structures 30 may be formed in the shape of a polygonal ring (quadrilateral ring) that collectively surrounds the plurality of gate structures 15 and the plurality of source structures 90 in a plan view.

[0360] The plurality of isolation structures 30 are formed in a region outside the source region 11 and penetrate only the body region 10. The plurality of isolation structures 30 may also penetrate the source region 11. The plurality of isolation structures 30 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with part of the second semiconductor region 7 in between.

[0361] The plurality of isolation structures 30 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The plurality of isolation structures 30 are formed substantially perpendicular to the first main surface 3. The plurality of isolation structures 30 may be formed in a shape tapering toward the bottom of the second semiconductor region 7.

[0362] The side walls of the plurality of isolation structures 30 are formed by the m-plane ((1-100) plane) of the SiC single crystal and the a-plane ((11-20) plane) of the SiC single crystal. The bottom walls of the plurality of isolation structures 30 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the plurality of isolation structures 30 preferably extend substantially flat in the horizontal direction. The bottom walls of the plurality of isolation structures 30 may be curved in an arc shape toward the second main surface 4.

[0363] The inclination angle (absolute value) of the sidewall of the isolation structure 30 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0364] The isolation structure 30 may have a width that is approximately equal to the width of the gate structure 15. The width of the isolation structure 30 may be greater than or less than the width of the gate structure 15. The width of the isolation structure 30 may be approximately equal to the width of the source structure 90. The width of the isolation structure 30 may be greater than or less than the width of the source structure 90.

[0365] The width of the isolation structure 30 may be 0.1 μm or more and 2 μm or less. The width of the isolation structure 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0366] The isolation structure 30 may have a depth equal to or greater than the depth of the gate structure 15. The depth of the isolation structure 30 is measured from the first main surface 3. The depth of the isolation structure 30 may be greater than the depth of the gate structure 15 or may be less than the depth of the gate structure 15. In this embodiment, the depth of the isolation structure 30 is approximately equal to the depth of the gate structure 15.

[0367] The isolation structures 30 may have a depth equal to or greater than the depth of the source structures 90. The depth of the isolation structures 30 may be greater than the depth of the source structures 90 or may be less than the depth of the source structures 90. The depth of the isolation structures 30 is approximately equal to the depth of the source structures 90 in this embodiment.

[0368] The ratio (depth ratio) of the depth of the isolation structure 30 to the depth of the gate structure 15 (source structure 90) may be 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the following ranges: 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0369] The depth of the isolation structure 30 may be 0.1 μm or more and 3 μm or less. The depth of the isolation structure 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the isolation structure 30 is preferably 0.5 μm or more and 1.5 μm or less.

[0370] The isolation structure 30 may have an aspect ratio of 1 to 3. The aspect ratio of the isolation structure 30 is the ratio of the depth of the isolation structure 30 to the width of the isolation structure 30. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0371] The pitch of the centers of the isolation structures 30 (the pitch of the isolation structures 30) is preferably less than the pitch of the gate structures 15 and the source structures 90. The pitch of the isolation structures 30 may be greater than the pitch of the gate structures 15 and the source structures 90.

[0372] The pitch of the isolation structures 30 may be 0.1 μm or more and 2.5 μm or less. The pitch of the isolation structures 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0373] Each of the multiple isolation structures 30 includes a third trench 31, a third insulating film 32, and a third buried electrode 33. The third trench 31 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the isolation structure 30. The third trench 31 is a boundary trench that forms the peripheral boundary portion 19, which is the boundary portion between the active region 8 and the peripheral region 9. The terminal isolation structure 30A includes a terminal third trench 31A, a terminal third insulating film 32A, and a terminal third buried electrode 33A. Of the multiple third trenches 31, the terminal third trench 31A may be a boundary trench.

[0374] The third insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third insulating film 32 preferably includes the same insulating material as the insulating material of the first insulating film 17 (second insulating film 92). In this embodiment, the third insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.

[0375] The third insulating film 32 covers the wall surface of the third trench 31. The third insulating film 32 includes a first film portion and a second film portion. The first film portion covers the side wall of the third trench 31 in a film-like manner. The second film portion covers the bottom wall of the third trench 31 in a film-like manner and is continuous with the first film portion.

[0376] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the third insulating film 32 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the third insulating film 32 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0377] The third insulating film 32 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0378] The third buried electrode 33 is buried in the third trench 31 with the third insulating film 32 sandwiched therebetween. The third buried electrode 33 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The third buried electrode 33 preferably includes the same type of conductive material as the conductive material of the first buried electrode 18. The third buried electrode 33 faces the second semiconductor region 7 and the body region 10 with the third insulating film 32 sandwiched therebetween. The third buried electrode 33 may have a portion facing the source region 11.

[0379] The third buried electrode 33 has an electrode surface exposed from the third trench 31. The electrode surface is located closer to the bottom wall of the third trench 31 with respect to the height position of the first main surface 3. The electrode surface is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess in an inner portion that tapers toward the bottom wall of the third trench 31.

[0380] The semiconductor device 1B includes one or more (four in this embodiment) isolation well regions 35 formed in the chip 2 (second semiconductor region 7). The isolation well regions 35 may also be referred to as "third well regions," "first isolation well regions," etc. A source potential is applied to the isolation well regions 35. The number of isolation well regions 35 is less than the number of isolation structures 30.

[0381] The isolation well region 35 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the isolation well region 35 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0382] The p-type impurity concentration of the isolation well region 35 may be approximately equal to the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the isolation well region 35 may be higher than the p-type impurity concentration of the gate well region 25, or may be lower than the p-type impurity concentration of the gate well region 25.

[0383] The p-type impurity concentration of the isolation well region 35 may be approximately equal to the p-type impurity concentration of the source well region 26. The p-type impurity concentration of the isolation well region 35 may be higher than the p-type impurity concentration of the source well region 26, or may be lower than the p-type impurity concentration of the source well region 26. The p-type impurity (trivalent element) of the isolation well region 35 is preferably aluminum.

[0384] The plurality of isolation well regions 35 are formed in regions below (specifically, directly below) the plurality of isolation structures 30 so as to be adjacent to one another in the horizontal direction within the second semiconductor region 7. The plurality of isolation well regions 35 are formed in regions below a plurality (four in this embodiment) of the plurality of isolation structures 30 that are located on the active region 8 side.

[0385] The multiple isolation well regions 35 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple isolation structures 30, and overlap the multiple isolation structures 30 in a one-to-one correspondence in the thickness direction.

[0386] The plurality of isolation well regions 35 extend in a strip shape along the corresponding isolation structures 30 in plan view. The plurality of isolation well regions 35 have portions that extend in a first direction X along the corresponding isolation structures 30 in plan view, and portions that extend in a second direction Y along the corresponding isolation structures 30. In this embodiment, the plurality of isolation well regions 35 each extend in a polygonal ring shape (a square ring in this embodiment) along the corresponding isolation structures 30 in plan view.

[0387] The plurality of isolation well regions 35 are formed at intervals in the horizontal direction from the plurality of gate well regions 25 and the plurality of source well regions 26. In this embodiment, the plurality of isolation well regions 35 are connected to one another in the horizontal direction. The plurality of isolation well regions 35 may be formed at intervals in the horizontal direction and may face one another in the horizontal direction with a part of the second semiconductor region 7 sandwiched therebetween.

[0388] The plurality of isolation well regions 35 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of isolation structures 30, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of isolation well regions 35 each have an upper end located on the bottom wall side of the corresponding isolation structure 30, and a bottom located on the bottom side of the second semiconductor region 7.

[0389] The upper ends of the plurality of isolation well regions 35 may be connected to the bottom walls of the corresponding isolation structures 30. The upper ends of the plurality of isolation well regions 35 may extend along the side walls of the corresponding isolation structures 30 and be connected to the body region 10. The upper ends of the plurality of isolation well regions 35 may be formed at intervals from the bottom walls of the corresponding isolation structures 30 toward the bottom of the second semiconductor region 7.

[0390] The bottoms of the multiple isolation well regions 35 may be located on the bottom wall side of the corresponding isolation structure 30 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side of the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0391] Each of the isolation well regions 35 has a bulging portion 35a. The bulging portion 35a extends horizontally in an arc shape from the region directly below the corresponding isolation structure 30 to both sides of the corresponding isolation structure 30. The bulging portions 35a are connected to each other in the horizontal direction. Each of the isolation well regions 35 is formed in a tapered shape from the bulging portion 35a to the bottom.

[0392] The isolation well region 35 may have a width greater than or less than the width of the isolation structure 30. The width of the isolation well region 35 may be greater than or less than the width of the gate structure 15. The width of the isolation well region 35 may be greater than or less than the width of the source structure 90.

[0393] The width of the isolation well region 35 may be approximately equal to the width of the gate well region 25. The width of the isolation well region 35 may be greater than the width of the gate well region 25 or less than the width of the gate well region 25. The width of the isolation well region 35 may be approximately equal to the width of the source well region 26. The width of the isolation well region 35 may be greater than the width of the source well region 26 or less than the width of the source well region 26.

[0394] The width of the separation well region 35 may be 0.1 μm or more and 2 μm or less. The width of the separation well region 35 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0395] The isolation well region 35 may have a depth approximately equal to that of the gate well region 25. The depth of the isolation well region 35 is the depth of the isolation well region 35 when referenced to the bottom wall of the isolation structure 30. The bottom of the isolation well region 35 may be located at a depth approximately equal to that of the bottom of the gate well region 25. The depth of the isolation well region 35 may be greater than or less than the depth of the gate well region 25.

[0396] The depth of the isolation well region 35 may be approximately equal to the depth of the source well region 26. The bottom of the isolation well region 35 may be located at a depth approximately equal to the bottom of the source well region 26. The depth of the isolation well region 35 may be greater than or less than the depth of the source well region 26.

[0397] The depth of the separation well region 35 may be greater than 0 μm and less than or equal to 5 μm. The depth of the separation well region 35 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0398] The isolation well region 35 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the isolation well region 35 is the ratio of the depth of the isolation well region 35 to the width of the isolation well region 35.

[0399] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0400] The pitch of the centers of the isolation well regions 35 (the pitch of the isolation well regions 35) is approximately equal to the pitch of the isolation structures 30. In this embodiment, the pitch of the isolation well regions 35 is less than the pitch of the gate structures 15 and the source structures 90. The pitch of the isolation well regions 35 may be approximately equal to the pitch of the gate structures 15 and the source structures 90, or may be greater than the pitch of the gate structures 15 and the source structures 90.

[0401] In this embodiment, the pitch of the isolation well regions 35 is less than the pitch of the gate well regions 25 and the source well regions 26. The pitch of the isolation well regions 35 may be approximately equal to the pitch of the gate well regions 25 and the source well regions 26, or may be greater than the pitch of the gate well regions 25 and the source well regions 26.

[0402] The pitch of the separation well regions 35 may be 0.1 μm or more and 2.5 μm or less. The pitch of the separation well regions 35 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0403] The isolation well region 35 forms a pn junction with the second semiconductor region 7. The isolation well region 35 expands a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the isolation well region 35 expands in the horizontal and thickness directions and merges with the depletion layer originating from the body region 10 (inner portion of the active region 8). The isolation well region 35 expands the depletion layer originating from the body region 10 toward the periphery of the first main surface 3, thereby alleviating the electric field in the multiple isolation structures 30 (periphery portion of the active region 8).

[0404] The semiconductor device 1B includes one or more (five in this embodiment) isolation contact regions 37 formed in the chip 2 (second semiconductor region 7). The isolation contact regions 37 may also be referred to as "third contact regions," etc. A source potential is applied to the isolation contact regions 37. The isolation contact regions 37 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the isolation contact regions 37 is higher than the p-type impurity concentration of the body region 10.

[0405] The p-type impurity concentration of the isolation contact region 37 is higher than the p-type impurity concentration of the isolation well region 35. The p-type impurity concentration of the isolation contact region 37 is higher than the p-type impurity concentration of the gate well region 25. The p-type impurity concentration of the isolation contact region 37 is higher than the p-type impurity concentration of the source well region 26.

[0406] The p-type impurity concentration of the isolation contact region 37 may be approximately equal to the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the isolation contact region 37 may be higher than the p-type impurity concentration of the gate contact region 27, or may be lower than the p-type impurity concentration of the gate contact region 27.

[0407] The p-type impurity concentration of the isolation contact region 37 may be approximately equal to the p-type impurity concentration of the source contact region 28. The p-type impurity concentration of the isolation contact region 37 may be higher than the p-type impurity concentration of the source contact region 28, or may be lower than the p-type impurity concentration of the source contact region 28.

[0408] The plurality of isolation contact regions 37 are formed in regions along the plurality of isolation structures 30 for the isolation well region 35. The plurality of isolation contact regions 37 are formed at intervals from one another in regions between the plurality of isolation structures 30, and face one another with part of the second semiconductor region 7 interposed therebetween. The plurality of isolation contact regions 37 may be connected to one another in the regions between the plurality of isolation structures 30.

[0409] The plurality of isolation contact regions 37 are formed spaced apart from the plurality of gate structures 15 and the plurality of source structures 90. The plurality of isolation contact regions 37 are formed in a one-to-one correspondence with the plurality of isolation structures 30. The plurality of isolation contact regions 37 are interposed in regions between the bottom wall of the corresponding isolation structure 30 and the bottom of the corresponding isolation well region 35, and extend in strips along the corresponding isolation structure 30.

[0410] Each of the plurality of isolation contact regions 37 has a portion that extends in the first direction X along the corresponding isolation structure 30 in plan view, and a portion that extends in the second direction Y along the corresponding isolation structure 30. In this embodiment, each of the plurality of isolation contact regions 37 extends in a polygonal ring shape (a square ring in this embodiment) along the corresponding isolation structure 30 in plan view.

[0411] The plurality of isolation contact regions 37 may be formed at intervals following the extension direction of the corresponding isolation structures 30. In this case, the plurality of isolation contact regions 37 may each extend in a strip shape following the extension direction of the corresponding isolation structures 30.

[0412] The plurality of isolation contact regions 37 are respectively connected to the bottom walls of the corresponding isolation structures 30 and the corresponding isolation well regions 35. The plurality of isolation contact regions 37 increase the p-type impurity concentration at the upper end portions of the corresponding isolation well regions 35. The plurality of isolation contact regions 37 extend from the regions directly below the isolation structures 30 to both sides of the isolation structures 30, and have extensions that extend along the sidewalls of the corresponding isolation structures 30.

[0413] The thickness in the horizontal direction (first direction X) of the portions (extensions) of the multiple isolation contact regions 37 that extend along the side walls of the isolation structure 30 may be less than the thickness in the vertical direction Z of the portions of the multiple isolation contact regions 37 that extend along the bottom wall of the isolation structure 30.

[0414] The extensions of the plurality of isolation contact regions 37 are electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connect the corresponding isolation well regions 35 to the body region 10. This prevents the plurality of isolation well regions 35 from being electrically floating, and improves the electrical response characteristics of the plurality of isolation well regions 35.

[0415] The plurality of isolation contact regions 37 each have an upper end portion exposed from the first main surface 3. In this embodiment, the upper ends of the plurality of isolation contact regions 37 are exposed from the sidewall of the third trench 31 at the opening end of the third trench 31.

[0416] The upper ends of the multiple isolation contact regions 37 may extend horizontally in the surface layer portion of the body region 10. The upper ends of the multiple isolation contact regions 37 are electrically connected to each other within the body region 10. In this embodiment, the upper ends of the multiple isolation contact regions 37 are integrally formed within the body region 10.

[0417] The first outer well region 42 is formed deeper than the isolation well region 35 along the outer periphery boundary 19. The first outer well region 42 may also be approximately the same depth as the isolation well region 35.

[0418] In the horizontal direction along the first main surface 3, the first outer well region 42 partially covers at least the isolation well region 35 of the terminal third trench 31A.

[0419] More specifically, the isolation well region 35 includes a well side portion (in this embodiment, a bulging portion 35a) extending in the thickness direction of the second semiconductor region 7, and a well bottom portion 35b extending from the bulging portion 35a in a direction along the first main surface 3. The first outer well region 42 selectively covers the bulging portion 35a on the outer peripheral region 9 side (outside) of the isolation well region 35 of the terminal third trench 31A. The bulging portion 35a and well bottom portion 35b on the active region 8 side (inside) that are not covered by the first outer well region 42 are covered by the second semiconductor region 7 (in this embodiment, a cap region 72).

[0420] The outer contact region 41 extends in a strip shape along the terminal isolation structure 30A in the second direction Y. In this embodiment, the inner edge of the outer contact region 41 is connected to the terminal isolation structure 30A. In this embodiment, the inner edge of the outer contact region 41 is connected to the isolation well region 35 of the terminal third trench 31A. The inner edge of the outer contact region 41 extends along the terminal isolation structure 30A (peripheral boundary 19) in the thickness direction of the second semiconductor region 7 and is connected to the isolation well region 35 of the terminal third trench 31A. The first outer well region 42 is electrically connected to the body region 10 via the isolation well region 35 of the terminal third trench 31A.

[0421] The semiconductor device 1B includes an outer wiring 46 disposed on the main surface insulating film 45 in the peripheral region 9. The outer wiring 46 may also be referred to as "wiring," "main surface wiring," "peripheral wiring," "side wiring," etc. The outer wiring 46 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The outer wiring 46 preferably has the same type of conductive material (conductivity type) as at least one of the first buried electrode 18, the second buried electrode 93, and the third buried electrode 33.

[0422] The outer wiring 46 is arranged in the peripheral region 9 at a distance from the periphery of the first main surface 3 toward the active region 8. The outer wiring 46 is arranged on the outer well region 40 (first outer well region 42) and faces the first outer well region 42 with the main surface insulating film 45 interposed therebetween.

[0423] The outer wiring 46 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8) in the same direction as the first outer well region 42 in a plan view. The outer wiring 46 has a portion extending in the first direction X and a portion extending in the second direction Y.

[0424] In this embodiment, the outer wiring 46 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The outer wiring 46 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer wiring 46 may be either terminated or endless.

[0425] The outer wiring 46 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer wiring 46 is drawn out from the outer periphery region 9 into the active region 8. The inner edge portion of the outer wiring 46 covers one or more isolation structures 30 and is connected to one or more isolation structures 30.

[0426] In this embodiment, the inner edge of the outer wiring 46 covers the terminal isolation structure 30A and is connected to the third buried electrode 33 of the terminal isolation structure 30A.

[0427] The outer wiring 46 may be connected to at least one or all of the plurality of isolation structures 30 for the isolation well region 35. The outer wiring 46 is formed integrally with the third buried electrode 33 of the isolation structure 30. In other words, the outer wiring 46 is formed as an extension portion of the third buried electrode 33, and is routed over the main surface insulating film 45.

[0428] The outer edge of the outer wiring 46 is formed at a distance inward from the outer edge of the first outer well region 42. In this embodiment, the outer edge of the outer wiring 46 is disposed at a distance inward from the outer edge of the outer contact region 41, and has a portion facing the outer contact region 41 across the main surface insulating film 45. The outer edge of the outer wiring 46 may have a portion facing the first outer well region 42 in the stacking direction.

[0429] The semiconductor device 1B includes a plurality of gate openings 48 formed in an interlayer film 47 in the active region 8 (see FIG. 22 ). The plurality of gate openings 48 are formed in a one-to-many correspondence with a corresponding one of the gate structures 15. In this embodiment, the plurality of gate openings 48 penetrate the interlayer film 47 and expose one end or the other end of each of the plurality of gate structures 15 (first buried electrodes 18). The arrangement of the gate openings 48 relative to the gate structures 15 shown in FIG. 22 may be applied to the gate structure 15 of FIG. 3 .

[0430] The plurality of gate openings 48 may each have an opening end curved in an arc shape. The plurality of gate openings 48 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view. The plurality of gate openings 48 may each have an opening end curved in an arc shape.

[0431] The semiconductor device 1B includes a plurality of source openings 49 formed in the interlayer film 47 in the active region 8. The plurality of source openings 49 are formed in a portion of the interlayer film 47 that covers the active region 8. The plurality of source openings 49 are formed in a one-to-one correspondence with the plurality of source structures 90 in regions between the plurality of gate structures 15. The plurality of source openings 49 each extend in a strip shape in the second direction Y along the corresponding source structure 90.

[0432] The plurality of source openings 49 penetrate the main surface insulating film 45 and the interlayer film 47, and expose a corresponding source structure 90, a source region 11, a plurality of gate contact regions 27, and a plurality of source contact regions 28. Each of the plurality of source openings 49 may have an opening end curved in an arc shape.

[0433] The plurality of source openings 49 may be formed in a one-to-many correspondence with a corresponding one of the source structures 90. In this case, the plurality of source openings 49 may be formed at intervals along the corresponding one of the source structures 90. In this case, the plurality of source openings 49 may be formed in a quadrangular shape, a rectangular shape (strip shape), a circular shape, or the like in a plan view.

[0434] 28 is a cross-sectional view of a main part of a semiconductor device 1C according to a third embodiment of the present disclosure, showing a cross section taken at the same position as in FIG.

[0435] 28, semiconductor device 1C has a configuration obtained by modifying the configuration of a plurality of gate structures 15 in semiconductor device 1A. More specifically, semiconductor device 1C has gate structure 100, which is an example of a planar gate structure, instead of gate structure 15, which is an example of a trench gate structure.

[0436] Prior to describing the gate structure 100, the semiconductor device 1C includes a plurality of p-type body regions 101 formed in a surface layer portion of the first main surface 3 in the active region 8. The plurality of body regions 101 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 101 are arranged in stripes extending in the second direction Y.

[0437] The plurality of body regions 101 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 with a portion of the first semiconductor region 6 sandwiched between them. The plurality of body regions 101 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The plurality of body regions 101 are exposed from the first main surface 3. In this embodiment, the plurality of body regions 101 are formed at intervals from the bottom of the cap region 72 toward the first main surface 3, and face the base region 71 with a portion of the cap region 72 sandwiched between them.

[0438] The semiconductor device 1C includes n-type source regions 102 formed in the surface layer portions of the plurality of body regions 101. The source regions 102 have a higher n-type impurity concentration than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the source regions 102.

[0439] The source region 102 has an upper surface 102a exposed from the first main surface 3 of the active region 8. The upper surface 12a of the field stop region 12 and the upper surface 102a of the source region 102 are located at the same height position. In other words, there is no difference in height between the upper surface 12a and the upper surface 102a.

[0440] The semiconductor device 1C includes a plurality of p-type channel regions 103 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 103 are defined in the surface layer portions of the plurality of body regions 101 in regions between ends of the plurality of body regions 101 and peripheral edges of the source regions 102. In this embodiment, the plurality of channel regions 103 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 103 are arranged in stripes extending in the second direction Y.

[0441] The gate structure 100 is disposed on at least one channel region 103. In this embodiment, each gate structure 100 is disposed across the region between two adjacent body regions 101 to straddle the two body regions 101, and covers a plurality of channel regions 103. Specifically, each gate structure 100 is disposed across a source region 102 on one body region 101 side and a source region 102 on the other body region 101 side, and covers a part of the source region 102 and the channel region 103.

[0442] The gate structure 100 has a layered structure including an insulating film 104 and a gate electrode 105. The insulating film 104 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 104 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 104 includes a silicon oxide film made of an oxide of the chip 2.

[0443] The insulating film 104 covers the first main surface 3 in a film form and is disposed on at least one channel region 103. In this embodiment, the insulating film 104 is disposed so as to straddle two adjacent body regions 101 and covers the multiple channel regions 103.

[0444] Specifically, the insulating film 104 is arranged across the source region 102 on one body region 101 side and the source region 102 on the other body region 101 side, and covers part of the source region 102 and the channel region 103.

[0445] The thickness of the insulating film 104 may be 10 nm or more and 150 nm or less. The thickness of the insulating film 104 may be a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 104 is preferably 25 nm or more and 75 nm or less.

[0446] The gate electrode 105 is disposed on the insulating film 104 and faces at least one channel region 103 across the insulating film 104. A gate potential as a control potential is applied to the gate electrode 105. The gate electrode 105 controls inversion and non-inversion of the at least one channel region 103 in response to the gate potential.

[0447] The gate electrode 105 includes a conductive semiconductor polycrystalline. The gate electrode 105 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 105 is adjusted depending on the gate threshold voltage to be achieved. The gate electrode 105 may also be referred to as a "polysilicon gate," a "poly gate," or the like.

[0448] The semiconductor device 1C includes a second cap region 106 stacked on the cap region 72. The second cap region 106 is a part of the second semiconductor region 7. In other words, the second semiconductor region 7 of the semiconductor device 1C includes a stacked structure of the base region 71, the cap region 72, and the second cap region 106.

[0449] The second cap region 106 is formed on the side of the body region 101, between the cap region 72 and the first main surface 3. The second cap region 106 is formed in a layer shape that is in contact with the body region 101 and extends along the first main surface 3. The body region 101 crosses the boundary between the cap region 72 and the second cap region 106 in the thickness direction of the second semiconductor region 7, and is in contact with both side portions of the cap region 72 and the second cap region 106.

[0450] The thickness of the second cap region 106 may be 0.1 μm or more and 1.0 μm or less, and is preferably 0.1 μm or more and 0.5 μm or less.

[0451] The n-type impurity concentration of the second cap region 106 is preferably lower than the n-type impurity concentration of the cap region 72. The n-type impurity concentration of the second cap region 106 may be the same as the n-type impurity concentration of the base region 71. The second cap region 106 has an n-type impurity concentration of 1×10 １５ cm －３ 5x10 or more１６ cm －３ The n-type impurity concentration of the second cap region 106 may have a peak value of the following: The n-type impurity concentration of the second cap region 106 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the second cap region 106 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0452] In this embodiment, the n-type impurity concentration of the second cap region 106 is adjusted by nitrogen. The second cap region 106 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second cap region 106 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0453] 29 is a cross-sectional view of a main part of a semiconductor device 1D according to a fourth embodiment of the present disclosure, showing a cross section taken at the same position as in FIG.

[0454] Referring to FIG. 29, a semiconductor device 1D has a configuration in which a super junction structure is introduced into the semiconductor device 1C.

[0455] The semiconductor device 1D includes a plurality of p-type first pillar regions 108 formed in the second semiconductor region 7 in the active region 8. The first pillar regions 108 may also be referred to as "first pillar layers," "first column layers (regions)," "p-type layers (regions)," "p-type zones," etc. The plurality of first pillar regions 108 are formed at intervals in the horizontal direction within the second semiconductor region 7, and define a plurality of n-type second pillar regions 109, each of which is made up of a portion of the second semiconductor region 7. In this embodiment, the plurality of second pillar regions 109 are formed by the cap region 72. The second pillar regions 109 may also be referred to as "second pillar layers," "second column layers (regions)," "n-type layers (regions)," "n-type zones," etc.

[0456] The plurality of first pillar regions 108 form a superjunction structure SJ together with the plurality of second pillar regions 109 in the second semiconductor region 7 .

[0457] The p-type impurity concentration of the plurality of first pillar regions 108 may be higher than that of the body region 101 or may be lower than that of the body region 101. １６ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the first pillar region 108 may have the following peak value. The p-type impurity concentration of the first pillar region 108 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the first pillar region 108 is adjusted by a trivalent element that is heavier than carbon. In other words, the first pillar region 108 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the first pillar region 108 is adjusted by aluminum.

[0458] The width of the first pillar region 108 is preferably less than the thickness of the second semiconductor region 7. The width of the first pillar region 108 is the width in a direction perpendicular to the extension direction of the first pillar region 108. The width of the first pillar region 108 may be 0.1 μm or more and 5 μm or less.

[0459] The thickness of the first pillar region 108 may be referred to as the depth of the first pillar region 108. The thickness of the first pillar region 108 may be less than the thickness of the second semiconductor region 7. The thickness of the first pillar region 108 may be greater than the thickness of the second semiconductor region 7. The thickness of the first pillar region 108 may be approximately equal to the thickness of the second semiconductor region 7. The thickness of the first pillar region 108 is preferably 1 μm or more and 5 μm or less.

[0460] The pitch of the multiple first pillar regions 108 in the first direction X is preferably less than the thickness of the second semiconductor region 7. The pitch of the multiple first pillar regions 108 may be not less than 0.1 μm and not more than 5 μm.

[0461] In this embodiment, the plurality of second pillar regions 109 may have the same peak n-type impurity concentration as that of the cap region 72 of the second semiconductor region 7. The n-type impurity concentration is adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second pillar regions 109 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. In this embodiment, the n-type impurity concentration of the second pillar regions 109 is adjusted by phosphorus.

[0462] The width of the second pillar region 109 is the width in a direction perpendicular to the extension direction of the second pillar region 109. The width of the second pillar region 109 is preferably the same as the width of the first pillar region 108. Of course, the width of the second pillar region 109 may be wider or narrower than the width of the first pillar region 108. The width of the second pillar region 109 is preferably less than the thickness of the second semiconductor region 7. The width of the second pillar region 109 may be 0.1 μm or more and 5 μm or less.

[0463] The thickness of the second pillar region 109 may be referred to as the depth of the second pillar region 109. The thickness of the second pillar region 109 may be less than the thickness of the second semiconductor region 7. The thickness of the second pillar region 109 may be greater than the thickness of the second semiconductor region 7. The thickness of the second pillar region 109 may be approximately equal to the thickness of the second semiconductor region 7. The thickness of the second pillar region 109 is preferably not less than 1 μm and not more than 5 μm.

[0464] The pitch of the multiple second pillar regions 109 in the first direction X is preferably less than the thickness of the second semiconductor region 7. The pitch of the multiple second pillar regions 109 may be not less than 0.1 μm and not more than 5 μm.

[0465] The body regions 101 are formed in the surface layer portion of the first main surface 3 so as to overlap the first pillar regions 108 corresponding to them in the stacking direction. Specifically, the body regions 101 overlap the first pillar regions 108 in a one-to-one correspondence in the stacking direction.

[0466] The plurality of body regions 101 are each formed wider than the first pillar region 108 directly below them, and are formed at intervals from the adjacent plurality of first pillar regions 108 toward the first pillar region 108 directly below them. The plurality of body regions 101 expose a part of the second pillar region 109 from a region of the first main surface 3 between the adjacent plurality of first pillar regions 108.

[0467] The first outer well region 42 is formed deeper than the plurality of first pillar regions 108 along the outer circumferential boundary 19. The first outer well region 42 may also have approximately the same depth as the plurality of first pillar regions 108.

[0468] The above-described embodiment (including its modified examples) can be implemented in other embodiments. For example, in the above-described second embodiment, the outer wiring 46 is connected to the source electrode 51. However, the outer wiring 46 may be electrically separated from the source electrode 51. In this case, the outer wiring 46 may be formed in an electrically floating state as a floating wiring or a field wiring (a so-called field preplate).

[0469] In each of the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the first semiconductor region 6 may include a silicon single crystal. Similarly, the second semiconductor region 7 may include a silicon single crystal.

[0470] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0471] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0472] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0473] [Supplementary Note 1-1] A SiC chip (2) having a main surface (3), an active region (8) provided on the main surface (3), an outer peripheral region (9) provided on the main surface (3) and surrounding the periphery of the active region (8), a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), the semiconductor region (7) including a base region (71) spanning the active region (8) and the outer peripheral region (9), and a cap region (72) formed in at least the active region (8) in a surface layer portion of the base region (71) and having a higher impurity concentration than the base region (71), and a device structure formed in the active region (8), the device structure including a body region (10, 101) of a second conductivity type formed in a surface layer portion of the semiconductor region (7), and a source region (11, 102) of a first conductivity type formed in a surface layer portion of the body region (10, 101), A semiconductor device (1A, 1B, 1C, 1D) including: an outer well region (40) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in the peripheral region (9); and a field stop region (12) formed outside the outer well region (40), having a higher impurity concentration than the base region (71), and having the same depth as the cap region (72).

[0474] [Supplementary Note 1-2] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 1-1, wherein the field stop region (12) has a first concentration gradient (69) in a depth direction of the SiC chip (2) that is equal to a concentration gradient of the cap region (72).

[0475] [Supplementary Note 1-3] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 1-2, wherein the first concentration gradient (69) in the field stop region (12) includes a first peak value (94, P6), and the field stop region (12) further includes a second concentration gradient (70) including a second peak value (95, P7) higher than the first peak value (94, P6) on the main surface (3) side than the first peak value (94, P6).

[0476] [Appendix 1-4] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-3, wherein the second concentration gradient (70) in the field stop region (12) is equal to the concentration gradient (78) in the source region (11, 102) in the depth direction of the SiC chip (2).

[0477] [Supplementary Note 1-5] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Note 1-1 to Supplementary Note 1-4, wherein the field stop region (12) is formed deeper than the outer well region (40).

[0478] [Supplementary Note 1-6] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-1 to Supplementary Note 1-5, wherein the device structure includes a trench gate structure (15) having a gate trench (16) that penetrates the source region (11) and the body region (10) to reach the semiconductor region (7), a gate insulating film (17) formed on an inner surface of the gate trench (16), and a gate electrode (18) buried in the gate trench (16) via the gate insulating film (17), and the field stop region (12) is formed deeper than the trench gate structure (15).

[0479] [Appendix 1-7] The semiconductor device (1A, 1B) according to Appendix 1-6, further comprising a gate well region (25) of a second conductivity type formed at the bottom of the gate trench (16), wherein the field stop region (12) is formed deeper than the gate well region (25).

[0480] [Supplementary Note 1-8] The semiconductor device (1C, 1D) according to any one of Supplementary Note 1-1 to Supplementary Note 1-5, wherein the device structure includes a planar gate structure (100) formed on the main surface (3) and having a gate electrode (105) facing the body region (101), and a gate insulating film (104) between the gate electrode (105) and the main surface (3).

[0481] [Supplementary Note 1-9] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Note 1-1 to Supplementary Note 1-8, further comprising: an insulating layer (47) formed on the main surface (3) of the SiC chip (2); and source electrodes (51, 56) selectively connected to the source region (11, 102) and the outer well region (40) via the insulating layer (47) among the device structure, the outer well region (40), and the field stop region (12), wherein the field stop region (12) is covered by the insulating layer (47) and is formed in an electrically floating state.

[0482] [Appendix 1-10] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-9, wherein the source electrode (51, 56) selectively faces the device structure and the outer well region (40) of the device structure, the outer well region (40), and the field stop region (12), with the insulating layer (47) sandwiched therebetween.

[0483] [Supplementary Note 1-11] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Note 1-1 to Supplementary Note 1-10, wherein the field stop region (12) is arranged inwardly and apart from the end faces (4A, 4B, 4C, 4D) of the SiC chip (2), and the main surface (3) of the SiC chip (2) is a continuous, flat surface without steps from the active region (8) through the peripheral region (9) to the end faces (4A, 4B, 4C, 4D).

[0484] [Appendix 1-12] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-11, wherein both the field stop region (12) and the source region (11, 102) have upper surfaces (11 a, 12 a) exposed from the main surface (3), and the upper surface (12 a) of the field stop region (12) and the upper surface (11 a) of the source region (11, 102) are disposed at the same height.

[0485] [Supplementary Note 1-13] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Note 1-1 to Supplementary Note 1-12, wherein the outer well region (40) includes a first outer well region (42) formed along a peripheral boundary (19) between the active region (8) and the peripheral region (9), and a plurality of second outer well regions (43) formed outside the first outer well region (42) and surrounding the first outer well region (42), and the field stop region (12) is arranged apart from the outer side of the plurality of second outer well regions (43).

[0486] [Supplementary Note 1-14] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Note 1-1 to Supplementary Note 1-13, wherein the field stop region (12) is formed in a ring shape surrounding the active region (8).

[0487] [Appendix 1-15] The semiconductor device (1A, 1B, 1C, 1D) according to Appendix 1-14, further including an edge voltage relaxation region (60) of a second conductivity type that is arranged further outward than the field stop region (12), surrounds the field stop region (12), and is exposed from the end surface (4A, 4B, 4C, 4D) of the SiC chip (2), the field stop region (12) being arranged inward and spaced apart from the end surface (4A, 4B, 4C, 4D) of the SiC chip (2).

[0488] [Supplementary Note 1-16] A SiC chip (2) having a main surface (3), an active region (8) provided on the main surface (3), a peripheral region (9) provided on the main surface (3) and surrounding the periphery of the active region (8), and a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), the semiconductor region (7) including a base region (71) spanning the active region (8) and the peripheral region (9), and a cap region (72) formed in at least the surface layer portion of the base region (71) in the active region (8) and having a higher impurity concentration than the base region (71); a device structure formed in the active region (8), the device structure including: a body region (10) of a second conductivity type formed in a surface layer portion of the cap region (72); a source region (11) of a first conductivity type formed in a surface layer portion of the body region (10); a gate trench (16) penetrating the source region (11) and the body region (10) and having a bottom within the cap region (72); a gate insulating film (17) formed on an inner surface of the gate trench (16); and a plurality of trench gate structures (15) each having a gate electrode (18) embedded in the gate trench (16) via the gate insulating film (17); and an outer well region (40) of the second conductivity type selectively formed in a surface layer portion of the base region (71) in the peripheral region (9). a field stop region (12) selectively formed in a surface layer portion of the base region (71) outside the outer well region (40), having a higher impurity concentration than the base region (71), being deeper than the trench gate structure (15), and having the same depth as the cap region (72).

[0489] [Appendix 1-17] The semiconductor device (1A, 1B) according to Appendix 1-16, wherein the field stop region (12) has, in a depth direction of the SiC chip (2), a first concentration gradient (69) that includes a first peak value (94, P6) and is equal to the concentration gradient of the cap region (72), and a second concentration gradient (70) that includes a second peak value (95, P7) that is higher than the first peak value (94, P6) on the main surface (3) side.

[0490] [Appendix 1-18] The semiconductor device (1A, 1B) according to Appendix 1-17, wherein the second concentration gradient (70) of the field stop region (12) is equal to the concentration gradient of the source region (11) in the depth direction of the SiC chip (2).

[0491] [Appendix 1-19] The semiconductor device (1A, 1B) according to any one of Appendices 1-16 to 1-18, further comprising a gate well region (25) of a second conductivity type formed at the bottom of the gate trench (16), and the field stop region (12) is formed deeper than the gate well region (25).

[0492] [Appendix 1-20] The semiconductor device (1A, 1B) according to any one of Appendices 1-16 to 1-19, further comprising: an insulating layer (47) formed on the main surface (3) of the SiC chip (2); and source electrodes (51, 56) selectively facing the device structure and the outer well region (40) across the insulating layer (47) among the device structure, the outer well region (40), and the field stop region (12), and selectively connected to the source region (11) and the outer well region (40) via the insulating layer (47), wherein the field stop region (12) is covered by the insulating layer (47) and is formed in an electrically floating state.

[0493] 1A: Semiconductor device 1B: Semiconductor device 1C: Semiconductor device 1D: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor region 7: Second semiconductor region 8: Active region 9: Peripheral region 10: Body region 11: Source region 11a: Top surface 12: Field stop region 12a: Top surface 13: First region 14: Second region 15: Gate structure 15A: Terminal gate structure 16: First trench 16A: Terminal first trench 17: First insulating film 17A: Terminal first insulating film 18: First buried electrode 18A: Terminal first buried electrode 19: Peripheral boundary portion 20 : Gradual increase portion 21 : Peak portion 22 : Gradual decrease portion 23 : Gradual decrease portion 25 : Gate well region 25 a : Bulging portion 25 b : Well bottom 26 : Source well region 26 a : Bulging portion 27 : Gate contact region 28 : Source contact region 29 : Extension portion 30 : Isolation structure 30A : Terminal isolation structure 31 : Third trench 31A : Terminal third trench 32 : Third insulating film 32A : Terminal third insulating film 33 : Third buried electrode 33A : Terminal third buried electrode 35 : Isolation well region 35 a : Bulging portion 35 b : Well bottom 37 : Isolation contact region 40 : Outer well region 41 : Outer contact region 42 : First outer well region 42 a : First upper end portion 42 b : First lower end 42c : First main body portion 42d : First side portion 43 : Second outer well region 43a : Second upper end 43b : Second lower end 43c : Second main body portion 43d : Second side portion 45 : Main surface insulating film 46 : Outer wiring 47 : Interlayer film 48 : Gate opening 49 : Source opening 50 : Outer opening 51 : Source electrode 51a : First pad portion 51b : Second pad portion 51c : Third pad portion 52 : Lower electrode film 53 : Main electrode film 56 : Source wiring 57 : Gate electrode 58 : Gate wiring 59 : Drain electrode 60 : Voltage relaxation region 60a : Upper surface 60b : Side surface 61 : Boundary portion62: Boundary portion 63: Central portion 64: Edge portion 65: Gap 66: Central portion 67: Edge portion 68: Gap 69: First concentration gradient 70: Second concentration gradient 71: Base region 72: Cap region 73: Rapid increase portion 74: Peak portion 75: Rapid decrease portion 76: First concentration gradient 77: Second concentration gradient 78: Source concentration gradient 79: Peak portion 80: Peak portion 81: Increasing portion 82: Decreasing portion 83: Increasing portion 84: Decreasing portion 85: Gradual increase portion 86: Peak portion 87: Gradual increase portion 88: Gradual decrease portion 90: Source structure 91: Second trench 92: Second insulating film 93: Second buried electrode 94: Peak portion 95: Peak portion 96: Increasing portion 97: Decreasing portion 98: Increasing portion 99: Decreasing portion 100: Gate structure 101: Body region 102: Source region 103: Channel region 104: Insulating film 105: Gate electrode 106: Second cap region 108: First pillar region 109: Second pillar region

Claims

1. A semiconductor device comprising: a SiC chip having a main surface; an active region provided on the main surface; a peripheral region provided on the main surface and surrounding the active region; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, the semiconductor region including a base region spanning the active region and the peripheral region, and a cap region formed in at least the active region in a surface layer portion of the base region and having a higher impurity concentration than the base region; a device structure formed in the active region, the device structure including a body region of a second conductivity type formed in a surface layer portion of the semiconductor region, and a source region of a first conductivity type formed in a surface layer portion of the body region; an outer well region of the second conductivity type formed in a surface layer portion of the semiconductor region in the peripheral region; and a field stop region formed outside the outer well region, having a higher impurity concentration than the base region and having the same depth as the cap region.

2. The semiconductor device according to claim 1, wherein the field stop region has a first concentration gradient in the depth direction of the SiC chip that is equal to the concentration gradient of the cap region.

3. The semiconductor device described in claim 2, wherein the first concentration gradient in the field stop region includes a first peak value, and the field stop region further has a second concentration gradient including a second peak value higher than the first peak value on the main surface side of the first peak value.

4. The semiconductor device according to claim 3, wherein the second concentration gradient in the field stop region is equal to the concentration gradient in the source region in the depth direction of the SiC chip.

5. The semiconductor device according to claim 1, wherein the field stop region is formed deeper than the outer well region.

6. A semiconductor device according to any one of claims 1 to 5, wherein the device structure includes a trench gate structure having a gate trench that penetrates the source region and the body region to reach the semiconductor region, a gate insulating film formed on the inner surface of the gate trench, and a gate electrode embedded in the gate trench via the gate insulating film, and the field stop region is formed deeper than the trench gate structure.

7. The semiconductor device according to claim 6, further comprising a gate well region of the second conductivity type formed at the bottom of said gate trench, said field stop region being formed deeper than said gate well region.

8. The semiconductor device according to any one of claims 1 to 5, wherein the device structure includes a planar gate structure formed on the main surface and having a gate electrode facing the body region, and a gate insulating film between the gate electrode and the main surface.

9. The semiconductor device according to any one of claims 1 to 8, further comprising: an insulating layer formed on the main surface of the SiC chip; and a source electrode selectively connected to the source region and the outer well region via the insulating layer among the device structure, the outer well region, and the field stop region, wherein the field stop region is covered by the insulating layer and is formed in an electrically floating state.

10. The semiconductor device according to claim 9, wherein the source electrode selectively faces one of the device structure, the outer well region, and the field stop region, with the insulating layer sandwiched therebetween.

11. A semiconductor device according to any one of claims 1 to 10, wherein the field stop region is positioned inwardly away from the end face of the SiC chip, and the main surface of the SiC chip is a continuous, flat surface without steps extending from the active region through the peripheral region to the end face.

12. The semiconductor device according to claim 11, wherein both the field stop region and the source region have upper surfaces exposed from the main surface, and the upper surfaces of the field stop region and the source region are located at the same height.

13. A semiconductor device according to any one of claims 1 to 12, wherein the outer well region includes a first outer well region formed along the peripheral boundary between the active region and the peripheral region, and a plurality of second outer well regions formed outside the first outer well region and surrounding the first outer well region, and the field stop region is positioned outside and spaced apart from the plurality of second outer well regions.

14. The semiconductor device according to any one of claims 1 to 13, wherein the field stop region is formed in a ring shape surrounding the active region.

15. The semiconductor device according to claim 14, wherein the field stop region is positioned inwardly and away from the end face of the SiC chip, and further includes an edge voltage relaxation region of a second conductivity type that is positioned further outward than the field stop region, surrounds the field stop region, and is exposed from the end face of the SiC chip.

16. A SiC chip having a main surface, an active region provided on the main surface, a peripheral region provided on the main surface and surrounding the active region, a first conductivity type semiconductor region formed in a surface layer portion of the main surface, the semiconductor region including a base region spanning the active region and the peripheral region, and a cap region formed in at least the active region in a surface layer portion of the base region and having a higher impurity concentration than the base region, a device structure formed in the active region, the device structure including a body region of a second conductivity type formed in a surface layer portion of the cap region, a source region of the first conductivity type formed in a surface layer portion of the body region, a gate trench penetrating the source region and the body region and having a bottom within the cap region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded in the gate trench via the gate insulating film, and an outer well region of a second conductivity type selectively formed in a surface layer portion of the base region in the peripheral region. a field stop region selectively formed in a surface layer portion of the base region outside the outer well region, having a higher impurity concentration than the base region, being deeper than the trench gate structure and having the same depth as the cap region.

17. The semiconductor device according to claim 16, wherein the field stop region has, in the depth direction of the SiC chip, a first concentration gradient that includes a first peak value and is equal to the concentration gradient of the cap region, and a second concentration gradient that includes a second peak value that is higher than the first peak value and is located closer to the main surface than the first peak value.

18. The semiconductor device according to claim 17, wherein the second concentration gradient in the field stop region is equal to the concentration gradient in the source region in the depth direction of the SiC chip.

19. The semiconductor device according to any one of claims 16 to 18, further comprising a gate well region of the second conductivity type formed at the bottom of the gate trench, wherein the field stop region is formed deeper than the gate well region.

20. A semiconductor device according to any one of claims 16 to 19, further comprising: an insulating layer formed on the main surface of the SiC chip; and a source electrode selectively facing the device structure and the outer well region across the insulating layer from among the device structure, the outer well region, and the field stop region, and selectively connected to the source region and the outer well region via the insulating layer, wherein the field stop region is covered by the insulating layer and is formed in an electrically floating state.

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