Group iii nitride-based epitaxial wafer for HEMT power semiconductors and manufacturing method therefor

Abstract

Disclosed is a group III nitride-based epitaxial wafer for HEMP power semiconductors, the wafer comprising: a growth substrate; a nucleation region grown on the growth substrate; and a stress-relieving AlN region grown on the nucleation region and having Ga or In vacancies of nanoscale sizes, or microscale voids.

Description

Group III nitride epitaxial wafer for HEMT power semiconductors and method for manufacturing the same

[0001] The present invention (Disclosure) relates to a group III nitride epitaxy wafer for HEMT power semiconductors and a method for manufacturing the same, and more particularly, to a group III nitride epitaxy wafer for HEMT power semiconductors and a method for manufacturing the same, which can suppress vertical leakage current in a GaN HEMT power semiconductor device and significantly improve breakdown voltage by introducing an AlN region having a low dislocation density, which is a stress relief and crystal defect.

[0002] In the modern electronics industry, interest in the efficiency of power control systems is growing due to increasingly intense competition for energy efficiency, the development of new and renewable energy, and the expansion of related infrastructure industries.

[0003] Additionally, power systems that consider the efficiency and stability of electric vehicles and related charging infrastructure, as well as power networks such as smart grids, are attracting attention.

[0004] In line with these changing aspects of the modern electronics industry, interest in power semiconductors of various structures, especially power semiconductors using HEMTs (high electron mobility transistors) that can be used for high power and high frequency signal processing, is increasing.

[0005] Figure 1 is a drawing showing a conventional group III nitride epitaxy wafer for general HEMT power semiconductors.

[0006] Referring to FIG. 1, a conventional group III nitride epitaxy wafer for HEMT power semiconductors is composed of a growth substrate (1100), a nucleation region (1200), a stress relieving region (1300), a buffer region (1400), a channel region (1500), and a barrier region (1600) according to the growth sequence.

[0007] The growth substrate (1100) is generally a Si or SiC substrate, and an electrically high resistance material is used.

[0008] The nucleation region (1200) suppresses the melt back etching phenomenon that adversely affects the growth substrate surface due to the Si-Ga process reaction, and at the same time provides a basis for forming a high-quality buffer region (1400), channel region (1500), and barrier region (1600).

[0009] In HEMT power semiconductors having horizontal current paths and used under high voltage / high current conditions, a high-performance electrical insulating layer can be implemented by employing aluminum nitride (AlN), which has a wide energy bandgap compared to gallium nitride (GaN), as a nucleation region (1200).

[0010] The stress control region (1300) is formed to compensate for the thermal-mechanical stress generated by the formation of the buffer region (1400) and channel region (1500) formed on the upper side thereof and to reduce the density of dislocations, which are crystal defects that adversely affect quality.

[0011] In group III nitride epitaxy wafers, the buffer region (1400) and the channel region (1500) typically employ a GaN thick film and thin film structure, respectively, and at this time, the stress control region (1300) employs Al(1-x)Ga(x)N(0 <x<1) 박막층을 사용함으로써, 상술한 열적-기계적 스트레스에 의해 발생하는 에피웨이퍼의 휨 또는 크랙 발생을 억제할 수 있다.

[0012] The buffer region (1400) has the function of forming an electrically high resistance layer to reduce vertical leakage current, and uses carbon (C), iron (Fe), nickel (Ni), cobalt (Co), and rare-earth metals as dopants.

[0013] As described above, a high-density electron carrier of 2DEG (2-dimensional electron gas) is formed near the interface with the barrier region (1600) formed on the upper side of the channel region (1500).

[0014] The barrier region (1600) forms a heterojunction with the lower GaN channel region. However, conventional group III nitride epitaxial wafers for HEMT power semiconductors have several structural problems due to the stress control region (1300) and the buffer region (1400).

[0015] When forming a buffer region (1400), if high resistance characteristics are implemented by using carbon or iron as a dopant, the crystal quality of the channel region grown thereon deteriorates.

[0016] To solve this problem, there is a difficulty in finding the optimal growth conditions for the buffer region using carbon and iron as dopants.

[0017] The buffer region (1400) must have a minimum thickness to prevent lattice mismatch in the stress control region (1300) from spreading to the channel region (1500), and therefore, the thickness cannot be excessively reduced.

[0018] As a result, the thickness of the stress control region (1300) must also be grown to a considerable thickness suitable for the thicknesses of the buffer region (1400) and the channel region (1500).

[0019] In this case, the stress control region (1300) has a high density of lattice mismatch, so a fatal vertical leakage path may be formed.

[0020] In addition, according to the conventional group III nitride epitaxy wafer structure for HEMT power semiconductors, there is a disadvantage in that it is technically difficult to grow a thick film AlN with excellent film quality on the lower side of the channel region (1500).

[0021] As a nucleation region (1200), a thin film AlN material with excellent film quality is generally used. AlN material has a wide energy band gap and thus can perform an ideal electrical insulator function, but it is not easy to form a thick film exceeding a certain thickness.

[0022] On the other hand, the stress control region (1300) and buffer region (1400) formed on the nucleation region (1200) can be grown to a thick thickness, but have various and numerous crystal defects.

[0023] Basically, power semiconductors must have high breakdown voltage.

[0024] To increase the breakdown voltage, it is necessary to form a thick film as an electrical insulator.

[0025] In summary, in the group III nitride epitaxy wafer structure for conventional HEMT power semiconductors, AlN material, which can be used as an ideal electrical insulating film, is used as a thin film generation region, but thick film growth is difficult, the buffer region (1400) and stress control region (1300), where thick film growth is easy, have poor film quality, and in order to obtain high resistance, the film quality of the channel region (1500) deteriorates, which is a problem.

[0026] Therefore, there is a need to develop a new thin film or thick film structure with high resistance properties that can electrically seal the channel region and relieve stress by the Si or SiC substrate by replacing the buffer region and stress control region.

[0027] The present invention (Disclosure) aims to provide a group III nitride epitaxy wafer for HEMT power semiconductors and a method for manufacturing the same, which can improve the crystal quality of an epitaxy layer and prevent cracks.

[0028] A group III nitride epitaxial wafer for a HEMT power semiconductor according to any one of several aspects describing the present invention comprises: a growth substrate; a nucleation region grown on the growth substrate; and a stress-relieving AlN region grown on the nucleation region and having a nanoscale size of gallium vacancy, indium vacancy, or microscale hollow space.

[0029] The above stress-relieving AlN region may have a structure in which the density of the nanoscale Ga vacancy, In vacancy, or microscale hollow space decreases along the growth direction.

[0030] The above stress-relief AlN region is Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1) 성장 후, 성장온도 이상 고온 및 수소(H2)를 포함하는 환원 분위기에서 열처리(annealing) 과정이 수행되어 형성될 수 있다.

[0031] The above stress-relief AlN region is, the Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1)의 성장 및 상기 열처리(annealing) 과정이 반복적으로 수행되어 형성되는 것일 수 있다.

[0032] The nanoscale Ga vacancy, In vacancy or microscale void in the stress-relieving AlN region is formed by the grown Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1)에 포함된 Ga 또는 In 성분이 상기 열처리에 의해 분해 증발(decomposition & sublimation)되어 형성될 수 있다.

[0033] The above stress-relieving AlN region may be provided with gallium (Ga) or indium (In) remaining randomly in space.

[0034] It may include an active region grown in the above stress-relieving AlN region.

[0035] The above active region may include a channel region (GaN) in which 2DEG (2-dimensional electron gas) is formed, and a barrier region (AlGaN, AlScN, AlInN) grown in the channel region.

[0036] It may have a buffer region interposed between the above stress-relieving AlN region and the above active region, and composed of gallium nitride (GaN) doped with carbon (C), iron (Fe), nickel (Ni), cobalt (Co), and rare-earth elements.

[0037] The above active region is interposed between the channel region and the barrier region and may have an AlN thin film grown to a thickness of less than 5 nm.

[0038] A method for manufacturing a group III nitride epitaxy wafer for HEMT power semiconductors according to any one of several aspects describing the present invention comprises the steps of: growing a nucleation region on the growth substrate; and forming Al(1-y)Ga(y)N(0) in the nucleation region. <y<1) 또는 Al(1-z)In(z)N(0<z<1)을 설정된 성장온도에서 성장시키고, 상기 성장온도 이상의 고온 및 수소(H2)를 포함하는 환원 분위기에서 열처리(annealing) 과정을 진행하여, 나노스케일(nanoscale)의 크기를 갖는 Ga 공공(gallium vacancy), In 공공(indium vacancy) 또는 마이크로스케일의 중공(microscale)을 가지는 스트레스 완화 AlN 영역을 성장하는 단계;를 포함한다.

[0039] The step of growing the above stress-relieving AlN region can be performed repeatedly several times.

[0040] According to the present invention, the crystal quality of the active layer region of a HEMT power semiconductor can be improved by the newly introduced AlN region for stress control.

[0041] Therefore, the breakdown voltage of HEMT power semiconductors can be significantly improved.

[0042] Additionally, the AlN region for stress control has high resistance that can suppress vertical leakage current. Therefore, the conventional buffer region can be reduced or eliminated.

[0043] Additionally, the AlN region for stress control enables high-quality thick film growth while effectively alleviating stress caused by lattice mismatch.

[0044] Figure 1 is a drawing showing a group III nitride epitaxy wafer for a conventional HEMT power semiconductor.

[0045] FIG. 2 is a drawing showing one embodiment of a group III nitride epitaxy wafer for HEMT power semiconductors according to the present invention.

[0046] Figures 3 to 6 are drawings showing a manufacturing process of a group III nitride epitaxy wafer for the HEMT power semiconductor of Figure 2.

[0047] FIG. 7 is a drawing showing another embodiment of a group III nitride epitaxy wafer for HEMT power semiconductors according to the present invention.

[0048] FIG. 8 is a drawing showing another embodiment of a group III nitride epitaxy wafer for HEMT power semiconductors according to the present invention.

[0049] Hereinafter, an embodiment of a group III nitride epitaxy wafer for a HEMT power semiconductor according to the present invention and a manufacturing method thereof will be described in detail with reference to the drawings.

[0050] The terms used below have been selected for convenience of explanation, and therefore, in understanding the intrinsic technical idea of ​​the present invention, they should be appropriately interpreted in a meaning that is consistent with the technical idea of ​​the present invention, without being limited to their dictionary meanings.

[0051] FIG. 2 is a drawing showing one embodiment of a group III nitride epitaxy wafer for HEMT power semiconductors according to the present invention, and FIGS. 3 to 6 are drawings showing a manufacturing process of the group III nitride epitaxy wafer for HEMT power semiconductors of FIG. 2.

[0052] Referring to FIGS. 2 to 6, a group III nitride epitaxy wafer for a HEMT power semiconductor according to the present embodiment includes a growth substrate (100), a nucleation region (200) grown on the growth substrate (100), and a stress-relieving AlN region (700) grown on the nucleation region and having nanoscale Ga vacancies, In vacancies, or microscale voids.

[0053] The growth substrate (100) has electrical characteristics of high resistance and low electrical conductivity, and is preferably made of silicon (Si) and silicon carbide (SiC).

[0054] The nucleation region (200) promotes the formation of a high-quality active region, which will be described later. In the group III nitride-based epitaxy wafer for HEMT power semiconductors according to the present embodiment, the active region, particularly the active region, is made of a nitride-based material, so the nucleation region (200) is formed using aluminum nitride (AlN) as a material.

[0055] The stress-relieving AlN region (700) provides the effect of improving the characteristics of the device by alleviating the tensile stress applied to the active region due to the difference in lattice constant and coefficient of thermal expansion between silicon (Si) or silicon carbide (SiC), which is the material of the growth substrate (100), and GaN or AlGaN, which is the material constituting the active region.

[0056] The growth substrate (100) is several hundred micrometers (㎛) thick, while the active region is only several hundred nanometers (㎚) thick. When the active region is formed on the upper side of the growth substrate, it is unavoidable that a very large tensile stress is applied to the relatively thin active region due to the difference in lattice constant and thermal expansion coefficient between the two regions.

[0057] These issues can degrade the properties of the active region, leading to device characteristics issues and the formation of microcracks that cannot be detected. Furthermore, they can cause serious process issues, such as wafer-level breakage during the manufacturing process.

[0058] The stress-relieving AlN region (700) employed in the group III nitride epitaxy wafer for HEMT power semiconductors according to the present embodiment forms an AlN material having a lattice constant smaller than that of the GaN material and a thermal expansion coefficient larger than that of the GaN material on the upper side adjacent to the growth substrate (100), thereby compensating for and blocking in advance the tensile stress caused by the difference in lattice constant and thermal expansion coefficient with respect to the Si or SiC growth substrate.

[0059] Accordingly, since the active region formed on the upper side of the stress-relieving AlN region (700) is subjected to a greatly relaxed tensile stress due to the growth substrate, problems such as breakage and micro-cracks during the above-described process, as well as problems of deterioration of device characteristics, can be greatly improved.

[0060] In this embodiment, the stress-relieving AlN region (700) is 'Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1)'(710)을 설정된 성장온도(Tg)에서 성장 후, 상기 성장온도 이상의 고온 및 수소(H2)를 포함하는 환원 분위기에서 열처리(annealing) 과정이 수행되어 형성된다. 여기서, y 및 z는 0.05≤y 또는 z≤0.3인 것이 후술하는 스트레스 완화 AlN 영역(700)의 기능을 구현하는 데 바람직하다.

[0061] Accordingly, the stress-relieving AlN region (700) includes nanoscale gallium vacancy, indium vacancy, or microscale void.

[0062] Nanoscale gallium vacancy, indium vacancy or microscale void is formed during heat treatment process as 'Al(1-y)Ga(y)N (0 <y<1) 또는 Al(1-z)In(z)N (0<z<1)'(710)에 포함된 Ga 또는 In이 분해 증발(decomposition & sublimation)됨으로써 형성될 수 있다.

[0063] In addition, when growing the stress-relieving AlN region (700), the Ga or In component is 'Al(1-y)Ga(y)N (0 <y<1) 또는 Al(1-z)In(z)N (0<z<1)'(710) 성장시에 표면활성제(surfactant) 역할하여 Al Adatom(adsorbed atom) 이동(migration)을 촉진하여 종국엔 고품질의 후막 AlN 성장을 가능케 한다.

[0064] Above all, the upper interface of the stress-relieving AlN region (700) is formed of a high-quality AlN material having a low density of dislocations, which are crystal defects, and uniform Al surface polarity.

[0065] As a result, the stress-relieving AlN region (700) has electrically high insulating properties, and thereby, the stress-relieving AlN region (700) can replace part or all of the conventionally essentially composed carbon (C), iron (Fe), nickel (Ni), cobalt (Co), and rare-earth element doped GaN buffer region (400).

[0066] Meanwhile, the stress-relieving AlN region (700) according to the present embodiment is characterized by having a structure in which the density of nanoscale Ga vacancies, In vacancies, or microscale voids decreases along the growth direction.

[0067] Nanoscale Ga vacancies and In vacancies formed in the stress-relieving AlN region (700) are empty spaces remaining after Ga or In included in the AlN region (700) is decomposed and evaporated (decomposed and sublimated) during the heat treatment process, and microscale voids may be various types of empty spaces formed during the rearrangement process of Al and N molecules after Ga or In Adatom (adsorbed atom) material is discharged.

[0068] Unlike microscale voids, Ga vacancies and In vacancies have nanoscale sizes, and can be confirmed using crystallinity analysis and defect observation methods using various X-ray measurements including XRD (X-Ray diffractometer).

[0069] In the stress-relieving AlN region (700), not all of the Ga or In contained in the AlN material layer containing Ga or In may be discharged during the heat treatment process after forming the AlN layer containing Ga or In, and accordingly, gallium (Ga) or indium (In) may remain without forming a vacancy after the heat treatment described below.

[0070] The remaining Ga and In are randomly distributed spatially in the stress-relieving AlN region (700).

[0071] In other words, the AlGaN or AlInN molecules containing the remaining Ga and In may not have a uniform single crystal structure along the growth plane, but may have a single crystal, polycrystalline, or amorphous structure that is spaced apart from each other.

[0072] FIG. 7 is a drawing showing another embodiment of a group III nitride epitaxy wafer for HEMT power semiconductors according to the present invention.

[0073] Referring to FIG. 7, in the group III nitride epitaxial wafer for HEMT power semiconductor according to the present embodiment, the stress-relieving AlN region (700) is 'Al(1-y)Ga(y)N (0 <y<1) 또는 Al(1-z)In(z)N (0<z<1)'(710)의 성장 및 상술한 열처리 과정을 반복적으로 수회 수행하여, 스트레스 완화 AlN 영역(700)이 다수개 적층된 구조로 형성할 수 있다.

[0074] In this case, nanoscale Ga vacancies, In vacancies, or microscale voids formed in the stress-relieving AlN region (700) bend the direction of threading dislocations (TDs) growing from the bottom to the top, or cause multiple crystal defects to merge with each other, ultimately reducing the TD density in the upward direction.

[0075] As a result, in the channel region (500) and barrier region (600) that form the active region that is continuously grown in the subsequent process, the tensile stress can be alleviated, and along with this, the effect of significantly improving the device characteristics can be expected.

[0076] FIG. 8 is a drawing showing another embodiment of a group III nitride epitaxy wafer for HEMT power semiconductors according to the present invention.

[0077] Referring to FIG. 8, a group III nitride epitaxy wafer for a HEMT power semiconductor according to the present embodiment includes an active region (500, 600) grown in a stress-relieving AlN region (700).

[0078] The active region is composed of a channel region (GaN, 500) in which 2DEG (2-dimensional electron gas, 501) is formed and a barrier region (Al(1-y)Ga(y)N, 600) grown on the upper side of the channel region.

[0079] The group III nitride epitaxy wafer for HEMT power semiconductors according to the present embodiment means that an active region (500, 600) is grown in a stress-relieving AlN region (700) without a buffer region (400), which is a highly resistive layer doped with carbon (C), iron (Fe), nickel (Ni), cobalt (Co), and rare-earth elements.

[0080] This means that the high resistance-high insulation characteristics of the buffer region (400) can be sufficiently achieved with only the stress-relieving AlN region (700) having a wide energy band gap compared to the active region (500, 600).

[0081] According to this, instead of the buffer region (400) that is bound to have defects due to doping of carbon (C), iron (Fe), nickel (Ni), cobalt (Co) and rare-earth elements for implementing high resistance characteristics, the channel region (GaN, 500) is grown on a stress-relieving AlN region (700) with excellent film quality, thereby significantly improving the film quality of the channel region (500).

[0082] Meanwhile, in the group III nitride epitaxy wafer for HEMT power semiconductor according to the present embodiment, the active region (500, 600) is interposed between the channel region (500) and the barrier region (600) where the 2DEG is formed, and may additionally include an AlN thin film having a thickness of less than 5 nm.

[0083] Next, a method for manufacturing a group III nitride epitaxy wafer for a HEMT power semiconductor according to the present invention is described.

[0084] The manufacturing method according to the present embodiment comprises the steps of preparing a growth substrate (100), growing a nucleation region (200) on the growth substrate (100), and forming Al(1-y)Ga(y)N (0) on the nucleation region (200). <y<1) 또는 Al(1-z)In(z)N (0<z<1)을 설정된 성장온도에서 성장하고, 상기 성장온도 이상의 고온 및 수소를 포함하는 환원 분위기에서 열처리(annealing)하여, 나노스케일(nanoscale)의 Ga 공공(gallium vacancy), In 공공(indium vacancy) 또는 마이크로스케일의 중공(microscale void)을 가지는 스트레스 완화 AlN 영역(700)을 성장하는 단계를 포함한다.

[0085] In the present embodiment, the step of growing a stress-relieving AlN region (700) may be repeated several times, thereby further including a step of stacking a plurality of stress-relieving AlN regions (700).

[0086] In the present embodiment, the stress-relieving AlN region (700) through heat treatment has a structure in which the density of nanoscale Ga vacancies, In vacancies, or microscale voids decreases in the growth direction.

[0087] Table 1 shows the process conditions for each region according to the manufacturing method of a group III nitride epitaxy wafer for HEMT power semiconductor according to the present invention.

[0088] Nucleation region, stress relief AlN region, buffer region, channel region, barrier region, AlNAl 1-z Ga z NAl 1-z In z N heat treatment high resistance GaNGaNAl 1-y Ga z N Thickness 20 nm or less 50 nm or less 50 nm or less Adjust or delete according to design 100~300 nm 5~30 nm Composition (y,z) 5~30% 5~30% 60~95% Growth temperature 900~1200℃ 900~1200℃ 700~1200℃ 1000~1200℃ 950~1100℃ 950~1100℃ 950~1100℃ Growth pressure 30~150 torr 30~150 torr 30~150 torr 30~150 torr 50~100 torr 150~250 torr 50~150 torr Ⅴ / Ⅲ raito100~300100~300100~300500~1100500~10002000~3000Growth atmosphereH2 / N2100% or moreH2rich100% or moreH2richN2 Only100% or moreH2rich100% or moreH2rich100% or moreH2rich20% or moreH2rich

[0089] In Table 1, V / Ⅲ raito is the mole ratio of N / (Al, Ga, In). Growth atmosphere (H2 / N2) means the ratio of H2 flow rate to N2 flow rate.

[0090] In Table 1, the growth pressure and V / Ⅲ raito of the stress-relief AlN region are the optimal conditions for suppressing parasitic reactions.

[0091] Typically, epitaxy wafers form normal molecular structures such as AlN, AlGaN, AlGaInN, and GaN by reacting gaseous elements on the surface of the wafer placed on a carrier to form molecular bonds inside the epitaxy device where the epitaxy growth process is performed.

[0092] However, gaseous elements can interact with each other in the air after passing through the showerhead. If this occurs, unwanted molecules can form in the air and settle on the wafer surface.

[0093] This phenomenon may vary depending on the ratio between elements (Ⅴ / Ⅲ raito) and the growth pressure (i.e., vacuum).

[0094] The growth pressure and V / Ⅲ raito shown in Table 1 can suppress the parasitic reaction described above to the maximum extent and increase the quality of the film being grown.

Claims

1. Growth plate; A nucleation region growing on a growth substrate; and A group III nitride epitaxy wafer for HEMT power semiconductors, comprising a stress-relieving AlN region having a nanoscale-sized Ga vacancy, an In vacancy, or a microscale hollow, grown in the above nucleation region.

2. In claim 1, The above stress-relieving AlN region is, A group III nitride epitaxial wafer for HEMT power semiconductors, wherein the density of the nanoscale Ga vacancy, the nanoscale In vacancy, or the microscale hollow space decreases along the growth direction.

3. In claim 1, The above stress-relieving AlN region is, Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1) 성장 후, 성장온도 이상 고온 및 수소(H2)를 포함하는 환원 분위기에서 열처리(annealing) 과정이 수행되어 형성되는, HEMT 전력반도체용 그룹3족 질화물계 에피택시 웨이퍼.

4. In claim 3, The above stress-relieving AlN region is, The above Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1)의 성장 및 상기 열처리(annealing) 과정이 반복적으로 수행되어 형성되는, HEMT 전력반도체용 그룹3족 질화물계 에피택시 웨이퍼.

5. In claim 3, The nanoscale Ga vacancy, the nanoscale In vacancy or the microscale hollow in the above stress-relieving AlN region is formed by growing the Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1)에 포함된 Ga 또는 In 성분이 상기 열처리에 의해 분해 증발(decomposition & sublimation)되어 형성되는, HEMT 전력반도체용 그룹3족 질화물계 에피택시 웨이퍼.

6. In claim 1, The above stress-relieving AlN region is a group III nitride epitaxial wafer for HEMT power semiconductors, in which gallium (Ga) or indium (In) remains randomly in space.

7. In claim 1, A group III nitride epitaxial wafer for HEMT power semiconductors, comprising an active region grown in the above stress-relieving AlN region.

8. In claim 7, A group III nitride epitaxy wafer for HEMT power semiconductors, wherein the active region includes a channel region (GaN) in which 2DEG (2-dimensional electron gas) is formed, and a barrier region grown in the channel region.

9. In claim 7, A group III nitride epitaxial wafer for HEMT power semiconductors, having a buffer region interposed between the stress-relieving AlN region and the active region and composed of GaN doped with carbon (C), iron (Fe), nickel (Ni), cobalt (Co), and rare-earth elements.

10. In claim 7 A group III nitride epitaxial wafer for HEMT power semiconductors, wherein the active region is interposed between the channel region and the barrier region and has an AlN thin film grown to a thickness of less than 5 nm.

11. Steps to prepare the growth plate; A step of growing a nucleation region on the above growth substrate; In the above nucleation region, Al(1-y)Ga(y)N(0 <y<1) 또는 Al(1-z)In(z)N(0<z<1)을 설정된 성장온도에서 성장시키고, 상기 성장온도 이상의 고온 및 수소(H2)를 포함하는 환원 분위기에서 열처리(annealing) 과정을 진행하여, 나노스케일의 크기를 갖는 Ga 공공, 나노스케일의 크기를 갖는 In 공공 또는 마이크로스케일의 중공을 가지는 스트레스 완화 AlN 영역을 성장하는 단계;를 포함하는, HEMT 전력반도체용 그룹3족 질화물계 에피택시 웨이퍼 제조 방법.

12. In claim 11, A method for manufacturing a group III nitride epitaxial wafer for HEMT power semiconductors, wherein the step of growing the above-mentioned stress-relieving AlN region is repeated several times.

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