Circuit board and semiconductor package

Abstract

This circuit board comprises: a build-up layer including a plurality of insulating layers and wiring layers; and a first protective layer disposed on the build-up layer, wherein the wiring layers include a first circuit layer disposed on the upper surface of the build-up layer, the first circuit layer includes a pad portion and a metal layer, which has a smaller thickness than the pad portion, and the metal layer is disposed along the border of the upper surface of the build-up layer.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, electronic product technology has been moving toward multifunctionality and high-speed operation, and to respond to this trend, semiconductor chip manufacturing technology is also developing at a rapid pace.

[0004] In particular, the thickness of circuit boards applied for miniaturization of finished electronic products is also decreasing, and technologies related to multilayer circuit boards that configure more circuit layers within a circuit board of the same thickness are being actively researched.

[0005] A circuit board is a substrate made by printing a circuit line pattern with a conductive material, such as copper, onto an electrically insulating substrate. It is a general term for a board immediately before electronic components are mounted. To densely mount numerous electronic components on a flat surface, the mounting locations of each component are determined, and the circuit patterns connecting the components are printed and secured onto the flat surface.

[0006] Specifically, electronic components, such as semiconductor chips, can be mounted on a circuit board. The circuit board and the electronic components can be electrically connected by pads. The pads are arranged in multiple locations on the surface, creating a structure where the pitch between adjacent pads is defined.

[0007] Circuit boards according to conventional technology have problems such as poor contact (open) between some pads and electronic components due to warpage of the insulating substrate constituting the circuit board, or short circuits between adjacent pads due to fine pitch implementation.

[0008]

[0009] The present embodiment provides a circuit board and a semiconductor package that can prevent warpage of an insulating substrate and improve bonding to an electronic device through a conductive bonding member on a pad portion.

[0010]

[0011] A circuit board according to an embodiment comprises: a build-up layer including a plurality of insulating layers and wiring layers; and a first protective layer disposed on the build-up layer, wherein the wiring layer includes a first circuit layer disposed on an upper surface of the build-up, wherein the first circuit layer includes a pad portion and a metal layer having a thickness thinner than a thickness of the pad portion, and wherein the metal layer is disposed along a perimeter of an upper surface of the build-up layer.

[0012] The above pad portion does not overlap with the first protective layer in the vertical direction, and the metal layer may overlap with the first protective layer in the vertical direction.

[0013] The above metal layer may not be electrically connected to the above pad portion.

[0014] The size of the crystal grains of the above metal layer may be smaller than the size of the crystal grains of the above pad portion.

[0015] The size of the crystal grains of the above metal layer may be the same as the size of the crystal grains of the above pad portion.

[0016] The build-up layer includes a second insulating layer facing the first protective layer, the wiring layer includes a first via electrode penetrating the second insulating layer, and the first via electrode includes a second layer having a crystal grain size different from that of the first layer and the crystal grain size of the first layer, and the crystal grain size of the metal layer may be the same as that of the crystal grain of the first layer.

[0017] The above first layer may be placed below the above second layer.

[0018] The side surface of the above metal layer and the side surface of the first protective layer can be arranged horizontally with a step.

[0019] A first bonding member may be placed on the above pad portion.

[0020] A semiconductor package according to an embodiment comprises: a build-up layer including a plurality of insulating layers and wiring layers; a first protective layer disposed on the build-up layer; and a semiconductor element disposed on the build-up layer, wherein the wiring layer includes a first circuit layer disposed on an upper surface of the build-up; the first circuit layer includes a pad portion and a metal layer having a thickness thinner than a thickness of the pad portion; and the metal layer is disposed along a perimeter of an upper surface of the build-up layer.

[0021]

[0022] This embodiment has the advantage of minimizing warpage of the circuit board through the second and fourth sections covered by a protective layer on the surface of the build-up layer.

[0023] In addition, the electrical connection structure with the semiconductor element through the first part and the first bonding member has the advantage of preventing short circuits with adjacent terminals or poor contact due to solder flow.

[0024]

[0025] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] Figure 2 is an enlarged view of Z in Figure 1.

[0027] Figures 3 to 11 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0028] Fig. 12 is a drawing showing a modified example of a circuit board according to an embodiment of the present invention.

[0029] Fig. 13 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0030]

[0031] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0032] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0033] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0034] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0035] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0036] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0037] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0038] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0039] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view of Z in FIG. 1, and FIGS. 3 to 11 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0040] Referring to FIGS. 1 to 11, a circuit board (10) according to an embodiment of the present invention may include a build-up layer (100), a first protective layer (116), a second protective layer (118), a first bonding member (140), and a second bonding member (150).

[0041] The above circuit board (10) may include a build-up layer (100). The build-up layer (100) may include a plurality of insulating layers and wiring layers.

[0042] The above-described plurality of insulating layers may include a first insulating layer (102), a second insulating layer (112) disposed on one surface of the first insulating layer (102), and a third insulating layer (114) disposed on the other surface of the first insulating layer (102). Here, the meaning of being disposed on one surface and the other surface is not only understood as a configuration in direct contact with the one surface and the other surface, but may also be understood as another configuration between one surface of the first insulating layer (102) and the second insulating layer (112), and between the other surface of the first insulating layer (102) and the second insulating layer (114).

[0043] The above first insulating layer (102) is a member forming the basis of the circuit board (10), and may be composed of an insulating layer in which a metallic material and / or glass fiber is embedded.

[0044] When the first insulating layer (102) is composed of a metallic material, the rigidity of the circuit board (10) increases, thereby improving the bending characteristics and enhancing the heat dissipation characteristics. Therefore, the first insulating layer (102) may be called a core layer. In this case, the material of the first insulating layer (102) may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), titanium (Ti), hafnium (Hf), and zinc (Zn). The material of the first insulating layer (102) may also be composed of a metal including tungsten (W), molybdenum (Mo), and aluminum (Al), or an alloy including invar, kovar, or nickel (Ni) and iron (Fe), or any one of ceramics.

[0045] In addition, the first insulating layer (102) may be a prepreg (PPG) containing glass fibers in a resin. The resin of the first insulating layer (102) may include at least one of an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. When the resin of the first insulating layer (102) is used as an insulating layer resin, it may include a reinforcing material such as glass fibers or aramid fibers.

[0046] The second insulating layer (112) may be disposed on the upper surface of the first insulating layer (102). The second insulating layer (112) is formed of any insulator, such as a photocurable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a prepreg (PPG) including glass fibers in a resin may be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic filler may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material formed of glass fibers or aramid fibers may be included.

[0047] The third insulating layer (114) may be disposed on the lower surface of the first insulating layer (102). The third insulating layer (114) is formed of any insulator, such as a photocurable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a prepreg (PPG) including glass fibers in a resin may be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic filler may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material formed of glass fibers or aramid fibers may be included.

[0048] The above plurality of wiring layers may include a first circuit layer (122, 160), a first via electrode (124), a second circuit layer (126), a second via electrode (128), a third circuit layer (130), a third via electrode (132), and a fourth circuit layer (134, 170).

[0049] The first circuit layer (122, 160) may be disposed on the upper surface of the build-up layer (100). The first circuit layer (122, 160) may be disposed on the second insulating layer (112). The first circuit layer (122, 160) may include a first portion (122) and a metal layer (160). The materials of the first portion (122) and the metal layer (160) may each be metal. For example, the material of the first portion (122) and the material of the metal layer (160) may be copper (Cu). However, this is exemplary, and the material of the first portion (122) and the material of the metal layer (160) may be different from each other.

[0050] The first portion (122) may be disposed on the build-up layer (100). The first portion (122) may be disposed on the second insulating layer (112). The first portion (122) may be disposed so as not to overlap with the first protective layer (116) in the vertical direction. The first portion (122) may be a pad portion having a pad shape. Accordingly, the first portion (122) may be referred to as a pad portion. The first bonding member (140) may be disposed on the pad portion.

[0051] The metal layer (160) may be disposed on the build-up layer (100). The metal layer (160) may be referred to as a second portion. The metal layer (160) may be disposed on the upper surface of the second insulating layer (112). The metal layer (160) may be disposed along the upper perimeter of the build-up layer (100). The metal layer (160) may be disposed to overlap the first protective layer (116) in the vertical direction. The upper surface of the metal layer (160) may be covered by the first protective layer (116). The side surface of the metal layer (160) facing the first hole (110) of the first protective layer (116), which will be described later, may be disposed closer to the edge of the build-up layer (100) than the side surface of the first protective layer (116) facing the first hole (110). The end surface of the metal layer (160) may be exposed to the outside through the side surface of the circuit board (10), but alternatively, the end surface of the metal layer (160) may be covered by the first protective layer (116).

[0052] Meanwhile, in FIG. 1, the metal layer (160) is illustrated as being disposed only around the upper surface of the build-up layer (100) covered by the first protective layer (116), but this is not limited thereto, and the metal layer (160) may be disposed between the first portions (122), i.e., between a plurality of adjacent pads. In this case, a part of the metal layer (160) disposed between the plurality of first portions (122) may be covered by the first portions (122), and another part may be exposed upward through the first hole (110). In another embodiment, the metal layer (160) may be disposed so that the entirety of the metal layer (160) is covered by the first portions (122).

[0053] The first portion (122) and the metal layer (160) may not be electrically connected to each other. The first portion (122) and the metal layer (160) may be spaced apart from each other along the horizontal direction of the circuit board (10).

[0054] The thickness of the first portion (122) may be thicker than the thickness of the metal layer (160). Accordingly, the formation of the first bonding member (140) can be achieved more easily.

[0055] The size of the crystal grains of the material constituting the first portion (122) may be larger than the size of the crystal grains of the material constituting the metal layer (160). Alternatively, the size of the crystal grains of the material constituting the first portion (122) may be the same as the size of the crystal grains of the material constituting the metal layer (160). This will be described later.

[0056] Warpage of the circuit board (10) can be minimized through the metal layer (160).

[0057] The first circuit layer (122, 160) may include an additional circuit layer (120, see FIG. 6) that overlaps the first protective layer (116) in a vertical direction. The additional circuit layer (120) may be patterned on the upper surface of the build-up layer (100) covered by the first protective layer (116). The additional circuit layer (120) includes a plurality of circuit areas spaced apart in the horizontal direction, and as illustrated in FIG. 6, the plurality of circuit areas may be electrically connected to each other via the metal layer (160).

[0058] The first via electrode (124) may be arranged to penetrate the second insulating layer (112). The first via electrode (124) may include a via hole penetrating at least a portion of the second insulating layer (122) and a metal material arranged within the via hole. The first portion (122) and the second circuit layer (126) may be electrically connected through the first via electrode (124).

[0059] The second circuit layer (126) may be disposed on the first insulating layer (102). The second circuit layer (126) may be embedded in the lower surface of the second insulating layer (112). The second circuit layer (126) may include a pad portion. The second circuit layer (126) may be electrically connected to the first portion (122) of the first circuit layer (122, 160) through the first via electrode (124).

[0060] The second via electrode (128) may be arranged to penetrate the first insulating layer (102). The second via electrode (128) may include a via hole that penetrates at least a portion of the first insulating layer (102) and a metal material arranged in the via hole. The second circuit layer (126) and the third circuit layer (130) may be electrically connected through the second via electrode (128).

[0061] The third circuit layer (130) may be arranged on the lower surface of the first insulating layer (102). The third circuit layer (130) may be embedded in the upper surface of the third insulating layer (114). The third circuit layer (130) may include a pad portion. The third circuit layer (130) may be electrically connected to the second circuit layer (126) through the second via electrode (128).

[0062] The third via electrode (132) may be arranged to penetrate the third insulating layer (114). The third via electrode (132) may include a via hole that penetrates at least a portion of the third insulating layer (114) and a metal material arranged within the via hole. The third circuit layer (130) and the fourth circuit layer (134) may be electrically connected through the third via electrode (132).

[0063] The fourth circuit layer (134, 170) may be arranged on the lower surface of the build-up layer (100). The fourth circuit layer (134, 170) may be arranged on the lower surface of the third insulating layer (114). The fourth circuit layer (134, 170) may include a third portion (134) and a fourth portion (170). The third portion (134) and the fourth portion (170) may each be metal. For example, the material of the third portion (134) and the material of the fourth portion (170) may be copper (Cu). However, this is exemplary, and the material of the third portion (134) and the material of the fourth portion (170) may be different from each other.

[0064] The third portion (134) may be disposed on the lower surface of the build-up layer (100). The third portion (134) may be disposed on the lower surface of the third insulating layer (114). At least a portion of the third portion (134) may be wrapped by the second protective layer (118). For example, the second protective layer (118) may be disposed to wrap a portion of the side surface and the lower surface of the third portion (134). The third portion (134) may be disposed to overlap a second hole (119) of the second protective layer (118), which will be described later, in the vertical direction. The third portion (134) may include a pad portion. The second bonding member (150) may be disposed on the lower surface of the pad portion.

[0065] The fourth portion (170) may be disposed on the lower surface of the build-up layer (100). The fourth portion (170) may be disposed on the lower surface of the third insulating layer (114). The fourth portion (170) may be disposed along the lower surface perimeter of the build-up layer (100). The fourth portion (170) may be disposed to overlap the metal layer (160) in a vertical direction. The fourth portion (170) may be disposed to overlap the second protective layer (118) in a vertical direction. The lower surface of the fourth portion (170) may be covered by the second protective layer (118). The first end surface of the fourth portion (170) facing the third portion (134) may be wrapped by the second protective layer (118). The second end surface of the fourth portion (170) facing the first end surface may be exposed to the outside through the side surface of the circuit board (10), but alternatively, the second end surface of the fourth portion (170) may be covered by the second protective layer (118).

[0066] The third part (134) and the fourth part (170) may not be electrically connected to each other. The third part (134) and the fourth part (170) may be spaced apart from each other along the horizontal direction of the circuit board (10).

[0067] The thickness of the third portion (134) may be thicker than the thickness of the fourth portion (170). Accordingly, the formation of the second joining member (150) can be achieved more easily.

[0068] The above fourth part (170) can minimize warpage of the circuit board (10) together with the metal layer (160).

[0069] The circuit board (10) may include a first protective layer (116). The first protective layer (116) may be disposed on the upper surface of the build-up layer (100). The first protective layer (116) may be disposed on the upper surface of the second insulating layer (112). When a semiconductor element is disposed on the circuit board (10) using a material such as solder, the first protective layer (116) may perform a function of preventing a short circuit between solders due to low wettability with the solder. The first protective layer (116) may use a photocurable insulating material. For example, the first protective layer (116) may use a solder resist.

[0070] The first protective layer (116) may include a first hole (110). The first hole (110) may have a shape that penetrates from the upper surface to the lower surface of the first protective layer (116). The first hole (110) may be disposed on the build-up layer (100). Through the first hole (110), a portion of the upper surface of the second insulating layer (112), the first portion (122), and the first bonding member (140) may be exposed upward. Since the first protective layer (116) is not disposed in the formation area of ​​the first hole (110), it may be understood that the first portion (122) and the first bonding member (140) do not overlap the first protective layer (116) in the vertical direction.

[0071] As illustrated in FIG. 2, the side surface of the first protective layer (116) may be arranged horizontally with a step from the side surface of the metal layer (160). The side surface of the first protective layer (116) facing the first hole (110) may be arranged relatively closer to the first hole (110) than the side surface of the metal layer (160). The side surface of the metal layer (160) facing the first hole (110) may be arranged closer to the edge of the circuit board (10) than the side surface of the first protective layer (116). Here, the edge of the circuit board (10) may be in a direction facing the periphery of the upper surface of the build-up layer (100).

[0072] A concave surface (117) having a concave shape may be formed on the side of the first protective layer (116) facing the first hole (110) toward the periphery of the upper surface of the build-up layer (100). The concave surface (117) may be a curved surface. The concave surface (117) may have a shape in which the distance to the metal layer (160) becomes closer as it goes downwards of the circuit board (10).

[0073] However, this is exemplary, and the first protective layer (116) may be arranged to cover the end surface of the metal layer (160) facing the first hole (110).

[0074] The circuit board (10) may include a second protective layer (118). The second protective layer (118) may be disposed on the lower surface of the build-up layer (100). The second protective layer (118) may be disposed on the lower surface of the third insulating layer (114). When a semiconductor element is disposed on the lower surface of the circuit board (10) using a material such as solder, the second protective layer (118) may perform a function of preventing a short circuit between solders due to low wettability with the solder. The second protective layer (118) may use a photocurable insulating material. For example, the second protective layer (118) may use a solder resist.

[0075] The second protective layer (118) may include a second hole (119). The second hole (119) may have a shape that penetrates from the upper surface to the lower surface of the second protective layer (119). The second hole (119) may be arranged on the lower surface of the build-up layer (100). The second hole (119) may be arranged in an area that overlaps the third portion (134) in the vertical direction. When a plurality of third portions (134) are provided on the lower surface of the third insulating layer (114), a plurality of second holes (119) may be provided along the area where the third portion (134) is arranged. The second hole (119) may have a cross-sectional area smaller than that of the third portion (134). Accordingly, the second protective layer (118) may be arranged to surround a side surface and a portion of the lower surface of the third portion (134). The second joining member (150) can be exposed downward through the second hole (119). The cross-sectional area of ​​the second hole (119) may correspond to the cross-sectional area of ​​the second joining member (150), but is not limited thereto.

[0076] The first bonding member (140) may be disposed on the upper surface of the first portion (122). The first bonding member (140) is for electrically connecting a die, a semiconductor element, etc., and may be made of a conductive material. The die, the semiconductor element, etc. may be soldered onto the first bonding member (140). The first bonding member (140) may be disposed on a pad portion constituting the first portion (122). The material of the first bonding member (140) may be SnAg. The first bonding member (140) may be electrolytically plated onto the first portion (140).

[0077] The upper surface of the first bonding member (140) may be positioned higher than the upper surface of the first protective layer (116).

[0078] The first portion (122) and the first bonding member (140) may be implemented on the build-up layer (100) in a NSMD (Non-Solder Mask Defined) manner. When the first portions (122) and the first bonding members (140) are provided in multiple numbers and are arranged to be spaced apart from each other in the horizontal direction, the plurality of first portions (122) and the first bonding members (140) may be exposed upward through the first hole (110) of the first protective layer (116). In this case, as described above, the upper surface of the second insulating layer (112) formed between the plurality of first portions (122) and between the plurality of first bonding members (140) may also be exposed upward through the first hole (110).

[0079] The horizontal length (B) of the first portion (122) may be greater than the horizontal length (D) of the first joining member (140). The thickness of the first portion (122) may be greater than the thickness of the first joining member (140). The horizontal pitch (A) between two adjacent first portions (122) may be greater than the horizontal length (B) of the first portion (122).

[0080] The second bonding member (150) may be disposed on the lower surface of the third portion (134). The second bonding member (150) is for electrically connecting a die, a semiconductor element, etc., and may be made of a conductive material. The die, the semiconductor element, etc. may be soldered onto the second bonding member (150). The second bonding member (150) may be disposed on the lower surface of the pad portion constituting the third portion (134). The material of the second bonding member (150) may include gold (Au), palladium (Pd), nickel (Ni), etc., and the second bonding member (150) may be formed on the lower surface of the third portion (134) using ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), i.e., an electroless gold plating method.

[0081] Hereinafter, a method for manufacturing a circuit board (10) according to an embodiment of the present invention will be described.

[0082] First, as illustrated in FIG. 3, the build-up layer (100) having a plurality of insulating layers and wiring layers formed thereon can be manufactured. In this case, a first metal layer (20A) for forming the metal layer (160) among the first circuit layers (122, 160) can be formed on one side of the build-up layer (100), that is, the upper surface of the build-up layer (100), and a second metal layer (20B) for forming the fourth part (170) among the fourth circuit layers (134, 170) can be formed on the other side of the build-up layer (100), that is, the lower surface of the build-up layer (100). The first metal layer (20A) can be formed on the upper surface of the build-up layer (100) together with the first part (122) by an electrolytic plating method. The second metal layer (20B) may be formed on the upper surface of the build-up layer (100) by electroplating together with the third portion (134). In this case, the size of the crystal grains of the material constituting the first portion (122) in the circuit board (10) may be the same as the size of the crystal grains of the material constituting the metal layer (160), and the size of the crystal grains of the material constituting the third portion (134) may be the same as the size of the crystal grains of the material constituting the fourth portion (170).

[0083] However, the first metal layer (20A) and the second metal layer (20B) can be formed on the surface of the build-up layer (100) by a chemical copper plating method. Before forming the first portion (122) and the first via electrode (124) on the upper surface of the build-up layer (100), the first metal layer (20A) can be first formed by a chemical copper plating method, and then the first portion (122) and the first via electrode (124) can be formed in the hole in the second insulating layer (122) and on the surface of the second insulating layer (122) by an electrolytic copper plating method. Accordingly, as illustrated in FIG. 12, the first via electrode (124) may include a first layer (124A) and a second layer (124B) having different crystal grain sizes, and the second layer (124B) may be formed on the upper surface of the first layer (124A). In addition, the crystal grain sizes of the first layer (124A) formed by a chemical copper plating method and the metal layer (160) may be the same, and the crystal grain sizes of the second layer (124B) and the first portion (122) may be larger than the crystal grain sizes of the first layer (124A) and the metal layer (160).

[0084] Next, as illustrated in FIGS. 4 and 5, the method may include a step of attaching a mask film (30) to the lower surface of the build-up layer (100) for forming the fourth portion (170), and a step of etching the surface of the build-up layer (100) to which the mask film (30) is attached. The fourth portion (170) may be formed by a DFR (Dry Film Resist) method. Accordingly, after attaching the mask film (30) so as to cover the entire upper surface of the build-up layer (100) and the formation area of ​​the fourth portion (170) among the lower surface of the build-up layer (10), etching is performed through the opening (34) of the mask film (30) attached to the lower surface of the build-up layer (10), so that the fourth portion (170) may be formed on the lower surface of the build-up layer (100), as illustrated in FIG. 5.

[0085] Next, as illustrated in FIG. 6, a step of pretreating the surface of the build-up layer (100) may be performed. The surface pretreating of the build-up layer (10) may be performed by applying CZ ink. Accordingly, the surface roughness of the surface of the first portion (122) may be increased and the thickness thereof may be decreased together with the first metal layer (20A) formed on the upper surface of the build-up layer (10). Similarly, the surfaces of the third portion (134) and the fourth portion (170) formed on the lower surface of the build-up layer (10) may also be increased and the thickness thereof may be decreased.

[0086] Next, as illustrated in FIG. 7, the first protective layer (116) and the second protective layer (118) may be formed on the surface of the build-up layer (100). Accordingly, a portion of the first metal layer (20A) and the surface of the fourth portion (170) may be covered by the first protective layer (116) and the second protective layer (118), respectively. Meanwhile, as described above, an additional circuit layer (120) covered by the first protective layer (116) may be formed on the upper surface of the build-up layer (100), and the additional circuit layer (120) may have a structure in which it is electrically connected by the first metal layer (20A), i.e., the metal layer (160).

[0087] Next, as illustrated in FIGS. 8 and 9, the second bonding member (150) may be formed on the surface of the build-up layer (100). As illustrated in FIG. 8, after attaching a mask film (40) to the surface of the build-up layer (100) on which the first and second protective layers (116, 118) are formed, the second bonding member (150) may be formed on the lower surface of the third portion (134) through an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) method. In this case, an opening (42) for exposing the third portion (134) may be formed in the mask film (40) attached to the lower surface of the build-up layer (100).

[0088] Next, as illustrated in FIGS. 10 and 11, the first bonding member (140) may be formed on the surface of the build-up layer (100). As illustrated in FIG. 10, after attaching a mask film (50) to the surface of the build-up layer (100) on which the first and second protective layers (116, 118) are formed, the first bonding member (140) may be formed on the upper surface of the first portion (122) by an electrolytic plating method. In this case, an opening (52) that exposes a portion of the upper surface of the first portion (122) upward may be formed in the mask film (50) attached to the upper surface of the build-up layer (100). The cross-sectional area of ​​the opening (52) may be smaller than the cross-sectional area of ​​the first portion (122). Accordingly, the first bonding member (140) made of SnAg material can be formed on the first part (122).

[0089] Next, the metal layer (160) may be formed on the upper surface of the build-up layer (100). The formation of the metal layer (160) may be performed by a process of etching the surface of the build-up layer (100) after the formation of the first bonding member (140) and the removal of the mask film (50). In this case, the etching for the formation of the metal layer (160) may be performed by an organic acid etching method in which etching is performed with a relatively weak acid through pH control. Accordingly, the first metal layer (20A) for the formation of the metal layer (160) may be etched, but the surface of the first bonding member (140) may not be etched.

[0090] According to the above structure, there is an advantage in that the bending phenomenon of the circuit board can be minimized through the second and fourth sections covered by the protective layer on the surface of the build-up layer (100).

[0091] In addition, the electrical connection structure with the semiconductor element through the first part and the first bonding member has the advantage of preventing short circuits with adjacent terminals or poor contact due to solder flow.

[0092] Fig. 13 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. Referring to Fig. 13, a semiconductor package according to an embodiment of the present invention may include a first semiconductor element (200) disposed on an upper surface of a circuit board (10), and a second semiconductor element (300) disposed on a lower surface of the circuit board (10).

[0093] The first semiconductor element (200) includes a first pad (210), and the first pad (210) can be soldered to the first bonding member (140) through a solder portion (220).

[0094] The second semiconductor element (300) above also has a second pad formed on the upper surface, and can be electrically connected to the circuit board (10) by a solder ball (310) that electrically connects the second pad and the second bonding member (150).

[0095] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0096] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A build-up layer including multiple insulating layers and wiring layers; and Including a first protective layer disposed on the above build-up layer, The above wiring layer includes a first circuit layer arranged on the upper surface of the build-up, The first circuit layer includes a pad portion and a metal layer having a thickness thinner than the thickness of the pad portion, A circuit board in which the metal layer is arranged along the upper surface perimeter of the build-up layer.

2. In paragraph 1, The above pad portion does not overlap with the first protective layer in the vertical direction, A circuit board in which the metal layer overlaps the first protective layer in a vertical direction.

3. In paragraph 1, A circuit board in which the metal layer is not electrically connected to the pad portion.

4. In paragraph 1, A circuit board in which the crystal grain size of the metal layer is smaller than the crystal grain size of the pad portion.

5. In paragraph 1, A circuit board in which the crystal grain size of the metal layer is the same as the crystal grain size of the pad portion.

6. In paragraph 4, The above build-up layer includes a second insulating layer facing the first protective layer, The above wiring layer includes a first via electrode penetrating the second insulating layer, The above first via electrode includes a first layer and a second layer having a crystal grain size different from that of the first layer, A circuit board in which the crystal grain size of the above metal layer is the same as the crystal grain size of the first layer.

7. In paragraph 6, The above first layer is a circuit board placed below the above second layer.

8. In paragraph 1, A circuit board in which the side of the metal layer and the side of the first protective layer are arranged horizontally with a step.

9. In paragraph 1, A circuit board having a first bonding member arranged on the above pad portion.

10. A build-up layer including multiple insulating layers and wiring layers; A first protective layer disposed on the above build-up layer; and Including a semiconductor device arranged on the above build-up layer, The above wiring layer includes a first circuit layer arranged on the upper surface of the build-up, The first circuit layer includes a pad portion and a metal layer having a thickness thinner than the thickness of the pad portion, A semiconductor package in which the metal layer is arranged along the upper surface perimeter of the build-up layer.

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