Gate driving circuit, display substrate and display device

Abstract

Disclosed are a gate driving circuit, a display substrate and a display device. The gate driving circuit comprises a plurality of transistors arranged on a base. The plurality of transistors at least include a fourth transistor (T4) serving as a first output transistor and a fifth transistor (T5) serving as a second output transistor. A first electrode of the fourth transistor (T4) is connected to a high-potential signal line (34), a first electrode of the fifth transistor (T5) is connected to a second clock signal line (32), a second electrode of the fourth transistor (T4) and a second electrode of the fifth transistor (T5) are connected to an output signal line (35), and the output signal line (35) is configured to output a gate driving signal to a display region. The fifth transistor (T5) is arranged on the side of the fourth transistor (T4) close to the display region, and at least one transistor is arranged between the fourth transistor (T4) and the fifth transistor (T5) in a direction approaching the display region.

Description

Gate driving circuit, display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a gate driving circuit, a display substrate, and a display device. Background Art

[0002] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of micro-display that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates to manufacture OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer high resolution (PPI), but also high brightness, low power consumption, fast response time, wide color gamut, and excellent thermal stability.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a gate drive circuit, comprising a plurality of transistors arranged on a substrate, the plurality of transistors including at least a fourth transistor serving as a first output transistor and a fifth transistor serving as a second output transistor; a first electrode of the fourth transistor is connected to a high-potential signal line, a first electrode of the fifth transistor is connected to a second clock signal line, a second electrode of the fourth transistor and a second electrode of the fifth transistor are connected to an output signal line, and the output signal line is configured to output a gate drive signal to a display area; the fifth transistor is arranged on a side of the fourth transistor close to the display area, and at least one transistor is arranged between the fourth transistor and the fifth transistor along a direction close to the display area.

[0006] In an exemplary embodiment, four transistors are disposed between the fourth transistor and the fifth transistor in a direction approaching the display area.

[0007] In an exemplary embodiment, the fourth transistor has a first width-to-length ratio, the fifth transistor has a second width-to-length ratio, and a ratio of the first width-to-length ratio to the second width-to-length ratio is 0.95 to 1.05.

[0008] In an exemplary embodiment, the fourth transistor includes at least a fourth active area, the fourth active area having a first active length and a first active width, the fifth transistor includes at least a fifth active area, the fifth active area having a second active length and a second active width, a ratio of the first active length to the second active length is 0.95 to 1.05, and a ratio of the first active width to the second active width is 0.95 to 1.05, the active length is a dimension in a first direction, the active width is a dimension in a second direction, and the first direction and the second direction intersect.

[0009] In an exemplary embodiment, the fourth transistor further includes a fourth source electrode and a fourth drain electrode, the fourth source electrode being connected to the first region of the fourth active region through a fourth source via, and the fourth drain electrode being connected to the second region of the fourth active region through a fourth drain via; the fifth transistor further includes a fifth source electrode and a fifth drain electrode, the fifth source electrode being connected to the first region of the fifth active region through a fifth source via, and the fifth drain electrode being connected to the second region of the fifth active region through a fifth drain via; the fourth transistor has a first source-drain length, and the fifth transistor has a second source-drain length, a ratio of the first source-drain length to the second source-drain length being 0.95 to 1.05, the first source-drain length being the distance between the fourth source via and the fourth drain via, and the second source-drain length being the distance between the fifth source via and the fifth drain via.

[0010] In an exemplary embodiment, the plurality of transistors further include an eighth transistor, wherein the eighth transistor is disposed between the fourth transistor and the fifth transistor, a gate electrode of the eighth transistor is connected to a low-potential signal line, and a second electrode of the eighth transistor is connected to the gate electrode of the fifth transistor; the eighth transistor includes at least an eighth active area, the eighth active area has a third active width, and the third active width is 20% to 30% of the second active width.

[0011] In an exemplary embodiment, the fifth active region has an active center line, which is a straight line bisecting the fifth active region in the second direction and extending along the first direction; the eighth active region is disposed on one side of the active center line in the second direction.

[0012] In an exemplary embodiment, an orthographic projection of the eighth active region on the substrate does not overlap with an orthographic projection of the active center line on the substrate.

[0013] In an exemplary embodiment, an edge of the fourth active region on the second direction, an edge of the fifth active region on the second direction, and an edge of the eighth active region on the second direction are flush.

[0014] In an exemplary embodiment, the plurality of transistors further include a third transistor, the third transistor being arranged on a side of the fourth transistor away from the fifth transistor, the gate electrode of the third transistor being connected to the first clock signal line, the first electrode of the third transistor being connected to the low potential signal line, the second electrode of the third transistor being connected to the gate electrode of the fourth transistor, and the third transistor including at least a third active area; the gate drive circuit further includes a power supply active area, the power supply active area being connected to the low potential signal line, the power supply active area being in the shape of a straight line or a broken line extending along the first direction, and the power supply active area being arranged in the On one side of the second direction Y of the third active area, the first direction and the second direction intersect; in the first direction, the multiple transistors have a first device length, the power active area has a second device length, and the ratio of the first device length to the second device length is 0.95 to 1.05; the first device length is the distance between the edge of the third active area away from the fifth active area and the edge of the fifth active area away from the third active area, and the second device length is the distance between the edge of the power active area away from the fifth active area and the edge of the power active area away from the third active area.

[0015] In an exemplary embodiment, the low-level signal line has a third device length, a ratio of the first device length to the third device length is 0.95 to 1.05, and the third device length is a distance between an edge of the low-level signal line away from the fifth transistor and an edge of the low-level signal line away from the third transistor.

[0016] In an exemplary embodiment, the plurality of transistors further include a second transistor, which is disposed between the third transistor and the fourth transistor, wherein a first electrode of the second transistor is connected to a first clock signal line, a second electrode of the second transistor is connected to a second electrode of the third transistor, and the second transistor includes at least a second active area, wherein the second active area and the third active area are an integral structure connected to each other.

[0017] In an exemplary embodiment, the first active width is greater than an active width of any one of the second active region and the third active region, and is less than a sum of active widths of the second active region and the third active region.

[0018] In an exemplary embodiment, the plurality of transistors further include a first transistor, a sixth transistor, and a seventh transistor, wherein a first electrode of the first transistor is connected to a control signal line, a second electrode of the first transistor is connected to a first electrode of the seventh transistor T7, a first electrode of the sixth transistor is connected to a high-level signal line, and a second electrode of the sixth transistor is connected to a second electrode of the seventh transistor; the first transistor includes at least a first active area, the sixth transistor includes at least a sixth active area, and the seventh transistor includes at least a seventh active area, and the first active area, the sixth active area, and the seventh active area are an integrated structure connected to each other.

[0019] In an exemplary embodiment, the first active width is greater than the active width of any one of the first active region, the sixth active region, and the seventh active region, and is less than the sum of the active widths of the first active region, the sixth active region, and the seventh active region.

[0020] In an exemplary embodiment, the first clock signal line and the second clock signal line are shaped as straight lines or broken lines extending along the first direction, the first clock signal line has a first extension length, and the second clock signal line has a second extension length, which is greater than the first extension length.

[0021] In an exemplary embodiment, the first clock signal line and the second clock signal line are shaped as straight lines or broken lines extending along the first direction, there is a first spacing between the first clock signal line and the second clock signal line, there is a second spacing between the gate electrode of the second transistor and the gate electrode of the third transistor, and the first spacing is smaller than the second spacing.

[0022] In an exemplary embodiment, a third distance is provided between the first clock signal line and the gate electrode of the second transistor, a fourth distance is provided between the second clock signal line and the gate electrode of the third transistor, the first distance is greater than the third distance, and the first distance is greater than the fourth distance.

[0023] In an exemplary embodiment, in a direction perpendicular to the substrate, the gate drive circuit includes at least a gate conductive layer and a first conductive layer arranged on a side of the gate conductive layer away from the substrate, the gate electrode of the second transistor and the gate electrode of the third transistor are arranged in the gate conductive layer, and the first clock signal line and the second clock signal line are arranged in the first conductive layer.

[0024] In an exemplary embodiment, the gate drive circuit further includes a first capacitor and a second capacitor, wherein the first end of the first capacitor is connected to the first electrode of the fourth transistor, the second end of the first capacitor is connected to the gate electrode of the fourth transistor, the first end of the second capacitor is connected to the second electrode of the fifth transistor, and the second end of the second capacitor is connected to the gate electrode of the fifth transistor; the second capacitor is arranged on a side of the first capacitor close to the display area, the area of ​​the first capacitor's direct projection on the substrate is larger than the area of ​​the fourth transistor's direct projection on the substrate, and the area of ​​the second capacitor's direct projection on the substrate is larger than the area of ​​the fifth transistor's direct projection on the substrate.

[0025] In an exemplary embodiment, the orthographic projection of the first capacitor on the substrate includes at least two transistors projected on the substrate, and the orthographic projection of the second capacitor on the substrate includes at least two transistors projected on the substrate.

[0026] In an exemplary embodiment, the first capacitor includes a plurality of stacked plates, the second capacitor includes a plurality of stacked plates, and a distance between an edge of at least one plate of the first capacitor close to a side of the second capacitor and an edge of at least one plate of the second capacitor close to a side of the first capacitor is greater than 5.2 μm.

[0027] In an exemplary embodiment, the first capacitor includes a stacked first electrode plate, a third electrode plate, a fifth electrode plate, and a seventh electrode plate, wherein the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate, the orthographic projection of the fifth electrode plate on the substrate at least partially overlaps with the orthographic projection of the seventh electrode plate on the substrate, the fifth electrode plate is connected to the first electrode plate, and the seventh electrode plate is connected to the third electrode plate; the second capacitor includes a stacked second electrode plate, a fourth electrode plate, a sixth electrode plate, and an eighth electrode plate, wherein the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate, the orthographic projection of the sixth electrode plate on the substrate at least partially overlaps with the orthographic projection of the eighth electrode plate on the substrate; the sixth electrode plate is connected to the second electrode plate, and the eighth electrode plate is connected to the fourth electrode plate.

[0028] In an exemplary embodiment, the fifth plate is connected to the first plate through a via, the seventh plate is connected to the third plate through a first plate electrode and a third plate electrode; the sixth plate is connected to the second plate through a via, and the eighth plate is connected to the fourth plate through a second plate electrode and a fourth plate electrode.

[0029] In an exemplary embodiment, in a direction perpendicular to the substrate, the gate drive circuit includes a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer arranged in sequence along a direction away from the substrate; the first plate and the second plate are arranged in the third conductive layer, the third plate and the fourth plate are arranged in the fourth conductive layer, the fifth plate, the sixth plate, the first plate electrode, and the second plate electrode are arranged in the fifth conductive layer, the seventh plate and the eighth plate are arranged in the sixth conductive layer, and the third plate electrode and the fourth plate electrode are arranged in the seventh conductive layer; the third plate electrode is connected to the seventh plate and the first plate electrode respectively through vias, and the first plate electrode is connected to the third plate through a via; the fourth plate electrode is connected to the eighth plate and the second plate electrode respectively through vias, and the second plate electrode is connected to the fourth plate through a via.

[0030] On the other hand, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in a pixel row in the display area; at least one gate driving circuit includes the aforementioned gate driving circuit.

[0031] On the other hand, embodiments of the present disclosure provide a display device including the aforementioned display substrate.

[0032] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0034] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0035] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0036] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0037] FIG4 is an equivalent circuit diagram of a pixel driving circuit;

[0038] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0039] FIG6 is a schematic structural diagram of a gate driving device;

[0040] FIG7A is a working principle diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0041] FIG7B is a driving timing diagram of the gate driving circuit shown in FIG7A ;

[0042] FIG8 is an equivalent circuit diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0043] FIG9 is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0044] FIG10 is a schematic diagram of an embodiment of the present disclosure after forming an active area pattern;

[0045] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after a gate conductive layer pattern is formed;

[0046] 12A and 12B are schematic diagrams of an embodiment of the present disclosure after forming an N-type doping region pattern;

[0047] 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming a P-type doping region pattern;

[0048] FIG14 is a schematic diagram of an embodiment of the present disclosure after forming a second insulating layer pattern;

[0049] 15A and 15B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0050] FIG16 is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0051] 17A and 17B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0052] FIG18 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern;

[0053] 19A and 19B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0054] 20A and 20B are schematic diagrams of the embodiment of the present disclosure after forming patterns of the fifth insulating layer and the fourth conductive layer;

[0055] FIG21 is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern;

[0056] 22A and 22B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0057] 23A and 23B are schematic diagrams of the seventh insulating layer and the sixth conductive layer after patterns are formed according to an embodiment of the present disclosure;

[0058] FIG24 is a schematic diagram of an embodiment of the present disclosure after forming an eighth insulating layer pattern;

[0059] 25A and 25B are schematic diagrams of an embodiment of the present disclosure after forming a seventh conductive layer pattern;

[0060] FIG26 is a cross-sectional view taken along line AA in FIG25A;

[0061] FIG27 is a cross-sectional view taken along line BB in FIG25A .

[0062] DESCRIPTION OF NUMERALS AND SIGNS: 10—power supply active region; 11—first active region; 12—second active region; 13—third active region; 14—fourth active region; 15—fifth active region; 16—sixth active region; 17—seventh active region; 18—eighth active region; 20—N-type doped region; 21—first gate electrode; 22—second gate electrode; 23—third gate electrode; 24—fourth gate electrode; 25—fifth gate electrode; 26—sixth gate electrode; 27—seventh gate electrode; 28—eighth gate electrode; 30—P-type doped region; 31—first clock signal line; 32—second clock signal line; 33—low-level signal line; 34—high-level signal line; 35—output signal line; 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode; 44—fourth connecting electrode; 45—fifth connecting electrode; 46—sixth connecting electrode; 47—seventh connecting electrode; 48—eighth connecting electrode; 49—ninth connecting electrode; 50—tenth connecting electrode; 51—eleventh connecting electrode; 52—twelfth connecting electrode; 53—thirteenth connecting electrode; 54—fourteenth connecting electrode; 55—fifteenth connecting electrode; 56—sixteenth connecting electrode; 57—seventeenth connecting electrode; 58—eighteenth connecting electrode; 61—first connecting line; 62—second connecting line; 63—third connecting line; 64—fourth connecting line; 71—twenty-first connecting electrode; 72—twenty-second connecting electrode; 73—twenty-third connecting electrode; 74—twenty-fourth connecting electrode; 75—twenty-fifth connecting electrode; 76—twenty-sixth connecting electrode; 77—twenty-seventh connecting electrode; 81—first plate electrode; 82—second plate electrode; 83—third plate electrode; 84—fourth plate electrode; 91—first plate; 92—second plate; 93—third plate; 94—fourth plate;95 — fifth plate; 96 — sixth plate; 97 — seventh plate; 98 — eighth plate; 100 — first capacitor; 101 — substrate; 102 — driving circuit layer; 103 — light-emitting structure layer; 104 — first encapsulation layer; 105 — color filter structure layer; 106 — second encapsulation layer; 107 — cover layer; 114 — fourth insulating layer; 115 — fifth insulating layer; 116 — sixth insulating layer; 117 — seventh insulating layer; 118 — eighth insulating layer; 200 — second capacitor. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0064] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0065] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0066] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0067] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0068] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0069] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0070] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0071] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0072] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0073] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0074] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0075] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0076] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to realize the display progressive scanning function. The data driver is respectively connected to a plurality of data signal lines in the display area, and the data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to realize the switching and control of the display screen.

[0077] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0078] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel emitting red light, the second sub-pixel P2 may be a blue (B) sub-pixel emitting blue light, and the third sub-pixel P3 may be a green (G) sub-pixel emitting green light. The shape of the sub-pixels may be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in this disclosure. In other possible embodiments, the pixel unit may include four sub-pixels, which is not limited in this disclosure.

[0079] Figure 3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in Figure 3, in the direction perpendicular to the display device, the silicon-based OLED display device may include: a substrate 101, a driving circuit layer 102 arranged on the substrate 101, a light-emitting structure layer 103 arranged on the side of the driving circuit layer 102 away from the substrate 101, a first encapsulation layer 104 arranged on the side of the light-emitting structure layer 103 away from the substrate 101, a color filter structure layer 105 arranged on the side of the first encapsulation layer 104 away from the substrate 101, a second encapsulation layer 106 arranged on the side of the color filter structure layer 105 away from the substrate 101, and a cover layer 107 arranged on the side of the second encapsulation layer 106 away from the substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0080] In an exemplary embodiment, the substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, the source electrode S, and the drain electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), respectively, and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0081] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the drain electrode D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0082] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0083] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit has a 4T2C structure, which can include four transistors (an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14) and two storage capacitors (a first storage capacitor CS1 and a second storage capacitor CS2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0084] In an exemplary embodiment, the pixel driving circuit may include an eleventh node N11, a twelfth node N12, and a thirteenth node N13. The eleventh node N11 is connected to the second electrode of the eleventh transistor T11, the gate electrode of the thirteenth transistor T13, and the first end of the first storage capacitor CS1, respectively. The twelfth node N12 is connected to the second electrode of the twelfth transistor T12, the first electrode of the thirteenth transistor T13, the second end of the first storage capacitor CS1, and the first end of the second storage capacitor CS2, respectively. The thirteenth node N13 is connected to the second electrode of the thirteenth transistor T13 and the second electrode of the fourteenth transistor T14, respectively.

[0085] In an exemplary embodiment, the eleventh transistor T11 can be referred to as a write switch transistor, a gate electrode of the eleventh transistor T11 is connected to the first scan signal line S1, a first electrode of the eleventh transistor T11 is connected to the data signal line DATA, and a second electrode of the eleventh transistor T11 is connected to the eleventh node N11.

[0086] In an exemplary embodiment, the twelfth transistor T12 is called a display switch transistor, a gate electrode of the twelfth transistor T12 is connected to the second scan signal line S2, a first electrode of the twelfth transistor T12 is connected to the first power line VDD, and a second electrode of the twelfth transistor T12 is connected to the twelfth node N12.

[0087] In an exemplary embodiment, the thirteenth transistor T13 may be referred to as a driver transistor, a gate electrode of the thirteenth transistor T13 is connected to the eleventh node N11, a first electrode of the thirteenth transistor T13 is connected to the twelfth node N12, and a second electrode of the thirteenth transistor T13 is connected to the thirteenth node N13.

[0088] In an exemplary embodiment, the fourteenth transistor T14 can be referred to as a reset (Auto Zero) transistor, a gate electrode of the fourteenth transistor T14 is connected to the third scan signal line S3, a first electrode of the fourteenth transistor T14 is connected to the second power line VSS, and a second electrode of the fourteenth transistor T14 is connected to the thirteenth node N13.

[0089] In an exemplary embodiment, a first end of the first storage capacitor CS1 is connected to the eleventh node N11, and a second end of the first storage capacitor CS1 is connected to the twelfth node N12. A first end of the second storage capacitor CS2 is connected to the twelfth node N12, and a second end of the second storage capacitor CS2 is connected to the first power line VDD.

[0090] In an exemplary embodiment, the light emitting device XL may be an organic light emitting diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the thirteenth node N13, and the second electrode of the light emitting device XL is connected to the common voltage line VCOM.

[0091] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0092] In an exemplary embodiment, the eleventh to fourteenth transistors T11 to T14 may be PMOS transistors or NMOS transistors. For example, the eleventh to fourteenth transistors T11 to T14 are all transistors. Using the same type of transistors in the pixel driving circuit can simplify the process, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0093] In an exemplary embodiment, the eleventh to fourteenth transistors T11 to T14 may include transistors and N-type transistors. For example, the eleventh to thirteenth transistors T11 to T13 may be transistors, and the fourteenth transistor T14 may be an N-type transistor, as shown in FIG4 .

[0094] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0095] The first phase A1 can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is high-level signal, so that the eleventh transistor T11, the twelfth transistor T12 and the fourteenth transistor T14 are turned on. The eleventh transistor T11 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first storage capacitor CS1, and the potential Vs of the eleventh node N11 (i.e., the gate electrode of the thirteenth transistor T13) is equal to Vofs. The twelfth transistor T12 is turned on so that the first power supply voltage ELVDD output by the first power supply line VDD is written into the twelfth node N12, and the potential Vg of the twelfth node N12 (i.e., the first electrode of the thirteenth transistor T13) is equal to ELVDD. At this time, the gate-source voltage Vgs of the thirteenth transistor T13 is equal to ELVDD-Vofs, and the storage voltage V ini =ELVDD-Vofs, the potential Vd of the thirteenth node N13 (ie, the second electrode of the thirteenth transistor T13) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the thirteenth transistor T13.

[0096] The second stage A2 can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourteenth transistor T14 is continuously turned on. The signal of the first scanning signal line S13 changes from a low-level signal to a high-level signal, causing the eleventh transistor T11 to be disconnected first, and the eleventh node N11 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the twelfth transistor T12 to be disconnected, and the twelfth node N12 forms a loop through the turned-on thirteenth transistor T13, the thirteenth node N13 and the turned-on fourteenth transistor T14, and begins to discharge, and the potential of the twelfth node N12 drops. Because the eleventh node N11 floats, the voltage difference across the first storage capacitor CS1 remains unchanged, and thus the potential of the eleventh node N11 drops as the potential of the twelfth node N12 drops. Due to the back-gate effect of the thirteenth transistor T13, the gate-source voltage Vgs of the thirteenth transistor T13 remains unchanged, so the equivalent threshold voltage |V th_EF As the potential of the twelfth node N12 decreases, the equivalent threshold voltage of the thirteenth transistor T13 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the thirteenth transistor T13 |V th_EF When the voltage Vgs increases to the gate-source voltage Vgs of the thirteenth transistor T13, the thirteenth transistor T13 is turned off and the twelfth node N12 stops discharging.

[0097] The third stage A3 can be called the data writing stage and the threshold compensation stage. The signal on the second scan signal line S2 is a high-level signal, and the twelfth transistor T12 is continuously off. The signal on the third scan signal line S3 is a high-level signal, and the fourteenth transistor T14 is continuously on. The signal on the first scan signal line S13 changes from a high-level signal to a low-level signal, turning on the eleventh transistor T11. The turning on of the eleventh transistor T11 causes the data voltage Vdata output by the data signal line DATA to be written to the eleventh node N11, and the potential of the eleventh node N11 changes from Vofs to Vdata. Since the twelfth node N12 is floating, threshold compensation can be achieved in this stage.

[0098] The fourth phase A4 can be referred to as the light-emitting phase. The signals on the second scan signal line S2 and the third scan signal line S3 are low-level signals, while the signal on the first scan signal line S1 is high-level. This turns on the twelfth transistor T12, while the eleventh transistor T11 and the fourteenth transistor T14 are off. The twelfth transistor T12 turns on, causing the power supply voltage output from the first power supply line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on twelfth transistor T12 and the thirteenth transistor T13, thereby driving the light-emitting device EL to emit light.

[0099] In the light-emitting stage, the driving current of the thirteenth transistor T13 is not affected by the threshold voltage of the thirteenth transistor T13, thereby eliminating the influence of the threshold voltage of the thirteenth transistor T13 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0100] An exemplary embodiment of the present disclosure provides a display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit and at least one scan signal line, the scan signal line configured to provide a scan signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit being connected to the scan signal line in a pixel row in the display area. At least one gate driving circuit comprises a plurality of transistors disposed on a substrate, the plurality of transistors including at least a fourth transistor serving as a first output transistor and a fifth transistor serving as a second output transistor; a first electrode of the fourth transistor being connected to a high-potential signal line, a first electrode of the fifth transistor being connected to a second clock signal line, and a second electrode of the fourth transistor and a second electrode of the fifth transistor being connected to an output signal line, the output signal line being configured to output a gate driving signal to the display area; the fifth transistor being disposed on a side of the fourth transistor closer to the display area, with at least one transistor disposed between the fourth transistor and the fifth transistor along a direction closer to the display area.

[0101] In an exemplary embodiment, four transistors are disposed between the fourth transistor and the fifth transistor in a direction approaching the display area.

[0102] In an exemplary embodiment, both transistors disposed between the fourth transistor and the fifth transistor are non-output transistors.

[0103] In an exemplary embodiment, the fourth transistor has a first width-to-length ratio, the fifth transistor has a second width-to-length ratio, and a ratio of the first width-to-length ratio to the second width-to-length ratio is 0.95 to 1.05.

[0104] In an exemplary embodiment, the fourth transistor includes at least a fourth active area, the fourth active area having a first active length and a first active width, the fifth transistor includes at least a fifth active area, the fifth active area having a second active length and a second active width, a ratio of the first active length to the second active length is 0.95 to 1.05, and a ratio of the first active width to the second active width is 0.95 to 1.05, the active length is a dimension in a first direction, the active width is a dimension in a second direction, and the first direction and the second direction intersect.

[0105] In an exemplary embodiment, the plurality of transistors further include a third transistor, the third transistor being arranged on a side of the fourth transistor away from the fifth transistor, the gate electrode of the third transistor being connected to the first clock signal line, the first electrode of the third transistor being connected to the low potential signal line, the second electrode of the third transistor being connected to the gate electrode of the fourth transistor, and the third transistor including at least a third active area; the gate drive circuit further includes a power supply active area, the power supply active area being connected to the low potential signal line, the power supply active area being in the shape of a straight line or a broken line extending along the first direction, and the power supply active area being arranged in the On one side of the second direction Y of the third active area, the first direction and the second direction intersect; in the first direction, the multiple transistors have a first device length, the power active area has a second device length, and the ratio of the first device length to the second device length is 0.95 to 1.05; the first device length is the distance between the edge of the third active area away from the fifth active area and the edge of the fifth active area away from the third active area, and the second device length is the distance between the edge of the power active area away from the fifth active area and the edge of the power active area away from the third active area.

[0106] In an exemplary embodiment, the gate drive circuit further includes a first capacitor and a second capacitor, wherein the first end of the first capacitor is connected to the first electrode of the fourth transistor, the second end of the first capacitor is connected to the gate electrode of the fourth transistor, the first end of the second capacitor is connected to the second electrode of the fifth transistor, and the second end of the second capacitor is connected to the gate electrode of the fifth transistor; the area of ​​the first capacitor's direct projection on the substrate is greater than the area of ​​the fourth transistor's direct projection on the substrate, and the area of ​​the second capacitor's direct projection on the substrate is greater than the area of ​​the fifth transistor's direct projection on the substrate.

[0107] In an exemplary embodiment, the first capacitor includes a plurality of stacked plates, the second capacitor includes a plurality of stacked plates, and a distance between an edge of at least one plate of the first capacitor close to a side of the second capacitor and an edge of at least one plate of the second capacitor close to a side of the first capacitor is greater than 5.2 μm.

[0108] FIG6 is a schematic diagram of the structure of a gate drive device. In an exemplary embodiment, the gate drive device may include multiple cascaded gate drive circuits (GOA circuits), which convert clock signals into on / off voltages and output them to the display area respectively. The multi-stage gate drive circuit is connected to the scan signal lines in multiple unit rows. Each gate drive circuit sequentially outputs the on voltage in turn to achieve row-by-row scanning of multiple unit rows in the display area. As shown in FIG6 , the gate drive device may include a first-stage gate drive circuit, a second-stage gate drive circuit, a third-stage gate drive circuit, ..., an i-th-stage gate drive circuit. The first-stage gate drive circuit may generate a scan signal OUT1 based on an initial signal provided by an initial signal line STV, a clock signal provided by a clock signal line CK / CB, and a signal provided by a high-level signal line VH / low-level signal line VL, and provide it to the pixel drive circuit of the first unit row in the display area. The i-th level gate driving circuit can generate a scanning signal OUTi based on the scanning signal OUTi-1 generated by the i-1-th level gate driving circuit, the first clock signal provided by the first clock signal line CK, the second clock signal provided by the second clock signal line CB, the high-level signal provided by the high-level signal line VH, and the low-level signal provided by the low-level signal line VL, and provide it to the pixel driving circuit of the i-th unit row in the display area, where i is a positive integer greater than 1.

[0109] The technical solution of the display substrate disclosed herein is described below through exemplary embodiments.

[0110] Figure 7A is a schematic diagram illustrating the operating principle of a gate drive circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 7A , the gate drive circuit has an 8T2C structure and may include eight transistors (first transistor T1 to eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). The gate drive circuit is connected to six signal lines (control signal line GI, first clock signal line CK, second clock signal line CB, high-level signal line VH, low-level signal line VL, and output signal line OUT).

[0111] In an exemplary embodiment, the gate driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, the first electrode of the seventh transistor T7, and the first electrode of the eighth transistor T8. The second node N2 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, the gate electrode of the fourth transistor T4, the gate electrode of the sixth transistor T6, and the second end of the first capacitor C1. The third node N3 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The fourth node N4 is respectively connected to the gate electrode of the fifth transistor T5, the second electrode of the eighth transistor T8, and the second end of the second capacitor C2.

[0112] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the high-level signal line VH, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the output signal line OUT, and a second end of the second capacitor C2 is connected to the fourth node N4.

[0113] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the first clock signal line CK, a first electrode of the first transistor T1 is connected to the control signal line GI, and a second electrode of the first transistor T1 is connected to the first node N1.

[0114] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first clock signal line CK, and a second electrode of the second transistor T2 is connected to the second node N2 .

[0115] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first clock signal line CK, a first electrode of the third transistor T3 is connected to the low-level signal line VL, and a second electrode of the third transistor T3 is connected to the second node N2.

[0116] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the second node N2 , a first electrode of the fourth transistor T4 is connected to the high-level signal line VH, and a second electrode of the fourth transistor T4 is connected to the output signal line OUT.

[0117] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the fourth node N4 , a first electrode of the fifth transistor T5 is connected to the second clock signal line CB, and a second electrode of the fifth transistor T5 is connected to the output signal line OUT.

[0118] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the second node N2 , a first electrode of the sixth transistor T6 is connected to the high-level signal line VH, and a second electrode of the sixth transistor T6 is connected to the third node N3 .

[0119] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the second clock signal line CB, a first electrode of the seventh transistor T7 is connected to the first node N1 , and a second electrode of the seventh transistor T7 is connected to the third node N3 .

[0120] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the low-level signal line VL, a first electrode of the eighth transistor T8 is connected to the first node N1 , and a second electrode of the eighth transistor T8 is connected to the fourth node N4 .

[0121] In an exemplary embodiment, the first to eighth transistors T1 to T8 may be P-type transistors or N-type transistors. Using the same type of transistors in the gate drive circuit can simplify the process, reduce the difficulty of display substrate processing, and improve product yield.

[0122] FIG7B is a driving timing diagram of the gate driving circuit shown in FIG7A. As shown in FIG7B , in an exemplary embodiment, taking the first transistor T1 to the eighth transistor T8 as P-type transistors as an example, the operation process of the gate driving circuit may include:

[0123] In the first period B1, the signals of the first clock signal line CK and the control signal line GI are low level signals, and the signal of the second clock signal line CB is high level signal, so that the first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0124] The first transistor T1 is turned on, causing the first node N1 to be at a low potential. The second transistor T2 is also turned on. Due to the low-level signal line VL, the eighth transistor T8 is turned on, causing the potential of the fourth node N4 to begin to decrease, and the fifth transistor T5 is turned on. The third transistor T3 is turned on, causing the second node N2 to be at a low potential. The fourth and sixth transistors T4 and T6 are turned on, and the output signal line OUT outputs a high-level signal from the high-level signal line VH and the second clock signal line CB.

[0125] In the second period B2, the signal of the second clock signal line CB is a low level signal, and the signals of the first clock signal line CK and the control signal line GI are high level signals, so that the seventh transistor T7 is turned on and the first transistor T1 and the third transistor T3 are turned off.

[0126] Since the first node N1 was at a low potential in the previous period, the seventh transistor T7 is turned on, causing the potentials of the first node N1 and the third node N3 to be low. The second transistor T2 is turned on, the second node N2 is at a high potential, and the fourth transistor T4 and the sixth transistor T6 are turned off. Since the low-level signal line VL turns on the eighth transistor T8 and the fifth transistor T5, the output signal line OUT outputs the low-level signal of the second clock signal line CB. Under the action of the second capacitor C2, the potential of the fourth node N4 continues to decrease.

[0127] In the third period B3, the signal of the first clock signal line CK is a low level signal, and the signals of the second clock signal line CB and the control signal line GI are high level signals, so that the first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0128] The first transistor T1 is turned on, causing the first node N1 to be at a high potential, while the second transistor T2 is turned off. Due to the low-level signal line VL, the eighth transistor T8 is turned on, causing the fourth node N4 to be at a high potential, and the fifth transistor T5 is turned off. The third transistor T3 is turned on, causing the second node N2 to be at a low potential. The fourth and sixth transistors T4 and T6 are turned on, and the output signal line OUT outputs the high-level signal of the high-level signal line VH.

[0129] In the fourth period B4, the signal of the second clock signal line CB is a low level signal, and the signals of the first clock signal line CK and the control signal line GI are high level signals, so that the seventh transistor T7 is turned on, and the first transistor T1 and the third transistor T3 are turned off.

[0130] Because the first node N1 was at a high potential in the previous period, the seventh transistor T7 is turned on, causing the potentials of the first node N1 and the third node N3 to be high, and the second transistor T2 is turned off. Due to the low-level signal line VL, the eighth transistor T8 is turned on, causing the potential of the fourth node N4 to be high, and the fifth transistor T5 is turned off. Under the action of the first capacitor C1, the second node N2 maintains the low potential of the previous period, the fourth transistor T4 and the sixth transistor T6 are turned on, and the output signal line OUT outputs the high-level signal of the high-level signal line VH.

[0131] Figure 8 is an equivalent circuit diagram of a gate drive circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 8, in the display substrate of the present embodiment, the gate drive circuit may include eight transistors (first transistor T1 to eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). The gate drive circuit is connected to six signal lines (control signal line GI, first clock signal line CK, second clock signal line CB, high-level signal line VH, low-level signal line VL, and output signal line OUT).

[0132] In an exemplary embodiment, the third transistor T3, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first transistor T1, the eighth transistor T8, and the fifth transistor T5 may be sequentially arranged along the first direction X (a direction approaching the display area), the first capacitor C1 may be arranged between the second transistor T2 and the fourth transistor T4, and the second capacitor C2 may be arranged between the eighth transistor T8 and the fifth transistor T5.

[0133] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first clock signal line CK, a first electrode of the third transistor T3 is connected to the low-level signal line VL, and a second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, the gate electrode of the fourth transistor T4, the gate electrode of the sixth transistor T6, and the second end of the first capacitor C1, respectively.

[0134] In an exemplary embodiment, a gate electrode of the second transistor T2 is respectively connected to the second electrode of the first transistor T1, the first electrode of the seventh transistor T7, and the first electrode of the eighth transistor T8, the first electrode of the second transistor T2 is connected to the first clock signal line CK, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3, the gate electrode of the fourth transistor T4, and the gate electrode of the sixth transistor T6.

[0135] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the gate electrode of the sixth transistor T6, respectively. A first electrode of the fourth transistor T4 is connected to the high-level signal line VH. A second electrode of the fourth transistor T4 is connected to the output signal line OUT. The fourth transistor T4 can be referred to as a first output transistor.

[0136] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the gate electrode of the fourth transistor T4, respectively. A first electrode of the sixth transistor T6 is connected to the high-level signal line VH. A second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.

[0137] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the second clock signal line CB, a first electrode of the seventh transistor T7 is respectively connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first electrode of the eighth transistor T8, and a second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6.

[0138] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the first clock signal line CK, a first electrode of the first transistor T1 is connected to the control signal line GI, and a second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2, the first electrode of the seventh transistor T7, and the first electrode of the eighth transistor T8.

[0139] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the low-level signal line VL, a first electrode of the eighth transistor T8 is respectively connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first electrode of the seventh transistor T7, and a second electrode of the eighth transistor T8 is respectively connected to the gate electrode of the fifth transistor T5 and the second end of the second capacitor C2.

[0140] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the second electrode of the eighth transistor T8 and the second end of the second capacitor C2, respectively. A first electrode of the fifth transistor T5 is connected to the second clock signal line CB. A second electrode of the fifth transistor T5 is connected to the output signal line OUT. The fifth transistor T5 can be referred to as a second output transistor.

[0141] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the high-level signal line VH, and a second end of the first capacitor C1 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, the gate electrode of the fourth transistor T4, and the gate electrode of the sixth transistor T6.

[0142] In an exemplary embodiment, a first end of the second capacitor C2 is connected to the output signal line OUT, and a second end of the second capacitor C2 is connected to the gate electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8.

[0143] Figure 9 is a schematic diagram of the structure of a gate drive circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate of the exemplary embodiment of the present disclosure may include at least a display area and a non-display area. The display area may include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel including a pixel drive circuit and at least one scan signal line, and the scan signal line is configured to provide a scan signal to the connected pixel drive circuit. The non-display area may include a plurality of cascaded gate drive circuits, at least one gate drive circuit being connected to a scan signal line in a pixel row in the display area. As shown in Figure 9, at least one gate drive circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor 100 and a second capacitor 200, and the gate drive circuit may be connected to at least a first clock signal line 31, a second clock signal line 32, a low level signal line 33, a high level signal line 34 and an output signal line 35.

[0144] In an exemplary embodiment, along the first direction X (the direction close to the display area), the third transistor T3, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first transistor T1, the eighth transistor T8 and the fifth transistor T5 are arranged in sequence, and the second capacitor 200 is arranged on one side of the first direction X of the first capacitor 100 (the side close to the display area).

[0145] In an exemplary embodiment, the fifth transistor T5 serving as the second output transistor can be arranged on one side of the first direction X (the side close to the display area) of the fourth transistor T4 serving as the first output transistor, and at least one transistor is spaced between the fourth transistor T4 and the fifth transistor T5, that is, in the first direction X, the fourth transistor T4 and the fifth transistor T5 are not adjacent to each other.

[0146] In an exemplary embodiment, four transistors may be arranged between the fourth transistor T4 and the fifth transistor T5, and the four transistors are a sixth transistor T6, a seventh transistor T7, a first transistor T1, and an eighth transistor T8. The above transistors are all non-output transistors, and the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first transistor T1, the eighth transistor T8, and the fifth transistor T5 may be arranged in sequence along the first direction X.

[0147] In an exemplary embodiment, the fourth transistor T4 may have a first width-to-length ratio, the fifth transistor T5 may have a second width-to-length ratio, and a ratio of the first width-to-length ratio to the second width-to-length ratio may be approximately 0.95 to 1.05.

[0148] In an exemplary embodiment, the first width-to-length ratio and the second width-to-length ratio may be substantially the same, ie, the width-to-length ratios of both the first output transistor and the second output transistor are substantially the same.

[0149] In an exemplary embodiment, the shape of the first clock signal line 31 can be a straight line or a broken line extending along the first direction X. Along the first direction X, the first clock signal line 31 can be respectively connected to the gate electrode of the third transistor T3, the first electrode of the second transistor T2 and the gate electrode of the first transistor T1.

[0150] In an exemplary embodiment, the second clock signal line 32 may be in a straight line or a zigzag shape extending along the first direction X. Along the first direction X, the second clock signal line 32 may be connected to the gate electrode of the seventh transistor T7 and the first electrode of the fifth transistor T5, respectively.

[0151] In an exemplary embodiment, the first clock signal line 31 may have a first extension length CKL, the second clock signal line 32 may have a second extension length CBL, the second extension length CBL may be greater than the first extension length CKL, and the first extension length CKL and the second extension length CBL may be dimensions in the first direction X.

[0152] In an exemplary embodiment, the low-level signal line 33 may be in a straight line or a broken line shape extending along the first direction X. Along the first direction X, the low-level signal line 33 may be connected to the first electrode of the third transistor T3 and the gate electrode of the eighth transistor T8, respectively.

[0153] In an exemplary embodiment, the high-level signal line 34 may be in a straight line or a broken line shape extending along the first direction X. Along the first direction X, the high-level signal line 34 may be connected to the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6, respectively.

[0154] In an exemplary embodiment, the output signal line 35 may be in a straight line or a zigzag shape extending along the first direction X. Along the first direction X, the output signal line 35 may be connected to the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 .

[0155] In an exemplary embodiment, the third transistor T3 may be located at an end of the gate driver circuit away from the display area, and the fifth transistor T5 may be located at an end of the gate driver circuit closer to the display area. That is, the third transistor T3 and the fifth transistor T5 may be located at opposite ends of the gate driver circuit in the first direction X. The plurality of transistors in the gate driver circuit may have a first device length QL1, and the low-level signal line 33 may have a third device length QL3. The ratio of the first device length QL1 to the third device length QL3 may be approximately 0.95 to 1.05. In an exemplary embodiment, the first device length QL1 may be the distance between an edge of the active region of the third transistor T3 on a side away from the fifth transistor T5 and an edge of the active region of the fifth transistor T5 on a side away from the third transistor T3. The third device length QL3 may be the distance between an edge of the low-level signal line 33 on a side away from the fifth transistor T5 and an edge of the low-level signal line 33 on a side away from the third transistor T3.

[0156] In an exemplary embodiment, the second capacitor 200 can be located on one side of the first capacitor 100 in the first direction X, the orthographic projection of the first capacitor 100 on the silicon substrate at least partially overlaps with the orthographic projection of the fourth transistor T4 on the silicon substrate, and the orthographic projection of the second capacitor 200 on the silicon substrate at least partially overlaps with the orthographic projection of the fifth transistor T5 on the silicon substrate.

[0157] In an exemplary embodiment, the projected area of ​​the first capacitor 100 on the substrate may be larger than the projected area of ​​the fourth transistor T4 on the substrate, and the projected area of ​​the second capacitor 200 on the substrate may be larger than the projected area of ​​the fifth transistor T5 on the substrate.

[0158] In an exemplary embodiment, first capacitor 100 may include a plurality of stacked plates, and second capacitor 200 may include a plurality of stacked plates. A plate spacing CL may be defined between first capacitor 100 and second capacitor 200. Plate spacing CL may be greater than or equal to 5.2 μm. In an exemplary embodiment, plate spacing CL may be the distance between an edge of at least one plate of first capacitor 100 on a side closer to second capacitor 200 and an edge of at least one plate of second capacitor 200 on a side closer to first capacitor 100.

[0159] In an exemplary embodiment, the first capacitor 100 may include a stacked first plate, a third plate, a fifth plate, and a seventh plate. The orthographic projection of the first plate on the substrate at least partially overlaps the orthographic projection of the third plate on the substrate, and the first plate and the third plate form a first sub-capacitor. The orthographic projection of the fifth plate on the substrate at least partially overlaps the orthographic projection of the seventh plate on the substrate, and the fifth plate and the seventh plate form a second sub-capacitor. The fifth plate is connected to the first plate, and the seventh plate is connected to the third plate, so that the first sub-capacitor and the second sub-capacitor form a parallel structure, forming the first capacitor 100 of the gate drive circuit.

[0160] In an exemplary embodiment, the second capacitor 200 may include a stacked second plate, a fourth plate, a sixth plate, and an eighth plate. The orthographic projection of the second plate on the substrate at least partially overlaps the orthographic projection of the fourth plate on the substrate, and the second plate and the fourth plate form a third sub-capacitor. The orthographic projection of the sixth plate on the substrate at least partially overlaps the orthographic projection of the eighth plate on the substrate, and the sixth plate and the eighth plate form a fourth sub-capacitor. The sixth plate is connected to the second plate, and the eighth plate is connected to the fourth plate, so that the third sub-capacitor and the fourth sub-capacitor form a parallel structure, forming the second capacitor 200 of the gate drive circuit.

[0161] In an exemplary embodiment, in a direction perpendicular to the substrate, the gate drive circuit may include a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer arranged in sequence away from the substrate. The first clock signal line 31, the second clock signal line 32, the low-potential signal line 33, and the output signal line 35 may be arranged in the first conductive layer, and the high-potential signal line 34 may be arranged in the second conductive layer.

[0162] In an exemplary embodiment, the first electrode plate and the second electrode plate may be disposed in the third conductive layer, the third electrode plate and the fourth electrode plate may be disposed in the fourth conductive layer, the fifth electrode plate and the sixth electrode plate may be disposed in the fifth conductive layer, and the seventh electrode plate and the eighth electrode plate may be disposed in the sixth conductive layer.

[0163] The following is an illustrative explanation through the preparation process of the display device. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display device. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0164] In an exemplary embodiment, a process of preparing a display substrate may include the following steps.

[0165] (1) Provide a substrate. In an exemplary embodiment, the substrate may be a silicon substrate, which may be an N-type silicon substrate. In an exemplary embodiment, the N-type silicon substrate may serve as a channel region of a P-type transistor.

[0166] In some possible implementations, the silicon substrate may be a P-type silicon material, which may serve as a channel region of an N-type transistor, and this disclosure does not limit this.

[0167] In some possible implementations, the substrate may be a glass substrate.

[0168] (2) Forming an Active Area (AA) Pattern. In an exemplary embodiment, a photoresist pattern including an opening region can be formed by coating a photoresist on an N-type silicon substrate, exposing and developing the photoresist, removing the photoresist in the opening region to expose the surface of the N-type silicon substrate, and then implanting p-type dopant ions in the opening region by ion implantation. The remaining photoresist is then stripped off to form an active area pattern on the N-type silicon substrate, as shown in FIG10 .

[0169] In example embodiments, the active area pattern may include at least first, second, third, fourth, fifth, sixth, seventh, and eighth active regions 11 , 12 , 13 , 14 , 15 , 16 , 17 , and 18 , and a power supply active region 10 .

[0170] In an exemplary embodiment, the third active region 13, the second active region 12, the fourth active region 14, the sixth active region 16, the seventh active region 17, the first active region 11, the eighth active region 18, and the fifth active region 15 may be sequentially arranged along the first direction X, with the third active region 13 and the fifth active region 15 respectively located on both sides of the plurality of active regions in the first direction X, and the power supply active region 10 may be disposed on one side of the plurality of active regions in the second direction Y.

[0171] In an exemplary embodiment, the third active region 13 may have a stripe shape extending along the first direction X, and the third active region 13 may serve as an active region of the third transistor T3 .

[0172] In an exemplary embodiment, the second active region 12 may be in a strip shape extending along the first direction X and may be disposed on one side of the third active region 13 in the first direction X. The second active region 12 may serve as an active region of the second transistor T2 .

[0173] In exemplary embodiments, the third active region 13 and the second active region 12 may be an integral structure connected to each other.

[0174] In an exemplary embodiment, the fourth active region 14 may be in a strip shape extending along the first direction X and may be disposed on one side of the second active region 12 in the first direction X. The fourth active region 14 may serve as an active region of the fourth transistor T4 .

[0175] In an exemplary embodiment, the sixth active region 16 may be in a strip shape extending along the first direction X and may be disposed on one side of the fourth active region 14 in the first direction X. The sixth active region 16 may serve as an active region of the sixth transistor T6 .

[0176] In an exemplary embodiment, the seventh active region 17 may be in a strip shape extending along the first direction X and may be disposed on one side of the sixth active region 16 in the first direction X. The seventh active region 17 may serve as an active region of the seventh transistor T7 .

[0177] In an exemplary embodiment, the first active region 11 may be in a strip shape extending along the first direction X and may be disposed on one side of the seventh active region 17 in the first direction X. The first active region 11 may serve as an active region of the first transistor T1 .

[0178] In exemplary embodiments, the sixth active region 16 , the seventh active region 17 , and the first active region 11 may be an integral structure connected to each other.

[0179] In an exemplary embodiment, the eighth active region 18 may be in a strip shape extending along the first direction X and may be disposed on one side of the first active region 11 in the first direction X. The eighth active region 18 may serve as an active region of the eighth transistor T8 .

[0180] In an exemplary embodiment, the fifth active region 15 may be in a strip shape extending along the first direction X and may be disposed on one side of the eighth active region 18 in the first direction X. The fifth active region 15 may serve as an active region of the fifth transistor T5 .

[0181] In an exemplary embodiment, the power active area 10 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on one side of the plurality of active areas in the second direction Y. The power active area 10P is configured to be connected to a subsequently formed low-level signal line.

[0182] In an exemplary embodiment, each active region may have an active width, which is the distance between an edge of the active region close to the power active region 10 and an edge of the active region away from the power active region 10 . The active width may be a dimension in the second direction Y.

[0183] In an exemplary embodiment, for the fourth active region 14 and the fifth active region 15 that are separately provided and non-adjacent, the fourth active region 14 may have a first active width W1, the fifth active region 15 may have a second active width W2, and a ratio of the first active width W1 to the second active width W2 may be approximately 0.95 to 1.05.

[0184] In example embodiments, the first active width W1 and the second active width W2 may be substantially the same.

[0185] In example embodiments, the eighth active region 18 may have a third active width W3 , which may be smaller than the first active width W1 .

[0186] In an exemplary embodiment, the third active width W3 may be approximately 20% to 30% of the first active width W1. For example, the third active width W3 may be approximately 27% of the first active width W1.

[0187] In an exemplary embodiment, the second active region 12 and the third active region 13 may have substantially the same active width. The first active width W1 may be greater than the active width of either the second active region 12 or the third active region 13, but less than the sum of the active widths of the second active region 12 and the third active region 13. The second active width W2 may be greater than the active width of either the second active region 12 or the third active region 13, but less than the sum of the active widths of the second active region 12 and the third active region 13.

[0188] In an exemplary embodiment, the first active region 11, the sixth active region 16, and the seventh active region 17 may have substantially the same active width. The first active width W1 may be greater than the active width of any one of the first active region 11, the sixth active region 16, and the seventh active region 17, but less than the sum of the active widths of the first active region 11, the sixth active region 16, and the seventh active region 17. The second active width W2 may be greater than the active width of any one of the first active region 11, the sixth active region 16, and the seventh active region 17, but less than the sum of the active widths of the first active region 11, the sixth active region 16, and the seventh active region 17.

[0189] In example embodiments, one or more of the first through seventh active regions 11 through 17 may have an active center line O, which may be a straight line bisecting the active region in the second direction Y and extending along the first direction X.

[0190] In an exemplary embodiment, in the second direction Y, the eighth active area 18 may be disposed on a side of the active center line O close to the power active area 10. The orthographic projection of the eighth active area 18 on the substrate does not overlap with the orthographic projection of the active center line O on the substrate. That is, the eighth active area 18 is offset downward relative to the first active area 11 to the seventh active area 17. By disposing the eighth active area downward, the present disclosure can effectively reduce the overlap between the subsequently formed second capacitor and the eighth transistor T8, effectively reducing parasitic capacitance and effectively reducing the impact of the capacitor manufacturing process on the eighth transistor T8.

[0191] In an exemplary embodiment, in the second direction Y, edges of the first to eighth active regions 11 to 18 on a side close to the power supply active region 10 may be substantially flush.

[0192] In an exemplary embodiment, in the first direction X, a spacing between the second active region 12 and the fourth active region 14, a spacing between the fourth active region 14 and the sixth active region 16, a spacing between the first active region 11 and the eighth active region 18, and a spacing between the eighth active region 18 and the fifth active region 15 may be substantially the same.

[0193] In an exemplary embodiment, each active region may have an active length, which is a distance between an edge of the active region in a first direction X and an edge in an opposite direction of the first direction X. The active length may be a dimension in the first direction X.

[0194] In an exemplary embodiment, for the fourth active region 14 and the fifth active region 15 that are separately provided and non-adjacent, the fourth active region 14 may have a first active length L1, the fifth active region 15 may have a second active length L2, and a ratio of the first active length L1 to the second active length L2 may be approximately 0.95 to 1.05.

[0195] In an exemplary embodiment, the first active length L1 and the second active length L2 may be substantially the same.

[0196] In an exemplary embodiment, the active length may be the length of a transistor, and thus the fourth transistor T4 and the fifth transistor T5 are not adjacent and have the same transistor length.

[0197] In an exemplary embodiment, in the first direction X, the first active region 11, the sixth active region 16, the seventh active region 17, and the eighth active region 18 may be disposed between the fourth active region 14 and the fifth active region 15, that is, the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be disposed between the fourth transistor T4 and the fifth transistor T5.

[0198] In an exemplary embodiment, the fourth transistor T4 is mounted with a first capacitor, and the fifth transistor T5 is mounted with a second capacitor. Both the first capacitor and the second capacitor are capacitors of a stacked structure. The present disclosure places the fourth transistor T4 and the fifth transistor T5 separately (not adjacent) with four transistors between them. This not only effectively ensures the placement space for the first capacitor and the second capacitor, reduces the complexity of the connection, and is beneficial to layout optimization, but also effectively reduces the mutual influence between the two capacitors and minimizes the parasitic capacitance between the first capacitor and the second capacitor.

[0199] In an exemplary embodiment, in the first direction X, the active regions of the plurality of transistors may have a first device length QL1. The first device length QL1 may be the distance between an edge of the third active region 13 on a side away from the fifth active region 15 and an edge of the fifth active region 15 on a side away from the third active region 13. The first device length QL1 may be a dimension in the first direction X. In an exemplary embodiment, the first device length QL1 may serve as the length of the plurality of transistors.

[0200] In an exemplary embodiment, in the first direction X, the power active area 10 may have a second device length QL2. The second device length QL2 may be the distance between an edge of the power active area 10 away from the fifth active area 15 (the edge on the side opposite to the first direction X) and an edge of the power active area 10 away from the third active area 13 (the edge on the side in the first direction X). The second device length QL2 may be the dimension in the first direction X.

[0201] In an exemplary embodiment, a ratio of the first device length QL1 to the second device length QL2 may be approximately 0.95 to 1.05.

[0202] In example embodiments, the first device length QL1 and the second device length QL2 may be substantially the same.

[0203] In an exemplary embodiment, the power active area 10 can be referred to as a constant potential connection point (Pick-up AA) connected to the substrate, and can provide a stable low-voltage potential. In the present disclosure, by arranging the power active area 10 to extend along a first direction X (horizontal direction), and having a device length substantially consistent with the device length of multiple transistors, when the gate drive circuits are arrayed and cascaded along a second direction Y (vertical direction), the power active area 10 can form a constant potential isolation zone with shielding function between the two-stage gate drive circuits, thereby reducing the mutual influence between the two-stage gate drive circuits.

[0204] (3) Forming a gate conductive layer pattern. In an exemplary embodiment, forming the gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on the substrate on which the aforementioned pattern is formed, first patterning the polysilicon film through a patterning process to form a first insulating layer covering the substrate and a polysilicon layer disposed on the first insulating layer, and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in FIG11A and FIG11B , where FIG11B is a schematic diagram of the gate conductive layer in FIG11A .

[0205] In example embodiments, the gate conductive layer pattern may include at least first, second, third, fourth, fifth, sixth, seventh, and eighth gate electrodes 21 , 22 , 23 , 24 , 25 , 26 , 27 , and 28 .

[0206] In example embodiments, the third gate electrode 23 , the second gate electrode 22 , the fourth gate electrode 24 , the sixth gate electrode 26 , the seventh gate electrode 27 , the first gate electrode 21 , the eighth gate electrode 28 , and the fifth gate electrode 25 may be sequentially disposed along the first direction X.

[0207] In an exemplary embodiment, the third gate electrode 23 may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the third gate electrode 23 on the substrate at least partially overlaps with the orthographic projection of the third active region on the substrate. The third gate electrode 23 may serve as the gate electrode of the third transistor T3.

[0208] In an exemplary embodiment, the second gate electrode 22 may be in the shape of a strip extending along the second direction Y, and may be disposed on one side of the third gate electrode 23 in the first direction X. The orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second active region on the substrate, and the second gate electrode 22 may serve as the gate electrode of the second transistor T2.

[0209] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the second gate electrode 22 in the first direction X. The orthographic projection of the fourth gate electrode 24 on the substrate at least partially overlaps with the orthographic projection of the fourth active region on the substrate. The fourth gate electrode 24 may serve as the gate electrode of the fourth transistor T4.

[0210] In an exemplary embodiment, the sixth gate electrode 26 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the fourth gate electrode 24 in the first direction X. The orthographic projection of the sixth gate electrode 26 on the substrate at least partially overlaps with the orthographic projection of the sixth active region on the substrate. The sixth gate electrode 26 may serve as the gate electrode of the sixth transistor T6.

[0211] In an exemplary embodiment, the seventh gate electrode 27 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the sixth gate electrode 26 in the first direction X. The orthographic projection of the seventh gate electrode 27 on the substrate at least partially overlaps with the orthographic projection of the seventh active region on the substrate. The seventh gate electrode 27 may serve as the gate electrode of the seventh transistor T7.

[0212] In an exemplary embodiment, the first gate electrode 21 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the seventh gate electrode 27 in the first direction X. The orthographic projection of the first gate electrode 21 on the substrate at least partially overlaps with the orthographic projection of the seventh active region on the substrate. The first gate electrode 21 may serve as the gate electrode of the first transistor T1.

[0213] In an exemplary embodiment, the eighth gate electrode 28 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the first gate electrode 21 in the first direction X. The orthographic projection of the eighth gate electrode 28 on the substrate at least partially overlaps with the orthographic projection of the seventh active region on the substrate. The eighth gate electrode 28 may serve as the gate electrode of the eighth transistor T8.

[0214] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the second direction Y and may be disposed on one side of the eighth gate electrode 28 in the first direction X. The orthographic projection of the fifth gate electrode 25 on the substrate at least partially overlaps with the orthographic projection of the seventh active region on the substrate. The fifth gate electrode 25 may serve as the gate electrode of the fifth transistor T5.

[0215] In example embodiments, each gate electrode may have a gate length L, which is a dimension of the gate electrode in the first direction X.

[0216] In an exemplary embodiment, the first to third gate electrodes 21 to 23 and the sixth to eighth gate electrodes 26 to 28 may have substantially the same first gate length L1, the fourth gate electrode 24 and the fifth gate electrode 25 may have substantially the same second gate length L2, and the second gate length L2 may be greater than the first gate length L1.

[0217] In an exemplary embodiment, the second gate length L2 may be approximately 1.5 to 2.5 times the first gate length L1. For example, the second gate length L2 may be approximately 2 times the first gate length L1.

[0218] In an exemplary embodiment, since the active widths W of the first to seventh active regions 11 to 17 are substantially the same and the gate lengths L of the first to third gate electrodes 21 to 23 and the sixth to seventh gate electrodes 26 to 27 are substantially the same, the first to third transistors T1 to T3 and the sixth to eighth transistors T6 to T7 have substantially the same first width-to-length ratio (W1 / L1).

[0219] In an exemplary embodiment, since the active widths W of the first to seventh active regions 11 to 17 are substantially the same and the gate lengths L of the fourth gate electrode 24 and the fifth gate electrode 25 are substantially the same, the fourth transistor T4 and the fifth transistor T5 have substantially the same second width-to-length ratio (W1 / L2).

[0220] In an exemplary embodiment, the eighth transistor T8 has a third width-to-length ratio ( W2 / L1 ).

[0221] In an exemplary embodiment, since the second gate length L2 is greater than the first gate length L1, the first width-to-length ratio may be greater than the second width-to-length ratio, that is, the width-to-length ratios of the first to third transistors T1 to T3 and the sixth to eighth transistors T6 to T7 are greater than the width-to-length ratios of the fourth transistor T4 and the fifth transistor T5.

[0222] In an exemplary embodiment, since the first active width W1 is greater than the third active width W3, the first aspect ratio may be greater than the third aspect ratio, that is, the aspect ratios of the first to third transistors T1 to T3 and the sixth to eighth transistors T6 to T7 are greater than the aspect ratio of the eighth transistor T8.

[0223] In an exemplary embodiment, the second aspect ratio may be greater than the third aspect ratio, ie, the aspect ratio of the fourth transistor T4 and the fifth transistor T5 is greater than the aspect ratio of the eighth transistor T8 .

[0224] In an exemplary embodiment, in the second direction Y, edges of the first to eighth gate electrodes 101 to 108 close to the power active region 10 may be staggered, and edges of the first to eighth gate electrodes 101 to 108 away from the power active region 10 may be staggered.

[0225] In an exemplary embodiment, in the first direction X, a spacing between the second gate electrode 102 and the fourth gate electrode 104, a spacing between the fourth gate electrode 104 and the sixth gate electrode 106, a spacing between the first gate electrode 101 and the eighth gate electrode 108, and a spacing between the eighth gate electrode 108 and the fifth gate electrode 105 may be substantially the same.

[0226] In an exemplary embodiment, the fourth transistor T4 is mounted with a first capacitor, the fifth transistor T5 is mounted with a second capacitor, and both the fourth transistor T4 and the fifth transistor T5 are connected to an output signal line. The present disclosure effectively reduces the mutual influence between the two transistors and ensures the stability of the output signal by setting the fourth transistor T4 and the fifth transistor T5 to have substantially the same width-to-length ratio.

[0227] (4) Forming an N-type doping (SN) region pattern. In an exemplary embodiment, forming the N-type doping region pattern may include: coating a photoresist on the substrate on which the aforementioned pattern is formed, forming a plurality of opening regions through exposure and development, removing the photoresist within the plurality of opening regions, and forming N-type doping regions 20 within the opening regions through a doping process, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the N-type doping region in FIG12A .

[0228] In an exemplary embodiment, the shape of the N-type doping region 20 can be a strip shape extending along the first direction X, and the orthographic projection of the N-type doping region 20 on the substrate includes the orthographic projections of the first active region 11 to the eighth active region 18 on the substrate, so that doping regions are formed on both sides of the active region.

[0229] In an exemplary embodiment, the active region between some adjacent gate electrodes can serve as the source region of one transistor and the source region of another transistor at the same time, or can serve as the drain region of one transistor and the drain region of another transistor at the same time, or can serve as the source region of one transistor and the drain region of another N-type transistor at the same time.

[0230] (5) Forming a P-type doping (SP) region pattern. In an exemplary embodiment, forming the P-type doping region pattern may include: coating a photoresist on the substrate on which the aforementioned pattern is formed, forming a plurality of opening regions through exposure and development, removing the photoresist within the plurality of opening regions, and forming P-type doping regions 30 within the opening regions through a doping process, as shown in FIG13A and FIG13B , where FIG13B is a schematic diagram of the P-type doping region in FIG13A .

[0231] In an exemplary embodiment, the shape of the P-type doping region 30 can be a straight line or a broken line extending along the first direction X. The orthographic projection of the P-type doping region 30 on the substrate includes the orthographic projection of the power active region 10 on the substrate, so that the power active region 10 forms a P-type doping region.

[0232] (6) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG. 14 .

[0233] In an exemplary embodiment, the plurality of via holes may include at least first to twenty-second via holes V1 to V22 .

[0234] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate may be located within the range of the orthographic projection of the first region of the first active region on the substrate, the first insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active region, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first region of the first active region through the via hole.

[0235] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate can be located within the range of the orthographic projection of the second area of ​​the first active area (also the first area of ​​the seventh active area) on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second area of ​​the first active area (also the first area of ​​the seventh active area), and the second via V2 is configured to connect the subsequently formed second connecting electrode to the second area of ​​the first active area (also the first area of ​​the seventh active area) through the via.

[0236] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate can be located within the range of the orthographic projection of the first area of ​​the second active area on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first area of ​​the second active area, and the third via V3 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the second active area through the via.

[0237] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate can be located within the range of the orthographic projection of the second area of ​​the second active area (also the second area of ​​the third active area) on the substrate, the first insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the second area of ​​the second active area (also the second area of ​​the third active area), and the fourth via V4 is configured to connect the subsequently formed fourth connecting electrode to the second area of ​​the second active area (also the second area of ​​the third active area) through the via.

[0238] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate can be located within the range of the orthographic projection of the first area of ​​the third active area on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the third active area, and the fifth via V5 is configured to connect the subsequently formed fifth connecting electrode to the first area of ​​the third active area through the via.

[0239] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate may be located within the orthographic projection of the first region of the fourth active region on the substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the fourth active region. The sixth via V6 is configured to connect a subsequently formed sixth connection electrode to the first region of the fourth active region through the via. In an exemplary embodiment, the sixth via V6 may be referred to as a fourth source via of the fourth transistor T4.

[0240] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate may be located within the orthographic projection of the second region of the fourth active region on the substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the fourth active region. The seventh via V7 is configured to connect a subsequently formed seventh connection electrode to the second region of the fourth active region through the via. In an exemplary embodiment, the seventh via V7 may be referred to as a fourth drain via of the fourth transistor T4.

[0241] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate may be located within the orthographic projection of the first region of the fifth active region on the substrate. The first and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the fifth active region. The eighth via V8 is configured to connect a subsequently formed eighth connection electrode to the first region of the fifth active region through the via. In an exemplary embodiment, the eighth via V8 may be referred to as a fifth source via of the fifth transistor T5.

[0242] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate may be located within the orthographic projection of the second region of the fifth active region on the substrate. The first and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the fifth active region. The ninth via V9 is configured to connect a subsequently formed ninth connection electrode to the second region of the fifth active region through the via. In an exemplary embodiment, the ninth via V9 may be referred to as a fifth drain via of the fifth transistor T5.

[0243] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate may be located within the range of the orthographic projection of the first area of ​​the sixth active area on the substrate, the first insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the first area of ​​the sixth active area, and the tenth via hole V10 is configured to connect the subsequently formed tenth connecting electrode 50 to the first area of ​​the sixth active area through the via hole.

[0244] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate may be located within the range of the orthographic projection of the first area of ​​the eighth active area on the substrate, the first insulating layer and the second insulating layer within the eleventh via hole V11 are etched away to expose the surface of the first area of ​​the eighth active area, and the eleventh via hole V11 is configured to connect the subsequently formed eleventh connecting electrode 51 to the first area of ​​the eighth active area through the via hole.

[0245] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate can be located within the range of the orthographic projection of the second area of ​​the eighth active area on the substrate, the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the second area of ​​the eighth active area, and the twelfth via V12 is configured to connect the subsequently formed twelfth connecting electrode to the second area of ​​the eighth active area through the via.

[0246] In an exemplary embodiment, one or more of the first to twelfth via holes V1 to V12 may be plural, and the plurality of via holes may be sequentially disposed along the second direction Y to reduce contact resistance and increase connection reliability.

[0247] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate can be located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the second insulating layer in the thirteenth via V13 is etched away to expose the surface of the first gate electrode 21, and the thirteenth via V13 is configured to connect the subsequently formed first clock signal line to the first gate electrode 21 through the via.

[0248] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate can be located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the second insulating layer in the fourteenth via V14 is etched away to expose the surface of the second gate electrode 22, and the fourteenth via V14 is configured to connect the subsequently formed thirteenth connecting electrode 53 to the second gate electrode 22 through the via.

[0249] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate can be located within the range of the orthographic projection of the third gate electrode 23 on the substrate, the second insulating layer in the fifteenth via V15 is etched away to expose the surface of the third gate electrode 23, and the fifteenth via V15 is configured to connect the subsequently formed first clock signal line to the third gate electrode 23 through the via.

[0250] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate can be located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the second insulating layer in the sixteenth via V16 is etched away to expose the surface of the fourth gate electrode 24, and the sixteenth via V16 is configured to connect the subsequently formed fourteenth connecting electrode to the fourth gate electrode 24 through the via.

[0251] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate can be located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the second insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the fifth gate electrode 25, and the seventeenth via hole V17 is configured to connect the subsequently formed fifteenth connecting electrode to the fifth gate electrode 25 through the via hole.

[0252] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate can be located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the second insulating layer in the eighteenth via V18 is etched away to expose the surface of the sixth gate electrode 26, and the eighteenth via V18 is configured to connect the subsequently formed sixteenth connecting electrode 56 to the sixth gate electrode 26 through the via.

[0253] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate can be located within the range of the orthographic projection of the seventh gate electrode 27 on the substrate, the second insulating layer in the nineteenth via V19 is etched away to expose the surface of the seventh gate electrode 27, and the nineteenth via V19 is configured to connect the subsequently formed second clock signal line to the seventh gate electrode 27 through the via.

[0254] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate may be located within the range of the orthographic projection of the eighth gate electrode 28 on the substrate, the second insulating layer within the twentieth via hole V20 is etched away to expose the surface of the eighth gate electrode 28, and the twentieth via hole V20 is configured to connect the subsequently formed seventeenth connecting electrode to the eighth gate electrode 28 through the via hole.

[0255] In an exemplary embodiment, one or more of the thirteenth to twentieth via holes V13 to V20 may be plural, and the plurality of via holes may be sequentially disposed along the first direction X to reduce contact resistance and increase connection reliability.

[0256] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate can be located within the range of the orthographic projection of the power active area 10 on the substrate, the first insulating layer and the second insulating layer in the twenty-first via V21 are etched away to expose the surface of the power active area 10, and the twenty-first via V21 is configured to connect a subsequently formed low-level signal line to the power active area 10 through the via.

[0257] In an exemplary embodiment, the twenty-first via hole V21 may be in plurality, and the plurality of twenty-first via holes V21 may be sequentially disposed along the first direction X.

[0258] In an exemplary embodiment, the twenty-second via V22 can be located on the substrate, the first insulating layer and the second insulating layer within the twenty-second via V22 are etched away to expose the surface of the substrate, and the twenty-second via V22 is configured to connect the subsequently formed eighteenth connecting electrode 58 to the substrate through the via.

[0259] In an exemplary embodiment, each transistor may have a source-drain length, where the source-drain length is the distance between a via centerline of a source via and a via centerline of a drain via in the transistor, and the source-drain length may be a dimension in a first direction X, where the via centerline is a straight line passing through a geometric center of the via and extending along a second direction Y.

[0260] In an exemplary embodiment, the distance between the via centerline of the sixth via V6 (fourth source via) and the via centerline of the seventh via V7 (fourth drain via) is the first source-drain length L3, meaning that the fourth transistor T4 has the first source-drain length L3. The distance between the via centerline of the eighth via V8 (fifth source via) and the via centerline of the ninth via V9 (fifth drain via) is the second source-drain length L4, meaning that the fifth transistor T5 has the second source-drain length L4. In an exemplary embodiment, the ratio of the first source-drain length L3 to the second source-drain length L4 may be approximately 0.95 to 1.05.

[0261] In example embodiments, the first source-drain length L3 and the second source-drain length L4 may be substantially the same.

[0262] In an exemplary embodiment, the fourth transistor T4 is mounted with a first capacitor, the fifth transistor T5 is mounted with a second capacitor, and both the fourth transistor T4 and the fifth transistor T5 are connected to an output signal line. The present disclosure effectively reduces the mutual influence between the two transistors and ensures the stability of the output signal by setting the fourth transistor T4 and the fifth transistor T5 to have substantially the same source-drain length.

[0263] (7) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the second insulating layer, as shown in FIG. 15A and FIG. 15B , where FIG. 15B is a schematic diagram of the first conductive layer in FIG. 15A . In an exemplary embodiment, the first conductive layer may be referred to as a first metal (Metal 1) layer.

[0264] In an exemplary embodiment, the first conductive layer pattern may include at least a first clock signal line 31 , a second clock signal line 32 , a low-level signal line 33 , first to eighteenth connection electrodes 41 to 58 , and first to fourth connection lines 61 to 64 .

[0265] In an exemplary embodiment, the shape of the first clock signal line 31 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side opposite to the second direction Y of the multiple active areas. On the one hand, the first clock signal line 31 is connected to the third gate electrode 23 through the fifteenth via V15, and on the other hand, it is connected to the first gate electrode 21 through the thirteenth via V13, so that the first clock signal line 31 can simultaneously control the conduction and disconnection of the first transistor T1 and the third transistor T3.

[0266] In example embodiments, the first clock signal line 31 may have a first extension length CKL, and the first extension length CKL may be a dimension in the first direction X.

[0267] In an exemplary embodiment, the shape of the second clock signal line 32 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side opposite to the second direction Y of the first clock signal line 31. The second clock signal line 32 is connected to the seventh gate electrode 27 through the nineteenth via V19, so that the second clock signal line 32 can control the conduction and disconnection of the seventh transistor T7.

[0268] In example embodiments, the second clock signal line 32 may have a second extension length CBL, and the second extension length CBL may be a dimension in the first direction X.

[0269] In an exemplary embodiment, the second extension length CBL may be greater than the first extension length CKL.

[0270] In an exemplary embodiment, the first clock signal line 31 and the second clock signal line 32 in the gate drive circuit have a mutually inverse phase relationship. When the first clock signal output by the first clock signal line 31 is at a high level, the second clock signal output by the second clock signal line 32 is at a low level. When the first clock signal output by the first clock signal line 31 is at a low level, the second clock signal output by the second clock signal line 32 is at a high level. The present disclosure sets the extension length of the second clock signal line 32 to be greater than the extension length of the first clock signal line 31, and the resistance of the second clock signal line 32 to be greater than the resistance of the first clock signal line 31, so that the delay of the second clock signal is greater than that of the first clock signal. When the gate drive circuit is operating, it can be ensured that the first clock signal line 31 jumps first (from a low level to a high level, or from a high level to a low level) before the second clock signal line 32 jumps, thereby improving the driving performance of the gate drive circuit.

[0271] In an exemplary embodiment, the first clock signal line 31 and the second clock signal line 32 in the first conductive layer are disposed on a side of the gate conductive layer away from the substrate, which can reduce the impact of the first clock signal line 31 and the second clock signal line 32 on other transistors.

[0272] In an exemplary embodiment, for the portion of the area where the first clock signal line 31 and the second clock signal line 32 extend along the first direction X (such as the area where the first transistor T1 and the second transistor T2 are located), a first spacing D1 is defined between the first clock signal line 31 and the second clock signal line 32, and a second spacing D2 is defined between the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3. The first spacing D1 may be smaller than the second spacing D2. The first spacing D1 refers to the distance between the edge of the first clock signal line 31 on the side closest to the second clock signal line 32 and the edge of the second clock signal line 32 on the side closest to the first clock signal line 31, and is the dimension in the second direction Y. The second spacing D2 refers to the distance between the edge of the second gate electrode 22 on the side closest to the third gate electrode 23 and the edge of the third gate electrode 23 on the side closest to the second gate electrode 22, and is the dimension in the first direction X.

[0273] In an exemplary embodiment, a third distance D3 is defined between the first clock signal line 31 and the gate electrode of the second transistor T2, and a fourth distance D4 is defined between the second clock signal line 32 and the gate electrode of the third transistor T3. The first distance D1 may be greater than the third distance D3, and the first distance D1 may be greater than the fourth distance D4. The third distance D3 refers to the distance between the edge of the first clock signal line 31 on the side closest to the second gate electrode 22 and the edge of the second gate electrode 22 on the side closest to the first clock signal line 31, and is the dimension in the second direction Y. The fourth distance D4 refers to the distance between the edge of the second clock signal line 32 on the side closest to the third gate electrode 23 and the edge of the third gate electrode 23 on the side closest to the second clock signal line 32, and is the dimension in the second direction Y.

[0274] In an exemplary embodiment, the low-level signal line 33 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged on one side of the multiple active areas in the second direction Y. The low-level signal line 33 is connected to the power active area 10 through multiple twenty-first vias V21.

[0275] In an exemplary embodiment, the low-level signal line 33 may have a third device length QL3, which may be the distance between an edge of the low-level signal line 33 on one side of the first direction X and an edge on the opposite side of the first direction X. The third device length QL3 may be the dimension in the first direction X.

[0276] In an exemplary embodiment, a ratio of the first device length QL1 to the third device length QL3 may be approximately 0.95 to 1.05.

[0277] In example embodiments, the first device length QL1 and the third device length QL3 may be substantially the same.

[0278] In an exemplary embodiment, the low-level signal line 33 can provide a low-potential voltage to the constant-potential connection point. In the present disclosure, by arranging the low-level signal line 33 to extend along a first direction X, with its device length substantially consistent with the device length of the plurality of transistors, when the gate drive circuits are arrayed and cascaded along a second direction Y, the low-level signal line 33 can form a constant-potential isolation zone with a shielding function between the two-stage gate drive circuits, thereby reducing the mutual influence between the two-stage gate drive circuits.

[0279] In an exemplary embodiment, the first connection electrode 41 may have a bar shape extending along the second direction Y, and the first connection electrode 41 is connected to the first region of the first active region through the first via hole V1 .

[0280] In an exemplary embodiment, the shape of the second connection electrode 42 can be a strip shape extending along the second direction Y, the first end of the second connection electrode 42 is connected to the first connection line 61, and the second end of the second connection electrode 42 is connected to the second area of ​​the first active area (also the first area of ​​the seventh active area) through the second via V2.

[0281] In an exemplary embodiment, the shape of the third connection electrode 43 can be a strip shape extending along the second direction Y, the first end of the third connection electrode 43 is connected to the first clock signal line 31, and the second end of the third connection electrode 43 is connected to the first area of ​​the second active area through the third via V3, thereby enabling the first clock signal line 31 to write the first clock signal into the first electrode of the second transistor T2.

[0282] In an exemplary embodiment, the shape of the fourth connection electrode 44 can be a strip shape extending along the second direction Y, the first end of the fourth connection electrode 44 is connected to the second connection line 62, and the second end of the fourth connection electrode 44 is connected to the second area of ​​the second active area (also the second area of ​​the third active area) through the fourth via hole V4.

[0283] In an exemplary embodiment, the shape of the fifth connection electrode 45 can be a strip shape extending along the second direction Y, the first end of the fifth connection electrode 45 is connected to the low-level signal line 33, and the second end of the fifth connection electrode 45 is connected to the first area of ​​the third active area through the fifth via V5, thereby realizing that the low-level signal line 33 can write a low-level signal into the first electrode of the third transistor T3.

[0284] In an exemplary embodiment, the sixth connection electrode 46 may have a bar shape extending along the second direction Y, and the sixth connection electrode 46 is connected to the first region of the fourth active region through the sixth via hole V6 .

[0285] In an exemplary embodiment, the seventh connection electrode 47 may have a bar shape extending along the second direction Y, and the seventh connection electrode 47 is connected to the second region of the fourth active region through the seventh via hole V7 .

[0286] In an exemplary embodiment, the shape of the eighth connection electrode 48 can be a strip shape extending along the second direction Y, the first end of the eighth connection electrode 48 is connected to the second clock signal line 32, and the second end of the eighth connection electrode 48 is connected to the first area of ​​the fifth active area through the eighth via V8, thereby realizing that the second clock signal line 32 can write the second clock signal into the first electrode of the fifth transistor T5.

[0287] In an exemplary embodiment, the ninth connection electrode 49 may have a bar shape extending along the second direction Y, and the ninth connection electrode 49 is connected to the second region of the fifth active region through a ninth via hole V9 .

[0288] In an exemplary embodiment, the tenth connection electrode 50 may have a bar shape extending along the second direction Y, and the tenth connection electrode 50 is connected to the first region of the sixth active region through the tenth via hole V10 .

[0289] In an exemplary embodiment, the eleventh connection electrode 51 may be shaped like a strip extending along the second direction Y, a first end of the eleventh connection electrode 51 is connected to the first connection line 61 , and a second end of the eleventh connection electrode 51 is connected to the first region of the eighth active region through the eleventh via hole V11 .

[0290] In an exemplary embodiment, the shape of the twelfth connection electrode 52 can be a strip shape extending along the second direction Y, the first end of the twelfth connection electrode 52 is connected to the third connection line 63, and the second end of the twelfth connection electrode 52 is connected to the second area of ​​the eighth active area through the twelfth via hole V12.

[0291] In an exemplary embodiment, the thirteenth connection electrode 53 may be in a strip shape extending along the first direction X, a first end of the thirteenth connection electrode 53 is connected to the second gate electrode 22 through the fourteenth via hole V14 , and a second end of the thirteenth connection electrode 53 is connected to the first connection line 61 .

[0292] In an exemplary embodiment, since the first connection line 61 is connected to the second connection electrode 42 and the eleventh connection electrode 51 respectively, the first connection line 61 realizes the mutual connection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, the first electrode of the seventh transistor T7 and the first electrode of the eighth transistor T8.

[0293] In an exemplary embodiment, the second connection electrode 42 , the eleventh connection electrode 51 , the thirteenth connection electrode 53 , and the first connection line 61 may be an integral structure connected to one another.

[0294] In an exemplary embodiment, the fourteenth connection electrode 54 may be in a strip shape extending along the first direction X, a first end of the fourteenth connection electrode 54 is connected to the second connection line 62 , and a second end of the fourteenth connection electrode 54 is connected to the fourth gate electrode 24 through a sixteenth via hole V16 .

[0295] In an exemplary embodiment, since the second connection line 62 is connected to the fourth connection electrode 44 , the second connection line 62 interconnects the second electrode of the second transistor T2 , the second electrode of the third transistor T3 , and the gate electrode of the fourth transistor T4 .

[0296] In exemplary embodiments, the fourth connection electrode 44 , the fourteenth connection electrode 54 , and the second connection line 62 may be an integral structure connected to each other.

[0297] In an exemplary embodiment, the fifteenth connection electrode 55 may be in a strip shape extending along the first direction X, a first end of the fifteenth connection electrode 55 is connected to the third connection line 63 , and a second end of the fifteenth connection electrode 55 is connected to the fifth gate electrode 25 through the seventeenth via hole V17 .

[0298] In an exemplary embodiment, since the third connection line 63 is connected to the twelfth connection electrode 52 , the third connection line 63 enables interconnection between the gate electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8 .

[0299] In an exemplary embodiment, the twelfth connection electrode 52 , the fifteenth connection electrode 55 and the third connection line 63 may be an integral structure connected to each other.

[0300] In an exemplary embodiment, the shape of the sixteenth connecting electrode 56 can be a strip shape extending along the first direction X, the first end of the sixteenth connecting electrode 56 is connected to the fourteenth connecting electrode 54, and the second end of the sixteenth connecting electrode 56 is connected to the sixth gate electrode 26 through the eighteenth via V18, thereby realizing the mutual connection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, the gate electrode of the fourth transistor T4 and the gate electrode of the sixth transistor T6.

[0301] In an exemplary embodiment, the fourth connection electrode 44 , the fourteenth connection electrode 54 , the sixteenth connection electrode 56 , and the second connection line 62 may be an integral structure connected to each other.

[0302] In an exemplary embodiment, the seventeenth connection electrode 57 may have a bar shape extending along the first direction X, and the seventeenth connection electrode 57 is connected to the eighth gate electrode 28 through the twentieth via hole V20 .

[0303] In an exemplary embodiment, the eighteenth connection electrode 58 may be block-shaped (e.g., rectangular) and connected to the substrate through the twenty-second via hole V22. In an exemplary embodiment, the eighteenth connection electrode 58 may be connected to a constant potential signal source to apply a constant voltage to the substrate.

[0304] In an exemplary embodiment, the fourth connection line 64 may be in the shape of a bar extending along the second direction Y. A first end of the fourth connection line 64 is connected to the seventeenth connection electrode 57, and a second end of the fourth connection line 64 is connected to the low-level signal line 33. Since the seventeenth connection electrode 57 is connected to the eighth gate electrode 28, the fourth connection line 64 connects the gate electrode of the eighth transistor T8 and the low-level signal line 33. The low-level signal line 33 can control the conduction and disconnection of the eighth transistor T8.

[0305] In an exemplary embodiment, the low-level signal line 33 , the seventeenth connection electrode 57 , and the fourth connection line 64 may be an integral structure connected to each other.

[0306] (8) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film through a patterning process to form a third insulating layer covering the first conductive layer pattern, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 16 .

[0307] In an exemplary embodiment, the plurality of via holes may include a thirty-first via hole V31 to a thirty-sixth via hole V36 .

[0308] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the third insulating layer in the thirty-first via hole V31 is etched away to expose the surface of the fourth connecting electrode 44, and the thirty-first via hole V31 is configured to connect the subsequently formed twenty-first connecting electrode to the fourth connecting electrode 44 through the via hole.

[0309] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 46 on the substrate, the third insulating layer in the thirty-second via V32 is etched away to expose the surface of the sixth connecting electrode 46, and the thirty-second via V32 is configured to connect a subsequently formed high-level signal line to the sixth connecting electrode 46 through the via.

[0310] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the seventh connecting electrode 47 on the substrate, the third insulating layer in the thirty-third via V33 is etched away to expose the surface of the seventh connecting electrode 47, and the thirty-third via V33 is configured to connect a subsequently formed output signal line to the seventh connecting electrode 47 through the via.

[0311] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the ninth connecting electrode 49 on the substrate, the third insulating layer in the thirty-fourth via V34 is etched away to expose the surface of the ninth connecting electrode 49, and the thirty-fourth via V34 is configured to connect the subsequently formed output signal line to the ninth connecting electrode 49 through the via.

[0312] In an exemplary embodiment, the orthographic projection of the thirty-fifth via hole V35 on the substrate is located within the range of the orthographic projection of the tenth connecting electrode 50 on the substrate, the third insulating layer in the thirty-fifth via hole V35 is etched away to expose the surface of the tenth connecting electrode 50, and the thirty-fifth via hole V35 is configured to connect a subsequently formed high-level signal line to the tenth connecting electrode 50 through the via hole.

[0313] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 52 on the substrate, the third insulating layer in the thirty-sixth via V36 is etched away to expose the surface of the twelfth connecting electrode 52, and the thirty-sixth via V36 is configured to connect the subsequently formed twenty-second connecting electrode to the twelfth connecting electrode 52 through the via.

[0314] In an exemplary embodiment, one or more of the thirty-first to thirty-sixth via holes V31 to V36 may be plural to reduce contact resistance and increase connection reliability.

[0315] (9) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, and forming a second conductive layer pattern on the third insulating layer, as shown in FIG. 17A and FIG. 17B , where FIG. 17B is a schematic diagram of the second conductive layer in FIG. 17A . In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal 2) layer.

[0316] In an exemplary embodiment, the second conductive layer pattern may include at least a high-level signal line 34 , an output signal line 35 , a twenty-first connection electrode 71 , and a twenty-second connection electrode 72 .

[0317] In an exemplary embodiment, the high-level signal line 34 may be in the shape of a straight line or a zigzag line extending along the first direction X. The high-level signal line 34 is connected to the sixth connection electrode 46 via the thirty-second via V32, and is connected to the tenth connection electrode 50 via the thirty-fifth via V35. Since the sixth connection electrode 46 is connected to the first region of the fourth active region via the via, and the tenth connection electrode 50 is connected to the first region of the sixth active region via the via, the high-level signal line 34 writes a high-level signal into the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6.

[0318] In an exemplary embodiment, a high-level connection block 34-1 may be provided on the high-level signal line 34. The high-level connection block 34-1 may be in the shape of a strip extending along the second direction Y and may be provided on a side of the high-level signal line 34 close to the low-level signal line 33 and a side of the high-level signal line 34 away from the low-level signal line 33, respectively. A first end of the high-level connection block 34-1 is connected to the high-level signal line 34, and a second end of the high-level connection block 34-1 extends in a direction away from the high-level signal line 34. The high-level connection block 34-1 is configured to be connected to the first plate of a first capacitor formed subsequently.

[0319] In an exemplary embodiment, the output signal line 35 may be in the shape of a straight line or a zigzag line extending along the first direction X. The output signal line 35 is connected to the seventh connection electrode 47 via a thirty-third via hole V33, and is connected to the ninth connection electrode 49 via a thirty-fourth via hole V34. Since the seventh connection electrode 47 is connected to the second region of the fourth active region via the via hole, and the ninth connection electrode 49 is connected to the second region of the fifth active region via the via hole, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 output drive signals via the output signal line 35.

[0320] In an exemplary embodiment, an output connection block 35-1 may be provided on the output signal line 35. The output connection block 35-1 may be in the shape of a bar extending along the second direction Y and may be provided on a side of the output signal line 35 close to the low-level signal line 33. A first end of the output connection block 35-1 is connected to the output signal line 35, and a second end of the output connection block 35-1 extends in a direction close to the low-level signal line 33. The output connection block 35-1 is configured to be connected to the second plate of a second capacitor to be formed later.

[0321] In an exemplary embodiment, the twenty-first connection electrode 71 may have a bar shape extending along the second direction Y, and the twenty-first connection electrode 71 is connected to the fourth connection electrode 44 through the thirty-first via hole V31 .

[0322] In an exemplary embodiment, the twenty-second connection electrode 72 may be in a bar shape extending along the second direction Y, and the twenty-second connection electrode 72 is connected to the twelfth connection electrode 52 through the thirty-sixth via hole V36 .

[0323] (10) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film through a patterning process to form a fourth insulating layer covering the second conductive layer pattern, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 18 .

[0324] In an exemplary embodiment, the plurality of via holes may include a forty-first via hole V41 , a forty-second via hole V42 , a forty-third via hole V43 , and a forty-fourth via hole V44 .

[0325] In an exemplary embodiment, the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the twenty-first connecting electrode 71 on the substrate, the fourth insulating layer in the forty-first via hole V41 is etched away to expose the surface of the twenty-first connecting electrode 71, and the forty-first via hole V41 is configured to connect the subsequently formed twenty-third connecting electrode to the twenty-first connecting electrode 71 through the via hole.

[0326] In an exemplary embodiment, the orthographic projection of the forty-second via hole V42 on the substrate is located within the range of the orthographic projection of the twenty-second connecting electrode 72 on the substrate, the fourth insulating layer in the forty-second via hole V42 is etched away to expose the surface of the twenty-second connecting electrode 72, and the forty-second via hole V42 is configured to connect the subsequently formed twenty-fourth connecting electrode to the twenty-second connecting electrode 72 through the via hole.

[0327] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the high-level connection block 34-1 of the high-level signal line 34 on the substrate, the fourth insulating layer in the forty-third via V43 is etched away, exposing the surface of the high-level connection block 34-1, and the forty-third via V43 is configured to connect the first plate of the first capacitor formed subsequently to the high-level connection block 34-1 through the via.

[0328] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the output connection block 35-1 of the output signal line 35 on the substrate, the fourth insulating layer in the forty-fourth via V44 is etched away, exposing the surface of the output connection block 35-1, and the forty-fourth via V44 is configured to connect the second plate of the second capacitor formed subsequently to the output connection block 35-1 through the via.

[0329] In an exemplary embodiment, there may be a plurality of the forty-third via hole V43 and the forty-fourth via hole V44 , and the plurality of via holes may be sequentially arranged along the second direction Y to improve connection reliability.

[0330] (11) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the fourth insulating layer, as shown in FIG. 19A and FIG. 19B , where FIG. 19B is a schematic diagram of the third conductive layer in FIG. 19A . In an exemplary embodiment, the third conductive layer may be referred to as a third metal (Metal 3) layer.

[0331] In an exemplary embodiment, the third conductive layer pattern may include at least a twenty-third connecting electrode 73 , a twenty-fourth connecting electrode 74 , a first plate 91 of the first capacitor, and a second plate 92 of the second capacitor.

[0332] In an exemplary embodiment, the twenty-third connection electrode 73 may be in a block shape (eg, rectangular) and connected to the twenty-first connection electrode 71 through the forty-first via hole V41 .

[0333] In an exemplary embodiment, the twenty-fourth connection electrode 74 may be in a block shape (eg, rectangular) and connected to the twenty-second connection electrode 72 through the forty-second via hole V42 .

[0334] In an exemplary embodiment, the first plate 91 of the first capacitor may be rectangular, with chamfered corners. The first plate 91 is connected to the high-level connection block 34-1 via the forty-third via V43. Since the high-level connection block 34-1 is connected to the high-level signal line 34, the first plate 91 has the potential of the high-level signal line 34, and the first plate 91 can serve as a first end of the first capacitor.

[0335] In an exemplary embodiment, the projected area of ​​the first electrode 91 on the substrate is larger than the projected area of ​​the fourth transistor T4 on the substrate. The projected area of ​​the fourth transistor T4 on the substrate may be the projected area of ​​the fourth active region of the fourth transistor T4 on the substrate.

[0336] In an exemplary embodiment, the orthographic projection of the first electrode 91 on the substrate may include the orthographic projections of the second transistor T2 , the third transistor T3 , and the fourth transistor T4 on the substrate, that is, the orthographic projection of the first capacitor on the substrate includes the orthographic projections of at least two transistors on the substrate.

[0337] In an exemplary embodiment, the second plate 92 of the second capacitor may be rectangular, with chamfered corners. The second plate 92 is connected to the output connection block 35-1 via the 44th via V44. Since the output connection block 35-1 is connected to the output signal line 35, the second plate 92 has the potential of the output signal line 35, and the second plate 92 can serve as a first end of the second capacitor.

[0338] In an exemplary embodiment, the projected area of ​​the second electrode plate 92 on the substrate is larger than the projected area of ​​the fifth transistor T5 on the substrate. The projected area of ​​the fifth transistor T5 on the substrate may be the projected area of ​​the fifth active region of the fifth transistor T5 on the substrate.

[0339] In an exemplary embodiment, the orthographic projection of the second electrode plate 92 on the substrate may include the orthographic projections of the fifth transistor T5 and the eighth transistor T8 on the substrate, that is, the orthographic projection of the second capacitor on the substrate includes the orthographic projections of at least two transistors on the substrate.

[0340] In an exemplary embodiment, in the first direction X, there may be a first plate spacing CL1 between the first plate 91 and the second plate 92, and the first plate spacing CL1 may be greater than or equal to 5.2 μm. The first plate spacing CL1 may be the distance between the edge of the first plate 91 on the side close to the second plate 92 and the edge of the second plate 92 on the side close to the first plate 91. Since the first capacitor and the second capacitor have a large number of metal layers and are both large pieces of metal, if there is no certain distance between the two, a relatively large parasitic capacitance will be generated, and the first capacitor and the second capacitor are directly related to the output signal line, which has a greater impact on the output performance of the gate drive circuit. By setting the spacing between the first plate 91 and the second plate 92, the present disclosure can effectively reduce the parasitic capacitance between the first capacitor and the second capacitor, improve the stability of the output signal performance, and improve the driving performance of the gate drive circuit.

[0341] (12) Forming patterns of the fifth insulating layer and the fourth conductive layer. In an exemplary embodiment, forming patterns of the fifth insulating layer and the fourth conductive layer may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed to form a fifth insulating layer covering the third conductive layer, then depositing a fourth conductive film, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the fifth insulating layer, as shown in Figures 20A and 20B, where Figure 20B is a schematic diagram of the fourth conductive layer in Figure 20A. In an exemplary embodiment, the fourth conductive layer may be referred to as a Metal-Insulator-Metal (MIM) structure, and the fourth conductive layer may be referred to as a MIM layer.

[0342] In an exemplary embodiment, the fourth conductive layer pattern may include at least a third plate 93 of the first capacitor and a fourth plate 94 of the second capacitor.

[0343] In an exemplary embodiment, the third electrode plate 93 of the first capacitor can be rectangular, with chamfered corners. The orthographic projection of the third electrode plate 93 on the substrate at least partially overlaps the orthographic projection of the first electrode plate 91 on the substrate. The third electrode plate 93 can serve as a second terminal of the first capacitor. The first electrode plate 91 and the third electrode plate 93 form a first sub-capacitor of the first capacitor.

[0344] In an exemplary embodiment, the orthographic projection of the third electrode plate 93 on the substrate may be located within the range of the orthographic projection of the first electrode plate 91 on the substrate, and the area of ​​the third electrode plate 93 is smaller than that of the first electrode plate 91 .

[0345] In an exemplary embodiment, the shape of the fourth plate 94 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the fourth plate 94 on the substrate at least partially overlaps with the orthographic projection of the second plate 92 on the substrate. The second plate 92 can serve as a second end of the second capacitor, and the second plate 92 and the fourth plate 94 form a third sub-capacitor of the second capacitor.

[0346] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 94 on the substrate may be located within the range of the orthographic projection of the second electrode plate 92 on the substrate, and the area of ​​the fourth electrode plate 94 is smaller than that of the second electrode plate 92 .

[0347] In an exemplary embodiment, a second inter-plate distance CL2 may be defined between the third electrode plate 93 and the fourth electrode plate 94 in the first direction X. The second inter-plate distance CL2 may be greater than the first inter-plate distance CL1. The second inter-plate distance CL2 may be the distance between an edge of the third electrode plate 93 on a side close to the fourth electrode plate 94 and an edge of the fourth electrode plate 94 on a side close to the third electrode plate 93.

[0348] (13) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the sixth insulating film through a patterning process to form a sixth insulating layer covering the fourth conductive layer pattern, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 21 .

[0349] In an exemplary embodiment, the plurality of via holes on the sixth insulation layer may include a fifty-first via hole V51 , a fifty-second via hole V52 , a fifty-third via hole V53 , a fifty-fourth via hole V54 , a fifty-fifth via hole V55 , and a fifty-sixth via hole V56 .

[0350] In an exemplary embodiment, the orthographic projection of the fifty-first via hole V51 on the substrate is located within the range of the orthographic projection of the twenty-third connecting electrode 73 on the substrate, the sixth insulating layer and the fifth insulating layer in the fifty-first via hole V51 are etched away to expose the surface of the twenty-third connecting electrode 73, and the fifty-first via hole V51 is configured to connect the subsequently formed twenty-fifth connecting electrode to the twenty-third connecting electrode 73 through the via hole.

[0351] In an exemplary embodiment, the orthographic projection of the fifty-second via hole V52 on the substrate is located within the range of the orthographic projection of the twenty-fourth connecting electrode 74 on the substrate, the sixth insulating layer and the fifth insulating layer within the fifty-second via hole V52 are etched away to expose the surface of the twenty-fourth connecting electrode 74, and the fifty-second via hole V52 is configured to connect the subsequently formed twenty-sixth connecting electrode to the twenty-fourth connecting electrode 74 through the via hole.

[0352] In an exemplary embodiment, the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the first electrode 91 on the substrate, the sixth insulating layer and the fifth insulating layer in the fifty-third via V53 are etched away to expose the surface of the first electrode 91, and the fifty-third via V53 is configured to connect the fifth electrode plate of the subsequently formed first capacitor to the first electrode 91 through the via.

[0353] In an exemplary embodiment, the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the second electrode plate 92 on the substrate, the sixth insulating layer and the fifth insulating layer in the fifty-fourth via V54 are etched away to expose the surface of the second electrode plate 92, and the fifty-fourth via V54 is configured to connect the sixth electrode plate of the subsequently formed second capacitor to the second electrode plate 92 through the via.

[0354] In an exemplary embodiment, the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the third electrode plate 93 on the substrate, the sixth insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the third electrode plate 93, and the fifty-fifth via V55 is configured to connect the subsequently formed twenty-seventh connecting electrode to the third electrode plate 93 through the via.

[0355] In an exemplary embodiment, the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 94 on the substrate, the sixth insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the fourth electrode plate 94, and the fifty-sixth via V56 is configured to connect the subsequently formed twenty-eighth connecting electrode to the fourth electrode plate 94 through the via.

[0356] In an exemplary embodiment, the fifty-third via hole V53, the fifty-fourth via hole V54, the fifty-fifth via hole V55, and the fifty-sixth via hole V56 may be plural, and the plurality of via holes may be sequentially arranged along the second direction Y to improve connection reliability.

[0357] (14) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fifth conductive film through a patterning process, and forming a fifth conductive layer pattern on the sixth insulating layer, as shown in FIG. 22A and FIG. 22B , where FIG. 22B is a schematic diagram of the fifth conductive layer in FIG. 22A . In an exemplary embodiment, the fifth conductive layer may be referred to as a fourth metal (Metal 4) layer.

[0358] In an exemplary embodiment, the fifth conductive layer pattern may include at least a twenty-fifth connecting electrode 75 , a twenty-sixth connecting electrode 76 , a first plate electrode 81 , a second plate electrode 82 , a fifth plate 95 of the first capacitor, and a sixth plate 96 of the second capacitor.

[0359] In an exemplary embodiment, the twenty-fifth connection electrode 75 may have a bar shape extending along the second direction Y, and the twenty-fifth connection electrode 75 is connected to the twenty-third connection electrode 73 through the fifty-first via hole V51 .

[0360] In an exemplary embodiment, the twenty-sixth connection electrode 76 may be in a block shape (eg, rectangular) and is connected to the twenty-fourth connection electrode 74 through the fifty-second via hole V52 .

[0361] In an exemplary embodiment, the first electrode plate electrode 81 may be in a strip shape extending along the second direction Y, and the first electrode plate electrode 81 is connected to the third electrode plate 93 through a fifty-fifth via hole V55 .

[0362] In an exemplary embodiment, the twenty-fifth connection electrode 75 and the first plate electrode 81 may be an integral structure connected to each other.

[0363] In an exemplary embodiment, the second plate electrode 82 may be in the shape of a strip extending along the second direction Y, and the second plate electrode 82 is connected to the fourth plate 94 through a fifty-sixth via hole V56 .

[0364] In an exemplary embodiment, the shape of the fifth electrode plate 95 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The fifth electrode plate 95 is connected to the first electrode plate 91 through the fifty-third via V53. The fifth electrode plate 95 can serve as the other first end of the first capacitor, and the first electrode plate 91 and the fifth electrode plate 95 have the same potential.

[0365] In an exemplary embodiment, an orthographic projection of the fifth electrode plate 95 on the substrate at least partially overlaps with an orthographic projection of the first electrode plate 91 and the third electrode plate 93 on the substrate.

[0366] In an exemplary embodiment, the orthographic projection of the fifth electrode plate 95 on the substrate may be located within the range of the orthographic projection of the first electrode plate 91 on the substrate, and the area of ​​the fifth electrode plate 95 is smaller than that of the first electrode plate 91 .

[0367] In an exemplary embodiment, the shape of the sixth plate 96 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The sixth plate 96 is connected to the second plate 92 through the fifty-fourth via V54. The sixth plate 96 can serve as the other first end of the second capacitor, and the second plate 92 and the sixth plate 96 have the same potential.

[0368] In an exemplary embodiment, the orthographic projection of sixth plate 96 on the substrate at least partially overlaps with the orthographic projections of second plate 92 and fourth plate 94 on the substrate.

[0369] In an exemplary embodiment, the orthographic projection of the sixth electrode plate 96 on the substrate may be located within the range of the orthographic projection of the second electrode plate 92 on the substrate, and the area of ​​the sixth electrode plate 96 is smaller than that of the second electrode plate 92 .

[0370] In an exemplary embodiment, a third plate distance CL3 may be defined between the fifth plate 95 and the sixth plate 96 in the first direction X. The third plate distance CL3 may be greater than the first plate distance CL1. The third plate distance CL3 may be the distance between an edge of the fifth plate 95 on a side closer to the sixth plate 96 and an edge of the sixth plate 96 on a side closer to the fifth plate 95.

[0371] (15) Forming patterns of the seventh insulating layer and the sixth conductive layer. In an exemplary embodiment, forming patterns of the seventh insulating layer and the sixth conductive layer may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed to form a seventh insulating layer covering the fifth conductive layer, then depositing a sixth conductive film, patterning the sixth conductive film through a patterning process, and forming a sixth conductive layer pattern on the seventh insulating layer, as shown in Figures 23A and 23B, where Figure 23B is a schematic diagram of the sixth conductive layer in Figure 23A. In an exemplary embodiment, the sixth conductive layer may be referred to as a first metal connection (TM1) layer or a capacitor top plate (CTOP) layer.

[0372] In an exemplary embodiment, the sixth conductive layer pattern may include at least a seventh plate 97 of the first capacitor and an eighth plate 98 of the second capacitor.

[0373] In an exemplary embodiment, the seventh electrode plate 97 of the first capacitor can be rectangular, with chamfered corners. The orthographic projection of the seventh electrode plate 97 on the substrate at least partially overlaps the orthographic projection of the fifth electrode plate 95 on the substrate. The seventh electrode plate 97 can serve as the other second end of the first capacitor. The fifth electrode plate 95 and the seventh electrode plate 97 form a second sub-capacitor of the first capacitor.

[0374] In an exemplary embodiment, the orthographic projection of the seventh electrode plate 97 on the substrate may be located within the range of the orthographic projection of the fifth electrode plate 95 on the substrate, and the area of ​​the seventh electrode plate 97 is smaller than that of the fifth electrode plate 95 .

[0375] In an exemplary embodiment, the shape of the eighth plate 98 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the eighth plate 98 on the substrate at least partially overlaps with the orthographic projection of the sixth plate 96 on the substrate. The eighth plate 98 can serve as the other second end of the second capacitor, and the sixth plate 96 and the eighth plate 98 form a fourth sub-capacitor of the second capacitor.

[0376] In an exemplary embodiment, the orthographic projection of the eighth electrode plate 98 on the substrate may be located within the range of the orthographic projection of the sixth electrode plate 96 on the substrate, and the area of ​​the eighth electrode plate 98 is smaller than that of the sixth electrode plate 96 .

[0377] In an exemplary embodiment, a fourth plate distance CL4 may be defined between the seventh plate 97 and the eighth plate 98 in the first direction X. The fourth plate distance CL4 may be greater than the first plate distance CL1. The fourth plate distance CL4 may be the distance between an edge of the seventh plate 97 on a side close to the eighth plate 98 and an edge of the eighth plate 98 on a side close to the seventh plate 97.

[0378] (16) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming the eighth insulating layer pattern may include: depositing an eighth insulating film on the substrate on which the aforementioned pattern is formed, patterning the seventh insulating film through a patterning process to form an eighth insulating layer covering the sixth conductive layer pattern, wherein a plurality of vias are provided on the eighth insulating layer, as shown in FIG. 24 .

[0379] In an exemplary embodiment, the plurality of via holes on the eighth insulation layer may include a sixty-first via hole V61 , a sixty-second via hole V62 , a sixty-third via hole V63 , a sixty-fourth via hole V64 , and a sixty-fifth via hole V65 .

[0380] In an exemplary embodiment, the orthographic projection of the sixty-first via hole V61 on the substrate is located within the range of the orthographic projection of the seventh electrode plate 97 on the substrate, the eighth insulating layer in the sixty-first via hole V61 is etched away to expose the surface of the seventh electrode plate 97, and the sixty-first via hole V61 is configured to connect the subsequently formed first electrode plate electrode to the seventh electrode plate 97 through the via hole.

[0381] In an exemplary embodiment, the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the eighth electrode plate 98 on the substrate, the eighth insulating layer in the sixty-second via V62 is etched away to expose the surface of the eighth electrode plate 98, and the sixty-second via V62 is configured to connect the subsequently formed second electrode plate electrode to the eighth electrode plate 98 through the via.

[0382] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the substrate is located within the range of the orthographic projection of the first plate electrode 81 on the substrate, the eighth insulating layer and the seventh insulating layer in the sixty-second via V62 are etched away to expose the surface of the first plate electrode 81, and the sixty-third via V63 is configured to connect the subsequently formed first plate electrode to the first plate electrode 81 through the via.

[0383] In an exemplary embodiment, the orthographic projection of the sixty-fourth via V64 on the substrate is located within the range of the orthographic projection of the second plate electrode 82 on the substrate, the eighth insulating layer and the seventh insulating layer within the sixty-fourth via V64 are etched away to expose the surface of the second plate electrode 82, and the sixty-fourth via V64 is configured to connect the subsequently formed second plate electrode to the second plate electrode 82 through the via.

[0384] In an exemplary embodiment, the orthographic projection of the sixty-fifth via hole V65 on the substrate is located within the range of the orthographic projection of the twenty-sixth connecting electrode 76 on the substrate, the eighth insulating layer and the seventh insulating layer within the sixty-fifth via hole V65 are etched away to expose the surface of the twenty-sixth connecting electrode 76, and the sixty-fifth via hole V65 is configured to connect the subsequently formed twenty-ninth connecting electrode to the twenty-sixth connecting electrode 76 through the via hole.

[0385] (17) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming the seventh conductive layer pattern may include: depositing a seventh conductive film on the substrate having the aforementioned pattern formed thereon, patterning the seventh conductive film through a patterning process, and forming a seventh conductive layer pattern on the eighth insulating layer, as shown in FIG. 25A and FIG. 25B , where FIG. 25B is a schematic diagram of the seventh conductive layer in FIG. 25A . In an exemplary embodiment, the seventh conductive layer may be referred to as a second metal connection (TM2) layer.

[0386] In exemplary embodiments, the seventh conductive layer pattern may include at least a twenty-seventh connection electrode 77 , a third plate electrode 83 , and a fourth plate electrode 84 .

[0387] In an exemplary embodiment, the twenty-seventh connection electrode 77 may have a bar shape extending along the second direction Y, and the twenty-seventh connection electrode 77 is connected to the twenty-sixth connection electrode 76 through the sixty-fifth via hole V65 .

[0388] In an exemplary embodiment, the shape of the third plate electrode 83 can be rectangular, and the corners of the rectangle can be chamfered. On the one hand, the third plate electrode 83 is connected to the seventh plate 97 through the sixty-first via V61, and on the other hand, it is connected to the first plate electrode 81 through the sixty-third via V63.

[0389] In an exemplary embodiment, the shape of the fourth plate electrode 84 can be rectangular, and the corners of the rectangle can be chamfered. On the one hand, the fourth plate electrode 84 is connected to the eighth plate 98 through the sixty-second via V62, and on the other hand, it is connected to the second plate electrode 82 through the sixty-fourth via V64.

[0390] In an exemplary embodiment, the twenty-seventh connection electrode 77 and the fourth plate electrode 84 may be an integral structure connected to each other.

[0391] Figure 26 is a cross-sectional view taken along line AA in Figure 25A, and Figure 27 is a cross-sectional view taken along line BB in Figure 25A, illustrating the structures of the third to seventh conductive layers. In an exemplary embodiment, the third conductive layer disposed on the fourth insulating layer 114 may include at least the twenty-third connecting electrode 73, the twenty-fourth connecting electrode 74, the first plate 91 of the first capacitor, and the second plate 92 of the second capacitor. A fifth insulating layer 115 is disposed on the side of the third conductive layer away from the fourth insulating layer 114, and a fourth conductive layer is disposed on the side of the fifth insulating layer 115 away from the fourth insulating layer 114. The fourth conductive layer may include at least the third plate 93 of the first capacitor and the fourth plate 94 of the second capacitor. A sixth insulating layer 116 is provided on the side of the fourth conductive layer away from the fourth insulating layer 114, and a fifth conductive layer is provided on the side of the sixth insulating layer 116 away from the fourth insulating layer 114. The fifth conductive layer may include at least a twenty-fifth connecting electrode 75, a twenty-sixth connecting electrode 76, a first plate electrode 81, a second plate electrode 82, a fifth plate 95 of the first capacitor and a sixth plate 96 of the second capacitor. The twenty-fifth connecting electrode 75 is connected to the twenty-third connecting electrode 73 through a via, the twenty-sixth connecting electrode is connected to the twenty-fourth connecting electrode 74 through a via, the first plate electrode 81 is connected to the third plate 93 through a via, the second plate electrode 82 is connected to the fourth plate 94 through a via, the fifth plate 95 is connected to the first plate 91 through a via, and the sixth plate 96 is connected to the second plate 92 through a via. A seventh insulating layer 117 is provided on the side of the fifth conductive layer away from the fourth insulating layer 114, and a sixth conductive layer is provided on the side of the seventh insulating layer 117 away from the fourth insulating layer 114. The sixth conductive layer may include at least the seventh plate 97 of the first capacitor and the eighth plate 98 of the second capacitor. An eighth insulating layer 118 is provided on the side of the sixth conductive layer away from the fourth insulating layer 114, and a seventh conductive layer is provided on the side of the eighth insulating layer 118 away from the fourth insulating layer 114. The seventh conductive layer may include at least the twenty-seventh connecting electrode 77, the third plate electrode 83, and the fourth plate electrode 84. The twenty-seventh connecting electrode 77 is connected to the twenty-sixth connecting electrode 76 through a via, the third plate electrode 83 is connected to the first plate electrode 81 and the seventh plate 97 respectively through vias, and the fourth plate electrode 84 is connected to the second plate electrode 82 and the eighth plate 98 respectively through vias.

[0392] In the exemplary embodiment, the third plate electrode 83 is connected to both the seventh plate 97 and the first plate electrode 81, and the first plate electrode 81 is connected to the third plate 93, thereby achieving interconnection between the third plate 93 and the seventh plate 97. Since the twenty-fifth connecting electrode 75 and the first plate electrode 81 are interconnected, the twenty-fifth connecting electrode 75 is connected to the twenty-third connecting electrode 73, the twenty-third connecting electrode 73 is connected to the twenty-first connecting electrode 71, the twenty-first connecting electrode 71 is connected to the fourth connecting electrode 44, and the fourth connecting electrode 44 is connected to the second region of the second active region (which is also the second region of the third active region), the third plate electrode 83 enables the third plate 93 and the seventh plate 97 to have the potential of the second electrode of the second transistor T2 and the second electrode of the third transistor T3.

[0393] In an exemplary embodiment, since the fifth plate 95 is connected to the first plate 91, and the first plate 91 is connected to the high-level signal line 34, the first plate 91 and the fifth plate 95 (the first end of the first capacitor) have the potential of the high-level signal line 34, and the third plate 93 and the seventh plate 97 (the second end of the first capacitor) have the potential of the second electrode of the second transistor T2 and the second electrode of the third transistor T3, the first plate 91 and the third plate 93 form a first sub-capacitor of the first capacitor, and the fifth plate 95 and the seventh plate 97 form a second sub-capacitor of the first capacitor. The first sub-capacitor and the second sub-capacitor in parallel structure constitute the first capacitor of the gate drive circuit.

[0394] In the exemplary embodiment, the fourth plate electrode 84 is connected to both the eighth plate 98 and the second plate electrode 82, and the second plate electrode 82 is connected to the fourth plate 94, thereby achieving interconnection between the fourth plate 94 and the eighth plate 98. Since the fourth plate electrode 84 is connected to the twenty-seventh connecting electrode 77, the twenty-seventh connecting electrode 77 is connected to the twenty-sixth connecting electrode 76, the twenty-sixth connecting electrode 76 is connected to the twenty-fourth connecting electrode 74, the twenty-fourth connecting electrode 74 is connected to the twenty-second connecting electrode 72, the twenty-second connecting electrode 72 is connected to the twelfth connecting electrode 52, the twelfth connecting electrode 52 is connected to the fifteenth connecting electrode 55 via the third connecting line 63, the twelfth connecting electrode 52 is connected to the second region of the eighth active region, and the fifteenth connecting electrode 55 is connected to the fifth gate electrode 25, the fourth plate electrode 84 enables the fourth plate 94 and the eighth plate 98 to have the potential of the gate electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8.

[0395] In an exemplary embodiment, the sixth plate 96 is connected to the second plate 92, the second plate 92 is connected to the output signal line 35, the second plate 92 and the sixth plate 96 (the first end of the second capacitor) have the potential of the output signal line 35, the fourth plate 94 and the eighth plate 98 (the second end of the second capacitor) have the potential of the gate electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8, so that the second plate 92 and the fourth plate 94 form a third sub-capacitor of the second capacitor, the sixth plate 96 and the eighth plate 98 form a fourth sub-capacitor of the second capacitor, and the third sub-capacitor and the fourth sub-capacitor in parallel structure constitute the second capacitor of the gate drive circuit.

[0396] At this point, the preparation of the display substrate according to the exemplary embodiment of the present disclosure is completed.

[0397] In an exemplary embodiment, the first to eighth insulating layers may be made of silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiON, and may be a single-layer structure or a multi-layer composite structure. The first to seventh conductive layers may be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or may be alloy materials composed of metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). The alloy materials may be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of a Mo layer, a Cu layer, and a Mo layer. In an exemplary embodiment, the planar shape of the via hole may be rectangular, circular, or elliptical, and the sizes of the multiple via holes may be the same or different, which is not limited in this disclosure.

[0398] An exemplary embodiment of the present disclosure provides a gate drive circuit. By arranging the fourth transistor T4 and the fifth transistor T5 to be non-adjacent and with at least one transistor between them, when the fourth transistor T4 is mounted with a first capacitor and the fifth transistor T5 is mounted with a second capacitor, not only can the placement space of the first capacitor and the second capacitor be effectively guaranteed, which is conducive to layout optimization, but the distance between the first capacitor and the second capacitor can also be increased, effectively reducing the mutual influence between the two capacitors and minimizing the parasitic capacitance between the first capacitor and the second capacitor.

[0399] The present disclosure can effectively reduce the parasitic capacitance between the first capacitor and the second capacitor by setting the distance between the first capacitor and the second capacitor, improve the stability of the output signal performance, and improve the driving performance of the gate drive circuit.

[0400] The present disclosure sets the fourth transistor T4 and the fifth transistor T5 to have substantially the same width-to-length ratio and substantially the same source-drain length, so that the fourth transistor T4 and the fifth transistor T5, both connected to the output signal line, have substantially the same electrical characteristics. This not only effectively ensures process uniformity and consistency of the connection structure, but also effectively reduces the mutual influence between the two transistors, thereby ensuring the stability of the output signal.

[0401] The present disclosure sets the eighth transistor T8 to shift downward, thereby effectively reducing the overlapping area between the second capacitor and the eighth transistor T8, effectively reducing parasitic capacitance, and effectively reducing the impact of capacitor process on the performance of the eighth transistor T8.

[0402] The present disclosure provides a power active area and a low-level signal line extending in a horizontal direction, and the device lengths of the power active area, the low-level signal line, and multiple transistors are substantially consistent. When the gate drive circuits are arrayed and cascaded, the power active area and the low-level signal line can form a constant potential isolation zone with a shielding function between the two-stage gate drive circuits, thereby reducing the mutual influence between the two-stage gate drive circuits.

[0403] The present disclosure sets the extension length of the second clock signal line to be greater than the extension length of the first clock signal line, and the resistance of the second clock signal line to be greater than the resistance of the first clock signal line, so that the delay of the second clock signal is greater than the first clock signal. When the gate drive circuit is working, it can be ensured that the first clock signal line jumps first and then the second clock signal line jumps, thereby improving the driving performance of the gate drive circuit.

[0404] The present disclosure provides a first capacitor and a second capacitor of a stacked structure, wherein the first capacitor includes a first sub-capacitor and a second sub-capacitor of a parallel structure, and the second capacitor includes a third sub-capacitor and a fourth sub-capacitor of a parallel structure, thereby maximizing the capacitance values ​​of the first capacitor and the second capacitor. This not only ensures the stability of the output current of the gate drive circuit, but also has a simple structure and a reasonable layout. On the basis of ensuring stable operation, the occupied area of ​​the gate drive circuit can be reduced, and a higher PPI and better display quality can be achieved.

[0405] The present disclosure optimizes the layout of the gate drive circuit through the above-mentioned structural design, optimizes the layout space, reduces the occupied area of ​​the gate drive circuit, improves the circuit quality and signal quality, and can achieve higher display quality and display effect.

[0406] The preparation process disclosed herein can be realized using mature preparation equipment, requires little process improvement, has high compatibility, is simple to realize, is easy to implement, has high production efficiency, low production cost, and high yield rate.

[0407] The structure and preparation process of the display substrate in the exemplary embodiments of the present disclosure are merely illustrative. The corresponding structure can be modified and patterning processes can be added or removed based on actual circumstances. For example, the substrate can be a glass substrate. In another example, the gate drive circuit of the present disclosure can be used to provide scan signals to pixel drive circuit structures such as 7T1C, 8T2C, or 4T1C, but this disclosure is not limited thereto.

[0408] The exemplary embodiments of the present disclosure further provide a display device including the aforementioned display substrate. The display device of the present disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights, rangefinders, and the like.

[0409] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A gate drive circuit, comprising a plurality of transistors disposed on a substrate, the plurality of transistors including at least a fourth transistor serving as a first output transistor and a fifth transistor serving as a second output transistor; a first electrode of the fourth transistor being connected to a high-potential signal line, a first electrode of the fifth transistor being connected to a second clock signal line, a second electrode of the fourth transistor and a second electrode of the fifth transistor being connected to an output signal line, the output signal line being configured to output a gate drive signal to a display area; the fifth transistor being disposed on a side of the fourth transistor close to the display area, and at least one transistor being disposed between the fourth transistor and the fifth transistor along a direction close to the display area.

2. The gate drive circuit according to claim 1, wherein: Along a direction close to the display area, four transistors are arranged between the fourth transistor and the fifth transistor.

3. The gate driving circuit according to claim 1, wherein: The fourth transistor has a first width-to-length ratio, the fifth transistor has a second width-to-length ratio, and a ratio of the first width-to-length ratio to the second width-to-length ratio is 0.95 to 1.

05.

4. The gate driving circuit according to claim 3, wherein: The fourth transistor includes at least a fourth active area, the fourth active area has a first active length and a first active width, the fifth transistor includes at least a fifth active area, the fifth active area has a second active length and a second active width, the ratio of the first active length to the second active length is 0.95 to 1.05, the ratio of the first active width to the second active width is 0.95 to 1.05, the active length is a dimension in a first direction, the active width is a dimension in a second direction, and the first direction and the second direction intersect.

5. The gate driving circuit according to claim 4, wherein: The fourth transistor also includes a fourth source electrode and a fourth drain electrode, the fourth source electrode is connected to the first area of ​​the fourth active area through a fourth source via, and the fourth drain electrode is connected to the second area of ​​the fourth active area through a fourth drain via; the fifth transistor also includes a fifth source electrode and a fifth drain electrode, the fifth source electrode is connected to the first area of ​​the fifth active area through a fifth source via, and the fifth drain electrode is connected to the second area of ​​the fifth active area through a fifth drain via; the fourth transistor has a first source-drain length, and the fifth transistor has a second source-drain length, the ratio of the first source-drain length to the second source-drain length is 0.95 to 1.05, the first source-drain length is the distance between the fourth source via and the fourth drain via, and the second source-drain length is the distance between the fifth source via and the fifth drain via.

6. The gate driving circuit according to claim 4, wherein: The multiple transistors also include an eighth transistor, which is arranged between the fourth transistor and the fifth transistor, the gate electrode of the eighth transistor is connected to the low-potential signal line, and the second electrode of the eighth transistor is connected to the gate electrode of the fifth transistor; the eighth transistor includes at least an eighth active area, and the eighth active area has a third active width, and the third active width is 20% to 30% of the second active width.

7. The gate driving circuit according to claim 6, wherein: The fifth active region has an active center line, which is a straight line bisecting the fifth active region in the second direction and extending along the first direction; the eighth active region is disposed on one side of the active center line in the second direction.

8. The gate driving circuit according to claim 7, wherein: An orthographic projection of the eighth active region on the substrate does not overlap with an orthographic projection of the active center line on the substrate.

9. The gate driving circuit according to claim 7, wherein: An edge of the fourth active region on the second direction, an edge of the fifth active region on the second direction, and an edge of the eighth active region on the second direction are flush.

10. The gate driving circuit according to claim 4, wherein: The plurality of transistors further include a third transistor, the third transistor being disposed on a side of the fourth transistor away from the fifth transistor, the gate electrode of the third transistor being connected to the first clock signal line, the first electrode of the third transistor being connected to the low potential signal line, and the second electrode of the third transistor being connected to the gate electrode of the fourth transistor, the third transistor including at least a third active area; the gate drive circuit further including a power supply active area, the power supply active area being connected to the low potential signal line, the power supply active area being in the shape of a straight line or a broken line extending along a first direction, the power supply active area being disposed on a side of the third active area in a second direction Y, the first direction intersecting the second direction; in the first direction, the plurality of transistors have a first device length, the power supply active area has a second device length, and a ratio of the first device length to the second device length is 0.95 to 1.05; the first device length is the distance between an edge of the third active area away from the fifth active area and an edge of the fifth active area away from the third active area, and the second device length is the distance between an edge of the power supply active area away from the fifth active area and an edge of the power supply active area away from the third active area.

11. The gate driving circuit according to claim 10, wherein: The low-level signal line has a third device length, and the ratio of the first device length to the third device length is 0.95 to 1.

05. The third device length is the distance between the edge of the low-level signal line away from the fifth transistor and the edge of the low-level signal line away from the third transistor.

12. The gate driving circuit according to claim 10, wherein: The multiple transistors also include a second transistor, which is arranged between the third transistor and the fourth transistor, the first electrode of the second transistor is connected to the first clock signal line, the second electrode of the second transistor is connected to the second electrode of the third transistor, the second transistor includes at least a second active area, and the second active area and the third active area are an integrated structure connected to each other.

13. The gate driving circuit according to claim 12, wherein: The first active width is greater than the active width of any one of the second active region and the third active region, and the first active width is less than the sum of the active widths of the second active region and the third active region.

14. The gate driving circuit according to claim 10, wherein: The multiple transistors also include a first transistor, a sixth transistor and a seventh transistor, wherein the first electrode of the first transistor is connected to the control signal line, the second electrode of the first transistor is connected to the first electrode of the seventh transistor T7, the first electrode of the sixth transistor is connected to the high-level signal line, and the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor; the first transistor includes at least a first active area, the sixth transistor includes at least a sixth active area, and the seventh transistor includes at least a seventh active area, and the first active area, the sixth active area and the seventh active area are an integrated structure connected to each other.

15. The gate driving circuit according to claim 14, wherein: The first active width is greater than the active width of any one of the first active region, the sixth active region, and the seventh active region, and is less than the sum of the active widths of the first active region, the sixth active region, and the seventh active region.

16. The gate driving circuit according to claim 10, wherein: The first clock signal line and the second clock signal line are in the shape of straight lines or broken lines extending along the first direction. The first clock signal line has a first extension length, and the second clock signal line has a second extension length, which is greater than the first extension length.

17. The gate driving circuit according to claim 12, wherein: The shapes of the first clock signal line and the second clock signal line are straight lines or broken lines extending along the first direction, there is a first spacing between the first clock signal line and the second clock signal line, there is a second spacing between the gate electrode of the second transistor and the gate electrode of the third transistor, and the first spacing is smaller than the second spacing.

18. The gate driving circuit according to claim 17, wherein: There is a third distance between the first clock signal line and the gate electrode of the second transistor, there is a fourth distance between the second clock signal line and the gate electrode of the third transistor, the first distance is greater than the third distance, and the first distance is greater than the fourth distance.

19. The gate driving circuit according to claim 17, wherein: In a direction perpendicular to the substrate, the gate drive circuit includes at least a gate conductive layer and a first conductive layer arranged on a side of the gate conductive layer away from the substrate, the gate electrode of the second transistor and the gate electrode of the third transistor are arranged in the gate conductive layer, and the first clock signal line and the second clock signal line are arranged in the first conductive layer.

20. The gate drive circuit according to any one of claims 1 to 19, wherein: The gate drive circuit also includes a first capacitor and a second capacitor, the first end of the first capacitor is connected to the first electrode of the fourth transistor, the second end of the first capacitor is connected to the gate electrode of the fourth transistor, the first end of the second capacitor is connected to the second electrode of the fifth transistor, and the second end of the second capacitor is connected to the gate electrode of the fifth transistor; the second capacitor is arranged on a side of the first capacitor close to the display area, the area of ​​the first capacitor's direct projection on the substrate is larger than the area of ​​the fourth transistor's direct projection on the substrate, and the area of ​​the second capacitor's direct projection on the substrate is larger than the area of ​​the fifth transistor's direct projection on the substrate.

21. The gate driving circuit according to claim 20, wherein: The orthographic projection of the first capacitor on the substrate includes at least two transistors projected on the substrate, and the orthographic projection of the second capacitor on the substrate includes at least two transistors projected on the substrate.

22. The gate driving circuit according to claim 20, wherein: The first capacitor includes multiple stacked plates, the second capacitor includes multiple stacked plates, and the distance between the edge of at least one plate in the first capacitor close to the second capacitor and the edge of at least one plate in the second capacitor close to the first capacitor is greater than 5.2 μm.

23. The gate driving circuit according to claim 20, wherein: The first capacitor includes a stacked first electrode plate, a third electrode plate, a fifth electrode plate, and a seventh electrode plate, wherein the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate, the orthographic projection of the fifth electrode plate on the substrate at least partially overlaps with the orthographic projection of the seventh electrode plate on the substrate, the fifth electrode plate is connected to the first electrode plate, and the seventh electrode plate is connected to the third electrode plate; the second capacitor includes a stacked second electrode plate, a fourth electrode plate, a sixth electrode plate, and an eighth electrode plate, wherein the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate, and the orthographic projection of the sixth electrode plate on the substrate at least partially overlaps with the orthographic projection of the eighth electrode plate on the substrate; The sixth electrode plate is connected to the second electrode plate, and the eighth electrode plate is connected to the fourth electrode plate.

24. The gate driving circuit according to claim 23, wherein: The fifth electrode plate is connected to the first electrode plate through a via, the seventh electrode plate is connected to the third electrode plate through the first electrode plate electrode and the third electrode plate electrode; the sixth electrode plate is connected to the second electrode plate through a via, and the eighth electrode plate is connected to the fourth electrode plate through the second electrode plate electrode and the fourth electrode plate electrode.

25. The gate driving circuit according to claim 24, wherein: In a direction perpendicular to the substrate, the gate drive circuit includes a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer sequentially arranged in a direction away from the substrate; the first electrode plate and the second electrode plate are arranged in the third conductive layer, the third electrode plate and the fourth electrode plate are arranged in the fourth conductive layer, the fifth electrode plate, the sixth electrode plate, the first electrode plate electrode, and the second electrode plate electrode are arranged in the fifth conductive layer, the seventh electrode plate and the eighth electrode plate are arranged in the sixth conductive layer, and the third electrode plate electrode and the fourth electrode plate electrode are arranged in the seventh conductive layer; The third plate electrode is connected to the seventh plate and the first plate electrode through vias, respectively, and the first plate electrode is connected to the third plate through vias; the fourth plate electrode is connected to the eighth plate and the second plate electrode through vias, respectively, and the second plate electrode is connected to the fourth plate through vias.

26. A display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, the scanning signal line being configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to a scanning signal line in a pixel row in the display area; at least one gate driving circuit comprises the gate driving circuit as described in any one of claims 1 to 25.

27. A display device comprising the display substrate according to claim 26.

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