Array substrate, display panel, and display device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel, and a display device. The array substrate comprises: a substrate; a plurality of terminals located in a binding area on one side of the substrate; a first common wire located on one side of the substrate, the first common wire being arranged around a display area and at least comprising a first sub-part which is located in a binding opposite-side area and extends in a first direction; and a plurality of second common wires located on one side of the substrate, the plurality of second common wires extending in a second direction, extending from the display area to the binding opposite-side area and intersecting with the first sub-part, and the second direction intersecting with the first direction, wherein the first sub-part and the plurality of second common wires are located on a same layer and are directly electrically connected at intersections.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] Dual Gate product design can halve the display panel data line requirement, thereby reducing the number of source COF used, which can significantly reduce the panel production cost, and thus has been widely concerned in recent years.

[0003] The existing dual gate display product has a problem that when the display area common line and the non-display area common line are turned on, the resistance is large, the common signal is difficult to recover when high-frequency refreshing, and ghosting and crosstalk problems occur.

[0004] SUMMARY

[0005] Embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate has a display area, a binding area located at the periphery of the display area, and a binding opposite area opposite to the binding area, wherein the array substrate comprises:

[0006] a substrate;

[0007] a plurality of terminals located in the binding area on one side of the substrate;

[0008] a first common line located on one side of the substrate, the first common line being arranged around the display area and comprising at least a first sub-portion located in the binding opposite area and extending in a first direction;

[0009] a plurality of second common lines located on one side of the substrate, the plurality of second common lines extending in a second direction and extending from the display area to the binding opposite area, intersecting the first sub-portion, the second direction intersecting the first direction;

[0010] wherein the first sub-portion and the plurality of second common lines are located in the same layer and are directly electrically connected at the intersection position.

[0011] In a possible implementation, the array substrate further comprises a plurality of data lines; the data lines and the second common lines are arranged alternately in the first direction.

[0012] The first sub-portion and the data lines are in the same layer and of the same material.

[0013] In a possible implementation, the first common line further includes: a second sub-portion extending in the second direction, and a third sub-portion extending in the first direction; the second sub-portion is located at the periphery of the display area, and the third sub-portion is located at the binding area.

[0014] The second sub-portion is located at the same layer as the first sub-portion and is electrically connected at the intersection position; the third sub-portion is located at a different layer from the second sub-portion and is electrically connected at the intersection position through a via hole.

[0015] In a possible implementation, the array substrate further includes: a first compensation line; the first compensation line is located at a side of the first common line away from the display area, and one end of the first compensation line is electrically connected at the intersection position of the first sub-portion and the second sub-portion.

[0016] The first compensation line is of the same layer and the same material as the first sub-portion.

[0017] In a possible implementation, the array substrate further includes: a first lead line; the other end of the first compensation line is electrically connected to one end of the first lead line, and the other end of the first lead line is electrically connected to the terminal; the first lead line and the first compensation line are located at different layers.

[0018] In a possible implementation, the first sub-portion includes: a first position; the first position is located at a distance of one fifth to one third of the length between the end of the first sub-portion in the first direction;

[0019] The array substrate further includes: a second compensation line; the second compensation line is located at a side of the first compensation line away from the display area; one end of the second compensation line is electrically connected to the first position.

[0020] The second compensation line is of the same layer and the same material as the first sub-portion.

[0021] In a possible implementation, the array substrate further includes: a second lead line;

[0022] The other end of the second compensation line is electrically connected to one end of the second lead line; the other end of the second lead line is electrically connected to the terminal; the second lead line and the second compensation line are located at different layers.

[0023] In a possible implementation, the second sub-portion includes: a second position; the second position is located at a distance of one fourth to three fourths of the length between the end of the second sub-portion in the second direction;

[0024] The array substrate further comprises a third compensation trace; the third compensation trace is located between the first compensation trace and the first common trace; one end of the third compensation trace is electrically connected to the second position, and the other end of the third compensation trace is electrically connected to the terminal;

[0025] The third compensation trace is of the same layer and material as the first subpart.

[0026] In a possible implementation, the array substrate further comprises a fourth compensation trace; one end of the fourth compensation trace is electrically connected to an end of the second subpart towards the terminal, and the other end of the fourth compensation trace is electrically connected to the terminal; the fourth compensation trace is of the same layer and material as the third subpart.

[0027] In a possible implementation, the second subpart comprises a third position; the third position is located at a length of 7 / 10 to 1 / 5 of the length of the second subpart in the second direction from the end of the second subpart close to the terminal;

[0028] The array substrate further comprises a first detection trace; the first detection trace is located between the first compensation trace and the third compensation trace; one end of the first detection trace is electrically connected to the third position.

[0029] The first detection trace is of the same layer and material as the first subpart.

[0030] In a possible implementation, the array substrate further comprises a third lead line.

[0031] One end of the first detection trace is electrically connected to one end of the third lead line; the other end of the third lead line is electrically connected to the terminal; the third lead line and the first detection trace are located in different layers.

[0032] In a possible implementation, the array substrate further comprises a plurality of first electrostatic protection units.

[0033] The plurality of first electrostatic protection units are located between the first subpart and the display area, and at least one first electrostatic protection unit in the plurality of first electrostatic protection units is electrically connected to the second subpart.

[0034] In a possible implementation, the array substrate further comprises a plurality of data lines extending in the second direction, a fan-out lead group located in the binding area, and a plurality of second electrostatic protection units; the fan-out lead group comprises a plurality of fan-out leads, and the fan-out leads are electrically connected to the data lines in correspondence;

[0035] The plurality of second electrostatic protection units are located between the third sub-portion and the fan-out lead group, and at least one of the plurality of second electrostatic protection units is electrically connected to the third sub-portion.

[0036] The display panel provided by the embodiments of the present disclosure can be included in a display device.

[0037] The display device provided by the embodiments of the present disclosure can include the display panel provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0038] FIG. 1 is a schematic diagram of an array substrate in the related art;

[0039] FIG. 2 is a schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0040] FIG. 3A is a specific display panel structure diagram corresponding to each position in FIG. 2;

[0041] FIG. 3B can be a schematic diagram of part of the film layers at the S1 position in FIG. 3A;

[0042] FIG. 3C can be a schematic diagram of part of the film layers at the S3 position in FIG. 3A. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like only represent relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0045] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art considering the measurement and error (i.e., limitations) associated with the measurement of the particular quantity. For example, "approximately" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.

[0046] In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. The exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0047] In order to make the following description of embodiments of the present disclosure clear and concise, known functions and components are omitted from the detailed description of the present disclosure.

[0048] With the market requirements for screen aperture ratio and transmittance being higher and higher, in the case of ensuring that the aperture ratio of the Dual Gate product is consistent with that of the Single Gate structure, in combination with FIG. 1, the display panel includes: a transparent metal oxide planar electrode 03 (for example, the transparent metal oxide can be indium tin oxide) located in the display area AA, and a vertical common wire 01 located in the same layer as the data line (SD) in the display area AA, and a horizontal common wire 02 located in the non-display area BB, that is, the pixel design of the high-transmittance Dual Gate structure, in the display area AA, the horizontal metal common wire is cancelled, and only the longitudinal metal common wire is reserved. Under this pixel design, the vertical common wire 01 in the display area AA is connected to the planar transparent metal oxide planar electrode 03 through the via hole K. The planar resistance of the transparent metal oxide planar electrode 03 is large, which leads to poor overall conduction and recovery of the common signal. Moreover, in the pixel design of the Dual Gate structure, the vertical common wire 01 of the display area AA also needs to be connected to the horizontal common wire 02 located in the non-display area BB and in different layers through the via hole K when it extends to the top end of the panel. For a mainstream product with high resolution, the vertical common wire 01 of the display area AA has about 2880 roots, which means that 2880 roots need to be additionally punched and connected to the horizontal common wire 02. In addition to the influence of the via hole resistance, the conduction ability of the horizontal common wire 02 is low. Secondly, although the two horizontal common wires 02 are designed in the same layer, an electrostatic short circuit ring (not shown in FIG. 1) is arranged between the two horizontal common wires 02. When the two horizontal common wires 02 are connected, they can only be connected through other film layer structures and via holes, which also affects the overall conduction performance of the common wire. Furthermore, compared with the Single Gate product, the Dual Gate structure panel without the mesh common wire structure has sufficient time to recover when the common voltage is disturbed by the coupling capacitor in the low-frequency case. However, in the high-brush case, the common voltage of the Dual Gate structure panel is difficult to recover in a very short charging time, that is, the common signal cannot be quickly recovered after coupling, resulting in line residual image and crosstalk and other defects.

[0049] Therefore, in combination with FIG. 2, FIG. 3A-FIG. 3C, FIG. 3A can be a specific structure diagram corresponding to each position in FIG. 2, S1 in FIG. 3A can be a structure diagram corresponding to the position S1 in FIG. 2, S2 in FIG. 3A can be a structure diagram corresponding to the position S2 in FIG. 2, S3 in FIG. 3A can be a structure diagram corresponding to the position S3 in FIG. 2, S4 in FIG. 3A can be a structure diagram corresponding to the position S4 in FIG. 2, the dashed box view on the upper right side of the position S2 in FIG. 3A can be an enlarged schematic view of the lower left side of the position S2, FIG. 3B can be a partial film layer schematic view of the position S1 in FIG. 3A, and FIG. 3C can be a partial film layer schematic view of the position S3 in FIG. 3A. An array substrate provided by the embodiment of the present disclosure has a display area AA, a binding area DP located at the periphery of the display area AA, and a binding opposite area DPO opposite to the binding area DP, wherein the array substrate comprises:

[0050] a substrate;

[0051] a plurality of terminals P located at the binding area DP on one side of the substrate, the plurality of terminals being used for electrical connection with pads of a circuit board, and the circuit board can be a flexible circuit board or a printed circuit board, etc.

[0052] a first common wire 1 located on one side of the substrate, the first common wire 1 being arranged around the display area AA and at least comprising a first sub-portion 11 located at the binding opposite area DPO and extending along a first direction X;

[0053] a plurality of second common wires 2 located on one side of the substrate, the plurality of second common wires 2 extending along a second direction Y and extending from the display area AA to the binding opposite area DPO, intersecting the first sub-portion 11, and the second direction Y intersecting the first direction X; specifically, the second common wire 2 can be partially located in the display area AA and partially located in the binding opposite area DPO; optionally, the second direction Y can be perpendicular to the first direction X;

[0054] wherein the first sub-portion 11 and the plurality of second common wires 2 are located in the same layer and are directly electrically connected at the intersecting position. That is, the first sub-portion 11 and the plurality of second common wires 2 are in the same layer and do not need to be electrically connected through punching, and the extending directions of the two are intersected and directly electrically connected at the intersecting position.

[0055] In the embodiments of the present disclosure, the first sub-part 11 of the DPO located at the opposite side of the binding pair is located in the same layer as the plurality of second common wires 2 partially located in the display area AA, and the two are directly electrically connected at the intersection position, without the need for electrical connection through punching, thereby avoiding the overall resistance of the common wire being reduced when conducting through the via, and thereby reducing the resistance value of the second common wire 2 in the display area AA and the peripheral common wire of the display area AA when conducting, thereby improving the recovery and conduction capability of the panel common signal, and improving the problems of ghosting and crosstalk in the Dual Gate structure panel under the condition of extremely short charging time and extremely difficult recovery of the common voltage.

[0056] In a possible implementation, the array substrate further includes a plurality of data lines (not shown in the figure); the data lines and the second common wires 2 are alternately arranged along the first direction X; the first sub-part 11 is of the same layer and the same material as the data lines. That is, the first sub-part 11, the second common wire 2, and the data lines are of the same layer and the same material.

[0057] In a possible implementation, in the embodiments of the present disclosure, the display area AA can not be provided with a metal common wire extending along the first direction X. Optionally, the array substrate provided by the embodiments of the present disclosure can be a dual gate structure, one pixel row includes two corresponding gate lines, the two gate lines are arranged on the two sides of the pixel row, and the same data line is electrically connected with the adjacent two sub-pixels. In the pixel column, the data line and the second common wire are alternately arranged in the adjacent pixel columns.

[0058] In a possible implementation, referring to FIG. 2, the display area AA can further be provided with a common electrode 3. In a possible implementation, the common electrode 3 can be a planar electrode. In another possible implementation, the common electrode 3 can include a plurality of common electrode strips extending along the first direction X and arranged in sequence along the second direction Y. One common electrode strip can correspond to one row of pixel electrodes, that is, the orthogonal projection of one common electrode strip on the substrate can cover the orthogonal projection of one row of pixel electrodes on the substrate. In a possible implementation, the common electrode 3 can also include a plurality of common electrode blocks, one common electrode block can correspond to a plurality of pixel electrodes, that is, the orthogonal projection of one common electrode block on the substrate can cover the orthogonal projection of a plurality of pixel electrodes on the substrate.

[0059] In a possible implementation, referring to FIG. 2, in the display area AA, the common electrode 3 can be electrically connected with the second common wire 2 through the first via K1.

[0060] In a possible implementation, the array substrate can include, in sequence on one side of the substrate: a pixel electrode layer (which can include a plurality of pixel electrodes), a gate line layer (which can include a plurality of gate lines extending along a first direction X and arranged in sequence along a second direction Y), a gate insulating layer, an active layer, a data line (which can include a plurality of data lines extending along the second direction Y and arranged on one side along the first direction X, and a plurality of second common lines 2 extending along the second direction Y and arranged on one side along the first direction X, the data lines and the second common lines 2 can be arranged alternately along the first direction X), a passivation layer, and a common electrode layer (which can include a common electrode 3); the material of the pixel electrode layer can be transparent metal oxide, for example, indium tin oxide; and the material of the common electrode layer can be transparent metal oxide, for example, indium tin oxide.

[0061] In a possible implementation, as shown in FIGS. 2, 3A-3C, the first common line 1 further includes: a second sub-portion 12 extending along the second direction Y, and a third sub-portion 13 extending along the first direction X; the second sub-portion 12 is located at the periphery of the display area AA, for example, as shown in FIG. 2, the second sub-portion 12 can be located on the left side and the right side of the display area AA; the third sub-portion 13 is located in the bonding area DP; the second sub-portion 12 and the first sub-portion 11 are located in the same layer and are electrically connected at the intersection position; the third sub-portion 13 and the second sub-portion 12 are located in different layers and are electrically connected by a via at the intersection position. Specifically, for example, as shown in FIGS. 3A and 3C, the third sub-portion 13 and the second sub-portion 12 overlap at the dashed box S6, and the two can be electrically connected by a via at the overlapping position; alternatively, for example, the two can be electrically connected by a via and a first adapter, and the first adapter can be located in the common electrode layer.

[0062] In a possible implementation, as shown in FIGS. 2, 3A-3C, the first common line 1 can be a closed ring, including the first sub-portion 11, the second sub-portion 12, and the third sub-portion 13 connected to each other.

[0063] In a possible implementation, the third sub-portion 13 can be located in the gate line layer and be of the same material as the gate lines. The third sub-portion 13 is formed at the same time as the gate lines, which is conducive to simplifying the manufacturing process of the array substrate.

[0064] In a possible implementation, as shown in FIGS. 2, 3A-3C, the array substrate further includes: a fourth compensation line C4; one end of the fourth compensation line C4 is electrically connected to the end portion of the second sub-portion 12 facing the terminal P, and the other end is electrically connected to the terminal P; the fourth compensation line C4 is of the same material as the third sub-portion 13. In the embodiments of the present disclosure, the fourth compensation line C4 can be configured as a proximal common compensation line of the display panel close to the terminal P, to compensate the common voltage signal for the common line close to the terminal P and maintain the stability of the common voltage of the display panel.

[0065] In a possible implementation, in combination with FIG. 2, FIG. 3A-FIG. 3C, the array substrate further includes: a first compensation wire C1; the first compensation wire C1 is located on a side of the first common wire 1 away from the display area AA, and one end is electrically connected to a position where the first sub-part 11 and the second sub-part 12 intersect; the first compensation wire C1 is of the same layer and the same material as the first sub-part 11. In the embodiment of the present disclosure, the array substrate further includes: the first compensation wire C1, one end of the first compensation wire C1 is electrically connected to the position where the first sub-part 11 and the second sub-part 12 intersect, which can serve as a far-end common compensation wire of the display panel away from the terminal P and electrically connected to a top corner of the display panel, compensating the common voltage of the common wire away from the terminal P and maintaining the stability of the far-end common voltage of the display panel; in addition, the first compensation wire C1 is of the same layer and the same material as the first sub-part 11, that is, can be located in the same layer as the data line and directly electrically connected to the first common wire 1, avoiding the reduction of the overall resistance of the common wire when electrically connected through the via, thereby improving the recovery and conduction ability of the panel common signal and improving the problems of residual image and crosstalk.

[0066] In a possible implementation, in combination with FIG. 3A and FIG. 3C, the array substrate further includes: a first lead Y1; the other end of the first compensation wire C1 is electrically connected to one end of the first lead Y1, and the other end of the first lead Y1 is electrically connected to the terminal. The first lead Y1 and the first compensation wire C1 are located in different layers, specifically, the first compensation wire C1 can be located in the layer of the data line, and the first lead Y1 can be located in the layer of the gate line, that is, the first compensation wire C1 is exchanged to the layer of the gate line to realize electrical connection with the corresponding terminal, so as to provide a signal for the first compensation wire C1 through the terminal.

[0067] In a possible implementation, the first compensation wire C1 can be directly electrically connected to the first lead Y1 at the overlapping position through the via.

[0068] In a possible implementation, as shown in FIG. 2, the first sub-portion 11 includes: a first position E1; the length a1 between the first position E1 and the end of the first sub-portion 11 is one fifth to one third of the length a2 of the first sub-portion 11 in the first direction X; optionally, the length a1 between the first position E1 and the end of the first sub-portion 11 is one fourth of the length a2 of the first sub-portion 11 in the first direction X; the array substrate further includes: a second compensation trace C2; the second compensation trace C2 is located on the side of the first compensation trace C1 away from the display area; one end of the second compensation trace C2 is electrically connected to the first position E1; the second compensation trace C2 is of the same layer and the same material as the first sub-portion 11. In the embodiment of the present disclosure, the array substrate further includes: a second compensation trace C2; one end of the second compensation trace C2 is electrically connected to the position one fourth of the length of the first sub-portion 11 (which can also be regarded as the position one fourth of the display panel in the first direction X), which can serve as a distal end common compensation trace of the display panel at the position one fourth of the display panel in the first direction X away from the terminal P, compensates the common voltage of the common trace away from the terminal P, and maintains the stability of the distal end common voltage of the display panel; moreover, the second compensation trace C2 is of the same layer and the same material as the first sub-portion 11, that is, can be located in the same layer as the data line and can be directly electrically connected to the first common trace 1. Compared with the conventional display panel shown in FIG. 1, the two horizontal common traces 02 on the upper end of the display area AA need to be conducted through the via and the switching structure, and in the embodiment of the present disclosure, the second compensation trace C2 can be directly electrically connected to the first sub-portion 11, avoiding the reduction of the overall resistance of the common trace when electrically connected through the via, thereby improving the recovery and conduction ability of the panel common signal, and improving the problems such as residual image and crosstalk.

[0069] In a possible implementation, as shown in FIG. 3A and FIG. 3C, the array substrate further includes: a second lead Y2; the other end of the second compensation trace C2 is electrically connected to one end of the second lead Y2; the other end of the second lead Y2 is electrically connected to the terminal P; the second compensation trace C2 and the second lead Y2 are located in different layers, specifically, the second compensation trace C2 can be located in the layer of the data line, and the second lead Y2 can be located in the layer of the gate line, that is, the second compensation trace C2 is switched to the layer of the gate line to realize electrical connection with the corresponding terminal, so as to provide a signal for the second compensation trace C2 through the terminal.

[0070] In a possible implementation, the second compensation trace C2 can be directly electrically connected to the second lead Y2 at the overlapping position through the via.

[0071] In a possible implementation, in combination with FIG. 2, the second sub-portion 12 includes: a second position E2; the second position E2 is located at a length b1 between the ends of the second sub-portion 12, and the length b1 is one fourth to three fourths of a length b2 of the second sub-portion 12 in the second direction Y; optionally, the second position E2 is located at the length b1 between the ends of the second sub-portion 12, and the length b1 is one half of the length b2 of the second sub-portion 12 in the second direction Y; the array substrate further includes: a third compensation trace C3; the third compensation trace C3 is located between the first compensation trace C1 and the first common trace 1; one end of the third compensation trace C3 is electrically connected to the second position E2, and the other end of the third compensation trace C3 is electrically connected to the terminal P; and the third compensation trace C3 is of the same layer and the same material as the first sub-portion 11. In the embodiment of the present disclosure, the array substrate further includes: the third compensation trace C3; one end of the third compensation trace C3 is electrically connected to a position at one half of the length of the second sub-portion 12 (which can also be regarded as a position at one half of the display panel in the second direction Y), and the third compensation trace C3 can serve as a common compensation trace at a center position of the display panel in the second direction Y, compensate for a common voltage of the common trace at the center position of the display panel in the second direction Y, and maintain the stability of the remote common voltage of the display panel; and the third compensation trace C3 is of the same layer and the same material as the first sub-portion 11, that is, the third compensation trace C3 can be located in the same layer as the data line, and can be directly electrically connected to the first common trace 1, thereby avoiding the overall resistance of the common trace from being reduced when the common trace is electrically connected through a via hole, and further improving the recovery and conduction capability of the common signal of the panel, and improving problems such as image sticking and crosstalk.

[0072] In a possible implementation, in combination with FIG. 2, the second sub-portion 12 includes: a third position E3; the third position E3 is located at a length b3 between the end of the second sub-portion 12 close to the terminal and the end of the second sub-portion 12 close to the terminal, and the length b3 is 1 / 7 to 1 / 5 of the length b2 of the second sub-portion 12 in the second direction Y; optionally, the third position E3 is located at a length b3 between the end of the second sub-portion 12 close to the terminal and the end of the second sub-portion 12 close to the terminal, and the length b3 is 1 / 6 of the length b2 of the second sub-portion 12 in the second direction Y; the array substrate further includes: a first detection trace F1; the first detection trace F1 is located between the first compensation trace C1 and the third compensation trace C3; one end of the first detection trace F1 is electrically connected to the third position E3; the first detection trace F1 is of the same layer and the same material as the first sub-portion 11. In the embodiment of the present disclosure, the array substrate further includes: the first detection trace F1; one end of the first detection trace F1 is electrically connected to a position at 1 / 6 of the length of the second sub-portion 12 (which can also be regarded as a position at 1 / 6 of the display panel in the second direction Y), which can be used as a display panel detection feedback trace, and can detect the actual common voltage signal of the display panel and feed back to the processing component (for example, an IC) of the display panel. The processing component receives the signal, and accordingly generates a compensation signal (through each common compensation trace) for the display panel, to ensure the stability of the common voltage of the entire display panel; and the first detection trace F1 is of the same layer and the same material as the first sub-portion 11, that is, can be located in the same layer as the data line, and can be directly electrically connected to the first common trace 1, avoiding the reduction of the overall resistance of the common trace when electrically connected through a via hole, thereby improving the recovery and conduction capability of the panel common signal, and improving the problems such as residual image and crosstalk (Crosstalk) defects.

[0073] In a possible implementation, in combination with FIG. 3A and FIG. 3C, the array substrate further includes: a third lead Y3; one end of the first detection trace F1 is electrically connected to one end of the third lead Y3; the other end of the third lead Y3 is electrically connected to the terminal P, and the third lead Y3 and the first detection trace F1 are located in different layers. Specifically, the first detection trace F1 can be located in the layer of the data line, and the third lead Y3 can be located in the layer of the gate line, that is, the first detection trace F1 is switched to the layer of the gate line to realize electrical connection with the corresponding terminal.

[0074] It can be understood that the first lead Y1, the second lead Y2, and the third lead Y3 can be electrically connected to different terminals respectively to obtain different signals.

[0075] In a possible implementation, as shown in FIGS. 3A-3C, the array substrate further includes: a plurality of first electrostatic protection units ESD1; the plurality of first electrostatic protection units ESD1 are located between the first sub-portion 11 and the display area AA, and at least one of the plurality of first electrostatic protection units ESD1 is electrically connected to the second sub-portion 12. In this way, the static electricity between the first common wire 1 and the display area AA is prevented from affecting the wires of the display area AA.

[0076] Specifically, one end of the first electrostatic protection unit ESD1 is electrically connected to the data line of the display area AA, and the other end is electrically connected to the first common wire 1. A second common wire 2 part is arranged between the adjacent two first electrostatic protection units ESD1, and is used to be electrically connected to the first common wire 1.

[0077] In a possible implementation, as shown in FIGS. 3A-3C, the array substrate further includes: a plurality of data lines (not shown in the figure) extending along the second direction Y, a fan-out lead group 4 located in the binding area DP, and a plurality of second electrostatic protection units ESD2; the fan-out lead group 4 includes a plurality of fan-out leads, and the fan-out leads are electrically connected to the data lines in a one-to-one correspondence. Specifically, the fan-out leads can be electrically connected to the data lines in a one-to-one correspondence. The plurality of second electrostatic protection units ESD2 are located between the third sub-portion 13 and the fan-out lead group 4, and at least one of the plurality of second electrostatic protection units ESD2 is electrically connected to the third sub-portion 13. In this way, the static electricity between the first common wire 1 and the display area AA is prevented from affecting the wires of the display area AA.

[0078] Specifically, the second electrostatic protection unit ESD2 is electrically connected to the data line of the display area.

[0079] In a possible implementation, as shown in FIG. 3A, the display panel provided by the embodiment of the present disclosure can further include a gate drive circuit GOA. In a possible implementation, the first compensation wire C1, the second compensation wire C2, and the first detection wire F1 can be located on a side of the gate drive circuit GOA away from the display area AA, and the second sub-portion 12 and the third compensation wire C3 can be located on a side of the gate drive circuit GOA close to the display area AA.

[0080] In a possible implementation, as shown in FIGS. 3A and 3C, the array substrate can further include a plurality of drive wires G1 extending along the second direction Y and electrically connected to the gate drive circuit GOA, a fourth lead Y4 extending along the first direction X, and a plurality of third electrostatic protection units ESD3. At least part of the drive wires G1 can be electrically connected to the third electrostatic protection units ESD3 through the fourth lead Y4, so as to achieve the anti-static protection of the drive wires G1.

[0081] Optionally, the fourth lead Y4 can be arranged in the same layer and of the same material as the common electrode; optionally, the fourth lead Y4 can also be arranged in the same layer and of the same material as the pixel electrode.

[0082] In a possible implementation, at least one of the first compensation trace C1, the second compensation trace C2, the third compensation trace C3, the fourth compensation trace C4, and the first detection trace F1 can also be electrically connected to the corresponding electrostatic protection unit through the corresponding fourth lead Y4.

[0083] Based on the same inventive concept, the embodiments of the present disclosure further provide a display panel, which comprises the array substrate provided in the embodiments of the present disclosure.

[0084] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, which comprises the display panel provided in the embodiments of the present disclosure.

[0085] Based on the same inventive concept, the embodiments of the present disclosure further provide a display panel, which comprises the array substrate provided in the embodiments of the present disclosure.

[0086] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, which comprises the display panel provided in the embodiments of the present disclosure.

[0087] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to cover all changes and modifications falling within the scope of the present application.

[0088] Obviously, persons skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. An array substrate having a display area, a bonding area located around the display area, and a bonding opposite area opposite to the bonding area, wherein, The array substrate includes: Substrate; Multiple terminals are located in the bonding area on one side of the substrate; A first common trace is located on one side of the substrate. The first common trace is disposed around the display area and includes at least a first sub-part located in the bonding opposite side area and extending along a first direction. Multiple second common traces are located on one side of the substrate. The multiple second common traces extend along a second direction and from the display area to the bonding opposite side area, intersecting with the first sub-part. The second direction intersects with the first direction. The first sub-section and the multiple second common wirings are located on the same layer and are directly electrically connected at their intersections.

2. The array substrate as claimed in claim 1, wherein, The array substrate further includes: multiple data lines; the data lines and the second common trace are arranged alternately along the first direction; The first sub-section is made of the same layer and material as the data line.

3. The array substrate as described in claim 1 or 2, wherein, The first common trace further includes: a second sub-section extending along the second direction, and a third sub-section extending along the first direction; the second sub-section is located outside the display area, and the third sub-section is located in the binding area; The second sub-part is located on the same layer as the first sub-part and is electrically connected at the intersection; the third sub-part is located on a different layer from the second sub-part and is electrically connected at the intersection via a via.

4. The array substrate as claimed in claim 3, wherein, The array substrate further includes: a first compensation trace; the first compensation trace is located on the side of the first common trace away from the display area, and one end is electrically connected to the intersection of the first sub-part and the second sub-part; The first compensation trace is on the same layer and made of the same material as the first sub-section.

5. The array substrate as claimed in claim 4, wherein, The array substrate further includes: a first lead; the other end of the first compensation trace is electrically connected to one end of the first lead, and the other end of the first lead is electrically connected to the terminal; the first lead and the first compensation trace are located on different layers.

6. The array substrate according to any one of claims 3-5, wherein, The first sub-part includes: a first position; the length between the first position and the end of the first sub-part is one-fifth to one-third of the length of the first sub-part in the first direction; The array substrate further includes: a second compensation trace; the second compensation trace is located on the side of the first compensation trace away from the display area; one end of the second compensation trace is electrically connected to the first position; The second compensation trace is on the same layer and made of the same material as the first sub-section.

7. The array substrate as claimed in claim 6, wherein, The array substrate further includes: a second lead; The other end of the second compensation trace is electrically connected to one end of the second lead; the other end of the second lead is electrically connected to the terminal; the second lead and the second compensation trace are located on different layers.

8. The array substrate according to any one of claims 3-7, wherein, The second sub-part includes: a second position; the length between the second position and the end of the second sub-part is one-quarter to three-quarters of the length of the second sub-part in the second direction; The array substrate further includes: a third compensation trace; the third compensation trace is located between the first compensation trace and the first common trace; one end of the third compensation trace is electrically connected to the second position, and the other end of the third compensation trace is electrically connected to the terminal; The third compensation wiring is on the same layer and made of the same material as the first sub-section.

9. The array substrate according to any one of claims 3-7, wherein, The array substrate further includes: a fourth compensation trace; one end of the fourth compensation trace is electrically connected to the end of the second sub-part facing the terminal, and the other end is electrically connected to the terminal; the fourth compensation trace is in the same layer and made of the same material as the third sub-part.

10. The array substrate as claimed in claim 8 or 9, wherein, The second sub-part includes: a third position; the length between the third position and the end of the second sub-part near the terminal is one-seventh to one-fifth of the length of the second sub-part in the second direction; The array substrate further includes: a first detection trace; the first detection trace is located between the first compensation trace and the third compensation trace; one end of the first detection trace is electrically connected to the third location; The first detection trace is in the same layer and made of the same material as the first sub-section.

11. The array substrate as claimed in claim 10, wherein, The array substrate further includes: a third lead; One end of the first detection trace is electrically connected to one end of the third lead; the other end of the third lead is electrically connected to the terminal; the third lead and the first detection trace are located on different layers.

12. The array substrate according to any one of claims 3-11, wherein, The array substrate further includes: a plurality of first electrostatic protection units; The plurality of first electrostatic discharge protection units are located between the first sub-section and the display area, and at least one of the plurality of first electrostatic discharge protection units is electrically connected to the second sub-section.

13. The array substrate according to any one of claims 3-12, wherein, The array substrate further includes: multiple data lines extending along the second direction, a fan-out lead group located in the bonding area, and multiple second electrostatic discharge protection units; the fan-out lead group includes multiple fan-out leads, and the fan-out leads are electrically connected to the data lines respectively; The plurality of second electrostatic discharge protection units are located between the third sub-section and the fan-out lead group, and at least one of the plurality of second electrostatic discharge protection units is electrically connected to the third sub-section.

14. A display panel, wherein, Includes the array substrate as described in any one of claims 1-13.

15. A display device, wherein, Includes the display panel as described in claim 14.

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