Power amplifier, power amplifier link, radio frequency front-end circuit and electronic device

Abstract

The present application relates to the technical field of power amplifiers. Provided are a power amplifier, a power amplifier link, a radio frequency front-end circuit and an electronic device, which can solve the problem in the related art of power amplifiers having relatively poor stability and being prone to self-oscillation phenomena. The power amplifier comprises a substrate layer, a heterostructure layer arranged on the substrate layer, and a gate, a source and a drain, which are arranged on the heterostructure layer. The heterostructure layer comprises a buffer layer arranged on the substrate layer, and a barrier layer arranged on the buffer layer. The gate is arranged on the barrier layer, and comprises a gate finger, wherein the source and the drain are respectively disposed on two opposite sides of the gate finger; the gate finger comprises a first conductive layer and second conductive layers, which are stacked; the sheet resistance of the first conductive layer is greater than that of the second conductive layers; a first insulating portion is provided on the gate finger; in the extension direction of the gate finger, the first insulating portion disconnects the second conductive layers; and the second conductive layers located on two sides of the first insulating portion are electrically connected by means of the first conductive layer. The present application can be used in a radio frequency system.

Description

Power amplifiers, power amplifier links, RF front-end circuits and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 26, 2024, with application number 202410210898.9 and application name “Power amplifier, power amplifier link, RF front-end circuit and electronic equipment”, the entire contents of which are incorporated by reference into this application.

[0002] In the field of technology

[0003] The present application relates to the field of camera technology, and in particular to a power amplifier, a power amplifier link, a radio frequency front-end circuit, and an electronic device. Background Art

[0004] Power amplifiers (PAs) are crucial components of electronic devices and are widely used in their RF systems. As high-frequency, high-gain, and high-power devices, PAs are the circuit modules most susceptible to self-excitation in RF systems. Especially in high-power PAs, self-excitation can generate uncontrollable high power and current, potentially damaging the PA and causing stability and robustness issues. Even if self-excitation is mild and doesn't damage the device, these stray signals can still degrade the RF system's transmit and receive performance. Therefore, self-excitation requires careful attention and avoidance during design and application.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a power amplifier, a power amplifier link, a radio frequency front-end circuit, and an electronic device, which are used to solve the problem in the related art that the power amplifier has poor stability and is prone to self-excitation.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a power amplifier, comprising a substrate layer, a heterostructure layer arranged on the substrate layer, and a gate, a source and a drain arranged on the heterostructure layer; the heterostructure layer comprises a buffer layer arranged on the substrate layer, and a barrier layer arranged on the buffer layer, the gate is arranged on the barrier layer, the gate comprises a gate finger, and a source and a drain are respectively provided on opposite sides of the gate finger; the gate finger comprises a first conductive layer and a second conductive layer arranged in a stacked manner, the square resistance of the first conductive layer is greater than the square resistance of the second conductive layer, a first insulating portion is provided on the gate finger, and along the extension direction of the gate finger, the first insulating portion disconnects the second conductive layer, and the second conductive layers located on both sides of the first insulating portion are electrically connected through the first conductive layer.

[0009] In the power amplifier of the embodiment of the present application, since the sheet resistance of the first conductive layer is greater than the sheet resistance of the second conductive layer, the second conductive layers located on both sides of the first insulating portion are electrically connected through the first conductive layer. Therefore, during operation, the signal transmitted on the gate finger first enters the region of the first conductive layer opposite the first insulating portion from the second conductive layer on one side of the first insulating portion (this region is called the first resistance region), and then enters the second conductive layer on the other side of the first insulating portion from the first resistance region of the first conductive layer. The first resistance region of the first conductive layer acts as an intermediate electrical connection. Since the sheet resistance of the first conductive layer is larger, the first resistance region of the first conductive layer is equivalent to a stable resistor connected in series with the second conductive layers on both sides of the first insulating portion. When the power amplifier is operating, the first resistance region of the first conductive layer can consume signal energy on the coupling path between the gate and drain of the power amplifier, thereby reducing the strength of the signal on the coupling path, thereby suppressing self-oscillation of the power amplifier and improving the stability of the power amplifier. In addition, a portion of the gate finger is made into a stabilizing resistor, so that the stabilizing resistor does not need to occupy space outside the gate finger, making the stabilizing resistor occupy less space, thereby making the structure of the power amplifier more compact; and without increasing the complexity of the process, the compatibility of the resistor manufacturing process and the electrode manufacturing process is achieved.

[0010] In some embodiments of the first aspect, the first conductive layer is disposed between the barrier layer and the second conductive layer, and the first conductive layer is a metal layer or an alloy layer, and is in contact with the barrier layer. With this arrangement, when the designed resistance value of the first resistive region of the first conductive layer is constant, the length of the first resistive region of the first conductive layer (i.e., the dimension in the direction in which the gate fingers extend) can be reduced.

[0011] In some embodiments of the first aspect, the thickness of the first conductive layer is less than the thickness of the second conductive layer. This configuration allows the sheet resistance of the first conductive layer and the second conductive layer to be precisely adjusted to target values ​​according to different requirements of the power amplifier, thereby increasing the applicability of the manufacturing process and facilitating reduced manufacturing costs of the power amplifier.

[0012] In some embodiments of the first aspect, the thickness of the first conductive layer ranges from 20 to 300 nm, and the thickness of the second conductive layer ranges from 50 to 1000 nm. This configuration can reduce the size of the first resistance region of the first conductive layer and the space occupied by the second conductive layer, while also controlling gate finger loss from being excessive.

[0013] In some embodiments of the first aspect, the sheet resistance of the first conductive layer ranges from 200 to 400 mΩ / sq, and the sheet resistance of the gate fingers ranges from 20 to 50 mΩ / sq. This configuration can both reduce the size of the first resistive region of the first conductive layer and control the loss of the gate fingers from being excessive.

[0014] In some embodiments of the first aspect, the resistance of the region where the first conductive layer faces the first insulating portion is in the range of 2 to 10 Ω. This configuration can suppress the self-oscillation of the power amplifier while reducing the gain loss of the link.

[0015] In some embodiments of the first aspect, the first conductive layer and the second conductive layer each include a plurality of stacked metal layers; the plurality of metal layers of the first conductive layer are a group selected from the group consisting of: W layer / Ti layer, W layer / Pt layer, W layer / Au layer, Ni layer / Ti layer, Ni layer / Pt layer, Ni layer / Au layer, W layer / Ti layer / Au layer, Ni layer / Pt layer / Au layer, and W layer / Pt layer / Au layer; and the plurality of metal layers of the second conductive layer are a group selected from the group consisting of: Ni layer / Au layer, Ni layer / Pt layer / Au layer, Ni layer / Pt layer / Au layer / Ti layer, Ti layer / Au layer, Ti layer / Pt layer / Au layer, and Ti layer / Pt layer / Au layer / Ti layer. Such a configuration can improve adhesion between the first conductive layer and the second conductive layer.

[0016] In some embodiments of the first aspect, there are multiple gate fingers, two adjacent gate fingers are spaced apart, and a source and a drain are provided on opposite sides of each gate finger. This arrangement can increase the power of the power amplifier and achieve high-power synthesis of the power amplifier.

[0017] In some embodiments of the first aspect, the source electrode includes a sub-source electrode, the drain electrode includes a sub-drain electrode, the sub-source electrodes and the sub-drain electrodes are arranged alternately, and gate fingers are provided between adjacent sub-source electrodes and sub-drain electrodes. The heterostructure layer, the gate fingers, and the sub-drain electrodes and sub-source electrodes on either side constitute a power amplifier cell. This arrangement can make the power amplifier cell more compact, thereby improving the area utilization of the power amplifier.

[0018] In some embodiments of the first aspect, the source and drain are both disposed on the barrier layer; the source further includes a first connection portion connected to each sub-source electrode; the drain further includes a second connection portion connected to each sub-drain electrode; and the first connection portion is provided with a clearance opening for circumventing the gate finger. This arrangement facilitates connection of the gate finger to a gate lead located outside the first connection portion.

[0019] In some embodiments of the first aspect, the sub-source and the sub-drain are both strip-shaped structures.

[0020] In some embodiments of the first aspect, the gate further includes a first routing wire connected to each gate finger; the first routing wire includes a first conductive layer and a second conductive layer; a second insulating portion is provided on the first routing wire between two adjacent gate fingers; the second insulating portion disconnects the second conductive layer along an extension direction of the first routing wire, and the second conductive layers on both sides of the second insulating portion are electrically connected via the first conductive layer. This arrangement suppresses self-oscillation between the gate fingers of the power amplifier and improves stability between the gate fingers of the power amplifier.

[0021] In some embodiments of the first aspect, the resistance of the region where the first conductive layer faces the second insulating portion is in the range of 2 to 10 Ω. This configuration can suppress self-oscillation between gate fingers of the power amplifier while reducing link gain loss.

[0022] In some embodiments of the first aspect, the gate, source, and drain electrodes constitute an electrode group, and there are multiple electrode groups. The gates of two adjacent electrode groups are connected by a second trace. The second trace includes a first conductive layer and a second conductive layer. A third insulating portion is provided on the second trace. Along the extension direction of the second trace, the third insulating portion disconnects the second conductive layer, and the second conductive layers on both sides of the third insulating portion are electrically connected via the first conductive layer. This arrangement suppresses self-oscillation between power amplification units of the power amplifier (the electrode group and the heterostructure layer constitute the power amplification unit), thereby improving the stability between gate fingers of the power amplifier.

[0023] In some embodiments of the first aspect, the resistance of the region where the first conductive layer faces the third insulating portion is in the range of 2 to 10Ω. This configuration can suppress self-oscillation between power amplification units of the power amplifier while reducing link gain loss.

[0024] In some embodiments of the first aspect, the distance between the gate and the drain is greater than the distance between the gate and the source. This configuration can improve the gate control capability of the power amplifier and reduce the on-resistance in low-voltage application scenarios.

[0025] In a second aspect, an embodiment of the present application provides a power amplifier link, comprising an input end, an output end, and the power amplifier in the first aspect, wherein the gate of the power amplifier is connected to the input end through an input matching circuit, and the drain of the power amplifier is connected to the output end through an output matching circuit.

[0026] The beneficial effects of the power amplifier link in the embodiment of the present application are the same as the beneficial effects of the power amplifier in the first aspect, and will not be repeated here.

[0027] In some embodiments of the second aspect, a first stabilization circuit is provided between the input matching circuit and the gate, and the first stabilization circuit includes a first resistor and a first capacitor connected in parallel. With this arrangement, the first resistor can dissipate power from the input signal of the power amplifier chain, and the first capacitor can filter out low-frequency oscillations, thereby further improving the stability of the power amplifier.

[0028] In some embodiments of the second aspect, the gate is grounded via a second stabilization circuit, the second stabilization circuit comprising a second resistor and a second capacitor connected in series, the second resistor being electrically connected to the gate, and the second capacitor being grounded. With this arrangement, the second resistor can increase the loss of the gate series impedance of the power amplifier, thereby further improving the stability of the power amplifier. The second capacitor can isolate the DC signal, preventing the DC signal from being directly connected to the ground circuit and causing a short circuit.

[0029] In some embodiments of the second aspect, the gate is electrically connected to the drain via a third stabilization circuit, the third stabilization circuit comprising a third resistor and a third capacitor connected in series, the third resistor being electrically connected to the gate, and the third capacitor being electrically connected to the drain. With this arrangement, the third resistor reduces the negative impedance of the power amplifier by lowering the low-frequency power gain, thereby improving the stability of the power amplifier. The third capacitor and the third resistor are connected in series to form a negative feedback network, thereby improving radio frequency performance.

[0030] In some embodiments of the second aspect, there are multiple power amplifiers, the gate of each power amplifier is connected to the input matching circuit via a first line, and the drain of each power amplifier is connected to the output matching circuit via a second line; a fourth resistor is connected between two adjacent first lines. With this arrangement, the fourth resistor can suppress odd-mode oscillations on the input side of two adjacent power amplifiers.

[0031] In some embodiments of the second aspect, there are multiple power amplifiers, the gate of each power amplifier is connected to the input matching circuit via a first line, and the drain of each power amplifier is connected to the output matching circuit via a second line; a fifth resistor is connected between two adjacent second lines. With this arrangement, the fifth resistor can suppress odd-mode oscillations on the output side of two adjacent power amplifiers.

[0032] In a third aspect, an embodiment of the present application provides a radio frequency front-end circuit, comprising a first connection end, a second connection end, an antenna connection end, a radio frequency switch, a duplexer, a low-noise amplifier, and the power amplifier link in the second aspect; the input end of the power amplifier link is electrically connected to the first connection end, the output end of the power amplifier link is electrically connected to the duplexer, the low-noise amplifier is connected between the second connection end and the duplexer, the radio frequency switch is connected between the duplexer and the antenna connection end, and the antenna connection end is used to be electrically connected to the antenna.

[0033] The beneficial effects of the RF front-end circuit in the embodiment of the present application are the same as the beneficial effects of the power amplifier in the first aspect, and will not be repeated here.

[0034] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a processor, an antenna, and the RF front-end circuit in the third aspect, wherein the first connection end and the second connection end of the RF front-end circuit are both electrically connected to the processor, and the antenna connection end of the RF front-end circuit is electrically connected to the antenna.

[0035] The beneficial effects of the electronic device in the embodiment of the present application are the same as the beneficial effects of the power amplifier in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a schematic diagram of the active region structure of a power amplifier in the related art;

[0037] FIG2 is a schematic diagram of a coupling path formed by the input and output ends of the power amplifier in FIG1 ;

[0038] FIG3 is a schematic diagram of the arrangement of electrodes of the power amplifier in the first embodiment of the present application;

[0039] FIG4 is a cross-sectional view taken along line AA of the power amplifier in FIG3 ;

[0040] FIG5 is a BB cross-sectional view of the power amplifier in FIG3 ;

[0041] FIG6 is a schematic diagram of another configuration of the source and drain of the power amplifier in the first embodiment of the present application;

[0042] FIG7 is a schematic diagram showing the arrangement of electrodes of a power amplifier in a second embodiment of the present application;

[0043] FIG8 a is a PP cross-sectional view of the power amplifier in FIG7 ;

[0044] FIG8 b is a QQ cross-sectional view of the power amplifier in FIG7 ;

[0045] FIG9 is a schematic diagram of the electrode arrangement of the power amplifier in the third embodiment of the present application;

[0046] FIG10 is a schematic diagram showing a stability comparison between a power amplifier with a single gate finger and a power amplifier with multiple gate fingers in an embodiment of the present application;

[0047] FIG11 is a simulation diagram of a power amplifier cell with multiple gate fingers according to an embodiment of the present application;

[0048] FIG12 is a schematic diagram of the electrode arrangement of a power amplifier in a fourth embodiment of the present application;

[0049] FIG13 is a CC cross-sectional view of the power amplifier shown in FIG12 ;

[0050] FIG14 is a DD cross-sectional view of the power amplifier in FIG12 ;

[0051] FIG15 is a cross-sectional view of the power amplifier EE in FIG12;

[0052] FIG16 is a schematic diagram of the electrode arrangement of a power amplifier in a fifth embodiment of the present application;

[0053] FIG17 is a schematic diagram showing the principle of the connection circuits between the power amplification units of the power amplifier of FIG16;

[0054] FIG18 is a FF cross-sectional view of the power amplifier in FIG16 ;

[0055] FIG19 is a stability simulation diagram of the power amplifier in FIG16 ;

[0056] FIG20 is a comparison diagram of the gain-frequency curves of the power amplifier in FIG16 and a power amplifier without a stabilizing resistor;

[0057] FIG21 is a schematic diagram of a power amplifier link in the first embodiment of the present application;

[0058] FIG22 is a schematic diagram of a power amplifier link in a second embodiment of the present application;

[0059] FIG23 is a schematic diagram of a power amplifier link in a third embodiment of the present application;

[0060] FIG24 is a schematic diagram of a power amplifier link in a fourth embodiment of the present application;

[0061] FIG25 is a schematic diagram of a power amplifier link in a fifth embodiment of the present application;

[0062] FIG26 is a schematic diagram of a power amplifier link in FIG25 according to a sixth embodiment of the present application;

[0063] FIG27 is a schematic diagram of an electronic device in some embodiments of the present application. DETAILED DESCRIPTION

[0064] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0065] The power amplifier is a very important component of electronic equipment. Its main function is to amplify the power of the input signal to obtain a high-power output signal.

[0066] Power amplifiers can be divided into first-generation transistor power amplifiers, second-generation transistor power amplifiers, and third-generation transistor power amplifiers. The main advantages of first-generation transistor power amplifiers, which use Si as the main material, are low price and easy availability. However, their disadvantages are low power density, susceptibility to electric shock, and low voltage resistance, which limit their application in certain areas. Second-generation transistor power amplifiers, which use GaAs and InP as the main materials, have higher mobility and wider bandgap compared to first-generation crystal power amplifier materials. Third-generation transistor power amplifiers, which use GaN and SiC as the main materials, have higher power density, higher electron mobility, and better switching characteristics compared to second-generation power amplifier materials. They are currently widely used in RF systems of electronic equipment.

[0067] During the power amplifier design process, there are many issues that must be addressed, such as self-oscillation. Self-oscillation refers to the phenomenon in which a circuit generates and maintains a periodic signal at an unstimulated frequency. Self-oscillation typically occurs when the circuit loop becomes unstable, causing oscillation at a certain frequency. Therefore, self-oscillation is also called stability or oscillation.

[0068] Power amplifiers, as high-frequency, high-gain, and high-power devices, are the circuit modules most prone to self-excitation in RF systems. Especially in high-power amplifiers, some self-excitation can generate uncontrollable high power and current, potentially damaging the amplifier and causing robustness issues. Even if some self-excitation is mild and does not damage the device, these spurious signals can still degrade the RF system's transmit and receive performance. Therefore, self-excitation requires close attention and avoidance in design and application.

[0069] As shown in Figure 1, the active region structure of a power amplifier in the related art is schematically illustrated. This power amplifier is a high electron mobility transistor power amplifier (GaN HEMT PA), manufactured using an advanced GaN HEMT process, and can provide high power density and high linearity. The power amplifier includes a substrate layer 01, a buffer layer 02 disposed on substrate layer 01, and a barrier layer 03 disposed on buffer layer 02. Buffer layer 02 is a GaN layer, and barrier layer 03 is an AlGaN layer. The buffer layer 02 and barrier layer 03 form an AlGaN / GaN heterojunction.

[0070] The barrier layer 03 is provided with a gate 04 (G), a source 05 (S), and a drain 06 (D). The gate 04 is arranged between the source 05 and the drain 06, and the gate 04 forms a Schottky contact with the barrier layer 03. Since the AlGaN material has a wider band gap than the GaN material, when reaching equilibrium, the energy band at the junction of the heterojunction interface bends, resulting in discontinuity between the conduction band and the valence band, forming a triangular potential well at the heterojunction interface. As can be seen from Figure 1, on the GaN side, the bottom of the conduction band E C It is already below the Fermi level E F , so a large number of electrons accumulate in the triangular potential well. At the same time, the high potential barrier on the wide-bandgap AlGaN side makes it difficult for electrons to cross the potential well. Electrons are restricted to lateral movement in a thin layer at the interface, which is called a two-dimensional electron gas (2DEG). The drain-source voltage of the power amplifier generates a transverse electric field in the channel. Under the action of the transverse electric field, the two-dimensional electron gas is transported along the heterojunction interface to form the drain 06 output current. The depth of the potential well in the AlGaN / GaN heterojunction is controlled by the gate 04 voltage, which changes the size of the two-dimensional electron gas surface density in the channel, thereby controlling the drain 06 output current in the channel.

[0071] As shown in Figures 1 and 2, Figure 2 is a schematic diagram of the coupling path formed by the input and output terminals of the power amplifier in Figure 1. When designing a high electron mobility transistor power amplifier, for low-voltage applications, in order to improve gate control capability and reduce on-resistance, at least one of the distance Lgd between the gate 04 and the drain 06 and the thickness Tb of the barrier layer 03 is generally reduced. However, reducing the distance Lgd between the gate 04 and the drain 06 will increase the parasitic capacitance Cgd1 between the gate 04 and the drain 06; reducing the thickness Tb of the barrier layer 03 will increase the parasitic capacitance Cgd2 between the gate 04 and the heterojunction interface, thereby increasing the parasitic capacitance Cgd between the gate and the drain = Cgd1 + Cgd2. The increase in the parasitic capacitance Cgd between the gate and the drain easily causes a coupling path between the input end (i.e., the gate 04) and the output end (i.e., the drain 06) of the power amplifier (as shown by the dotted arrow in Figure 2). When the phase and amplitude meet the requirements of in-phase amplification at a certain frequency point (such as 9GHz), the stability of the power amplifier is poor, and self-excitation will occur.

[0072] To this end, the present application provides a power amplifier, a power amplifier link, a radio frequency front-end circuit and an electronic device. By making a part of the gate of the power amplifier into a stabilizing resistor, and connecting the stabilizing resistor in series with other parts of the gate, the stabilizing resistor can suppress the self-oscillation of the power amplifier, thereby improving the stability of the power amplifier.

[0073] As shown in Figures 3 to 5, Figure 3 is a schematic diagram of the electrode arrangement of the power amplifier in the first embodiment of the present application, Figure 4 is a cross-sectional view taken along line AA of the power amplifier in Figure 3, and Figure 5 is a cross-sectional view taken along line BB of the power amplifier in Figure 3. The power amplifier may be a high electron mobility transistor power amplifier, but is not limited thereto and may also be other types of power amplifiers, such as a second-generation transistor power amplifier using GaAs or InP as primary materials.

[0074] The power amplifier includes a substrate layer 1, a heterostructure layer 2 disposed on the substrate layer 1, and a gate 3, a source 4, and a drain 5 disposed on the heterostructure layer 2. The heterostructure layer 2 includes a buffer layer 21 disposed on the substrate layer 1 and a barrier layer 22 disposed on the buffer layer 21. The gate 3 is disposed on the barrier layer 22 and includes gate fingers 31. The source 4 and the drain 5 are disposed on opposite sides of the gate fingers 31.

[0075] The gate finger 31 is a strip-shaped structure. As shown in FIG. 4 , the gate finger 31 may be a straight strip-shaped structure. However, the present invention is not limited thereto. The gate finger 31 may also be a strip-shaped structure with a certain curvature.

[0076] The substrate layer 1 may be a Si substrate layer, a SiC substrate layer, a sapphire substrate layer, a GaN substrate layer, a diamond substrate layer, a glass substrate layer, or a composite substrate layer thereof, without specific limitation herein. The barrier layer 22 may be an AlGaN layer, and the buffer layer 21 may be a GaN layer, with the barrier layer 22 and the buffer layer 21 forming an AlGaN / GaN heterojunction. However, the barrier layer 22 may also be a GaAlAs layer, and the buffer layer 21 may be a GaAs layer, with the barrier layer 22 and the buffer layer 21 forming a GaAlAs / GaAs heterojunction.

[0077] The source 4 and drain 5 can be arranged on the heterostructure layer 2 in various ways. In some embodiments, as shown in FIG4 , the source 4 and drain 5 are both arranged on the barrier layer 22. In other embodiments, as shown in FIG6 , which is a schematic diagram of another arrangement of the source 4 and drain 5 of the power amplifier in the first embodiment of the present application, the source 4 and drain 5 are both arranged on the buffer layer 21, with the barrier layer 22 arranged between the source 4 and drain 5.

[0078] As shown in Figures 4 to 6, the gate finger 31 includes a first conductive layer 32 and a second conductive layer 33 that are stacked. The square resistance (i.e., sheet resistance) of the first conductive layer 32 is greater than the square resistance of the second conductive layer 33. As shown in Figure 5, a first insulating portion 311 is provided on the gate finger 31. Along the extension direction Y of the gate finger 31, the first insulating portion 311 disconnects the second conductive layer 33, and the second conductive layers 33 located on both sides of the first insulating portion 311 are electrically connected through the first conductive layer 32.

[0079] As shown in FIG5 , the first insulating portion 311 may be a gap filled with an insulating medium. The insulating medium may be air or an insulating material such as SiN, which is not specifically limited here.

[0080] In the power amplifier of the embodiment of the present application, since the square resistance of the first conductive layer 32 is greater than the square resistance of the second conductive layer 33, the second conductive layers 33 on both sides of the first insulating portion 311 are electrically connected through the first conductive layer 32. Therefore, when the power amplifier is in operation, the signal transmitted on the gate finger 31 first enters the area of ​​the first conductive layer 32 opposite to the first insulating portion 311 from the second conductive layer 33 on one side of the first insulating portion 311 (this area is referred to as the first resistance area 321 herein, and the orthographic projection of the first resistance area 321 on the substrate layer 1 overlaps with the orthographic projection of the first insulating portion 311 on the substrate layer 1), and then enters the other side of the first insulating portion 311 from the first resistance area 321 of the first conductive layer 32. The second conductive layer 33 on one side (because the signal is transmitted along the path with lower resistance on the gate finger 31), the first resistance region 321 of the first conductive layer 32 serves as an intermediate electrical connection. Since the sheet resistance of the first conductive layer 32 is relatively large, the first resistance region 321 of the first conductive layer 32 is equivalent to a stable resistor connected in series with the second conductive layers 33 on both sides of the first insulating portion 311. When the power amplifier is operating, the first resistance region 321 of the first conductive layer 32 can consume the signal energy on the coupling path between the gate 3 and the drain 5 of the power amplifier to weaken the strength of the signal on the coupling path, thereby suppressing the self-oscillation of the power amplifier and improving the stability of the power amplifier.

[0081] In addition, a portion of the gate finger 31 is made into a stabilizing resistor, so that the stabilizing resistor does not need to occupy space outside the gate finger 31, so that the stabilizing resistor occupies less space, thereby making the structure of the power amplifier more compact; and without increasing the complexity of the process, the compatibility of the resistor manufacturing process and the electrode manufacturing process is achieved (the resistors in the related art are generally manufactured using a thin film resistor process, and their physical size is relatively difficult to reduce, and they are not compatible with the electrode manufacturing process of the power amplifier).

[0082] The positional relationship between the first conductive layer 32, the second conductive layer 33, and the barrier layer 22 is not unique. In some embodiments, as shown in Figures 4 and 6, the first conductive layer 32 is disposed between the barrier layer 22 and the second conductive layer 33. The first conductive layer 32 is a metal layer or an alloy layer and contacts the barrier layer 22 to form a Schottky gate structure, that is, the first conductive layer 32 forms a Schottky contact with the barrier layer 22. Based on the characteristics of the Schottky contact, the material of the first conductive layer needs to be a metal material or alloy material with a suitable work function, typically a metal material or alloy material with a relatively high resistivity. The use of a metal material or alloy material with a relatively high resistivity can increase the resistance of the first conductive layer 32 per unit length. In this way, when the designed resistance of the first resistance region 321 of the first conductive layer 32 is constant, the length of the first resistance region 321 (that is, the dimension in the gate finger extension direction Y) can be reduced, thereby reducing the size of the first insulating portion 311, thereby facilitating the optimized layout of the power amplifier gate 3.

[0083] Of course, the positional relationship between the first conductive layer 32, the second conductive layer 33, and the barrier layer 22 is not limited to the structures shown in Figures 4 and 6. In other embodiments, as shown in Figures 7, 8a, and 8b, Figure 7 is a schematic diagram of the electrode arrangement of the power amplifier in the second embodiment of the present application, Figure 8a is a PP cross-sectional view of the power amplifier in Figure 7, and Figure 8b is a QQ cross-sectional view of the power amplifier in Figure 7. A gate insulating layer 7 is stacked on the barrier layer 22, and the gate fingers 31 are disposed on the gate insulating layer 7 to form an insulated gate structure; the second conductive layer 33 is disposed between the gate insulating layer 7 and the first conductive layer 32, and the first conductive layer 32 covers the first insulating portion 311.

[0084] There are many ways to achieve that the square resistance of the first conductive layer 32 is greater than the square resistance of the second conductive layer 33. For example, in some embodiments, as shown in Figures 5 and 7, the thickness of the first conductive layer 32 is less than the thickness of the second conductive layer 33.

[0085] By adjusting the thickness relationship between the first conductive layer 32 and the second conductive layer 33, the square resistance of the first conductive layer 32 is greater than that of the second conductive layer 33. This allows the square resistance of the first conductive layer 32 and the second conductive layer 33 to be precisely adjusted to target values ​​according to the different requirements of the power amplifier, thereby increasing the applicability of the manufacturing process and thus helping to reduce the manufacturing cost of the power amplifier. In other embodiments, the thickness of the first conductive layer 32 is equal to the thickness of the second conductive layer 33, and the resistivity of the first conductive layer 32 is greater than the resistivity of the second conductive layer 33.

[0086] As shown in Figures 4 to 6, the thickness of the first conductive layer 32 should not be too large or too small. If the thickness of the first conductive layer 32 is too large, the sheet resistance of the first conductive layer 32 is too small. This, when the designed resistance value of the first resistance region 321 of the first conductive layer 32 is fixed, is not conducive to reducing the size of the first resistance region 321 of the first conductive layer 32. If the thickness of the first conductive layer 32 is too small, the sheet resistance of the first conductive layer 32 is too large. When the size of the first resistance region 321 of the first conductive layer 32 is fixed, the resistance value of the first resistance region 321 of the first conductive layer 32 is too large, which is not conducive to reducing the loss of the gate finger 31. Research has found that when the thickness of the first conductive layer 32 is in the range of 20 to 300 nm, the size of the first resistance region 321 of the first conductive layer 32 can be reduced while controlling the RF loss of the gate finger 31.

[0087] As shown in Figures 4 to 6, the thickness of the second conductive layer 33 should not be too large or too small. If the thickness of the second conductive layer 33 is too large, the second conductive layer 33 occupies a large space, which is not conducive to the optimized layout of the electrodes around the gate fingers 31. If the thickness of the second conductive layer 33 is too small, the square resistance of the second conductive layer 33 is too large. When the length of the gate finger 31 is constant, the resistance of the second conductive layer 33 is large, which is not conducive to reducing the loss of the gate finger 31. Research has found that when the thickness of the second conductive layer 33 ranges from 50 to 1000 nm, it can both reduce the space occupied by the second conductive layer 33 and control the loss of the gate finger 31.

[0088] In some embodiments, as shown in Figures 4 to 6, the square resistance of the first conductive layer 32 ranges from 200 to 400 mΩ / sq. This configuration can prevent the square resistance of the first conductive layer 32 from being too large or too small, thereby reducing the size of the first resistance region 321 of the first conductive layer 32 and controlling the wear of the gate finger 31 from being too large.

[0089] In some embodiments, as shown in FIG. 4 to FIG. 6 , the square resistance of the gate finger 31 ranges from 20 to 50 mΩ / sq. This configuration can prevent the square resistance of the gate finger 31 from being too large or too small, thereby controlling the wear of the gate finger 31 from being too large and reducing the difficulty of the manufacturing process (designing the square resistance of the gate finger 31 to be too small increases the difficulty of the process).

[0090] In some embodiments, as shown in Figures 4 to 6 , the resistance of the first resistive region 321 of the first conductive layer 32 ranges from 2 to 10Ω. This configuration prevents the resistance of the first resistive region 321 of the first conductive layer 32 from being too high or too low, thereby limiting the loss of gate finger 31 and reducing link gain. It also effectively dissipates more signal energy in the coupling path between the gate 3 and drain 5 of the power amplifier, thereby suppressing self-oscillation of the power amplifier.

[0091] In some embodiments, as shown in Figures 4 to 6, the first conductive layer 32 and the second conductive layer 33 both include multiple metal layers stacked together, and the multiple metal layers of the first conductive layer 32 are a group selected from the group consisting of: W layer / Ti layer, W layer / Pt layer, W layer / Au layer, Ni layer / Ti layer, Ni layer / Pt layer, Ni layer / Au layer, W layer / Ti layer / Au layer, Ni layer / Pt layer / Au layer, and W layer / Pt layer / Au layer.

[0092] The multiple metal layers of the second conductive layer 33 are a group selected from the group consisting of Ni layer / Au layer, Ni layer / Pt layer / Au layer, Ni layer / Pt layer / Au layer / Ti layer, Ti layer / Au layer, Ti layer / Pt layer / Au layer, and Ti layer / Pt layer / Au layer / Ti layer.

[0093] Among them, it is necessary to understand that: in the metal layer combination: a layer / b layer / c layer..., from left to right represents the stacking order of the metal layers, that is, b layer is arranged on a layer, c layer is arranged on b layer,...; for example, W layer / Pt layer / Au layer means: the Pt layer is arranged on the W layer, and the Au layer is arranged on the Pt layer; for another example, Ti layer / Pt layer / Au layer / Ti layer means: the Pt layer is arranged on the Ti layer, the Au layer is arranged on the Pt layer, and the Ti layer is arranged on the Au layer, and there are two Ti layers in this combination.

[0094] In this embodiment, since the second conductive layer 33 is arranged on the first conductive layer 32, and the metal layer closest to the first conductive layer 32 in the second conductive layer 33 is a Ni layer or a Ti layer, this can improve the adhesion between the first conductive layer 32 and the second conductive layer 33 (the Ni layer or the Ti layer can increase the adhesion with other metal layers), thereby making the connection between the first conductive layer 32 and the second conductive layer 33 more firm.

[0095] In some embodiments, as shown in Figure 4, the distance between the gate 3 and the drain 5 is greater than the distance between the gate 3 and the source 4. This arrangement can improve the gate control capability of the power amplifier and reduce the on-resistance in low-voltage application scenarios.

[0096] A power amplifier typically has lower power under low-voltage applications than under high-voltage applications. To increase the power of a power amplifier, in some embodiments, as shown in FIG9 , which is a schematic diagram of the electrode arrangement of a power amplifier in the third embodiment of the present application, there are multiple gate fingers 31, with adjacent gate fingers 31 spaced apart. A source 4 and a drain 5 are provided on opposite sides of each gate finger 31, respectively. By increasing the number of gate fingers 31, the power of the power amplifier can be increased, achieving high-power synthesis of the power amplifier, thereby meeting the circuit's design requirements for the power amplifier's power level.

[0097] As shown in FIG9 , the number of gate fingers 31 may be 8, but is not limited thereto. The number of gate fingers 31 may also be 4, 5, 6, 7, 9, etc., depending on the design requirements of the circuit for the power amplifier power level.

[0098] As shown in Figures 10 and 11, Figure 10 is a schematic diagram comparing the stability of a power amplifier with a single gate finger 31 and a power amplifier with multiple gate fingers 31 in an embodiment of the present application, and Figure 11 is a simulation diagram of a power amplifier cell with multiple gate fingers 31 in an embodiment of the present application. Because the amplitude and phase of a power amplifier composed of a single gate finger 31 do not meet the in-phase amplification condition, as shown in Figure 10(a), the single-gate finger 31 power amplifier is relatively stable and less prone to self-excitation. However, when a power amplifier composed of multiple gate fingers 31, for example, an eight-gate finger 31 power amplifier, meets the in-phase amplification condition at a certain frequency (m1 = 3.54 GHz), as shown in Figure 10(b), instability factors are likely to occur at this frequency. For example, the loop between different gate fingers 31 is prone to oscillation (i.e., odd-mode oscillation), thereby reducing the stability of the multi-gate finger 31 power amplifier. Figure 11 illustrates that in the tube cell model of a power amplifier, a power amplifier with a single gate finger 31 has no frequency at which self-oscillation occurs. However, a power amplifier with multiple gate fingers 31 will inevitably self-oscillate at a specific frequency, with a phase difference of 0 and a non-zero amplitude. This demonstrates that, compared to a power amplifier with a single gate finger 31, a power amplifier with multiple gate fingers 31 is more susceptible to stability issues at certain frequencies.

[0099] To address the stability issues of a power amplifier with multiple gate fingers 31, in some embodiments, as shown in Figures 12 and 13 (Figure 12 is a schematic diagram of the electrode arrangement of a power amplifier in a fourth embodiment of the present application, and Figure 13 is a CC cross-sectional view of the power amplifier shown in Figure 12), the gate 3 further includes a first trace 34, which is connected to each gate finger 31. The first trace 34 includes a first conductive layer 32 and a second conductive layer 33. A second insulating portion 341 is provided on the first trace 34 between two adjacent gate fingers 31. Along the extension direction X of the first trace 34, the second insulating portion 341 disconnects the second conductive layer 33, and the second conductive layers 33 on both sides of the second insulating portion 341 are electrically connected through the first conductive layer 32.

[0100] With this arrangement, the region of the first conductive layer 32 opposing the second insulating portion 341 (referred to herein as the second resistance region 322, where the orthographic projection of the second resistance region 322 on the substrate layer 1 overlaps with the orthographic projection of the second insulating portion 341 on the substrate layer 1) acts as a stabilizing resistor connected in series with the second conductive layer 33 on both sides of the second insulating portion 341. During operation of the power amplifier, the second resistance region 322 of the first conductive layer 32 dissipates the energy of the oscillating signal between the gate fingers 31, thereby weakening the intensity of the oscillating signal between the gate fingers 31 and improving the stability of the power amplifier gate fingers 31. Furthermore, by forming a portion of the first trace 34 into a stabilizing resistor, the stabilizing resistor no longer occupies space outside the first trace 34, thereby making the power amplifier structure more compact.

[0101] As shown in FIG12 , the first routing line 34 includes a plurality of connecting segments, each connecting segment electrically connecting two corresponding adjacent gate fingers 31, and the second insulating portion 341 can be respectively provided on each connecting segment; the second insulating portion 341 can also be respectively provided on a portion of the connecting segments. For example, as shown in FIG12 , the gate 3 has six gate fingers 31, and the first routing line 34 has five connecting segments, each connecting segment is respectively connected between two corresponding gate fingers 31, one of the connecting segments is connected to the gate lead 35, and the remaining four connecting segments are all provided with the second insulating portion 341.

[0102] In some embodiments, as shown in FIG13 , the second insulating portion 341 may be a gap filled with an insulating medium. The insulating medium may be air or an insulating material such as SiN, which is not specifically limited here.

[0103] In some embodiments, as shown in FIG13 , the resistance of the second resistance region 322 of the first conductive layer 32 ranges from 2 to 10Ω. This configuration prevents the resistance of the second resistance region 322 of the first conductive layer 32 from being too high or too low, thereby controlling the power consumption of the gate fingers 31 and reducing the gain loss of the link. It also effectively dissipates the energy of the oscillation signal between the gate fingers 31, thereby improving the stability of the gate fingers 31 of the power amplifier.

[0104] In some embodiments, as shown in Figures 12 and 14 , Figure 14 is a cross-sectional view of the power amplifier in Figure 12 . The source 4 includes sub-source electrodes 41, and the drain 5 includes sub-drain electrodes 51. The sub-source electrodes 41 and sub-drain electrodes 51 are arranged alternately, with gate fingers 31 disposed between adjacent sub-source electrodes 41 and sub-drain electrodes 51. The heterostructure layer 2, gate fingers 31, and the sub-drain electrodes 51 on either side thereof, along with the sub-source electrodes 41, constitute the cells of the power amplifier. Because the sub-source electrodes 41 and sub-drain electrodes 51 are arranged alternately, two adjacent cells can share a single sub-source electrode 41 or sub-drain electrode 51. This makes the cells of the power amplifier more compact, thereby improving the area utilization of the power amplifier.

[0105] In some embodiments, as shown in Figures 12, 14, and 15, Figure 15 is an EE cross-sectional view of the power amplifier in Figure 12. The source 4 and drain 5 are both disposed on the barrier layer 22; the source 4 further includes a first connecting portion 42 connected to each sub-source 41; the drain 5 further includes a second connecting portion 52 connected to each sub-drain 51; and the first connecting portion 42 is provided with a clearance opening 421 for circumventing the gate finger 31. As shown in Figure 12, the sub-source 41 and the sub-drain 51 are both strip-shaped structures, but this is not limited to this. The sub-source 41 and the sub-drain 51 can also be configured as other structures, such as a block structure, depending on actual conditions.

[0106] Since both the source 4 and drain 5 are disposed on the barrier layer 22, the source 4, drain 5, and gate 3 are disposed on the same layer, thereby reducing the manufacturing process difficulty of the source 4, drain 5, and gate 3, thereby reducing the manufacturing cost of the power amplifier. Since the first connecting portion 42 is provided with a clearance opening 421 for circumventing the gate finger 31, the gate finger 31 can extend outside the first connecting portion 42 through the clearance opening 421, thereby facilitating connection between the gate finger 31 and the gate lead 35 located outside the first connecting portion 42.

[0107] 15 , the avoidance opening 421 is filled with an insulating medium to separate the gate finger 31 from the first connection portion 42. The insulating medium may be a SiN layer, etc., which is not specifically limited here.

[0108] To further increase the power of the power amplifier, in some embodiments, as shown in FIG12 , the gate 3, source 4, and drain 5 form an electrode group 6, and there are multiple electrode groups 6. The electrode group 6 and the heterostructure layer 2 can be considered a power amplifier unit. Providing multiple electrode groups 6 is equivalent to increasing the number of power amplifier units, thereby further increasing the power of the power amplifier and better meeting the circuit's design requirements for the power amplifier's power level.

[0109] As shown in FIG12 , the number of electrode groups 6 is two, but it is not limited thereto. The number of electrode groups 6 may also be three or more.

[0110] When a power amplifier has multiple power amplifying units, odd-mode oscillation is likely to occur between two adjacent power amplifying units. To address this issue, in some embodiments, as shown in Figures 16, 17, and 18, Figure 16 is a schematic diagram of the electrode arrangement of the power amplifier in the fifth embodiment of the present application, Figure 17 is a schematic diagram of the principle of the connection circuit between the power amplifying units of the power amplifier in Figure 16, and Figure 18 is a FF cross-sectional view of the power amplifier in Figure 16. The gates 3 of two adjacent electrode groups 6 are connected via a second trace 36; the second trace 36 includes a first conductive layer 32 and a second conductive layer 33. A third insulating portion 361 is provided on the second trace 36. Along the extension direction X of the second trace 36, the third insulating portion 361 disconnects the second conductive layer 33. The second conductive layers 33 on both sides of the third insulating portion 361 are electrically connected via the first conductive layer 32.

[0111] With this arrangement, the region of the first conductive layer 32 opposing the third insulating portion 361 (referred to herein as the third resistor region 323, where the orthographic projection of the third resistor region 323 on the substrate layer 1 overlaps with the orthographic projection of the third insulating portion 361 on the substrate layer 1) acts as a stabilizing resistor connected in series between the gates 3 of two adjacent electrode groups 6 (as shown in FIG17 ). During operation of the power amplifier, the third resistor region 323 of the first conductive layer 32 can dissipate the energy of the odd-mode oscillation signal between the power amplifier units, thereby reducing the intensity of the odd-mode oscillation signal between the power amplifier units and improving the stability of the power amplifier between the power amplifier units. Furthermore, by forming a portion of the second trace 36 into a stabilizing resistor, the stabilizing resistor no longer occupies space outside the second trace 36, thereby making the power amplifier structure more compact.

[0112] In some embodiments, as shown in FIG18 , the third insulating portion 361 may be a gap filled with an insulating medium. The insulating medium may be air or an insulating material such as SiN, which is not specifically limited here.

[0113] In some embodiments, as shown in FIG18 , the resistance of the third resistance region 323 of the first conductive layer 32 ranges from 2 to 10Ω. This configuration prevents the resistance of the third resistance region 323 of the first conductive layer 32 from being too high or too low, thereby controlling the power consumption of the gate finger 31 and reducing the gain loss of the link. Furthermore, it effectively dissipates the energy of the odd-mode oscillation signal between the power amplification units of the power amplifier, thereby improving the stability between the power amplification units of the power amplifier.

[0114] In some embodiments, as shown in Figure 16, the number of electrode groups 6 is 2, and in each electrode group 6, the number of gate fingers 31 is 6, the width of the gate finger 31 is 150μm, the resistance of the first resistance region 321 of the first conductive layer 32 is 3Ω, the resistance of the second resistance region 322 of the first conductive layer 32 is 3Ω, and the resistance of the third resistance region 323 of the first conductive layer 32 is 2Ω; the first conductive layer 32 includes three stacked metal layers, the three metal layers are Ni layer / Pt layer / Au layer, and the thickness of the first conductive layer 32 is 100nm, the second conductive layer 33 includes three stacked metal layers, the three metal layers are Ti layer / Pt layer / Au layer, and the thickness of the second conductive layer 33 is 600nm.

[0115] Figure 19 is a stability simulation diagram of the power amplifier in Figure 16, and Figure 20 is a comparison diagram of the gain-frequency curves of the power amplifier in Figure 16 and a power amplifier without a stabilizing resistor. As can be seen from Figure 19, there is no frequency point in the stability circle of the power amplifier where the phase and amplitude are in phase, which indicates that the stability of the power amplifier is good. As shown in Figure 20, the thick line in Figure 20 represents the gain variation with frequency curve of the power amplifier without a stabilizing resistor, and the thin line represents the gain variation with frequency curve of the power amplifier in the fifth embodiment of the present application. As can be seen from Figure 20, the gain of the power amplifier in the fifth embodiment of the present application does not drop significantly in the Sub6G frequency band.

[0116] In some embodiments, as shown in Figures 16 and 18, the manufacturing process of the power amplifier is as follows: S1, stacking a buffer layer 21 and a barrier layer 22 in sequence on the substrate layer 1; S2, forming a first conductive layer 32 on the barrier layer 22 through a first mask plate; S3, forming a second conductive layer 33 on the first conductive layer 32 through a second mask plate; S4, removing a preset area of ​​the second conductive layer 33 through an etching process to form a first insulating portion 311, a second insulating portion 341, and a third insulating portion 361.

[0117] FIG21 is a schematic diagram of a power amplifier chain 300 according to the first embodiment of the present application. As shown in FIG21 , the power amplifier chain 300 includes an input terminal P1, an output terminal P2, and a power amplifier 100 as described in any of the above embodiments. The gate 3 of the power amplifier 100 is connected to the input terminal P1 via an input matching circuit 210, and the drain 5 of the power amplifier 100 is connected to the output terminal P2 via an output matching circuit 220.

[0118] As shown in FIG21 , the source 4 of the power amplifier 100 is grounded, and the drain 5 of the power amplifier 100 is also connected to a voltage source (Vdd).

[0119] In some embodiments, as shown in FIG22 , FIG22 is a schematic diagram of a power amplifier chain 300 in a second embodiment of the present application. A first stabilization circuit 230 is provided between the input matching circuit 210 and the gate 3. The first stabilization circuit 230 includes a first resistor R1 and a first capacitor C1 connected in parallel. With this configuration, the first resistor R1 can dissipate the power of the input signal of the power amplifier chain 300, thereby effectively preventing self-oscillation caused by the negative input impedance of the power amplifier 100 when the input signal is a low-frequency signal. By providing the first capacitor C1, the first capacitor C1 can filter out oscillations generated by low frequencies, thereby further improving the stability of the power amplifier 100.

[0120] In some embodiments, as shown in FIG23 , FIG23 is a schematic diagram of a power amplifier link 300 in the third embodiment of the present application. The gate 3 is grounded through a second stabilization circuit 240. The second stabilization circuit 240 includes a second resistor R2 and a second capacitor C2 connected in series. The second resistor R2 is electrically connected to the gate 3, and the second capacitor C2 is grounded. In this way, the second resistor R2 can increase the loss of the series impedance of the gate 3 of the power amplifier 100, thereby effectively preventing the self-oscillation caused by the negative input impedance of the RF power tube core at high frequencies, thereby further improving the stability of the power amplifier 100. By setting the second capacitor C2, the second capacitor C2 can isolate the DC signal and prevent the DC signal from being directly grounded through the second stabilization circuit 240 and causing a short circuit.

[0121] As shown in FIG. 23 , the second resistor R2 is connected between the input matching circuit 210 and the gate 3 of the power amplifier 100 .

[0122] In some embodiments, as shown in FIG24 , FIG24 is a schematic diagram of a power amplifier chain 300 in a fourth embodiment of the present application. The gate 3 is electrically connected to the drain 5 via a third stabilization circuit 250. The third stabilization circuit 250 includes a third resistor R3 and a third capacitor C3 connected in series. The third resistor R3 is electrically connected to the gate 3, and the third capacitor C3 is electrically connected to the drain 5. In this configuration, the third resistor R3 reduces the negative impedance of the power amplifier 100 by reducing the low-frequency power gain, thereby improving the stability of the power amplifier 100. By providing the third capacitor C3, the third capacitor C3 and the third resistor R3 are connected in series to form a negative feedback network. The negative feedback network is very effective for envelope distortion circuits caused by amplitude modulation with fast rising edges or high peak-to-average ratios, thereby improving RF performance.

[0123] As shown in FIG. 24 , the third resistor R3 is connected between the input matching circuit 210 and the gate 3 of the power amplifier 100 .

[0124] To increase the power of the power amplifier chain 300, in some embodiments, as shown in FIG25 , which is a schematic diagram of the power amplifier chain 300 according to the fifth embodiment of the present application, there are multiple power amplifiers 100, with the gate 3 of each power amplifier 100 connected to the input terminal P1 via an input matching circuit 210, and the drain 5 of each power amplifier 100 connected to the output terminal P2 via an output matching circuit 220.

[0125] As shown in FIG25 , the number of power amplifiers 100 is two, but it is not limited thereto. The number of power amplifiers 100 may also be three or more, depending on the actual situation.

[0126] In some embodiments, as shown in FIG25 , a bias circuit 260 is further connected between the gate 3 of each power amplifier 100 and the input matching circuit 210 . The bias circuit 260 is used to provide DC power to the power amplifier chain 300 .

[0127] In some embodiments, as shown in FIG25 , in a power amplifier chain 300 , the gate 3 of each power amplifier 100 is connected to the input terminal P1 via an input matching circuit 210 , and the drain 5 of each power amplifier 100 is connected to the output terminal P2 via an output matching circuit 220 .

[0128] In other embodiments, as shown in FIG26 , FIG26 is a schematic diagram of a power amplifier chain 300 according to the sixth embodiment of the present application, which is shown in FIG25 . In the power amplifier chain 300, the gates 3 of all power amplifiers 100 are connected to the input terminal P1 via an input matching circuit 210, and the drains 5 of all power amplifiers 100 are connected to the output terminal P2 via an output matching circuit 220.

[0129] In some embodiments, as shown in FIG26 , the gate 3 of each power amplifier 100 is connected to the input matching circuit 210 via a first line 270, and a fourth resistor R4 is connected between two adjacent first lines 270. With this arrangement, the fourth resistor R4 can suppress odd-mode oscillations on the input side of two adjacent power amplifiers 100.

[0130] In some embodiments, as shown in FIG26 , the drain 5 of each power amplifier 100 is connected to the output matching circuit 220 via a second line 280, and a fifth resistor R5 is connected between two adjacent second lines 280. With this arrangement, the fifth resistor R5 can suppress odd-mode oscillations on the output side of two adjacent power amplifiers 100.

[0131] Figure 27 is a schematic diagram of an electronic device in some embodiments of the present application. The electronic device can be a mobile phone, tablet computer, smart wearable device (such as a smart watch, wireless headphones), laptop computer, smart screen, wireless router, or other electronic device with wireless radio frequency communication function.

[0132] The electronic device includes a processor 400 , an antenna 500 , and a radio frequency front-end circuit 600 .

[0133] The RF front-end circuit 600 includes a first connection terminal P3, a second connection terminal P4, an antenna connection terminal P5, an RF switch 700, a duplexer 800, a low-noise amplifier 910, and the power amplifier chain 300 described in any of the above embodiments. The input terminal P1 of the power amplifier chain 300 is electrically connected to the first connection terminal P3, the output terminal P2 of the power amplifier chain 300 is electrically connected to the duplexer 800, the low-noise amplifier 910 is connected between the second connection terminal P4 and the duplexer 800, and the RF switch 700 is connected between the duplexer 800 and the antenna connection terminal P5. The first connection terminal P3 and the second connection terminal P4 of the RF front-end circuit 600 are both electrically connected to the processor 400, and the antenna connection terminal P5 of the RF front-end circuit 600 is electrically connected to the antenna 500.

[0134] The RF switch 700 switches between receiving and transmitting RF signals, or between different frequency bands. The duplexer 800 isolates the transmit and receive signals of the antenna 500, ensuring that both receive and transmit signals function properly while sharing the same antenna 500. The low-noise amplifier 910 reduces noise and amplifies the RF signal in the receive channel.

[0135] In some embodiments, as shown in Figure 27, the processor 400 can be a SOC (System on Chip), and the processor 400 includes a baseband processing unit 410, and a transceiver unit 420 electrically connected to the baseband processing unit 410, and the transceiver unit 420 is electrically connected to the first connection terminal P3 and the second connection terminal P4 of the RF front-end circuit 600.

[0136] In some embodiments, as shown in Figure 27, filters 920 are provided between the power amplifier chain 300 and the duplexer 800, and between the low noise amplifier 910 and the duplexer 800. The filters 920 are used to retain signals within a specific frequency band and filter out signals outside the specific frequency band.

[0137] The types of hatching in the drawings of this application are for the purpose of distinguishing different components and should not be understood as limiting the materials of the components. The drawings of this application are for the purpose of illustrating the structural composition and are not shown to scale with the actual product.

[0138] Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to these embodiments. On the contrary, the purpose of introducing the application in conjunction with the embodiments is to cover other options or modifications that may be extended based on the claims of this application. In order to provide a deep understanding of this application, the above description will contain many specific details. This application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.

[0139] In the embodiments of this application, the terms "first," "second," "third," "fourth," and "fifth" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first," "second," "third," "fourth," or "fifth" may explicitly or implicitly include one or more of the features.

[0140] In the embodiments of this application, "and / or" is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0141] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The directional terms mentioned in the embodiments of the present application, such as "up", "down", "left", "right", "inside", "outside", etc., are only reference to the directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. "Multiple" means at least two.

[0142] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power amplifier, characterized in that: The device comprises a substrate layer, a heterostructure layer provided on the substrate layer, and a gate, a source electrode and a drain electrode provided on the heterostructure layer; The heterostructure layer includes a buffer layer disposed on the substrate layer, and a barrier layer disposed on the buffer layer, the gate is disposed on the barrier layer, the gate includes gate fingers, and the source and the drain are respectively disposed on opposite sides of the gate fingers; The gate finger includes a first conductive layer and a second conductive layer stacked together, the square resistance of the first conductive layer is greater than the square resistance of the second conductive layer, and a first insulating portion is provided on the gate finger. Along the extension direction of the gate finger, the first insulating portion disconnects the second conductive layer, and the second conductive layers located on both sides of the first insulating portion are electrically connected through the first conductive layer.

2. The power amplifier according to claim 1, wherein: The first conductive layer is disposed between the barrier layer and the second conductive layer. The first conductive layer is a metal layer or an alloy layer and is in contact with the barrier layer.

3. The power amplifier according to claim 1 or 2, characterized in that: The thickness of the first conductive layer is smaller than the thickness of the second conductive layer.

4. The power amplifier according to claim 3, wherein: The thickness of the first conductive layer ranges from 20 to 300 nm, and the thickness of the second conductive layer ranges from 50 to 1000 nm.

5. The power amplifier according to any one of claims 1 to 4, characterized in that: The square resistance of the first conductive layer ranges from 200 to 400 mΩ / sq; the square resistance of the gate finger ranges from 20 to 50 mΩ / sq.

6. The power amplifier according to any one of claims 1 to 5, characterized in that: The resistance value of the region where the first conductive layer faces the first insulating portion is in a range of 2 to 10Ω.

7. The power amplifier according to any one of claims 2 to 6, characterized in that: The first conductive layer and the second conductive layer each include a plurality of metal layers stacked; The plurality of metal layers of the first conductive layer is a group consisting of: W layer / Ti layer, W layer / Pt layer, W layer / Au layer, Ni layer / Ti layer, Ni layer / Pt layer, Ni layer / Au layer, W layer / Ti layer / Au layer, Ni layer / Pt layer / Au layer, and W layer / Pt layer / Au layer; The multiple metal layers of the second conductive layer are a group selected from the group consisting of Ni layer / Au layer, Ni layer / Pt layer / Au layer, Ni layer / Pt layer / Au layer / Ti layer, Ti layer / Au layer, Ti layer / Pt layer / Au layer, and Ti layer / Pt layer / Au layer / Ti layer.

8. The power amplifier according to any one of claims 1 to 7, wherein: There are a plurality of gate fingers, and two adjacent gate fingers are spaced apart from each other. The source and the drain are respectively provided on two opposite sides of each gate finger.

9. The power amplifier according to claim 8, wherein: The gate further includes a first wiring connected to each of the gate fingers; The first routing line includes the first conductive layer and the second conductive layer. A second insulating portion is provided on the first routing line between two adjacent gate fingers. Along the extension direction of the first routing line, the second insulating portion disconnects the second conductive layer, and the second conductive layers located on both sides of the second insulating portion are electrically connected through the first conductive layer.

10. The power amplifier according to claim 9, wherein: The resistance value of the region where the first conductive layer faces the second insulating portion is in a range of 2 to 10Ω.

11. The power amplifier according to any one of claims 8 to 10, characterized in that: The source includes a sub-source electrode, the drain includes a sub-drain electrode, the sub-source electrodes and the sub-drain electrodes are arranged alternately, and the gate fingers are respectively provided between adjacent sub-source electrodes and sub-drain electrodes.

12. The power amplifier according to claim 11, wherein: The source and the drain are both arranged on the barrier layer; the source also includes a first connecting portion connected to each of the sub-source electrodes; the drain also includes a second connecting portion connected to each of the sub-drain electrodes; the first connecting portion is provided with an escape opening for avoiding the gate finger.

13. The power amplifier according to any one of claims 8 to 12, characterized in that: The gate, the source, and the drain constitute an electrode group, there are multiple electrode groups, and the gates of two adjacent electrode groups are connected via a second wiring; The second routing includes the first conductive layer and the second conductive layer. A third insulating portion is provided on the second routing. Along the extension direction of the second routing, the third insulating portion disconnects the second conductive layer. The second conductive layers located on both sides of the third insulating portion are electrically connected through the first conductive layer.

14. The power amplifier according to claim 13, wherein: The resistance value of the region where the first conductive layer faces the third insulating portion is in a range of 2 to 10Ω.

15. A power amplifier link, characterized in that: The invention comprises an input end, an output end and a power amplifier according to any one of claims 1 to 14, wherein the gate of the power amplifier is connected to the input end through an input matching circuit, and the drain of the power amplifier is connected to the output end through an output matching circuit.

16. The power amplifier chain according to claim 15, characterized in that A first stabilization circuit is provided between the input matching circuit and the gate, and the first stabilization circuit includes a first resistor and a first capacitor connected in parallel.

17. The power amplifier chain according to claim 15, wherein: The gate is grounded through a second stabilization circuit. The second stabilization circuit includes a second resistor and a second capacitor connected in series. The second resistor is electrically connected to the gate, and the second capacitor is grounded.

18. The power amplifier chain according to claim 15, wherein: The gate is electrically connected to the drain through a third stabilization circuit. The third stabilization circuit includes a third resistor and a third capacitor connected in series. The third resistor is electrically connected to the gate, and the third capacitor is electrically connected to the drain.

19. The power amplifier chain according to any one of claims 15 to 18, characterized in that: There are multiple power amplifiers, the gate of each power amplifier is connected to the input matching circuit via a first line, and the drain of each power amplifier is connected to the output matching circuit via a second line; A fourth resistor is connected between two adjacent first lines; and / or a fifth resistor is connected between two adjacent second lines.

20. A radio frequency front-end circuit, characterized in that: comprising a first connection end, a second connection end, an antenna connection end, a radio frequency switch, a duplexer, a low noise amplifier, and a power amplifier chain as described in any one of claims 15 to 19; The input end of the power amplifier chain is electrically connected to the first connection end, the output end of the power amplifier chain is electrically connected to the duplexer, the low noise amplifier is connected between the second connection end and the duplexer, the radio frequency switch is connected between the duplexer and the antenna connection end, and the antenna connection end is used to be electrically connected to the antenna.

21. An electronic device, characterized in that: It includes a processor, an antenna and the RF front-end circuit according to claim 20, the first connection end and the second connection end of the RF front-end circuit are both electrically connected to the processor, and the antenna connection end of the RF front-end circuit is electrically connected to the antenna.

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