Semiconductor device and fabrication method therefor, and power switch device, power source conversion circuit and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Disclosed are a semiconductor device and a fabrication method therefor, and a power switch device and an electronic device. The semiconductor device comprises a substrate, a channel layer, a barrier layer, a gate cap layer, a first passivation layer, a second passivation layer, a source electrode and a drain electrode, wherein the substrate has a first surface; the channel layer, the barrier layer and the gate cap layer are sequentially stacked on the first surface; a first functional portion of the first passivation layer at least covers a sidewall of the gate cap layer; the second passivation layer is formed by stacking at least two dielectric layers in a first direction; a second functional portion of the second passivation layer is located on the barrier layer and is at least located on two opposite sides of the gate cap layer in a second direction, the first functional portion separating the second functional portion from the gate cap layer, the first direction being perpendicular to the first surface, and the second direction being parallel to the first surface; and the first passivation layer is used for suppressing a gate leakage current, and the second passivation layer is used for improving dynamic characteristics of the device. By means of providing a plurality of passivation layers, the requirements for good performance under different metrics can be met.

Description

Semiconductor device and manufacturing method thereof, power switching device, power conversion circuit, and electronic equipment

[0001] This application claims priority to Chinese patent application filed on February 29, 2024, with application number 202410236083.8, and application name “Semiconductor device and preparation method thereof, power switching device, power conversion circuit, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power switching device, a power conversion circuit, and an electronic device. Background Art

[0003] In the field of power electronics, a large amount of AC-DC (alternating current to direct current) or DC-DC (direct current to direct current) power conversion is required, which necessitates power conversion modules centered around power switching devices. Power switching devices are key components in power electronics systems. Currently, gallium nitride (GaN)-based high electron mobility transistors (HEMTs) offer advantages such as faster switching speeds, higher breakdown voltages, and improved system conversion efficiency. Therefore, they can be used to construct semiconductor power switching devices for use in these power electronics systems.

[0004] When GaN HEMT devices are used in power conversion modules, they are essentially in a dynamic switching state. In this scenario, their resistance can be referred to as the dynamic on-resistance (DRon). Because GaN HEMT devices are semiconductor devices that are sensitive to surface states and defect states, their dynamic on-resistance is relatively high, resulting in poor dynamic characteristics. Furthermore, GaN HEMT devices also suffer from high gate leakage, which impacts their performance.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a semiconductor device and a preparation method thereof, a power switching device, a power conversion circuit, and an electronic device for reducing gate leakage of the semiconductor device, improving the dynamic characteristics of the semiconductor device, and improving the performance of the semiconductor device.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a semiconductor device is provided, comprising: a substrate, a channel layer, a barrier layer, a gate cap layer, a first passivation layer, a second passivation layer, a source electrode, and a drain electrode. The substrate has a first surface. The channel layer is located on the first surface. The barrier layer is located on the channel layer. The gate cap layer is located on the barrier layer. The first passivation layer includes a first functional portion, which at least covers the sidewalls of the gate cap layer. The second passivation layer is composed of at least two dielectric layers stacked along a first direction. The second passivation layer includes a second functional portion, which is located on the barrier layer and at least on opposite sides of the gate cap layer along a second direction. The first functional portion separates the second functional portion from the gate cap layer. The source electrode and the drain electrode respectively extend through the second functional portion and the barrier layer to the channel layer. Along the second direction, the source electrode and the drain electrode are respectively located on opposite sides of the gate cap layer. The first direction is perpendicular to the first surface, and the second direction is parallel to the first surface.

[0009] The semiconductor devices provided by some embodiments of the present application are provided with a first passivation layer and a second passivation layer, so that the first functional portion in the first passivation layer at least covers the sidewall of the gate cap layer, the second functional portion of the second passivation layer is located on the barrier layer, and the first functional portion separates the second functional portion and the gate cap layer. The first functional portion of the first passivation layer can be used to reduce the number of charge traps in the sidewall (or the sidewall and part of the upper surface) in contact with it in the gate cap layer, or the first functional portion can be used to reduce the hole concentration in the sidewall (or the sidewall and part of the upper surface) in contact with it in the gate cap layer, thereby forming a good leakage suppression effect on the sidewall of the gate cap layer and reducing gate leakage; the second functional portion of the second passivation layer composed of at least two dielectric layers stacked together and the barrier layer can also be used to form a better lattice match, reduce the number of surface states caused by dangling bonds or atomic vacancies, suppress the charge and discharge effects in dynamic switching scenarios, thereby reducing the dynamic on-resistance of the semiconductor device and improving the device dynamic characteristics of the semiconductor device. That is to say, the embodiment of the present application combines the advantages of two different passivation layers, and at the same time improves the gate leakage problem and poor dynamic characteristics of the semiconductor device, which can effectively improve the performance of the semiconductor device and enable the semiconductor device to achieve better performance under different indicators.

[0010] In a possible design of the first aspect, along the first direction, the dielectric layer closest to the barrier layer of the at least two dielectric layers is the first dielectric layer, and the dielectric layer farthest from the barrier layer is the second dielectric layer. The breakdown field strength of the first dielectric layer is lower than the breakdown field strength of the second dielectric layer; and / or the dielectric constant of the first dielectric layer is higher than the dielectric constant of the second dielectric layer.

[0011] In a possible design of the first aspect, the material of the first dielectric layer includes at least one of aluminum nitride, aluminum oxide, and aluminum oxynitride, and the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0012] In a possible design of the first aspect, a material of the first passivation layer includes at least one of silicon nitride and silicon oxynitride.

[0013] In a possible design of the first aspect, the first passivation layer further includes a first shielding portion. The first shielding portion is connected to the first functional portion and covers the second functional portion. The source and drain electrodes also extend through the first shielding portion. This allows the first shielding portion of the first passivation layer to shield and protect the second passivation layer, preventing damage to the second passivation layer and, in turn, preventing the second passivation layer from affecting the semiconductor device's dynamic characteristics. Furthermore, the second functional portion may have relatively weak breakdown resistance. Providing the first shielding portion on the second functional portion can, in conjunction with the second functional portion, improve the breakdown resistance, thereby enhancing the reliability of the semiconductor device.

[0014] In a possible design of the first aspect, the semiconductor device further includes a third passivation layer. This third passivation layer is located between the second functional portion and the first shielding portion. The orthographic projection of the third passivation layer on the first surface coincides with the orthographic projection of the second functional portion on the first surface. The source and drain electrodes also extend through the third passivation layer. This allows the third passivation layer to shield the second functional portion, preventing damage to the second functional portion. Furthermore, the provision of the third passivation layer helps improve the overall flatness of the semiconductor device and enhances its compatibility with subsequent processes.

[0015] In a possible design of the first aspect, the semiconductor device further includes a field plate. Along the second direction, the field plate is positioned between the gate cap layer and the drain. A portion of the field plate is positioned on the first functional portion, while another portion is positioned on the first shielding portion. By defining the positional relationship between the field plate and the first passivation layer, the electric field within the barrier layer on the drain side of the gate can be regulated, thereby improving the breakdown voltage and reliability of the semiconductor device.

[0016] In a possible design of the first aspect, the semiconductor device further includes a first protective layer. The first protective layer is positioned between the first passivation layer and the field plate. A first opening is defined in the first protective layer, exposing the source and drain electrodes. This first protective layer protects the source and drain electrodes, preventing damage to the source and drain electrodes during field plate fabrication, thereby improving the electrical performance and reliability of the semiconductor device.

[0017] In a possible design of the first aspect, the semiconductor device further includes a second protective layer. The second protective layer covers the first passivation layer and the field plate. The source and drain electrodes also extend through the second protective layer. This second protective layer protects the field plate, preventing damage to the field plate during the fabrication of the source and drain electrodes, thereby improving the electrical performance and reliability of the semiconductor device.

[0018] In a possible design of the first aspect, the semiconductor device further includes a third protective layer, located between the second functional portion and the first shielding portion. A second opening is defined in the first shielding portion and the third protective layer, exposing the source and drain electrodes. This allows the third protective layer and the first shielding portion to protect the source and drain electrodes, preventing damage to the source and drain electrodes during field plate fabrication, thereby improving the electrical performance and reliability of the semiconductor device.

[0019] In a possible design of the first aspect, the second passivation layer further includes a second shielding portion. The second shielding portion is connected to the second functional portion and covers the first functional portion. This allows the second shielding portion of the second passivation layer to shield and protect the first passivation layer, preventing damage to the first passivation layer and, in turn, preventing an impact on the first passivation layer's ability to suppress gate leakage of the semiconductor device.

[0020] In a possible design of the first aspect, the distance between the second functional portion and the gate cap layer along the second direction ranges from 0.1 μm to 100 μm, which can improve the dynamic characteristics of the semiconductor device and effectively suppress gate leakage.

[0021] In a possible design of the first aspect, the thickness of the second passivation layer is smaller than the thickness of the first passivation layer, which can improve the dynamic characteristics of the semiconductor device and reduce the thickness of the semiconductor device.

[0022] In a possible design of the first aspect, the thickness of the first passivation layer ranges from 0.1 nm to 1000 nm. And / or, the thickness of the second passivation layer ranges from 0.1 nm to 1000 nm. By adjusting the thickness of the first passivation layer, the material used in the first passivation layer can be reduced, thereby reducing costs, while ensuring a good suppression effect on gate leakage. By adjusting the thickness of the second passivation layer, the material used in the second passivation layer can be reduced, thereby reducing costs, while ensuring a good improvement in the dynamic characteristics of the semiconductor device.

[0023] In a possible design of the first aspect, the semiconductor device further includes a gate. A third opening is defined in the first functional portion. A portion of the gate is located within the third opening and in contact with the gate cap layer, while another portion of the gate overlaps the first functional portion. Alternatively, the gate is located between the gate cap layer and the first functional portion.

[0024] In a second aspect, a method for fabricating a semiconductor device is provided, the method comprising: providing a substrate having a first surface; sequentially forming a channel layer, a barrier layer, and a gate cap layer on the first surface; forming a first passivation layer and a second passivation layer on the barrier layer and the gate cap layer; the first passivation layer comprising a first functional portion, the first functional portion at least covering the sidewalls of the gate cap layer; and the second passivation layer comprising at least two dielectric layers stacked along a first direction. The second passivation layer comprising a second functional portion, the second functional portion being located on the barrier layer and at least on opposite sides of the gate cap layer along a second direction, the first functional portion separating the second functional portion from the gate cap layer; the first direction being perpendicular to the first surface, and the second direction being parallel to the first surface. Forming a source electrode and a drain electrode, respectively, extending through the second functional portion and the barrier layer to the channel layer; the source electrode and the drain electrode being located on opposite sides of the gate cap layer along the second direction.

[0025] Some embodiments of the present application provide methods for preparing semiconductor devices. After forming a channel layer, a barrier layer, and a gate cap layer, a first passivation layer and a second passivation layer are formed, such that the first functional portion of the first passivation layer at least covers the sidewalls of the gate cap layer, the second functional portion of the second passivation layer is located on the barrier layer, and the first functional portion separates the second functional portion from the gate cap layer. The first functional portion of the first passivation layer can be used to effectively suppress leakage on the sidewalls of the gate cap layer, thereby reducing gate leakage. The second functional portion of the second passivation layer, which is composed of at least two stacked dielectric layers, can be used to suppress charge and discharge effects in dynamic switching scenarios, reduce the dynamic on-resistance of the semiconductor device, and improve the dynamic characteristics of the semiconductor device. In other words, the embodiments of the present application combine the advantages of two different passivation layers while improving the gate leakage problem and poor device dynamic characteristics of the semiconductor device. This can effectively improve the performance of the semiconductor device and enable the semiconductor device to achieve better performance under different indicators.

[0026] In a possible design of the second aspect, a first passivation layer and a second passivation layer are formed on the barrier layer and the gate cap layer, including: forming a sacrificial layer on the barrier layer, the sacrificial layer covering the gate cap layer and exposing a portion of the surface of the barrier layer; forming a second passivation film on the barrier layer and the sacrificial layer; removing the sacrificial layer and the portion of the second passivation film located on the sacrificial layer, retaining the portion of the second passivation film located on the barrier layer, to obtain a second functional portion of the second passivation layer; and forming a first passivation layer on the second functional portion, the barrier layer, and the gate cap layer, the first passivation layer further comprising a first shielding portion connected to the first functional portion, the first shielding portion covering the second functional portion. This not only reduces etching of the first passivation layer and simplifies the difficulty of fabricating the first passivation layer, but also utilizes the first shielding portion of the first passivation layer to shield and protect the second functional portion of the second passivation layer, thereby preventing damage to the second functional portion during subsequent fabrication processes (e.g., fabrication of the source and drain electrodes, opening of the opening in the first functional portion, etc.), thereby preventing the second functional portion from affecting the effect of the second functional portion on improving the dynamic characteristics of the semiconductor device.

[0027] In a second possible design, a first passivation layer and a second passivation layer are formed on the barrier layer and the gate cap layer, including: forming a first passivation film on the barrier layer, the first passivation film covering the gate cap layer and the barrier layer; removing a portion of the first passivation film to expose the barrier layer, thereby obtaining a first functional portion of the first passivation layer; and forming a second passivation layer on the first functional portion and the barrier layer, the second passivation layer further comprising a second shielding portion connected to the second functional portion, the second shielding portion covering the first functional portion. This not only reduces etching of the second passivation layer and simplifies its fabrication, but also allows the second shielding portion of the second passivation layer to shield and protect the first passivation layer, preventing damage to the first passivation layer during subsequent fabrication processes, thereby preventing the first passivation layer from affecting its ability to suppress gate leakage in the semiconductor device. Furthermore, this method facilitates simplifying the semiconductor device fabrication process and improving fabrication efficiency.

[0028] In a possible design of the second aspect, forming a first passivation layer and a second passivation layer on the barrier layer and the gate cap layer includes: forming a second passivation film on the barrier layer and the gate cap layer; removing a portion of the second passivation film covering the gate cap layer and exposing the barrier layer to obtain a second functional portion of the second passivation layer; forming a first passivation layer on the second functional portion, the barrier layer, and the gate cap layer; the first passivation layer further including a first shielding portion connected to the first functional portion, the first shielding portion covering the second functional portion. The above method for forming the first and second passivation layers is relatively simple and easy to implement, thereby improving the manufacturing efficiency of semiconductor devices.

[0029] In a possible design of the second aspect, before removing the portion of the second passivation film covering the gate cap layer, the preparation method further includes: forming a third passivation film on the second passivation film. Removing the portion of the second passivation film covering the gate cap layer includes: simultaneously removing the third passivation film and the portion of the second passivation film covering the gate cap layer. This avoids the need for an additional etching step and allows the third passivation film to shield the second passivation film, preventing damage to the second functional portion during etching to form the second functional portion. Furthermore, the provision of the third passivation layer helps improve the overall flatness of the semiconductor device and enhances compatibility with subsequent processes.

[0030] In a possible design of the second aspect, the first passivation layer also includes a first shielding portion, which is connected to the first functional portion and covers the second functional portion. After forming the source and drain, the preparation method also includes: forming a first protective layer on the first passivation layer, the first protective layer also covering the source and drain; forming a field plate on the first protective layer, wherein a portion of the field plate is located on the first functional portion in a direction perpendicular to the first surface, and another portion of the field plate is located on the first shielding portion, and along the second direction, the field plate is located between the gate cap layer and the drain. In this way, the first protective layer can be used to protect the source and drain to avoid damage to the source and drain, and the formation position of the field plate can be limited to effectively control the electric field on the side of the gate close to the drain.

[0031] In a possible design method of the second aspect, the first passivation layer further includes a first shielding portion, which is connected to the first functional portion and covers the second functional portion. Before forming the source and drain, the preparation method includes: forming a field plate on the first passivation layer, wherein a portion of the field plate is located on the first functional portion in a direction perpendicular to the first surface, and another portion of the field plate is located on the first shielding portion, and along the second direction, the field plate is located between the gate cap layer and the drain; forming a second protective layer on the field plate and the first passivation layer. In this way, during the process of preparing and forming the source and drain, the second protective layer can be used to protect the field plate, avoid damaging the field plate, and improve the electrical performance and reliability of the semiconductor device. In addition, by limiting the formation position of the field plate, it is beneficial to regulate the electric field on the side of the gate close to the drain.

[0032] In a possible design of the second aspect, the first passivation layer further includes a first shielding portion, which is connected to the first functional portion and covers the second functional portion. The source and drain electrodes are formed after the second passivation layer and before the first passivation layer. Forming the second passivation layer includes forming a second passivation film on the barrier layer and gate cap layer. After forming the source and drain electrodes, the fabrication method includes forming a third protective layer on the second passivation film, the third protective layer also covering the source and drain electrodes; and removing portions of the second passivation film and the third protective layer covering the gate cap layer to expose the barrier layer. After forming the first passivation layer, the fabrication method includes forming a field plate on the first passivation layer. In a direction perpendicular to the first surface, a portion of the field plate is located on the first functional portion, and another portion of the field plate is located on the first shielding portion. In the second direction, the field plate is located between the gate cap layer and the drain electrode. This allows the third protective layer and the first passivation layer to simultaneously protect the source and drain electrodes, preventing damage to the source and drain electrodes during field plate fabrication and improving the electrical performance and reliability of the semiconductor device. In addition, by limiting the formation position of the field plate, it is helpful to regulate the electric field on the side of the gate close to the drain.

[0033] In a possible design of the second aspect, after forming the source and drain electrodes, the fabrication method further includes: forming a third opening on the first functional portion; and forming a gate, wherein a portion of the gate is located within the third opening and contacts the gate cap layer, and another portion of the gate overlaps the first functional portion. Alternatively, before forming the first passivation layer and the second passivation layer, the fabrication method further includes: forming a gate on the gate cap layer.

[0034] In a third aspect, a power switching device is provided, comprising a package substrate and a semiconductor device electrically connected to the package substrate. The semiconductor device comprises the semiconductor device according to any embodiment of the first aspect.

[0035] In a fourth aspect, a power conversion circuit is provided, comprising a circuit board and a power switch device electrically connected to the circuit board. The power switch device is the power switch device as described in any embodiment of the third aspect.

[0036] In a fifth aspect, an electronic device is provided, comprising: a housing, and a power conversion circuit housed in the housing. The power conversion circuit is the power conversion circuit as described in any embodiment of the fourth aspect.

[0037] In a sixth aspect, an electronic device is provided, comprising: a power switching device and a circuit board electrically connected to the power switching device. The power switching device comprises the power switching device as described in any embodiment of the third aspect.

[0038] The technical effects brought about by any design method in the third to sixth aspects can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0040] FIG2 is a schematic structural diagram of an active antenna unit provided in an embodiment of the present application;

[0041] FIG3 is a schematic structural diagram of another electronic device provided in an embodiment of the present application;

[0042] FIG4 is a schematic diagram of a structure of a semiconductor device provided in an embodiment of the present application;

[0043] FIG5 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0044] FIG6 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0045] FIG7 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0046] FIG8 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0047] FIG9 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0048] FIG10 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0049] FIG11 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0050] FIG12 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0051] FIG13 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0052] FIG14 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0053] FIG15 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0054] FIG16 is a schematic diagram of a structure of another semiconductor device provided in an embodiment of the present application;

[0055] FIG17 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0056] 18a to 18h are schematic structural diagrams corresponding to the steps in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0057] 19a to 19e are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0058] 20a to 20d are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0059] 21a to 21e are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0060] 22a-22c are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0061] 23a to 23c are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0062] 24a to 24c are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0063] 25a-25c are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0064] 26a-26c are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0065] 27a to 27c are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0066] 28a to 28f are schematic structural diagrams corresponding to the steps in another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0067] FIG29 is a schematic structural diagram of a power switch device provided in an embodiment of the present application;

[0068] FIG30 is a schematic structural diagram of a power conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0070] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one item" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0071] "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0072] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0073] In the embodiments of the present application, "upper," "lower," "left," and "right" are not limited to being defined relative to the orientation of components schematically shown in the drawings. It should be understood that these directional terms can be relative concepts. They are used for relative description and clarification and may change accordingly depending on the orientation of the components in the drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity, and the dimensional ratios between the components in the drawings do not reflect the actual dimensional ratios.

[0074] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0075] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0076] Some embodiments of the present application provide an electronic device, which may be, for example, a charger, a charging small household appliance (such as a soy milk maker, a sweeping robot), an on-board charger (OBC), a drone, an aerospace equipment, a lidar driver, a laser, a detector, a radar, a 5G (the 5th generation mobile network, fifth generation mobile communication technology) communication device, and other different types of user equipment or terminal equipment; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device. The electronic device can be widely used in systems such as civilian consumer electronics, vehicle-mounted electronics, data center power supplies, and photovoltaic inverters.

[0077] Figure 1 is a structural diagram of an electronic device provided in an embodiment of the present application. Figure 1 takes a base station as an example. Those skilled in the art will understand that the structure of the electronic device shown in Figure 1 does not limit the electronic device, and the electronic device may include more or fewer components than those shown in Figure 1, or may combine some of the components shown in Figure 1, or may have a different arrangement of components than shown in Figure 1.

[0078] As shown in Figure 1, the base station includes a baseband unit (BBU) 100 and an active antenna unit (AAU) 200. The BBU 100 is primarily responsible for baseband digital signal processing, such as fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT), modulation / demodulation, and channel coding / decoding.

[0079] FIG2 is a structural diagram of an active antenna unit 200 provided in an embodiment of the present application.

[0080] As shown in FIG2 , the active antenna unit 200 includes a computing unit 210, a first transmission unit 220, and an antenna unit 230. The computing unit 210 includes a control unit 211, a second transmission unit 212, a baseband unit 213, and a power supply unit 214. The control unit 211, the second transmission unit 212, the baseband unit 213, and the power supply unit 214 are electrically connected to each other. The control unit 211 is responsible for controlling the radio frequency signal, the second transmission unit 212 is responsible for transmitting the radio frequency signal, and the baseband unit 213 is responsible for converting digital signals into analog signals. The baseband unit 213 is, for example, a digital to analog converter (DAC), which can convert the digital signal output by the baseband processing unit 100 into an analog signal. The power supply unit 214 is electrically connected to the power supply 240 and is used to supply power to the control unit 211, the second transmission unit 212, and the baseband unit 213 in the computing unit 210.

[0081] The first transmission unit 220 is responsible for transmitting and amplifying radio frequency signals. The first transmission unit 220 includes a radio frequency (RF) unit 221 and a power amplifier (PA) 222. The RF unit 221 is used to convert analog signals into low-power radio frequency signals. The power amplifier 222 is used to amplify the low-power radio frequency signals and output them to the antenna unit 230. The power amplifier 222 is a radio frequency device, which can be a radio frequency chip. Exemplarily, the power amplifier 222 can be a HEMT device.

[0082] The antenna unit 230 is responsible for radiating the radio frequency signal outward. As shown in FIG2 , the active antenna unit 200 may include multiple radio frequency units 221 , multiple power amplifiers 222 , and multiple antenna units 230 .

[0083] FIG3 is a structural diagram of another electronic device provided in an embodiment of the present application. FIG3 takes the electronic device as an example of a charger. Those skilled in the art will understand that the structure of the electronic device shown in FIG3 does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than those shown in FIG3, or may combine some of the components shown in FIG3, or may have a different arrangement of components than shown in FIG3.

[0084] As shown in Figure 3, the charger may include a power device 300, a resistor R, an inductor L, a capacitor C, etc. The power device 300 may be, for example, a HEMT device. The power device 300, resistor R, inductor L, and capacitor C may all be electrically connected to a circuit board (e.g., a printed circuit board) and interconnected.

[0085] An embodiment of the present application provides a semiconductor device for use in the aforementioned electronic device. The semiconductor device may be a HEMT device, and further, an enhancement-mode HEMT device. The enhancement-mode HEMT device is a normally-off device and can be used in power devices. Figure 4 illustrates the structure of a semiconductor device.

[0086] In some examples, as shown in FIG. 4 , the semiconductor device 400 includes a substrate 1 , a channel layer 2 , a barrier layer 3 , a gate cap layer 4 , a gate 5 , a source 6 , and a drain 7 .

[0087] The substrate 1 can be of various types. For example, the substrate 1 includes, but is not limited to, a sapphire substrate, a diamond substrate, a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, or a composite substrate based on any of these substrates. As shown in FIG4 , the substrate 1 has a first surface A. The first surface A is, for example, the top surface of the substrate 1 and is planar.

[0088] As shown in FIG4 , the channel layer 2 is located on the first surface A of the substrate 1 , and the barrier layer 3 is located on the channel layer 2 . The barrier layer 3 is in contact with a surface of the channel layer 2 that is away from the substrate 1 , for example.

[0089] Optionally, the material of the channel layer 2 includes, but is not limited to, GaN, etc., and the doping conditions in the material of the channel layer 2 can be determined according to the withstand voltage required by the semiconductor device 400. The material of the barrier layer 3 includes, but is not limited to, aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlInGaN), etc., and the composition of the material of the barrier layer 3 can be determined according to the power level required by the semiconductor device 400.

[0090] Here, the material of the channel layer 2 is GaN, and the material of the barrier layer 3 is AlGaN. As GaN is polar, no doping is required at the AlGaN / GaN interface. Therefore, the semiconductor device 400 can generate a high-concentration, highly confined two-dimensional electron gas (2DEG) at the AlGaN / GaN interface through spontaneous polarization and piezoelectric polarization. This two-dimensional electron gas can be used to efficiently conduct electrons. The location of the two-dimensional electron gas can serve as the main conduction area for the operation of the semiconductor device 400.

[0091] One or more buffer layers are provided between the channel layer 2 and the substrate 1. The materials of the buffer layers include, but are not limited to, aluminum nitride, aluminum gallium nitride, etc. The buffer layers can alleviate the strain caused by the lattice mismatch between the substrate 1 and the channel layer 2, and reduce or even prevent the formation of defects.

[0092] As shown in FIG4 , the gate cap layer 4 is located on the barrier layer 3, and the gate 5 is located on the gate cap layer 4. The gate cap layer 4, for example, contacts the surface of the barrier layer 3 away from the substrate 1. The orthographic projection area of ​​the gate cap layer 4 on the first surface A is smaller than the orthographic projection area of ​​the barrier layer 3 on the first surface A; the orthographic projection of the gate cap layer 4 on the first surface A is located within the orthographic projection range of the barrier layer 3 on the first surface A; the gate cap layer 4 only covers a portion of the barrier layer 3. The gate 5, for example, contacts the surface of the gate cap layer 4 away from the substrate 1 to form a Schottky contact. The orthographic projection area of ​​the gate 5 on the first surface A is smaller than or equal to the orthographic projection area of ​​the gate cap layer 4 on the first surface A; the orthographic projection of the gate 5 on the first surface A is located within the orthographic projection range of the gate cap layer 4 on the first surface A, or the orthographic projection of the gate 5 on the first surface A coincides with the orthographic projection of the gate cap layer 4 on the first surface A.

[0093] Optionally, the gate cap layer 4 is made of p-GaN or a P-type metal, and the gate 5 is made of a metal material. The gate cap layer 4 can raise the energy band at the channel position, depleting the two-dimensional electron gas below the gate 5, thereby realizing a normally-off semiconductor device.

[0094] As shown in FIG4 , along the second direction X, the source electrode 6 and the drain electrode 7 are located on opposite sides of the gate cap layer 4. Furthermore, the source electrode 6 and the drain electrode 7 each penetrate the barrier layer 3 to the channel layer 2, thereby contacting the channel layer 2 and forming an ohmic contact. The second direction X is parallel to the first surface A.

[0095] Optionally, the materials of the source electrode 6 and the drain electrode 7 may be the same or different. For example, the material of either the source electrode 6 or the drain electrode 7 includes but is not limited to copper, aluminum, tungsten, nickel, iron, cobalt, silver, gold or platinum.

[0096] The operating principle of the semiconductor device 400 is as follows: a two-dimensional electron gas (2DEG) channel is generated at the interface between the channel layer 2 and the barrier layer 3 due to a polarization effect. This 2DEG can be used to efficiently conduct electrons. When the gate 5 receives no voltage signal, that is, when there is no bias voltage, the 2DEG is in a pinch-off state, achieving a cutoff between the source 6 and the drain 7, and the semiconductor device 400 is in an off state. When the gate 5 receives a voltage signal, that is, when a bias voltage is applied, the 2DEG is allowed to pass, achieving a conduction between the source 6 and the drain 7, and the semiconductor device 400 is in an on state. Therefore, in the absence of a bias voltage, the semiconductor device 400 is a normally-off device.

[0097] It is understandable that the aforementioned semiconductor device is highly compatible with other components of the power conversion module, eliminating the need for a separate power supply system. This not only reduces circuit design complexity, power consumption, and cost, but also improves circuit safety. However, the aforementioned semiconductor device has a relatively high dynamic on-resistance, resulting in poor dynamic characteristics. Furthermore, the aforementioned semiconductor device also suffers from high gate leakage, which impacts its performance.

[0098] In one possible implementation, referring again to FIG. 4 , the semiconductor device 400 further includes a passivation layer 8'. The passivation layer 8' is located on the barrier layer 3 and contacts the sidewalls of the gate cap layer 4. The passivation layer 8' is used to terminate and passivate dangling bonds on the sidewalls of the gate cap layer 4 to limit the number of interface traps, thereby reducing gate leakage and improving the performance of the semiconductor device.

[0099] However, the provision of the passivation layer 8 ′ makes it difficult to simultaneously improve the dynamic characteristics of the semiconductor device 400 , making it difficult for the semiconductor device 400 to achieve better performance under different indicators.

[0100] Based on this, some embodiments of the present application further improve the semiconductor device 400 described above, namely, a first passivation layer is provided at least on the sidewalls of the gate cap layer, so that the first passivation layer can effectively suppress the sidewalls of the gate cap layer and reduce gate leakage; and a second passivation layer is provided at least around the gate cap layer, so that the second passivation layer can reduce the dynamic on-resistance of the semiconductor device 400 and improve the dynamic characteristics of the semiconductor device 400. In other words, the embodiments of the present application combine the advantages of two different passivation layers, while improving the gate leakage problem and poor device dynamic characteristics of the semiconductor device 400, effectively improving the performance of the semiconductor device 400 and enabling the semiconductor device 400 to achieve better performance under different indicators.

[0101] 5 to 13 respectively illustrate the structure of a semiconductor device.

[0102] In some examples, as shown in FIG. 5 and FIG. 6 , the semiconductor device 400 further includes a first passivation layer 8 and a second passivation layer 9 .

[0103] As shown in FIG. 5 and FIG. 6 , the first passivation layer 8 includes a first functional portion 81 . The first functional portion 81 at least covers the sidewall of the gate cap layer 4 and at least contacts the sidewall of the gate cap layer 4 .

[0104] Here, the positional relationship between the first functional portion 81 and the gate cap layer 4 may be determined according to the positional relationship between the gate cap layer 4 and the gate 5 .

[0105] For example, as shown in FIG5 , the orthographic projection of the gate 5 on the first surface A is within the orthographic projection of the gate cap layer 4 on the first surface A. Accordingly, the gate 5 only covers a portion of the surface (or upper surface) of the gate cap layer 4 away from the substrate 1, and exposes another portion of the surface of the gate cap layer 4 away from the substrate 1. In this case, the first functional portion 81 also covers the other portion of the surface of the gate cap layer 4 away from the substrate 1 that is exposed, and is in contact with the other portion of the surface.

[0106] For another example, as shown in FIG6 , the orthographic projection of the gate 5 on the first surface A coincides with the orthographic projection of the gate cap layer 4 on the first surface A. Accordingly, the gate 5 completely covers the surface of the gate cap layer 4 on the side away from the substrate 1. In this case, the first functional portion 81 only covers the sidewalls of the gate cap layer 4 and is in contact with the sidewalls of the gate cap layer 4.

[0107] 5 and 6 , while the first functional portion 81 covers the sidewall of the gate cap layer 4, the first functional portion 81 contacts the barrier layer 3, covering a portion of the surface of the barrier layer 3 away from the substrate 1. The orthographic projection of the first functional portion 81 on the first surface A is, for example, annular.

[0108] There are various positional relationships between the first functional portion 81 and the gate 5 , which are specifically related to the preparation order of the first passivation layer 8 and the gate 5 . These relationships can be selected based on actual needs and are not limited in this embodiment of the present application.

[0109] For example, the first passivation layer 8 is formed before the gate 5. In this case, the first functional portion 81 of the first passivation layer 8 can relatively completely cover the surface of the gate cap layer 4 facing away from the substrate 1. Accordingly, as shown in FIG5 , a third opening K3 is defined in the first functional portion 81. A portion of the gate 5 is located within this third opening K3, contacting the gate cap layer 4; another portion of the gate 5 overlaps the first functional portion 81.

[0110] For another example, compared to the gate 5, the first passivation layer 8 is formed later. In this case, as shown in FIG6 , the gate 5 is located between the gate cap layer 4 and the first functional portion 81 of the first passivation layer 8. The first functional portion 81 also covers the sidewalls of the gate 5 and a portion of the surface of the gate 5 facing away from the substrate 1.

[0111] It can be understood that the first functional portion 81 can reduce the number of charge traps in the side walls (or side walls and part of the upper surface) in contact with it in the gate cap layer 4; or, the first functional portion 81 can reduce the hole concentration in the side walls (or side walls and part of the upper surface) in contact with it in the gate cap layer 4, thereby effectively reducing the leakage of the side walls of the gate cap layer 4 and reducing the gate leakage.

[0112] As shown in Figures 5 and 6, at least a portion of the second passivation layer 9 is located on the barrier layer 3. Specifically, the second passivation layer 9 is composed of at least two dielectric layers 9a stacked along a first direction Z, where the first direction Z is perpendicular to the first surface A. Optionally, the second passivation layer 9 can be composed of two, three, four, or even more dielectric layers 9a, and each dielectric layer 9a in the second passivation layer 9 is stacked along the first direction Z. During the preparation and formation of the second passivation layer 9, the dielectric layers 9a can be deposited sequentially along the first direction Z. The orthographic projections of the dielectric layers 9a on the first surface, for example, overlap.

[0113] Along the first direction Z, the dielectric layer 9a closest to the barrier layer 3 of the at least two dielectric layers 9a is the first dielectric layer 9a1, and the dielectric layer 9a farthest from the barrier layer 3 is the second dielectric layer 9a2. The first dielectric layer 9a1 and the second dielectric layer 9a2 are made of different materials. Furthermore, when the second passivation layer 9 includes three, four, or even more dielectric layers 9a, the material of each dielectric layer located between the first dielectric layer 9a1 and the second dielectric layer 9a2 can be the same as or different from the material of one of the first dielectric layer 9a1 and the second dielectric layer 9a2.

[0114] Continuing with Figures 5 and 6 , the second passivation layer 9 includes a second functional portion 91, which is located on the barrier layer 3. For example, the second functional portion 91 contacts the surface of the barrier layer 3 facing away from the substrate 1. In other words, the portion of the second passivation layer 9 that contacts the barrier layer 3 constitutes the second functional portion 91. Furthermore, the second functional portion 91 includes at least a portion of each of the dielectric layers 9a. The second functional portion 91 is located at least on two opposing sides of the gate cap layer 4 along the second direction X. For example, the second functional portion 91 may be located only on two opposing sides of the gate cap layer 4 along the second direction X. Alternatively, the second functional portion 91 may be annular and surround the gate cap layer 4.

[0115] The first functional portion 81 separates the second functional portion 91 from the gate cap layer 4. This means that there is a certain distance between the second functional portion 91 and the gate cap layer 4, and the two are not in direct contact. For example, along the second direction X, part of the sidewall of the second functional portion 91 contacts part of the sidewall of the first functional portion 81; the boundary of the orthographic projection of the second functional portion 91 on the first surface A partially overlaps with the boundary of the orthographic projection of the first functional portion 81 on the first surface A.

[0116] 5 and 6 , the source electrode 6 and the drain electrode 7 also respectively penetrate the second functional portion 91. The second functional portion 91 surrounds the source electrode 6 and the drain electrode 7.

[0117] It is understood that the second functional portion 91 has a better lattice match with the barrier layer 3, which can reduce the number of surface states caused by dangling bonds or atomic vacancies and suppress the charge-discharge effect in dynamic switching scenarios. Moreover, the second passivation layer 9 composed of multiple dielectric layers 9a can improve the reverse withstand voltage of the semiconductor device 400, suppress reverse leakage, reduce the dynamic on-resistance of the semiconductor device 400, and improve the dynamic characteristics of the semiconductor device 400.

[0118] Thus, in some embodiments of the present application, the semiconductor device 400 provided by the first passivation layer 8 and the second passivation layer 9 is provided, so that the first functional portion 81 of the first passivation layer 8 at least covers the sidewalls of the gate cap layer 4, the second functional portion 91 of the second passivation layer 9 is located on the barrier layer 3, and the first functional portion 81 separates the second functional portion 91 from the gate cap layer 4. The first functional portion 81 of the first passivation layer 8 can be used to effectively suppress leakage on the sidewalls of the gate cap layer 4, thereby reducing gate leakage. The second functional portion 91 of the second passivation layer 9, which is formed by stacking at least two dielectric layers 9a, can be used to suppress charge and discharge effects in dynamic switching scenarios, reduce the dynamic on-resistance of the semiconductor device 400, and improve the dynamic characteristics of the semiconductor device 400. In other words, the embodiments of the present application combine the advantages of two different passivation layers, while simultaneously improving the gate leakage problem and poor device dynamic characteristics of the semiconductor device 400, effectively improving the performance of the semiconductor device 400 and enabling the semiconductor device 400 to achieve better performance across various indicators.

[0119] It is understandable that the distance between the second functional portion 91 and the gate cap layer 4 along the second direction X can be set according to actual products, as long as it can simultaneously reduce gate leakage and improve device dynamic characteristics.

[0120] In some examples, along the second direction X, the distance between the second functional portion 91 and the gate cap layer 4 ranges from 0.1 μm to 100 μm.

[0121] Optionally, along the second direction X, the distance between the second functional portion 91 and the gate cap layer 4 may range from 0.1 μm to 10 μm, 30 μm to 50 μm, 55 μm to 80 μm, 80 μm to 100 μm, or 25 μm to 90 μm, etc. Specifically, along the second direction X, the distance between the second functional portion 91 and the gate cap layer 4 may range from 0.1 μm, 15 μm, 40 μm, 60 μm, 85 μm, or 100 μm, etc.

[0122] Here, when the boundary of the orthographic projection of the second functional portion 91 on the first surface A coincides with the boundary of the orthographic projection of the first functional portion 81 on the first surface A, along the second direction X, the distance between any side wall on the left or right sides of the above-mentioned first functional portion 81 and the gate cap layer 4 is also in the range of 0.1μm-100μm.

[0123] By setting the distance between the second functional portion 91 and the gate cap layer 4 along the second direction X, the dynamic characteristics of the semiconductor device 400 can be improved and the gate leakage can be suppressed.

[0124] The thickness of the first passivation layer 8 and the second passivation layer 9 can be set according to the actual product, as long as they can simultaneously reduce gate leakage and improve device dynamic characteristics.

[0125] In some examples, the thickness of the first passivation layer 8 is in the range of 0.1 nm to 1000 nm, and / or the thickness of the second passivation layer 9 is in the range of 0.1 nm to 1000 nm.

[0126] Optionally, the thickness of the first passivation layer 8 may be, for example, in the range of 0.1 nm-10 nm, 30 nm-100 nm, 200 nm-400 nm, 500 nm-1000 nm, or 150 nm-800 nm. Specifically, the thickness of the first passivation layer 8 may be, for example, 0.1 nm, 20 nm, 180 nm, 300 nm, 700 nm, 900 nm, or 1000 nm. The thickness of the second passivation layer 9 may be, for example, in the range of 0.1 nm-10 nm, 30 nm-100 nm, 200 nm-400 nm, 500 nm-1000 nm, or 150 nm-800 nm. Specifically, the thickness of the second passivation layer 9 may be, for example, 0.1 nm, 20 nm, 180 nm, 300 nm, 700 nm, 900 nm, or 1000 nm.

[0127] By adjusting the thickness of the first passivation layer 8, the material used in the first passivation layer 8 can be reduced, thereby reducing costs, while ensuring a good suppression effect on gate leakage. By adjusting the thickness of the second passivation layer 9, the material used in the second passivation layer 9 can be reduced, thereby reducing costs, while ensuring a good improvement in the device dynamic characteristics of the semiconductor device 400.

[0128] Exemplarily, the thickness of the second passivation layer 9 is less than that of the first passivation layer 8. On this basis, the thickness of the second passivation layer 9 is greater than or equal to 0.1 nm and less than 1000 nm; the thickness of the first passivation layer 8 is greater than 0.1 nm and less than or equal to 1000 nm.

[0129] For example, the thickness of the second passivation layer 9 is 100 nm, and the thickness of the first passivation layer 8 is 500 nm.

[0130] In this way, the dynamic characteristics of the semiconductor device 400 can be improved, and the thickness of the semiconductor device 400 can be reduced.

[0131] The materials of the first passivation layer 8 and the second passivation layer 9 are both dielectric materials, which can be selected according to actual needs.

[0132] In some examples, the material of the first passivation layer 8 includes at least one of silicon nitride (SiN) and silicon oxynitride (SiON). Furthermore, the material of the first passivation layer 8 may also include at least one of silicon oxide (SiO2), hafnium oxide (HfO2), titanium dioxide (TiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), nickel oxide (NiO), and gallium oxide (Ga2O3).

[0133] Optionally, when the material of the first passivation layer 8 is one type, the first passivation layer 8 is a single-layer thin film structure. When the material of the first passivation layer 8 is multiple types, the first passivation layer 8 can be a single-layer thin film structure or a structure composed of multiple thin films stacked together (as shown in FIG7 ).

[0134] When the first passivation layer 8 is a single-layer thin film structure, a complete conductive path may be formed inside the first passivation layer 8. After the first passivation layer 8 is configured as a multi-layer thin film stacked structure, the conductive path can be interrupted, thereby improving the reliability of the semiconductor device 400.

[0135] In some examples, in the second passivation layer 9 , the material of the first dielectric layer 9 a 1 includes at least one of aluminum nitride, aluminum oxide, and aluminum oxynitride, and the material of the second dielectric layer 9 a 2 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0136] When the second passivation layer 9 includes three, four or even more dielectric layers 9a, the material of each dielectric layer 9a located between the first dielectric layer 9a1 and the second dielectric layer 9a2 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide.

[0137] When the second passivation layer 9 is a single-layer thin film structure, a complete conductive path may be formed inside the second passivation layer 9. By configuring the second passivation layer 9 as a structure composed of multiple stacked dielectric layers 9a, the conductive path can be interrupted, thereby improving the reliability of the semiconductor device 400.

[0138] In some examples, the breakdown field strength of the first dielectric layer 9a1 is smaller than the breakdown field strength of the second dielectric layer 9a2, and / or the dielectric constant of the first dielectric layer 9a1 is larger than the dielectric constant of the second dielectric layer 9a2.

[0139] In this way, the first dielectric layer 9a1 can be used to improve the lattice matching between the second functional portion 91 of the second passivation layer 9 and the barrier layer 3, and the second dielectric layer 9a2 can be used to improve the breakdown field strength of the second functional portion 91 of the second passivation layer 9, thereby improving the reverse withstand voltage of the semiconductor device 400 and suppressing reverse leakage.

[0140] It is understandable that there are many ways to set the first passivation layer 8 and the second passivation layer 9, which can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0141] In some possible embodiments, as shown in FIG8 , the first passivation layer 8 further includes a first shielding portion 82 , which is connected to the first functional portion 81 . Furthermore, the second passivation layer 9 is composed of the second functional portion 91 , for example.

[0142] The first shielding portion 82 and the first functional portion 81 are, for example, integrally formed. That is, the first shielding portion 82 and the first functional portion 81 are continuous and uninterrupted. The first shielding portion 82 and the first functional portion 81 can be formed simultaneously in the same patterning process.

[0143] Continuing with FIG8 , the first shielding portion 82 covers the second functional portion 91. The source electrode 6 and the drain electrode 7 also extend through the first shielding portion 82. The first shielding portion 82 is located on the second functional portion 91, for example, in contact with the second functional portion 91. The orthographic projection of the second functional portion 91 on the first surface A is, for example, located within the orthographic projection of the first shielding portion 82 on the first surface A.

[0144] In this way, in the process of preparing the above-mentioned semiconductor device 400, not only can the etching of the first passivation layer 8 be reduced and the difficulty of preparing the first passivation layer 8 be simplified; the first blocking portion 82 of the first passivation layer 8 can also be used to block and protect the second passivation layer 9, thereby avoiding damage to the second passivation layer 9 in subsequent preparation processes, and thus avoiding affecting the improvement effect of the second passivation layer 9 on the dynamic characteristics of the semiconductor device 400.

[0145] In addition, the second functional portion 91 may have a relatively weak anti-puncture capability. Providing the first shielding portion 82 on the second functional portion 91 can cooperate with the second functional portion 91 to improve the anti-puncture capability, thereby improving the reliability of the semiconductor device 400.

[0146] In other possible embodiments, as shown in Figures 9 and 10, the first passivation layer 8 further includes a first shielding portion 82, which is connected to the first functional portion 81. Furthermore, the second passivation layer 9 is, for example, composed of a second functional portion 91. The positional relationship between the first shielding portion 82 and the second functional portion 91 is the same as the positional relationship between the first shielding portion 82 and the second functional portion 91 described above. For details, please refer to the relevant description above and will not be repeated here.

[0147] 9 and 10 , the semiconductor device 400 further includes a third passivation layer 10. The third passivation layer 10 is located between the second functional portion 91 and the first shielding portion 82. The source electrode 6 and the drain electrode 7 also penetrate the third passivation layer 10, respectively.

[0148] The orthographic projection of the third passivation layer 10 on the first surface A coincides with the orthographic projection of the second functional portion 91 on the first surface A. In other words, the orthographic projection of the third passivation layer 10 on the first surface A has the same shape as the orthographic projection of the second functional portion 91 on the first surface A. Furthermore, the orthographic projection area of ​​the third passivation layer 10 on the first surface A is equal to the orthographic projection area of ​​the second functional portion 91 on the first surface A. The third passivation layer 10 and the second functional portion 91 are formed simultaneously, for example, in the same patterning process.

[0149] By providing the third passivation layer 10 on the second functional portion 91, the third passivation layer 10 can be used to shield the second functional portion 91, protecting the second functional portion 91 during the etching process to form the second functional portion 91 and preventing damage to the second functional portion 91. Furthermore, the provision of the third passivation layer 10 increases the dielectric thickness around the source 6 and drain 7. In other words, it increases the distance between the surface of the first shielding portion 82 away from the first surface A and the first surface A (this distance can be referred to as the first distance), and reduces the difference between the first distance and the second distance (i.e., the distance between the surface of the portion of the first functional portion 81 located on the gate cap layer 4 away from the first surface A and the first surface A). This helps improve the overall flatness of the semiconductor device 400 and enhances its compatibility with subsequent processes.

[0150] 11 , 12 and 13 , the second passivation layer 9 further includes a second shielding portion 92 connected to the second functional portion 91 . Furthermore, the first passivation layer 8 is composed of the first functional portion 81 , for example.

[0151] The second shielding portion 92 and the second functional portion 91 are, for example, integrally formed. That is, the second shielding portion 92 and the second functional portion 91 are continuous and uninterrupted. The second shielding portion 92 and the second functional portion 91 can be formed simultaneously in the same patterning process.

[0152] Continuing with Figures 11, 12, and 13, the second shielding portion 92 covers the first functional portion 81. The second shielding portion 92 is located on the first functional portion 81, for example, in contact with the first functional portion 81. The orthographic projection of the second shielding portion 92 on the first surface A, for example, coincides with the orthographic projection of the first functional portion 81 on the first surface A. In the case where the first passivation layer 8 is formed prior to the gate 5, the second passivation layer 9 may also be formed prior to the gate 5. In this case, the gate 5 may also penetrate the second shielding portion 92 of the second passivation layer 9. In other words, the third opening K3 also penetrates the second shielding portion 92 of the second passivation layer 9.

[0153] In this way, in the process of preparing the above-mentioned semiconductor device 400, not only can the etching of the second passivation layer 9 be reduced and the difficulty of preparing the second passivation layer 9 be simplified; the second blocking portion 92 of the second passivation layer 9 can also be used to block and protect the first passivation layer 8, thereby avoiding damage to the first passivation layer 8 in subsequent preparation processes, and further avoiding affecting the first passivation layer 8's inhibitory effect on the gate leakage of the semiconductor device 400.

[0154] In this embodiment, as shown in Figures 11, 12, and 13, the semiconductor device 400 further includes, for example, a fourth passivation layer 11. The fourth passivation layer 11 is located on the second passivation layer 9 and covers the second passivation layer 9. The orthographic projection of the fourth passivation layer 11 on the first surface A, for example, coincides with the orthographic projection of the second passivation layer 9 on the first surface A. Compared to the aforementioned gate 5, source 6, and drain 7, the fourth passivation layer 11 is formed earlier.

[0155] In this way, the fourth passivation layer 11 can be used to shield and protect the second passivation layer 9 , thereby avoiding damage to the second passivation layer 9 in subsequent preparation processes and ensuring that the second passivation layer 9 can well improve the dynamic characteristics of the semiconductor device 400 .

[0156] It is understandable that when the semiconductor device 400 operates under high frequency and high voltage conditions, it needs to withstand a very high drain voltage. In this case, the electric field lines will gather between the drain 7 and the gate 5 of the semiconductor device 400. However, due to the inevitable defects in the device structure, this will cause the electric field to be unevenly distributed in the channel layer 2, and a very high peak electric field will accumulate on the edge of the gate 5 near the drain 7. The magnitude of the gate peak electric field determines the breakdown voltage of the entire semiconductor device 400, which often causes the actual breakdown voltage of the semiconductor device 400 to be lower than the theoretical breakdown voltage of the GaN material.

[0157] Based on this, in some embodiments, as shown in Figures 14, 15 and 16, the semiconductor device 400 provided in the embodiment of the present application further includes a field plate 12 (FP). Along the second direction X, the field plate 12 is, for example, located between the gate cap layer 4 and the drain 7.

[0158] Exemplarily, the material of the field plate 12 is a metal material. The field plate 12 is electrically connected to one of the gate 5, the source 6, and the drain 7, for example. Alternatively, the field plate 12 may not be electrically connected to the gate 5, the source 6, and the drain 7. The number of field plates 12 may be one or more. In the case where there are multiple field plates 12, the multiple field plates 12 are, for example, stacked in a direction perpendicular to the first surface A, with an insulating dielectric layer, for example, disposed between two adjacent field plates 12.

[0159] By setting the above-mentioned field plate 12, an additional potential can be generated between the drain 7 and the gate 5 to modulate the channel electric field distribution in the semiconductor device 400, adjust and slow down the electric field peak between the gate 5 and the drain 7, thereby improving the breakdown voltage and reliability of the semiconductor device 400.

[0160] In some examples, as shown in Figures 14, 15, and 16, when the first passivation layer 8 further includes a first blocking portion 82, the field plate 12 is, for example, located on the first passivation layer 8. Part of the field plate 12 is located on the first functional portion 81 of the first passivation layer 8, and another part of the field plate 12 is located on the first blocking portion 82 of the first passivation layer 8. That is, a portion of the orthographic projection of the field plate 12 on the first surface A overlaps with the orthographic projection of the first functional portion 81 on the first surface A, and another portion overlaps with the orthographic projection of the first blocking portion 82 on the first surface A.

[0161] Continuing with Figures 14, 15, and 16, since a portion of the first functional portion 81 is located between the gate cap layer 4 and the second functional portion 91 of the second passivation layer 9 and is in direct contact with the barrier layer 3, and the first shielding portion 82 is located on the second functional portion 91 or the third passivation layer 10 (or on the third protective layer described below), there is a height difference between the upper surface of the portion of the first functional portion 81 located between the gate cap layer 4 and the second functional portion 91 (i.e., the side facing away from the substrate 1) and the upper surface of the first shielding portion 82 (i.e., the side facing away from the substrate 1). This creates a step-like structure between the portion of the first functional portion 81 located between the gate cap layer 4 and the second functional portion 91 and the first shielding portion 82. Consequently, the field plate 12 located on the first passivation layer 8 also exhibits a step-like structure. With respect to the first surface A, the portion of the field plate 12 located on the first functional portion 81 is lower than the portion of the field plate 12 located on the first shielding portion 82.

[0162] Relative to the first surface A, a height difference between a portion of the field plate 12 located on the first functional portion 81 and a portion of the field plate 12 located on the first blocking portion 82 may be determined according to the structure between the first blocking portion 82 and the barrier layer 3 .

[0163] For example, if the first shielding portion 82 is located on the second functional portion 91, and only the second functional portion 91 is disposed between the first shielding portion 82 and the barrier layer 3, the height difference is the thickness of the second functional portion 91. For another example, if the first shielding portion 82 is located on the third passivation layer 10, and both the second functional portion 91 and the third passivation layer 10 are disposed between the first shielding portion and the barrier layer 3, the height difference is the sum of the thicknesses of the second functional portion 91 and the third passivation layer 10.

[0164] The closer the field plate 12 is to the barrier layer 3, the stronger the electric field control effect within the barrier layer 3. The area near the drain 7 needs to withstand higher voltages, so the dielectric thickness near the drain 7 is required to be greater. By defining the positional relationship between the field plate 12 and the first passivation layer 8, it is beneficial to control the electric field within the barrier layer 3 on the side of the gate 5 near the drain 7, thereby improving the breakdown voltage and reliability of the semiconductor device 400.

[0165] It is understandable that, when the field plate 12 is formed after the source 6 and the drain 7, the source 6 and the drain 7 may be damaged during the process of forming the field plate 12. When the field plate 12 is formed before the source 6 and the drain 7, the field plate 12 may be damaged during the process of forming the source 6 and the drain 7.

[0166] Based on this, in some embodiments, the semiconductor device 400 provided in the embodiments of the present application further includes a protective layer, which is used to protect the source electrode 6 and the drain electrode 7; or, the protective layer is used to protect the field plate 12 to prevent damage to the field plate 12 during the process of forming the source electrode 6 and the drain electrode 7. The protective layer can be provided in various positions, which are specifically related to the formation order of the protective layer, the first passivation layer 8, the source electrode 6, and the drain electrode 7. The protective layer can be provided according to actual needs and is not limited in the embodiments of the present application.

[0167] In some possible embodiments, the source 6 and drain 7 are formed after the first passivation layer 8; furthermore, the field plate 12 is formed after the source 6 and drain 7. In this case, the protective layer can be referred to as the first protective layer. As shown in FIG14 , the first protective layer 13 is located between the first passivation layer 8 and the field plate 12. A first opening K1 is defined in the first protective layer 13, exposing the source 6 and drain 7. This facilitates subsequent extraction of the source 6 and drain 7.

[0168] In other words, referring again to FIG. 14 , the first protective layer 13 is located on and covers the first passivation layer 8. The first protective layer 13 covers the sidewalls of the source 6 and the sidewalls of the drain 7. The first opening K1 exposes the side surface of the source 6 and the drain 7 away from the substrate 1. Alternatively, the first opening K1 may expose a portion of the side surface of the source 6 away from the substrate 1 and a portion of the side surface of the drain 7 away from the substrate 1, so that a portion of the first protective layer 13 is also located on the source 6 and the drain 7. The field plate 12 is located on the first protective layer 13. Compared to the field plate 12, the first opening K1 is formed later.

[0169] In this way, the first protective layer 13 can be used to protect the source 6 and the drain 7 , thereby preventing damage to the source 6 and the drain 7 during the preparation of the field plate 12 , thereby improving the electrical performance and reliability of the semiconductor device 400 .

[0170] In some other possible embodiments, the source 6 and drain 7 are formed later than the first passivation layer 8 and the field plate 12. In this case, the protective layer can be referred to as a second protective layer. As shown in FIG15 , the second protective layer 14 covers the first passivation layer 8 and the field plate 12. The orthographic projections of the first passivation layer 8 and the field plate 12 on the first surface A are, for example, both located within the orthographic projection range of the second protective layer 14 on the first surface A. The source 6 and drain 7 also respectively penetrate the second protective layer 14. This means that, compared to the second protective layer 14, the source 6 and drain 7 are formed later.

[0171] In this way, the second protective layer 14 can be used to protect the field plate 12 , thereby preventing damage to the field plate 12 during the process of preparing the source 6 and the drain 7 , thereby improving the electrical performance and reliability of the semiconductor device 400 .

[0172] In some other possible embodiments, the source 6 and drain 7 are formed before the first passivation layer 8, and the field plate 12 is formed later. In this case, the protective layer can be referred to as a third protective layer. As shown in FIG16 , the third protective layer 15 is located between the second functional portion 91 and the first shielding portion 82, and a second opening K2 is provided in the first shielding portion 82 and the third protective layer 15. The second opening K2 penetrates both the first shielding portion 82 and the third protective layer 15 and exposes the source 6 and drain 7. This facilitates the subsequent extraction of the source 6 and drain 7.

[0173] In other words, referring to FIG16 , the third protective layer 15 is located on the second functional portion 91, and the outer boundary of the orthographic projection of the third protective layer 15 on the first surface A coincides with the outer boundary of the orthographic projection of the second functional portion 91 on the first surface A. The third protective layer 15 covers the sidewalls of the source 6 and the sidewalls of the drain 7. The second opening K2 exposes the side surface of the source 6 and the drain 7 away from the substrate 1. Alternatively, the second opening K2 can expose a portion of the side surface of the source 6 away from the substrate 1 and expose a portion of the side surface of the drain 7 away from the substrate 1, so that the third protective layer 15 and a portion of the first shielding portion 82 are both located on the source 6 and the drain 7. The field plate 12 is located on the first passivation layer 8. Compared to the field plate 12, the second opening K2 is formed later.

[0174] In this way, the third protective layer 15 and the first shielding portion 82 can be used to protect the source 6 and the drain 7 , thereby avoiding damage to the source 6 and the drain 7 during the preparation of the field plate 12 , thereby improving the electrical performance and reliability of the semiconductor device 400 .

[0175] Some embodiments of the present application also provide a method for manufacturing a semiconductor device, which is used, for example, to manufacture the semiconductor device 400 in some of the above-mentioned embodiments. FIG. 17 illustrates a flow chart of a method for manufacturing a semiconductor device; FIG. 18a-18h, FIG. 19a-19e, FIG. 20a-20d, FIG. 21a-21e, FIG. 22a-22c, FIG. 23a-23c, FIG. 24a-24c, FIG. 25a-25c, FIG. 26a-26c, FIG. 27a-27c, and FIG. 28a-28f illustrate the structures corresponding to each step in a method for manufacturing a semiconductor device. It should be understood that the steps shown in FIG. 17 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in FIG. 17. In addition, some of the steps may be performed simultaneously or in an order different from that shown in FIG. 17.

[0176] The following is a schematic illustration of the manufacturing method of the semiconductor device described above with reference to the accompanying drawings. As shown in FIG17 , the manufacturing method includes: S100 to S400.

[0177] S100 , as shown in FIG. 18 a , provides a substrate 1 having a first surface A.

[0178] For example, regarding the substrate 1, reference may be made to the relevant description above, which will not be repeated here.

[0179] S200 , as shown in FIG. 18 b , FIG. 18 c and FIG. 18 d , a channel layer 2 , a barrier layer 3 and a gate cap layer 4 are sequentially formed on the first surface A.

[0180] For example, in the embodiment of the present application, a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, a hydride vapor phase epitaxy (HVPE) process, or other suitable growth processes may be used to grow a channel layer 2 on the first surface A. Then, a barrier layer 3 may be grown on the channel layer 2 using an MBE process, an MOCVD process, an HVPE process, or other suitable growth processes. Thereafter, a gate cap film may be grown on the barrier layer 3 using an MBE process, an MOCVD process, an HVPE process, or other suitable growth processes, and then the gate cap film may be etched using a photolithography process or other suitable etching process to obtain a gate cap layer 4. The materials of the channel layer 2, the barrier layer 3, and the structure and materials of the gate cap layer 4 may refer to the relevant descriptions above and will not be repeated here.

[0181] Optionally, before forming the channel layer 2 , the embodiment of the present application may further adopt MBE process, MOCVD process, HVPE process or other suitable growth process to grow a buffer layer on the first surface A. Accordingly, the channel layer 2 is grown on the buffer layer.

[0182] S300, as shown in FIG18e, forms a first passivation layer 8 and a second passivation layer 9 on the barrier layer 3 and the gate cap layer 4. The first passivation layer 8 includes a first functional portion 81, which at least covers the sidewalls of the gate cap layer 4. The second passivation layer 9 is composed of at least two dielectric layers 9a stacked along a first direction Z. The second passivation layer 9 includes a second functional portion 91, which is located on the barrier layer 3. The second functional portion 91 is located at least on opposite sides of the gate cap layer 4 along a second direction X. The first functional portion 81 separates the second functional portion 91 from the gate cap layer 4. The first direction Z is perpendicular to the first surface A, and the second direction X is parallel to the first surface A.

[0183] For example, the materials of the first passivation layer 8 and the second passivation layer 9, the positional relationship between the first functional portion 81 and the gate cap layer 4, and the positional relationship between the second functional portion 91 and the first functional portion 81 can be found in the above description and will not be repeated here.

[0184] It can be understood that the first functional portion 81 can reduce the number of charge traps in the side walls (or side walls and part of the upper surface) in contact with it in the gate cap layer 4; or, the first functional portion 81 can reduce the hole concentration in the side walls (or side walls and part of the upper surface) in contact with it in the gate cap layer 4, thereby effectively reducing the leakage of the side walls of the gate cap layer 4 and reducing the gate leakage.

[0185] The second functional portion 91 has a better lattice match with the barrier layer 3, which can reduce the number of surface states caused by dangling bonds or atomic vacancies and suppress the charge-discharge effect in dynamic switching scenarios. Moreover, the second passivation layer 9 composed of multiple dielectric layers 9a can improve the reverse withstand voltage of the semiconductor device 400, suppress reverse leakage, reduce the dynamic on-resistance of the semiconductor device 400, and improve the dynamic characteristics of the semiconductor device 400.

[0186] 18f, a source electrode 6 and a drain electrode 7 are formed respectively penetrating the second functional portion 91 and the barrier layer 3 to the channel layer 2. Along the second direction X, the source electrode 6 and the drain electrode 7 are located on opposite sides of the gate cap layer 4.

[0187] Therefore, the preparation method of the semiconductor device provided by some embodiments of the present application forms a first passivation layer 8 and a second passivation layer 9 after forming the channel layer 2, the barrier layer 3 and the gate cap layer 4, so that the first functional part 81 in the first passivation layer 8 at least covers the side wall of the gate cap layer 4, and the second functional part 91 of the second passivation layer 9 is located on the barrier layer 3, and the first functional part 81 separates the second functional part 91 and the gate cap layer 4. The first functional part 81 of the first passivation layer 8 can be used to form a good leakage suppression effect on the side wall of the gate cap layer 4, thereby reducing gate leakage; the second functional part 91 of the second passivation layer 9 composed of at least two dielectric layers 9a stacked together can be used to suppress the charge and discharge effects in the dynamic switching scenario, reduce the dynamic on-resistance of the semiconductor device 400, and improve the device dynamic characteristics of the semiconductor device 400. That is to say, the embodiment of the present application combines the advantages of two different passivation layers, and at the same time improves the gate leakage problem and poor device dynamic characteristics of the semiconductor device 400, which can effectively improve the performance of the semiconductor device 400 and enable the semiconductor device 400 to achieve better performance under different indicators.

[0188] In some embodiments, as shown in FIG18h , the semiconductor device further includes a gate 5. Compared with the source 6 and drain 7 , the gate 5 can be formed before or after.

[0189] Optionally, the gate 5 is formed later than the source 6 and drain 7. In this case, as shown in FIG18g and FIG18h , after S400, that is, after forming the source 6 and drain 7, the manufacturing method further includes: opening a third opening K3 in the first functional portion 81, wherein the third opening K3 exposes a portion of the gate cap layer 4; and forming the gate 5, wherein a portion of the gate 5 is located within the third opening K3 and contacts the gate cap layer 4, and another portion of the gate 5 overlaps the first functional portion 81.

[0190] For example, in the embodiment of the present application, a suitable etching process such as photolithography may be used to open an opening in the first functional portion 81 , and then a metal material may be deposited in the opening. Thereafter, a suitable etching process such as photolithography may be used to define the gate 5 .

[0191] Optionally, the gate 5 is formed before the source 6 and drain 7. In this case, referring to FIG. 18 d and FIG. 19 a , before S300 , that is, before forming the first passivation layer 8 and the second passivation layer 9 , the manufacturing method further includes forming the gate 5 on the gate cap layer 4 .

[0192] For example, in the embodiment of the present application, a deposition process may be used to deposit a metal material on the gate cap layer 4, and then a suitable etching process such as a photolithography process may be used to define the gate 5. In another example, in the embodiment of the present application, a metal material may be deposited on the gate cap film, and then a suitable etching process such as a photolithography process may be used to simultaneously define the gate 5 and the gate cap layer 4.

[0193] As shown in FIG. 19 e , in the above S300 , the first functional portion 81 of the formed first passivation layer 8 also covers at least the sidewall of the gate 5 .

[0194] It is understandable that there are multiple methods for preparing the first passivation layer 8 and the second passivation layer 9 , which can be selected and set according to actual needs, and the embodiments of the present application do not limit this.

[0195] In some possible embodiments, in the above S300 , forming the first passivation layer 8 and the second passivation layer 9 on the barrier layer 3 and the gate cap layer 4 includes: S310 a - S340 a .

[0196] S310a, as shown in FIG20a and FIG20b, a sacrificial layer 16 is formed on the barrier layer 3. The sacrificial layer 16 covers the gate cap layer 4 and exposes a portion of the surface of the barrier layer 3.

[0197] For example, as shown in FIG20a , an embodiment of the present application may adopt a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an MBE process, an atomic layer deposition (ALD) process or a spin coating process to form a sacrificial film 16a on the barrier layer 3 and the gate cap layer 4, and the sacrificial film 16a covers the gate cap layer 4 and the barrier layer 3; as shown in FIG20b , a first mask M1 is then set on the sacrificial film 16a, and the sacrificial film 16a is etched (or patterned) by an etching process such as a photolithography process to remove the portion of the sacrificial film 16a in contact with the barrier layer 3, and retain the portion of the sacrificial film 16a covering the gate cap layer 4 to obtain a sacrificial layer 16.

[0198] Optionally, the sacrificial film is made of at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The sacrificial film may be a single-layer structure or a structure composed of multiple layers. The thickness of the sacrificial film ranges from 0.1 nm to 1000 nm, for example.

[0199] Optionally, as shown in FIG. 20 b , along the second direction X, the distance between any sidewall on the left or right sides of the sacrificial layer 16 and the gate cap layer 4 may be in the range of 0.1 μm-100 μm.

[0200] Exemplarily, as shown in FIG19 b , when the gate 5 is formed before the first passivation layer 8 and the second passivation layer 9 are formed, the sacrificial layer 16 also covers the gate 5 .

[0201] S320 a , as shown in FIG. 19 c and FIG. 20 c , a second passivation film 9 b is formed on the barrier layer 3 and the sacrificial layer 16 .

[0202] For example, in the embodiment of the present application, a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process can be used to deposit a dielectric material on the barrier layer 3 and the sacrificial layer 16, sequentially forming at least two dielectric films stacked along the first direction Z to obtain the second passivation film 9b. The second passivation film 9b covers the barrier layer 3 and the sacrificial layer 16 and is in direct contact with the barrier layer 3 and the sacrificial layer 16.

[0203] Optionally, in the second passivation film 9b, the material of the dielectric film closest to the barrier layer 3 includes at least one of aluminum nitride, aluminum oxide, and aluminum oxynitride, and the material of the dielectric film farthest from the barrier layer 3 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. When there are three, four, or even more dielectric films, the material of the portion of the dielectric film located between the two dielectric films includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The thickness of the second passivation film 9b ranges from 0.1 nm to 1000 nm, for example.

[0204] S330a, as shown in Figures 19d and 20d, removes the sacrificial layer 16 and the portion of the second passivation film 9b located on the sacrificial layer 16, retaining the portion of the second passivation film 9b located on the barrier layer 3, thereby obtaining the second functional portion 91 of the second passivation layer 9. In this embodiment, the second passivation layer 9 is, for example, composed of the second functional portion 91.

[0205] For example, embodiments of the present application can utilize a wet etching process to simultaneously remove the sacrificial layer 16 and the portion of the second passivation film 9b located above the sacrificial layer 16. The second passivation film 9b has pores that expose the sacrificial layer 16. The etching solution in the wet etching process can pass through these pores to etch the sacrificial layer 16, and during the etching process, the portion of the second passivation film 9b located above the sacrificial layer 16 is removed. Along the second direction X, a gap exists between the second functional portion 91 and the gate cap layer 4, and the two are not in direct contact. The second functional portion 91 is located only on opposite sides of the gate cap layer 4 along the second direction X, or the second functional portion 91 surrounds the gate cap layer 4.

[0206] Optionally, the ratio of the etching rate of the second passivation film 9b to the etching rate of the sacrificial layer 16 in the wet etching process is in the range of 1:5-1:1000. For example, the ratio may be 1:5, 1:10, 1:100, 1:250, 1:600, or 1:1000. The etching solution may be a single-element solution such as sulfuric acid, hydrochloric acid, hydrofluoric acid, nitric acid, ammonia water, or hydrogen peroxide, or a mixed solution composed of at least two single-element solutions.

[0207] 18e and 19e , a first passivation layer 8 is formed on the second functional portion 91 , the barrier layer 3 and the gate cap layer 4 . The first passivation layer 8 further includes a first shielding portion 82 connected to the first functional portion 81 , and the first shielding portion 82 covers the second functional portion 91 .

[0208] For example, in the embodiment of the present application, a dielectric material may be deposited on the second functional portion 91, the barrier layer 3, and the gate cap layer 4 using a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form the first passivation layer 8. The portion of the first passivation layer 8 that is in direct contact with the second functional portion 91 constitutes the first shielding portion 82, and the portion of the first passivation layer 8 that is in direct contact with the barrier layer 3 and the gate cap layer 4 constitutes the first functional portion 81.

[0209] Optionally, the material of the first passivation layer 8 includes at least one of silicon nitride and silicon oxynitride. Furthermore, the material of the first passivation layer 8 also includes at least one of silicon oxide, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The first passivation layer 8 may have a single-layer thin film structure or a structure composed of multiple stacked thin films. The thickness of the first passivation layer 8 ranges from 0.1 nm to 1000 nm, for example.

[0210] The material of the first passivation layer 8 is different from the material of the second passivation film 9 b. Optionally, the thickness of the second passivation film 9 b is less than the thickness of the first passivation layer 8.

[0211] It is understood that, as shown in FIG19e, when the gate 5 is formed before the first passivation layer 8 and the second passivation layer 9 are formed, the first functional portion 81 of the first passivation layer 8 also covers the gate 5. After the first passivation layer 8 is formed, as shown in FIG6 , an opening can be opened on the first functional portion 81 to expose the gate 5 to facilitate the extraction of the gate 5. In the above S400, the method of forming the source 6 and the drain 7 includes, for example: forming two openings along the second direction X that penetrate the first blocking portion 82, the second functional portion 91 and the barrier layer 3 to the channel layer 2, and then forming the source 6 and the drain 7 in the two openings, respectively.

[0212] As shown in Figures 18f-18h, when the gate 5 is formed after forming the first passivation layer 8 and the second passivation layer 9, the first functional portion 81 of the first passivation layer 8 covers the gate cap layer 4. In this case, an opening can be first formed in the first functional portion 81 to expose the gate cap layer 4, and then the gate 5 can be formed in the opening. In the above S400, the method of forming the source 6 and the drain 7 includes, for example, forming two openings along the second direction X that penetrate the first blocking portion 82, the second functional portion 91, and the barrier layer 3 to the channel layer 2, and then forming the source 6 and drain 7 in the two openings, respectively.

[0213] The above-mentioned preparation method can not only reduce the etching of the first passivation layer 8 and simplify the difficulty of preparing the first passivation layer 8; it can also use the first blocking portion 82 of the first passivation layer 8 to block and protect the second functional portion 91 of the second passivation layer 9, thereby avoiding damage to the second functional portion 91 in subsequent preparation processes (such as the preparation of the source 6 and the drain 7, the opening of the opening in the first functional portion 81, etc.), thereby avoiding affecting the improvement effect of the second functional portion 91 on the dynamic characteristics of the semiconductor device 400.

[0214] In some other possible embodiments, in the above S300 , forming the first passivation layer 8 and the second passivation layer 9 on the barrier layer 3 and the gate cap layer 4 includes: S310 b - S330 b .

[0215] S310b, as shown in FIG21a, a first passivation film 8a is formed on the barrier layer 3. The first passivation film 8a covers the gate cap layer 4 and the barrier layer 3.

[0216] For example, in the embodiment of the present application, a dielectric material may be deposited on the barrier layer 3 and the gate cap layer 4 by using a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form the first passivation film 8 a.

[0217] Optionally, the first passivation film 8a may be a single-layer film structure or a structure composed of multiple layers of films. The thickness of the first passivation film 8a ranges from 0.1 nm to 1000 nm, for example.

[0218] S320b, as shown in FIG21b and FIG22a, a portion of the first passivation film 8a is removed to expose the barrier layer 3, thereby obtaining the first functional portion 81 of the first passivation layer 8. In this embodiment, the first passivation layer 8 is composed of the first functional portion 81, for example.

[0219] Illustratively, in an embodiment of the present application, a second mask M2 may be set on the first passivation film 8a, and the first passivation film 8a may be etched using an etching process such as a photolithography process to remove the portion of the first passivation film 8a in contact with the barrier layer 3, while retaining the portion of the first passivation film 8a covering the gate cap layer 4, thereby obtaining the first functional portion 81 of the first passivation layer 8.

[0220] Optionally, as shown in FIG. 21 b , along the second direction X, the distance between any sidewall on the left or right sides of the first functional portion 81 and the gate cap layer 4 may be in the range of 0.1 μm to 100 μm.

[0221] S330b, as shown in FIG21c and FIG22b, a second passivation layer 9 is formed on the first functional portion 81 and the barrier layer 3. The second passivation layer 9 further includes a second shielding portion 92 connected to the second functional portion 91, and the second shielding portion 92 covers the first functional portion 81.

[0222] For example, in the embodiments of the present application, a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process may be used to deposit a dielectric material on the first functional portion 81 and the barrier layer 3, sequentially forming at least two dielectric layers stacked along the first direction Z to obtain the second passivation layer 9. The portion of the second passivation layer 9 that is located on the first functional portion 81 and in direct contact with the first functional portion 81 constitutes the second shielding portion 92, and the portion of the second passivation layer 9 that is located on the barrier layer 3 and in direct contact with the barrier layer 3 constitutes the second functional portion 91.

[0223] Optionally, in the second passivation layer 9, the material of the dielectric layer closest to the barrier layer 3 includes at least one of aluminum nitride, aluminum oxide, and aluminum oxynitride, and the material of the dielectric layer farthest from the barrier layer 3 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. When the number of dielectric layers is three, four, or even more, the material of the dielectric layer located between the two dielectric layers includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The thickness of the second passivation layer 9 ranges from 0.1 nm to 1000 nm, for example.

[0224] The material of the second passivation layer 9 is different from the material of the first passivation film 8a. Optionally, the thickness of the second passivation layer 9 is less than the thickness of the first passivation film 8a.

[0225] It is understood that, as shown in FIG21e, when the gate 5 is formed after forming the first passivation layer 8 and the second passivation layer 9, the first functional portion 81 of the first passivation layer 8 and the second blocking portion 92 of the second passivation layer 9 both cover the gate cap layer 4. In this case, an opening can be first formed through the second blocking portion 92 and the first functional portion 81 to expose the gate cap layer 4, and then the gate 5 can be formed within the opening. As shown in FIG21e, in the above S400, the method of forming the source 6 and the drain 7, for example, includes: forming two openings along the second direction X through the second functional portion 91 and the barrier layer 3 to the channel layer 2, and then forming the source 6 and drain 7 within the two openings, respectively.

[0226] As shown in FIG22a, when the gate 5 is formed before forming the first passivation layer 8 and the second passivation layer 9, the first functional portion 81 of the first passivation layer 8 also covers the gate 5. After forming the first passivation layer 8 and the second passivation layer 9, as shown in FIG22c, an opening can be formed through the second blocking portion 92 of the second passivation layer 9 and the first functional portion 81 of the first passivation layer 8 to expose the gate 5 for facilitating the extraction of the gate 5. As shown in FIG22c, in the above-mentioned S400, the method of forming the source 6 and the drain 7, for example, includes: forming two openings along the second direction X, penetrating the second functional portion 91 and the barrier layer 3 to the channel layer 2, and then forming the source 6 and the drain 7 in the two openings, respectively.

[0227] The above-described preparation method not only reduces etching of the second passivation layer 9 and simplifies the preparation of the second passivation layer 9, but also utilizes the second shielding portion 92 of the second passivation layer 9 to shield and protect the first passivation layer 8, thereby preventing damage to the first passivation layer 8 during subsequent preparation processes, thereby preventing the first passivation layer 8 from affecting the gate leakage suppression effect of the semiconductor device 400. Furthermore, this method is beneficial for simplifying the preparation process of the semiconductor device and improving the preparation efficiency of the semiconductor device.

[0228] In this embodiment, with reference to Figures 21c, 21d, and 21e, after forming the second passivation layer 9 and before forming the source electrode 6 and the drain electrode 7, the above-mentioned preparation method further includes, for example: depositing a dielectric material on the second passivation layer 9 using a process such as a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form a fourth passivation layer 11. The fourth passivation layer 11 covers the second passivation layer 9. The orthographic projection of the fourth passivation layer 11 on the first surface A, for example, coincides with the orthographic projection of the second passivation layer 9 on the first surface A. The source electrode 6 and the drain electrode 7 also respectively penetrate the fourth passivation layer 11.

[0229] In this way, the fourth passivation layer 11 can be used to shield and protect the second passivation layer 9, avoiding damage to the second passivation layer 9 in subsequent preparation processes (such as the preparation of the source 6 and the drain 7, the opening through the second shielding part 92 and the first functional part 81, etc.), and ensuring that the second passivation layer 9 can well improve the device dynamic characteristics of the semiconductor device 400.

[0230] In some further possible embodiments, in the above S300 , forming the first passivation layer 8 and the second passivation layer 9 on the barrier layer 3 and the gate cap layer 4 includes: S310 c - S330 c .

[0231] S310 c , as shown in FIG. 23 a , a second passivation film 9 b is formed on the barrier layer 3 and the gate cap layer 4 .

[0232] For example, the formation process, materials, thickness, etc. of the second passivation film 9b can be found in the relevant description in S320a above, and will not be repeated here.

[0233] S320c, as shown in FIG23b, remove the portion of the second passivation film 9b covering the gate cap layer 4 and expose the barrier layer 3 to obtain the second functional portion 91 of the second passivation layer 9. In this embodiment, the second passivation layer 9 is composed of the second functional portion 91, for example.

[0234] For example, in this embodiment of the present application, a third mask M3 may be disposed on the second passivation film 9b, and the second passivation film 9b may be etched using an etching process such as photolithography. Along the second direction X, a gap exists between the second functional portion 91 and the gate cap layer 4, and the two do not directly contact each other. The second functional portion 91 is located only on two opposite sides of the gate cap layer 4 along the second direction X, or the second functional portion 91 surrounds the gate cap layer 4.

[0235] Optionally, as shown in FIG. 23 b , along the second direction X, the distance between the second functional portion 91 and the gate cap layer 4 may be in the range of 0.1 μm-100 μm.

[0236] 23c , a first passivation layer 8 is formed on the second functional portion 91 , the barrier layer 3 and the gate cap layer 4 . The first passivation layer 8 further includes a first shielding portion 82 connected to the first functional portion 81 , and the first shielding portion 82 covers the second functional portion 91 .

[0237] For example, the formation process, materials, thickness, etc. of the first passivation layer 8 can be found in the relevant description in the above S340a, which will not be repeated here.

[0238] The above method for preparing and forming the first passivation layer 8 and the second passivation layer 9 is relatively simple and easy to implement, which is beneficial to improving the preparation efficiency of semiconductor devices.

[0239] In some embodiments, before the above S320c, that is, before removing the portion of the second passivation film 8a covering the gate cap layer 4, as shown in Figures 24a and 25a, the above preparation method further includes: forming a third passivation film 10a on the second passivation film 8a.

[0240] For example, in the embodiment of the present application, a dielectric material may be deposited on the second passivation film 8a using a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form a third passivation film 10a. As shown in Figures 24a and 25a, the third passivation film 10a covers the second passivation film 9b and is in direct contact with the second passivation film 9b.

[0241] Optionally, the material of the third passivation film 10a includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The third passivation film 10a may have a single-layer structure or a structure composed of multiple layers. The thickness of the third passivation film 10a ranges from 0.1 nm to 1000 nm, for example.

[0242] In the above S320c, as shown in FIG. 24b and FIG. 25b, removing the portion of the second passivation film 9b covering the gate cap layer 4 includes: simultaneously removing the portion of the third passivation film 10a and the second passivation film 9b covering the gate cap layer 4.

[0243] For example, in the embodiment of the present application, the third mask M3 can be used to simultaneously etch the third passivation film 10a and the second passivation film 9b using an etching process such as a photolithography process, thereby simultaneously obtaining the third passivation layer 10 and the second passivation layer 9. The orthographic projection of the third passivation layer 10 on the first surface A coincides with the orthographic projection of the second functional portion 91 on the first surface A.

[0244] In the above S330 c , as shown in FIG. 24 c and FIG. 25 c , the formed first passivation layer 8 also covers the third passivation layer 10 .

[0245] This not only avoids adding an additional etching step, but also allows the third passivation film 10a to shield the second passivation film 9b, thereby protecting the second functional portion 91 during the etching process to form the second functional portion 91 and preventing damage to the second functional portion 91. Furthermore, the provision of the third passivation layer 10 increases the dielectric thickness around the source 6 and drain 7, i.e., increases the distance between the surface of the first shielding portion 82 away from the first surface A and the first surface A (this distance may be referred to as the first distance), and reduces the difference between the first distance and the second distance (i.e., the distance between the surface of the portion of the first functional portion 81 located on the gate cap layer 4 away from the first surface A and the first surface A). This helps improve the overall flatness of the semiconductor device 400 and enhances its compatibility with subsequent processes.

[0246] It can be understood that, in conjunction with Figure 24c and Figure 9, when the gate 5 is formed after forming the first passivation layer 8 and the second passivation layer 9, the first functional portion 81 of the first passivation layer 8 covers the gate cap layer 4. In this case, an opening can be first opened in the first functional portion 81 to expose the gate cap layer 4, and then the gate 5 is formed in the opening. In the above S400, the method of forming the source 6 and the drain 7 includes, for example: forming two openings along the second direction X that penetrate the first blocking portion 82, the third passivation layer 10, the second functional portion 91, and the barrier layer 3 to the channel layer 2, and then forming the source 6 and drain 7 in the two openings, respectively.

[0247] In conjunction with FIG25c and FIG10, when the gate 5 is formed before forming the first passivation layer 8 and the second passivation layer 9, the first functional portion 81 of the first passivation layer 8 also covers the gate 5. After forming the first passivation layer 8, an opening can be opened on the first functional portion 81 to expose the gate 5 to facilitate the extraction of the gate 5. In the above S400, the method of forming the source 6 and the drain 7 includes, for example: forming two openings along the second direction X that penetrate the first blocking portion 82, the third passivation layer 10, the second functional portion 91, and the barrier layer 3 to the channel layer 2, and then forming the source 6 and the drain 7 in the two openings, respectively.

[0248] The above-mentioned preparation method can not only reduce the etching of the first passivation layer 8 and simplify the difficulty of preparing the first passivation layer 8; it can also use the first blocking portion 82 of the first passivation layer 8 to block the third passivation layer 10 and the second functional portion 91, providing further protection for the second functional portion 91, avoiding damage to the second functional portion 91 in subsequent preparation processes (such as the preparation of the source 6 and the drain 7, the opening of the opening in the first functional portion 81, etc.), and thereby avoiding affecting the improvement effect of the second functional portion 91 on the device dynamic characteristics of the semiconductor device 400.

[0249] In some embodiments, the semiconductor device 400 further includes a field plate 12 . Along the second direction X, the field plate 12 is, for example, located between the gate cap layer 4 and the drain electrode 7 . Based on this, the above manufacturing method further includes: forming the field plate 12 between the gate cap layer 4 and the drain electrode 7 .

[0250] The formation of the field plate 12 can generate an additional potential between the drain 7 and the gate 5 to modulate the channel electric field distribution in the semiconductor device 400, adjust and slow down the electric field peak between the gate 5 and the drain 7, thereby improving the breakdown voltage and reliability of the semiconductor device 400.

[0251] It is understood that there are multiple methods for preparing the field plate 12, which can be selected and set according to actual needs, and the present embodiment does not limit this. The present embodiment takes the first passivation layer 8 including the first functional portion 81 and the first shielding portion 82 connected to each other, and the first shielding portion 82 covering the second functional portion 91 as an example to schematically illustrate the method for preparing the field plate 12.

[0252] In some possible embodiments, after S400, that is, after forming the source electrode 6 and the drain electrode 7, the manufacturing method further includes S500a-S600a. In particular, FIG26a-26c takes the example of forming the gate 5 after the first passivation layer 8, but the present invention is not limited thereto.

[0253] S500a, as shown in FIG26a, a first protective layer 13 is formed on the first passivation layer 8. The first protective layer 13 also covers the source electrode 6 and the drain electrode 7.

[0254] For example, in the embodiment of the present application, a dielectric material may be deposited on the first passivation layer 8 using a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form the first protective layer 13. The first protective layer 13 covers the first passivation layer 8, the source electrode 6, and the drain electrode 7, and is in direct contact with the first passivation layer 8, the source electrode 6, and the drain electrode 7.

[0255] Optionally, the material of the first protective layer 13 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The first protective layer 13 may have a single-layer thin film structure or a structure composed of multiple stacked thin films. The thickness of the first protective layer 13 ranges from 0.1 nm to 1000 nm, for example.

[0256] S600a, as shown in FIG26b, forms a field plate 12 on the first protective layer 13. Along a direction perpendicular to the first surface A, a portion of the field plate 12 is located on the first functional portion 81, and another portion of the field plate 12 is located on the first shielding portion 82. Along the second direction X, the field plate 12 is located between the gate cap layer 4 and the drain 7.

[0257] Illustratively, in an embodiment of the present application, a PVD process or other process may be used to deposit metal material on the first protective layer 13 to form a metal film, which covers the first passivation layer 8; the thickness of the metal film is relatively uniform, and its morphology is basically consistent with the surface morphology of the side of the first passivation layer 8 away from the substrate 1; and then an etching process such as a photolithography process is used to etch the metal film, retaining a portion of the metal film located between the gate cap layer 4 and the drain 7, and at the same time located on the first functional portion 81 and the first blocking portion 82, to obtain a field plate 12.

[0258] Continuing with FIG. 26 b , since a portion of the first functional portion 81 is located between the gate cap layer 4 and the second functional portion 91 of the second passivation layer 9 and is in direct contact with the barrier layer 3, and other structures (e.g., the second functional portion 91 and the third passivation layer 10) are interposed between the first shielding portion 82 and the barrier layer 3, there is a height difference between the upper surface of the portion of the first functional portion 81 located between the gate cap layer 4 and the second functional portion 91 (i.e., the side facing away from the substrate 1) and the upper surface of the first shielding portion 82 (i.e., the side facing away from the substrate 1). This creates a step-like structure between the portion of the first functional portion 81 located between the gate cap layer 4 and the second functional portion 91 and the first shielding portion 82. Consequently, the field plate 12 located on the first passivation layer 8 also exhibits a step-like structure. With respect to the first surface A, the portion of the field plate 12 located on the first functional portion 81 is lower than the portion of the field plate 12 located on the first shielding portion 82.

[0259] Relative to the first surface A, a height difference between a portion of the field plate 12 located on the first functional portion 81 and a portion of the field plate 12 located on the first blocking portion 82 may be determined according to the structure between the first blocking portion 82 and the barrier layer 3 .

[0260] The above-described fabrication method not only allows the first protective layer 13 to protect the source 6 and drain 7, preventing damage to the source 6 and drain 7 during the fabrication of the field plate 12, but also effectively regulates the electric field on the side of the gate 5 closest to the drain 7 by limiting the formation position of the field plate 12, thereby further adjusting and reducing the peak electric field between the gate 5 and the drain 7. This helps further improve the breakdown voltage, electrical performance, and reliability of the semiconductor device 400.

[0261] In the above embodiment, as shown in FIG26c, after forming the field plate 12, an opening can be formed through the first protective layer 13 and the first functional portion 81 to the gate cap layer 4 to expose the gate cap layer 4; the gate 5 can then be formed within the opening. Alternatively, referring to FIG26b and FIG14, after forming the field plate 12, a first opening K1 can be opened in the first protective layer 13 to expose the source 6 and drain 7, respectively, to facilitate subsequent extraction of the source 6 and drain 7.

[0262] In some other possible embodiments, before S400, that is, before forming the source electrode 6 and the drain electrode 7, the above-mentioned preparation method further includes: S380-S390. In particular, Figures 27a-27c take the example of forming the gate 5 after the first passivation layer 8 as an example, but the present invention is not limited to this.

[0263] S380, as shown in FIG27a, forms a field plate 12 on the first passivation layer 8. Along a direction perpendicular to the first surface A, a portion of the field plate 12 is located on the first functional portion 81, and another portion of the field plate 12 is located on the first shielding portion 82. Along the second direction X, the field plate 12 is located between the gate cap layer 4 and the drain 7.

[0264] For example, the formation process, materials, thickness, etc. of the field plate 12 can be found in the relevant description in S600a above, and will not be repeated here.

[0265] S390 , as shown in FIG. 27 b , forming a second protection layer 14 on the field plate 12 and the first passivation layer 8 .

[0266] For example, in the embodiment of the present application, a dielectric material may be deposited on the field plate 12 and the first passivation layer 8 using a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form the second protective layer 14. The second protective layer 14 covers the field plate 12 and the first passivation layer 8 and is in direct contact with the field plate 12 and the first passivation layer 8.

[0267] Optionally, the material of the second protective layer 14 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The second protective layer 14 may have a single-layer thin film structure or a structure composed of multiple stacked thin films. The thickness of the second protective layer 14 ranges from 0.1 nm to 1000 nm, for example.

[0268] Thus, during the process of forming the source electrode 6 and the drain electrode 7 in S400, the second protective layer 14 can be used to protect the field plate 12, thereby preventing damage to the field plate 12 during the process of forming the source electrode 6 and the drain electrode 7, thereby improving the electrical performance and reliability of the semiconductor device 400. In addition, by limiting the formation position of the field plate 12, it is helpful to regulate the electric field on the side of the gate 5 close to the drain electrode 7, thereby further adjusting and reducing the peak electric field between the gate 5 and the drain electrode 7, and further improving the breakdown voltage, electrical performance, and reliability of the semiconductor device 400.

[0269] In the above embodiment, as shown in FIG27 c , after forming the second protective layer 14, a source electrode 6 and a drain electrode 7 can be formed, respectively penetrating the second protective layer 14, the first blocking portion 82, the second functional portion 91, the barrier layer 3, and the channel layer 2. Alternatively, referring to FIG27 b and FIG15 , after forming the second protective layer 14, an opening can be formed penetrating the second protective layer 14 and the first functional portion 81 to the gate cap layer 4 to expose the gate cap layer 4; and then, a gate 5 can be formed in the opening.

[0270] In some other possible embodiments, the source electrode 6 and the drain electrode 7 are formed after the second passivation layer 9 and before the first passivation layer 8. In particular, Figures 28a to 28f take the example of the gate electrode 5 being formed after the first passivation layer 8, but the present invention is not limited thereto.

[0271] In this case, as shown in FIG. 23 a , in the above S300 , forming the second passivation layer 9 includes forming a second passivation film 9 b on the barrier layer 3 and the gate cap layer 4 .

[0272] For example, the formation process, materials, thickness, etc. of the second passivation film 9b can be found in the relevant description in S320a above, and will not be repeated here.

[0273] 23 a and 28 a , after forming the second passivation film 9 b , a source electrode 6 and a drain electrode 7 may be formed respectively penetrating the second passivation film 9 b , the barrier layer 3 and the channel layer 2 .

[0274] After the above S400 , that is, after the source electrode 6 and the drain electrode 7 are formed, the above preparation method further includes: S500 b - S600 b .

[0275] S500 b , as shown in FIG. 28 b , a third protection layer 15 is formed on the second passivation film 9 b . The third protection layer 15 also covers the source electrode 6 and the drain electrode 7 .

[0276] For example, in the embodiment of the present application, a dielectric material may be deposited on the second passivation film 9 b using a CVD process, a PVD process, an MBE process, an ALD process, or a spin coating process to form a third protective layer 15. The third protective layer 15 covers the second passivation film 9 b, the source electrode 6, and the drain electrode 7, and is in direct contact with the second passivation film 9 b, the source electrode 6, and the drain electrode 7.

[0277] Optionally, the material of the third protective layer 15 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide, titanium dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, nickel oxide, and gallium oxide. The third protective layer 15 may have a single-layer thin film structure or a structure composed of multiple stacked thin films. The thickness of the third protective layer 15 ranges from 0.1 nm to 1000 nm, for example.

[0278] S600b, as shown in FIG28c, remove the second passivation film 9b and the portion of the third protection layer 15 covering the gate cap layer 4, and expose the barrier layer 3.

[0279] For example, in the embodiment of the present application, an etching process such as a photolithography process can be used to simultaneously etch the second passivation film 9b and the third protective layer 15. The orthographic projection of the etched third protective layer 15 on the first surface A coincides with the orthographic projection of the second functional portion 91 of the etched second passivation layer 9 on the first surface A. The etched third protective layer 15 still covers the source electrode 6 and the drain electrode 7.

[0280] In S300, as shown in FIG28d, after forming the first passivation layer 8, the first passivation layer 8 covers the gate cap layer 4, the barrier layer 3, and the third protective layer 15. As shown in FIG28e, the above-mentioned preparation method includes: forming a field plate 12 on the first passivation layer 8. In a direction perpendicular to the first surface A, a portion of the field plate 12 is located on the first functional portion 81, and another portion of the field plate 12 is located on the first shielding portion 82. In the second direction X, the field plate 12 is located between the gate cap layer 4 and the drain 7.

[0281] For example, the formation process, materials, thickness, etc. of the field plate 12 can be found in the relevant description in S600a above, and will not be repeated here.

[0282] Using the above-described fabrication method, the third protective layer 15 and the first passivation layer 8 can simultaneously protect the source 6 and drain 7, preventing damage to the source 6 and drain 7 during the fabrication of the field plate 12, thereby improving the electrical performance and reliability of the semiconductor device 400. Furthermore, by defining the formation position of the field plate 12, it is advantageous to regulate the electric field on the side of the gate 5 closest to the drain 7, thereby further adjusting and reducing the peak electric field between the gate 5 and the drain 7, further improving the breakdown voltage, electrical performance, and reliability of the semiconductor device 400.

[0283] In the above embodiment, as shown in FIG28f, after forming the field plate 12, a second opening K2 can be formed through the first blocking portion 82 of the first passivation layer 8 and the third protective layer 15 to expose the source 6 and drain 7, respectively, to facilitate the subsequent extraction of the source 6 and drain 7. Alternatively, referring to FIG28e and FIG16, after forming the field plate 12, an opening can be formed through the first functional portion 81 of the first passivation layer 8 to the gate cap layer 4 to expose the gate cap layer 4; the gate 5 can then be formed within this opening.

[0284] The present application also provides a power switch device, as shown in FIG29 , comprising a package substrate 510 and a semiconductor device 400 , such as the semiconductor device 400 described in any of the above embodiments. The semiconductor device 400 is electrically connected to the package substrate 510 .

[0285] Exemplarily, the power switch device 500 may further include a first connector 520, through which the semiconductor device 400 may be connected to the package substrate 510. The first connector 520 may be, for example, a controlled collapse chip connection bump (C4 bump) or a micro bump. Furthermore, the power switch device 500 may further include a second connector 530, through which the package substrate 510 in the power switch device 500 may be connected to other electronic devices, such as a printed circuit board, via the second connector 530. The second connector 530 may be, for example, a solder ball or a micro bump.

[0286] In this way, communication between the semiconductor device 400 and other electronic devices can be achieved.

[0287] The present application also provides a power conversion circuit. As shown in FIG30 , the power conversion circuit 600 includes a circuit board 610 and a power switch 500 . The power switch 500 may be, for example, any of the power switches 500 described in the aforementioned embodiments. The power switch 500 and the circuit board 610 are electrically connected.

[0288] For example, the circuit board 610 may be a printed circuit board. The power conversion circuit 600 may be a step-down (Buck) power conversion circuit, a step-up (Boots) power conversion circuit, a voltage regulator (WS), a low-dropout (LDO) regulator, or other power conversion circuits. The embodiments of the present application do not impose any particular restrictions on the specific form of the power conversion circuit 600.

[0289] Embodiments of the present application also provide an electronic device. This electronic device may include a housing and a power conversion circuit, such as the power conversion circuit 600 described in any of the aforementioned embodiments. The power conversion circuit is housed within the housing. This electronic device may include a power adapter, a switching power supply, a computing device, a display module, a vehicle-mounted mobile device, or the like. The embodiments of the present application do not impose any particular limitations on the specific form of the electronic device.

[0290] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this disclosure should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a substrate having a first surface; a channel layer located on the first surface; a barrier layer, located on the channel layer; a gate cap layer, located on the barrier layer; A first passivation layer includes a first functional portion; the first functional portion at least covers a sidewall of the gate cap layer; a second passivation layer formed by stacking at least two dielectric layers along a first direction; the second passivation layer includes a second functional portion, the second functional portion is located on the barrier layer and at least on two opposite sides of the gate cap layer along the second direction, the first functional portion separating the second functional portion from the gate cap layer; the first direction is perpendicular to the first surface, and the second direction is parallel to the first surface; The source and the drain respectively penetrate the second functional portion and the barrier layer to the channel layer; along the second direction, the source and the drain are respectively located on two opposite sides of the gate cap layer.

2. The semiconductor device according to claim 1, wherein Along the first direction, the dielectric layer closest to the barrier layer among the at least two dielectric layers is the first dielectric layer, and the dielectric layer farthest from the barrier layer is the second dielectric layer; The breakdown field strength of the first dielectric layer is smaller than the breakdown field strength of the second dielectric layer; and / or the dielectric constant of the first dielectric layer is larger than the dielectric constant of the second dielectric layer.

3. The semiconductor device according to claim 2, wherein The material of the first dielectric layer includes at least one of aluminum nitride, aluminum oxide, and aluminum oxynitride. The material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The material of the first passivation layer includes at least one of silicon nitride and silicon oxynitride.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The first passivation layer further includes a first shielding portion, wherein the first shielding portion is connected to the first functional portion and covers the second functional portion; The source electrode and the drain electrode also penetrate the first shielding portion respectively.

6. The semiconductor device according to claim 5, wherein The semiconductor device further includes a third passivation layer, the third passivation layer being located between the second functional portion and the first shielding portion; an orthographic projection of the third passivation layer on the first surface coincides with an orthographic projection of the second functional portion on the first surface; The source electrode and the drain electrode also penetrate the third passivation layer respectively.

7. The semiconductor device according to claim 5 or 6, characterized in that The semiconductor device further includes a field plate; along the second direction, the field plate is located between the gate cap layer and the drain; A portion of the field plate is located on the first functional portion, and another portion of the field plate is located on the first shielding portion.

8. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a first protection layer, wherein the first protection layer is located between the first passivation layer and the field plate; A first opening is formed in the first protection layer, and the first opening exposes the source electrode and the drain electrode.

9. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a second protective layer, the second protective layer covering the first passivation layer and the field plate; The source electrode and the drain electrode also penetrate the second protection layer respectively.

10. The semiconductor device according to claim 7, wherein The semiconductor device further includes a third protective layer, wherein the third protective layer is located between the second functional portion and the first shielding portion; A second opening is formed in the first shielding portion and the third protective layer, and the second opening exposes the source electrode and the drain electrode.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that The second passivation layer further includes a second blocking portion connected to the second functional portion and covering the first functional portion.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that Along the second direction, a distance between the second functional portion and the gate cap layer ranges from 0.1 μm to 100 μm.

13. The semiconductor device according to any one of claims 1 to 12, wherein: The thickness of the second passivation layer is smaller than the thickness of the first passivation layer.

14. The semiconductor device according to any one of claims 1 to 13, wherein: The thickness of the first passivation layer is in the range of 0.1 nm to 1000 nm; and / or, The thickness of the second passivation layer is in the range of 0.1 nm to 1000 nm.

15. The semiconductor device according to any one of claims 1 to 14, characterized in that The semiconductor device further includes a gate; A third opening is formed in the first functional portion, a portion of the gate is located in the third opening and in contact with the gate cap layer, and another portion of the gate is overlapped on the first functional portion; or, The gate is located between the gate cap layer and the first functional portion.

16. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: providing a substrate having a first surface; forming a channel layer, a barrier layer and a gate cap layer in sequence on the first surface; A first passivation layer and a second passivation layer are formed on the barrier layer and the gate cap layer; the first passivation layer includes a first functional portion, the first functional portion at least covering a sidewall of the gate cap layer; the second passivation layer is formed by stacking at least two dielectric layers along a first direction, the second passivation layer includes a second functional portion, the second functional portion is located on the barrier layer and at least on two opposite sides of the gate cap layer along a second direction, the first functional portion separating the second functional portion from the gate cap layer; the first direction is perpendicular to the first surface, and the second direction is parallel to the first surface; A source electrode and a drain electrode are formed respectively penetrating the second functional portion and the barrier layer to the channel layer; along the second direction, the source electrode and the drain electrode are respectively located on opposite sides of the gate cap layer.

17. The preparation method according to claim 16, characterized in that The first passivation layer further includes a first shielding portion, wherein the first shielding portion is connected to the first functional portion and covers the second functional portion; After forming the source electrode and the drain electrode, the preparation method further includes: forming a first protective layer on the first passivation layer; the first protective layer also covers the source electrode and the drain electrode; A field plate is formed on the first protective layer; along a direction perpendicular to the first surface, a portion of the field plate is located on the first functional portion, and another portion of the field plate is located on the first shielding portion; along the second direction, the field plate is located between the gate cap layer and the drain.

18. The preparation method according to claim 16, characterized in that The first passivation layer further includes a first shielding portion, wherein the first shielding portion is connected to the first functional portion and covers the second functional portion; Before forming the source electrode and the drain electrode, the preparation method includes: forming a field plate on the first passivation layer; along a direction perpendicular to the first surface, a portion of the field plate is located on the first functional portion, and another portion of the field plate is located on the first shielding portion; along the second direction, the field plate is located between the gate cap layer and the drain; A second protection layer is formed on the field plate and the first passivation layer.

19. The preparation method according to claim 16, characterized in that The first passivation layer further includes a first shielding portion, wherein the first shielding portion is connected to the first functional portion and covers the second functional portion; The source electrode and the drain electrode are formed behind the second passivation layer and before the first passivation layer; Forming the second passivation layer includes: forming a second passivation film on the barrier layer and the gate cap layer; After forming the source electrode and the drain electrode, the preparation method includes: forming a third protective layer on the second passivation film, wherein the third protective layer also covers the source electrode and the drain electrode; removing the second passivation film and the portion of the third protective layer covering the gate cap layer, and exposing the barrier layer; After forming the first passivation layer, the preparation method includes: A field plate is formed on the first passivation layer; along a direction perpendicular to the first surface, a portion of the field plate is located on the first functional portion, and another portion of the field plate is located on the first shielding portion; along the second direction, the field plate is located between the gate cap layer and the drain.

20. The preparation method according to any one of claims 16 to 19, characterized in that: After forming the source electrode and the drain electrode, the preparation method further includes: opening a third opening on the first functional portion; forming a gate; a portion of the gate is located within the third opening and in contact with the gate cap layer, and another portion of the gate is overlapped on the first functional portion; or, Before forming the first passivation layer and the second passivation layer, the preparation method further includes: A gate is formed on the gate cap layer.

21. A power switching device, characterized in that: The power switching device includes a packaging substrate and a semiconductor device electrically connected to the packaging substrate; the semiconductor device is the semiconductor device according to any one of claims 1 to 15.

22. A power conversion circuit, characterized in that: The power conversion circuit includes a circuit board and a power switching device electrically connected to the circuit board; the power switching device is the power switching device as claimed in claim 21.

23. An electronic device, characterized in that: The electronic device includes: a housing, and a power conversion circuit housed in the housing; the power conversion circuit is the power conversion circuit as claimed in claim 22.

24. An electronic device, characterized in that: The electronic device includes: a power switching device and a circuit board electrically connected to the power switching device; the power switching device is the power switching device according to claim 21.

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