Double-layer component having isolation structure, and semiconductor device

Abstract

A double-layer component having an isolation structure, and a semiconductor device. The double-layer component comprises an upper structure, a lower structure, and an isolation structure located between the upper structure and the lower structure. The isolation structure comprises: a main dielectric layer, located between the lower structure and the upper structure; and a first buffer structure, located on the main dielectric layer and comprising a first buffer layer and a second buffer layer, wherein the material of the second buffer layer comprises silicon nitride and / or silicon oxynitride, and the dielectric constant of the first buffer layer is greater than that of the second buffer layer. By providing the double-layer first buffer structure between the main dielectric layer and the upper structure, wherein the first buffer layer has a higher dielectric constant, the surface electric field intensity can be effectively reduced, thereby improving the withstand voltage of the double-layer component.

Description

Double-layer components and semiconductor devices with isolation structure Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a double-layer component with an isolation structure, and also to a semiconductor device. Background Art

[0002] In the semiconductor integration process, an exemplary capacitor uses silicon dioxide as an isolation medium between its upper and lower plates for capacitance isolation (capacitance isolation). By increasing the thickness of the silicon dioxide, the voltage resistance between the upper and lower plates can be improved. Since the metal etching of the upper plate will cause more defects on the surface of the etched material, the high electric field area of ​​the upper plate is prone to dielectric breakdown first, thereby limiting the voltage resistance of the entire capacitor.

[0003] Similarly, an exemplary transformer uses silicon dioxide as the insulating dielectric between its upper and lower coils. Increasing the thickness of the silicon dioxide can improve the withstand voltage of the upper and lower coils. However, because metal etching of the upper coil creates numerous surface defects, dielectric breakdown occurs first in the high-electric-field region of the upper coil, limiting the withstand voltage of the entire transformer.

[0004] Summary of the Invention

[0005] Based on this, it is necessary to provide a double-layer component with an isolation structure and higher withstand voltage.

[0006] A double-layer component with an isolation structure includes an upper structure, a lower structure, and an isolation structure located between the upper and lower structures. The isolation structure includes: a main dielectric layer located between the lower structure and the upper structure; a first buffer structure located on the main dielectric layer and including a first buffer layer and a second buffer layer, wherein the second buffer layer is made of silicon nitride and / or silicon oxynitride, and the dielectric constant of the first buffer layer is greater than the dielectric constant of the second buffer layer.

[0007] The above-mentioned double-layer component with an isolation structure is provided with a double-layer first buffer structure between the main dielectric layer and the upper structure, wherein the first buffer layer has a higher dielectric constant. Through the combined action of the first buffer layer and the second buffer layer, the surface electric field strength can be effectively reduced, thereby improving the withstand voltage of the double-layer component.

[0008] In one embodiment, the material of the first buffer layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide.

[0009] In one embodiment, the double-layer component is a transformer, the upper structure is an upper coil, and the lower structure is a lower coil.

[0010] In one embodiment, the double-layer component is a capacitor, the upper structure is an upper plate, and the lower structure is a lower plate.

[0011] In one embodiment, the second buffer layer is located on the first buffer layer.

[0012] In one embodiment, the first buffer layer is located on the second buffer layer.

[0013] In one embodiment, the isolation structure also includes a second buffer structure, which is located between the lower structure and the main dielectric layer. The second buffer structure includes a third buffer layer and a fourth buffer layer. The material of the fourth buffer layer includes silicon nitride and / or silicon oxynitride, and the dielectric constant of the third buffer layer is greater than the dielectric constant of the fourth buffer layer.

[0014] In one embodiment, the material of the third buffer layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide.

[0015] In one embodiment, the fourth buffer layer is located between the lower structure and the third buffer layer.

[0016] In one embodiment, the third buffer layer is located between the lower structure and the fourth buffer layer.

[0017] In one embodiment, the double-layer component with an isolation structure also includes a third buffer structure, the lower structure is located on the third buffer structure, the third buffer structure includes a fifth buffer layer and a sixth buffer layer, the material of the sixth buffer layer includes silicon nitride and / or silicon oxynitride, and the dielectric constant of the fifth buffer layer is greater than the dielectric constant of the sixth buffer layer.

[0018] In one embodiment, the material of the fifth buffer layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide. In one embodiment, the double-layer component with an isolation structure further includes a fourth buffer structure, the fourth buffer structure being located on the upper structure, the fourth buffer structure including a seventh buffer layer and an eighth buffer layer, the eighth buffer layer being made of silicon nitride and / or silicon oxynitride, and the dielectric constant of the seventh buffer layer being greater than the dielectric constant of the eighth buffer layer.

[0019] In one embodiment, the material of the seventh buffer layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide.

[0020] In one embodiment, the sixth buffer layer is located between the lower structure and the fifth buffer layer.

[0021] In one embodiment, the fifth buffer layer is located between the lower structure and the sixth buffer layer.

[0022] In one embodiment, the eighth buffer layer is located between the upper structure and the seventh buffer layer.

[0023] In one embodiment, the seventh buffer layer is located between the upper structure and the eighth buffer layer.

[0024] In one embodiment, a passivation layer is further included, and the passivation layer covers at least a portion of the upper structure.

[0025] In one embodiment, the main dielectric layer includes a silicon oxide layer.

[0026] In one embodiment, the thickness of the main dielectric layer is greater than 3 microns.

[0027] In one embodiment, the upper coil and the lower coil are both made of copper and aluminum.

[0028] There is also a need to provide a semiconductor device.

[0029] A semiconductor device includes a double-layer component region and a low-voltage region, wherein the low-voltage region includes a low-voltage device, and the double-layer component region includes the double-layer component with an isolation structure as described in any of the aforementioned embodiments.

[0030] The above-mentioned semiconductor device is provided with a double-layer first buffer structure between the main dielectric layer and the upper structure, wherein the first buffer layer has a higher dielectric constant. Through the combined action of the first buffer layer and the second buffer layer, the surface electric field strength can be effectively reduced, thereby improving the withstand voltage of the double-layer component. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0032] FIG1 is a schematic cross-sectional view of a double-layer component with an isolation structure in Example 1 of the present application;

[0033] FIG2 is a schematic diagram of the shapes of the upper coil 101 and the lower coil 104 in one embodiment of the present application;

[0034] FIG3 is a schematic cross-sectional view of a double-layer component with an isolation structure in Example 2 of the present application;

[0035] FIG4 is a schematic cross-sectional view of a double-layer component with an isolation structure in Example 3 of the present application;

[0036] FIG5 is a schematic cross-sectional view of a double-layer component with an isolation structure in Example 4 of the present application;

[0037] FIG6 is a schematic cross-sectional view of a double-layer component with an isolation structure in Example 5 of the present application;

[0038] FIG7 is a schematic diagram of the cross-sectional structure of a double-layer component with an isolation structure in Example 6 of the present application. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the first element, first component, first region, first layer, or portion discussed below may be represented as a second element, second component, second region, second layer, or portion without departing from the teachings of the present invention.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0045] This application proposes a novel double-layer component with an isolation structure. The double-layer component specifically refers to a double-layer component comprising an upper structure, a lower structure, and an isolation structure located between the upper and lower structures. For example, a transformer having a special dielectric isolation structure formed between an upper coil and a lower coil, or a capacitor having a special dielectric isolation structure formed between an upper plate and a lower plate. The special dielectric isolation structure includes:

[0046] A main dielectric layer, located between the lower structure and the upper structure;

[0047] The first buffer structure is located on the main dielectric layer and includes a first buffer layer and a second buffer layer. The second buffer layer is made of silicon nitride and / or silicon oxynitride. The dielectric constant of the first buffer layer is greater than the dielectric constant of the second buffer layer. For example, the first buffer layer is made of a dielectric material with a greater dielectric constant than silicon nitride. In one embodiment of the present application, the first buffer layer is made of at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide.

[0048] The above-mentioned double-layer component with an isolation structure is provided with a double-layer first buffer structure between the main dielectric layer and the upper structure, wherein the first buffer layer has a higher dielectric constant. Through the combined action of the first buffer layer and the second buffer layer, the surface electric field strength can be effectively reduced, thereby improving the withstand voltage of the double-layer component.

[0049] In some embodiments of the present application, the double-layer component is a transformer, the upper structure is an upper coil, and the lower structure is a lower coil.

[0050] In some embodiments of the present application, the double-layer component is a capacitor, the upper structure is an upper plate, and the lower structure is a lower plate.

[0051] FIG1 is a schematic cross-sectional view of a double-layer component with an isolation structure in an embodiment of the present application (hereinafter referred to as Example 1). In this embodiment, the double-layer component is specifically a transformer. Referring to FIG1 , the transformer 100 (i.e., the area outlined by the dotted line in FIG1 ) is integrated into a semiconductor device and includes a lower coil 104, a main dielectric layer 105, a first buffer structure (including a first buffer layer 108 and a second buffer layer 103), and an upper coil 101. The material of the first buffer layer 108 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and can further be hafnium oxide and / or zirconium oxide. The material of the second buffer layer 103 includes silicon nitride and / or silicon oxynitride. The main dielectric layer 105 covers the lower coil 104. The first buffer layer 108 is located on the main dielectric layer 105, the second buffer layer 103 is located on the first buffer layer 108, and the upper coil 101 is located on the second buffer layer 103, that is, the first buffer layer 108 and the second buffer layer 103 are located between the main dielectric layer 105 and the upper coil 101. In other embodiments, the positions of the first buffer layer 108 and the second buffer layer 103 can be interchanged, that is, the first buffer layer 108 can be located on the second buffer layer 103. Because the dielectric constant of the first buffer layer 108 is greater than that of the second buffer layer 103, in this embodiment, the dielectric constant of the upper coil 101, the first buffer layer 108, the second buffer layer 103, and the main dielectric layer 105 are arranged in a stepwise manner, which effectively reduces the surface electric field. When the transformer 100 is in operation, mutual inductance is generated between the upper coil 101 and the lower coil 104.

[0052] In the embodiment shown in FIG. 1 , the device further includes a low-voltage region 106 for arranging a low-voltage device (not shown in FIG. 1 ).

[0053] Figure 2 is a schematic diagram of the shape of the upper coil 101 and the lower coil 104 in one embodiment of the present application. In the embodiment shown in Figures 1 and 2, the upper coil 101 and the lower coil 104 have the same shape. Specifically, the shape of the lower coil 104 is the positive projection of the upper coil 101 on the surface where the lower coil 104 is located, which can improve the mutual coupling coefficient of the inductance. In the embodiment shown in Figures 1 and 2, the upper coil 101 and the lower coil 104 are square spirals; in other embodiments, the upper coil 101 and the lower coil 104 can also be other conventional inductor coil shapes in the field. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are metal coils or alloy coils, and the main material is generally a mixture of Al and Cu. In one embodiment of the present application, the upper coil 101 and the lower coil 104 are made of the same material.

[0054] In one embodiment of the present application, the transformer 100 further includes a passivation layer 102 , which covers at least a portion of the upper coil 101 and is used to protect the dielectric layer of the device and circuit.

[0055] In the embodiment shown in Figures 1 and 2, transformer 100 further includes a pad portion 107 located on second buffer layer 103. Pad portion 107 is electrically connected to upper coil 101. Passivation layer 102 exposes pad portion 107, which is used to connect upper coil 101 to peripheral circuits.

[0056] The hafnium oxide / zirconium oxide in the first buffer layer 108 has a wide bandgap and a relatively high dielectric constant (approximately twice that of silicon nitride), effectively reducing the surface electric field strength, thereby improving the withstand voltage of the inductor of the transformer 100. In one embodiment of the present application, the thickness of the first buffer structure is greater than 200 nanometers. Furthermore, the thickness of the first buffer structure is less than the thickness of the main dielectric layer 105. That is, the thickness of the first buffer structure is greater than 200 nanometers and less than the thickness of the main dielectric layer 105.

[0057] In one embodiment of the present application, the material of the main dielectric layer 105 includes silicon oxide, such as silicon dioxide. In one embodiment of the present application, the thickness of the main dielectric layer 105 is greater than 3 microns.

[0058] In the embodiment shown in FIG. 1 , the device further includes a substrate 112. In one embodiment of the present application, the upper coil 101 and the lower coil 104 serve as the top metal and intermetallic layers of the device, respectively. Substrate 112 is a semiconductor substrate, and its material can be undoped single crystal silicon, doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In one embodiment of the present application, substrate 112 is made of single crystal silicon. Devices, such as NMOS and / or PMOS transistors, can be formed on substrate 112; these structures are omitted in FIG. 1 . Similarly, conductive members may be formed in and / or on the substrate 112. The conductive members may be gates, sources, or drains of transistors, or metal interconnect structures electrically connected to the transistors, etc. In the embodiment shown in FIG1 , a shallow trench isolation (STI) structure 114 is also formed in the substrate 112.

[0059] 1 , the device further includes contact holes 115 and multi-layer metal interconnects 116. The contact holes 115 are filled with a conductive material, such as a tungsten plug, and are electrically connected to corresponding metal interconnects 116 to lead out device structures such as active areas in the substrate 112.

[0060] FIG3 is a schematic cross-sectional view of a double-layer component with an isolation structure in an embodiment of the present application (hereinafter referred to as Example 2), in which the double-layer component is a transformer. The transformer 100 (i.e., the area outlined by the dotted line in FIG3 ) is integrated into a semiconductor device and includes a lower coil 104, a second buffer structure (including a third buffer layer 109 and a fourth buffer layer 110), a main dielectric layer 105, a first buffer structure (including a first buffer layer 108 and a second buffer layer 103), and an upper coil 101. The material of the fourth buffer layer 110 includes silicon nitride and / or silicon oxynitride. The dielectric constant of the third buffer layer 109 is greater than the dielectric constant of the fourth buffer layer 110. For example, the third buffer layer 109 uses a dielectric material with a dielectric constant greater than that of silicon nitride. In one embodiment of the present application, the material of the third buffer layer 109 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and can further be hafnium oxide and / or zirconium oxide. The second buffer structure is located between the lower coil 104 and the main dielectric layer 105. The fourth buffer layer 110 covers the lower coil 104. The third buffer layer 109 is located on the fourth buffer layer 110. The main dielectric layer 105 is located on the third buffer layer 109. In other embodiments, the positions of the third buffer layer 109 and the fourth buffer layer 110 can also be interchanged, that is, the fourth buffer layer 110 can be located on the third buffer layer 109.

[0061] The first buffer layer 108 is located on the main dielectric layer 105, the second buffer layer 103 is located on the first buffer layer 108, and the upper coil 101 is located on the second buffer layer 103. That is, the first buffer layer 108 and the second buffer layer 103 are located between the main dielectric layer 105 and the upper coil 101. In other embodiments, the positions of the first buffer layer 108 and the second buffer layer 103 can also be reversed, that is, the first buffer layer 108 can be located on the second buffer layer 103.

[0062] Providing the second buffer structure can further improve the withstand voltage of the transformer 100 .

[0063] In the embodiment shown in FIG. 3 , the device further includes a low-voltage region 106 for arranging a low-voltage device (not shown in FIG. 3 ).

[0064] For the related description of other structures in FIG3 , please refer to Example 1.

[0065] FIG4 is a schematic cross-sectional view of a dual-layer component with an isolation structure in an embodiment of the present application (hereinafter referred to as Example 3). In this embodiment, the dual-layer component is a transformer. Transformer 100 (i.e., the area outlined by the dashed line in FIG4 ) is integrated into a semiconductor device and includes a third buffer structure (including a fifth buffer layer 119 and a sixth buffer layer 120), a lower coil 104, a second buffer structure (including a third buffer layer 109 and a fourth buffer layer 110), a main dielectric layer 105, a first buffer structure (including a first buffer layer 108 and a second buffer layer 103), an upper coil 101, and a fourth buffer structure (including a seventh buffer layer 117 and an eighth buffer layer 118). The sixth buffer layer 120 is made of silicon nitride and / or silicon oxynitride, and the eighth buffer layer 118 is made of silicon nitride and / or silicon oxynitride. The dielectric constant of the fifth buffer layer 119 is greater than that of the sixth buffer layer 120. For example, the fifth buffer layer 119 is made of a dielectric material having a dielectric constant greater than that of silicon nitride. In one embodiment of the present application, the material of the fifth buffer layer 119 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide. The dielectric constant of the seventh buffer layer 117 is greater than the dielectric constant of the eighth buffer layer 118. For example, the seventh buffer layer 117 uses a dielectric material with a dielectric constant greater than that of silicon nitride. In one embodiment of the present application, the material of the seventh buffer layer 117 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide. The lower coil 104 is located on the third buffer structure, and the sixth buffer layer 120 is located between the fifth buffer layer 119 and the lower coil 104. In other embodiments, the positions of the fifth buffer layer 119 and the sixth buffer layer 120 can also be interchanged, that is, the fifth buffer layer 119 can be located on the sixth buffer layer 120.

[0066] The second buffer structure is located between the lower coil 104 and the main dielectric layer 105. The fourth buffer layer 110 covers the lower coil 104. The third buffer layer 109 is located on the fourth buffer layer 110. The main dielectric layer 105 is located on the third buffer layer 109. In other embodiments, the positions of the third buffer layer 109 and the fourth buffer layer 110 can also be interchanged, that is, the fourth buffer layer 110 can be located on the third buffer layer 109.

[0067] The first buffer layer 108 is located on the main dielectric layer 105, the second buffer layer 103 is located on the first buffer layer 108, and the upper coil 101 is located on the second buffer layer 103. That is, the first buffer layer 108 and the second buffer layer 103 are located between the main dielectric layer 105 and the upper coil 101. In other embodiments, the positions of the first buffer layer 108 and the second buffer layer 103 can also be reversed, that is, the first buffer layer 108 can be located on the second buffer layer 103.

[0068] The fourth buffer structure is located on the upper coil 101, and the eighth buffer layer 118 is located between the upper coil 101 and the seventh buffer layer 117. In other embodiments, the positions of the seventh buffer layer 117 and the eighth buffer layer 118 can also be interchanged, that is, the eighth buffer layer 118 can be located on the seventh buffer layer 117.

[0069] Providing the third buffer structure and the fourth buffer structure can further improve the withstand voltage of the transformer 100 .

[0070] In the embodiment shown in FIG. 4 , the device further includes a low-voltage region 106 for arranging a low-voltage device (not shown in FIG. 4 ).

[0071] For the related description of other structures in FIG. 4 , please refer to Example 1.

[0072] The present application accordingly provides a semiconductor device, which includes a transformer area and a low-voltage area 106 . Low-voltage devices are provided in the low-voltage area 106 . The transformer area includes the transformer 100 described in any of the aforementioned embodiments.

[0073] FIG5 is a schematic cross-sectional view of a double-layer component with an isolation structure in an embodiment of the present application (hereinafter referred to as Example 4). In this embodiment, the double-layer component is a capacitor. Capacitor 200 (i.e., the area outlined by the dashed line in FIG5 ) is integrated into a semiconductor device and includes a lower plate 204, a main dielectric layer 205, a first buffer structure (including a first buffer layer 208 and a second buffer layer 203), and an upper plate 201. The material of the first buffer layer 208 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and may further be hafnium oxide and / or zirconium oxide. The material of the second buffer layer 203 includes silicon nitride and / or silicon oxynitride. The main dielectric layer 205 covers the lower plate 204. The first buffer layer 208 is located on the main dielectric layer 205, the second buffer layer 203 is located on the first buffer layer 208, and the upper plate 201 is located on the second buffer layer 203, that is, the first buffer layer 208 and the second buffer layer 203 are located between the main dielectric layer 205 and the upper plate 201. In other embodiments, the positions of the first buffer layer 208 and the second buffer layer 203 can also be interchanged, that is, the first buffer layer 208 can be located on the second buffer layer 203. In one embodiment of the present application, the material of the main dielectric layer 205 includes silicon oxide, such as silicon dioxide. In the embodiment shown in Figure 5, the device also includes a low-voltage region 206 for arranging a low-voltage device (not shown in Figure 5).

[0074] In one embodiment of the present application, the shape of the upper plate 201 and the lower plate 204 can be a chamfered rectangle, an ellipse, a circle, or other conventional capacitor plate shapes in the art, and the shape of the upper plate 201 and the lower plate 204 can be the same. In one embodiment of the present application, the upper plate 201 and the lower plate 204 are metal plates or alloy plates, generally the main material is a mixture of Al and Cu. In one embodiment of the present application, the material of the upper plate 201 and the lower plate 204 is the same.

[0075] In one embodiment of the present application, capacitor 200 further includes a passivation layer 202, which covers at least a portion of top plate 201 and is used to protect the dielectric layer of the device and circuit. In the embodiment shown in FIG1 , passivation layer 202 partially exposes top plate 201, and top plate 201 can be connected to peripheral circuitry through the exposed portion.

[0076] The hafnium oxide / zirconium oxide in the first buffer layer 208 has a wide bandgap and a relatively high dielectric constant (approximately twice that of silicon nitride), which can effectively reduce the surface electric field strength, thereby improving the withstand voltage of the capacitor 200. In one embodiment of the present application, the thickness of the first buffer structure is greater than 200 nanometers. Furthermore, the thickness of the first buffer structure is less than the thickness of the main dielectric layer 205. In other words, the thickness of the first buffer structure is greater than 200 nanometers and less than the thickness of the main dielectric layer 205.

[0077] In one embodiment of the present application, the material of the main dielectric layer 205 includes silicon oxide, such as silicon dioxide. In one embodiment of the present application, the thickness of the main dielectric layer 205 is greater than 3 microns.

[0078] In the embodiment shown in FIG5 , the device further includes a substrate 212. In one embodiment of the present application, the upper plate 201 and the lower plate 204 are the top metal and the intermetallic layer of the device, respectively. The substrate 212 is a semiconductor substrate, and its material can be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In one embodiment of the present application, the constituent material of the substrate 212 is single crystal silicon. Devices, such as NMOS and / or PMOS transistors, can be formed on the substrate 212, but these structures are omitted in FIG5 . Similarly, conductive members may be formed in and / or on the substrate 212 , and the conductive members may be gates, sources, or drains of transistors, or metal interconnect structures electrically connected to the transistors, etc. In the embodiment shown in FIG5 , a shallow trench isolation (STI) structure 214 is also formed in the substrate 212 .

[0079] 5 , the device further includes contact holes 215 and multi-layer metal interconnects 216. The contact holes 215 are filled with a conductive material, such as a tungsten plug, and are electrically connected to corresponding metal interconnects 216 to lead out device structures such as active areas in the substrate 212.

[0080] Figure 6 is a schematic cross-sectional view of a double-layer component with an isolation structure in an embodiment of the present application (hereinafter referred to as Example 5), in which the double-layer component is a capacitor. Capacitor 200 (i.e., the area outlined by the dotted line in Figure 6) is integrated into a semiconductor device and includes a lower plate 204, a second buffer structure (including a third buffer layer 209 and a fourth buffer layer 210), a main dielectric layer 205, a first buffer structure (including a first buffer layer 208 and a second buffer layer 203), and an upper plate 201. The material of the fourth buffer layer 210 includes silicon nitride and / or silicon oxynitride. The dielectric constant of the third buffer layer 209 is greater than the dielectric constant of the fourth buffer layer 210. For example, the third buffer layer 209 uses a dielectric material with a dielectric constant greater than that of silicon nitride. In one embodiment of the present application, the material of the third buffer layer 209 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and can further be hafnium oxide and / or zirconium oxide. The second buffer structure is located between the lower plate 204 and the main dielectric layer 205. The fourth buffer layer 210 covers the lower plate 204. The third buffer layer 209 is located on the fourth buffer layer 210. The main dielectric layer 205 is located on the third buffer layer 209. In other embodiments, the positions of the third buffer layer 209 and the fourth buffer layer 210 can also be interchanged, that is, the fourth buffer layer 210 can be located on the third buffer layer 209.

[0081] The first buffer layer 208 is located on the main dielectric layer 205, and the top plate 201 is located on the second buffer layer 203, that is, the first buffer layer 208 and the second buffer layer 203 are located between the main dielectric layer 205 and the top plate 201. In other embodiments, the positions of the first buffer layer 208 and the second buffer layer 203 can also be interchanged, that is, the first buffer layer 208 can be located on the second buffer layer 203.

[0082] Providing the second buffer structure can further improve the withstand voltage of the capacitor 200 .

[0083] In the embodiment shown in FIG. 6 , the device further includes a low-voltage region 206 for arranging a low-voltage device (not shown in FIG. 6 ).

[0084] For the related description of other structures in FIG6 , please refer to Example 5.

[0085] FIG7 is a schematic cross-sectional view of a double-layer component with an isolation structure in an embodiment of the present application (hereinafter referred to as Example 6). In this embodiment, the double-layer component is a capacitor. Capacitor 200 (i.e., the area outlined by the dashed line in FIG7 ) is integrated into a semiconductor device and includes a third buffer structure (including a fifth buffer layer 219 and a sixth buffer layer 220), a lower plate 204, a second buffer structure (including a third buffer layer 209 and a fourth buffer layer 210), a main dielectric layer 205, a first buffer structure (including a first buffer layer 208 and a second buffer layer 203), an upper plate 201, and a fourth buffer structure (including a seventh buffer layer 217 and an eighth buffer layer 218). The sixth buffer layer 220 is made of silicon nitride and / or silicon oxynitride, and the eighth buffer layer 218 is made of silicon nitride and / or silicon oxynitride. The dielectric constant of the fifth buffer layer 219 is greater than that of the sixth buffer layer 220. For example, the fifth buffer layer 219 is made of a dielectric material having a dielectric constant greater than that of silicon nitride. In one embodiment of the present application, the material of the fifth buffer layer 219 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and can further be hafnium oxide and / or zirconium oxide. The dielectric constant of the seventh buffer layer 217 is greater than the dielectric constant of the eighth buffer layer 218. For example, the seventh buffer layer 217 uses a dielectric material with a dielectric constant greater than that of silicon nitride. In one embodiment of the present application, the material of the seventh buffer layer 217 includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and can further be hafnium oxide and / or zirconium oxide. The lower plate 204 is located on the third buffer structure, and the sixth buffer layer 220 is located between the fifth buffer layer 219 and the lower plate 204. In other embodiments, the positions of the fifth buffer layer 219 and the sixth buffer layer 220 can also be interchanged, that is, the fifth buffer layer 219 can be located on the sixth buffer layer 220.

[0086] The second buffer structure is located between the lower plate 204 and the main dielectric layer 205. The fourth buffer layer 210 covers the lower plate 204. The third buffer layer 209 is located on the fourth buffer layer 210. The main dielectric layer 205 is located on the third buffer layer 209. In other embodiments, the positions of the third buffer layer 209 and the fourth buffer layer 210 can also be interchanged, that is, the fourth buffer layer 210 can be located on the third buffer layer 209.

[0087] The first buffer layer 208 is located on the main dielectric layer 205, the second buffer layer 203 is located on the first buffer layer 208, and the top plate 201 is located on the second buffer layer 203, that is, the first buffer layer 208 and the second buffer layer 203 are located between the main dielectric layer 205 and the top plate 201. In other embodiments, the positions of the first buffer layer 208 and the second buffer layer 203 can also be interchanged, that is, the first buffer layer 208 can be located on the second buffer layer 203.

[0088] The fourth buffer structure is located on the upper plate 201, and the eighth buffer layer 218 is located between the upper plate 201 and the seventh buffer layer 217. In other embodiments, the positions of the seventh buffer layer 217 and the eighth buffer layer 218 can also be interchanged, that is, the eighth buffer layer 218 can be located on the seventh buffer layer 217.

[0089] Providing the third buffer structure and the fourth buffer structure can further improve the withstand voltage of the capacitor 200 .

[0090] In the embodiment shown in FIG. 7 , the device further includes a low-voltage region 206 for arranging a low-voltage device (not shown in FIG. 7 ).

[0091] For the related description of other structures in FIG. 7 , please refer to Example 5.

[0092] The present application accordingly provides a semiconductor device, which includes a capacitor region and a low-voltage region 206 , wherein a low-voltage device is provided in the low-voltage region 206 , and the capacitor region includes the capacitor 200 described in any of the aforementioned embodiments.

[0093] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0094] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A double-layer component with an isolation structure, comprising an upper structure, a lower structure, and an isolation structure located between the upper structure and the lower structure, characterized in that: The isolation structure includes: a main dielectric layer, located between the lower structure and the upper structure; The first buffer structure is located on the main dielectric layer and includes a first buffer layer and a second buffer layer. The second buffer layer is made of silicon nitride and / or silicon oxynitride. The dielectric constant of the first buffer layer is greater than that of the second buffer layer.

2. The double-layer component with an isolation structure according to claim 1, characterized in that: The double-layer component is a transformer, the upper structure is an upper coil, and the lower structure is a lower coil; or The double-layer component is a capacitor, the upper structure is an upper plate, and the lower structure is a lower plate.

3. The double-layer component with an isolation structure according to claim 1 or 2, characterized in that: The second buffer layer is located on the first buffer layer, or the first buffer layer is located on the second buffer layer.

4. The double-layer component with an isolation structure according to claim 1 or 2, characterized in that: The isolation structure also includes a second buffer structure, which is located between the lower structure and the main dielectric layer. The second buffer structure includes a third buffer layer and a fourth buffer layer. The material of the fourth buffer layer includes silicon nitride and / or silicon oxynitride. The dielectric constant of the third buffer layer is greater than the dielectric constant of the fourth buffer layer.

5. The double-layer component with an isolation structure according to claim 4, characterized in that: The fourth buffer layer is located between the lower structure and the third buffer layer, or the third buffer layer is located between the lower structure and the fourth buffer layer.

6. The double-layer component with an isolation structure according to claim 1 or 2, characterized in that: It also includes a third buffer structure, the lower structure is located on the third buffer structure, the third buffer structure includes a fifth buffer layer and a sixth buffer layer, the material of the sixth buffer layer includes silicon nitride and / or silicon oxynitride, and the dielectric constant of the fifth buffer layer is greater than the dielectric constant of the sixth buffer layer.

7. The double-layer component with an isolation structure according to claim 6, characterized in that: It also includes a fourth buffer structure, which is located on the upper structure. The fourth buffer structure includes a seventh buffer layer and an eighth buffer layer. The material of the eighth buffer layer includes silicon nitride and / or silicon oxynitride. The dielectric constant of the seventh buffer layer is greater than the dielectric constant of the eighth buffer layer.

8. The double-layer component with an isolation structure according to claim 7, characterized in that: The sixth buffer layer is located between the lower structure and the fifth buffer layer, or the fifth buffer layer is located between the lower structure and the sixth buffer layer; The eighth buffer layer is located between the upper structure and the seventh buffer layer, or the seventh buffer layer is located between the upper structure and the eighth buffer layer.

9. The double-layer component with an isolation structure according to claim 1, characterized in that: The material of the first buffer layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide.

10. A semiconductor device comprising a double-layer component area and a low-voltage area, wherein the low-voltage area comprises a low-voltage device, characterized in that: The double-layer component area includes a double-layer component with an isolation structure according to any one of claims 1 to 9.

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