Heterojunction structure for a high-electron-mobility transistor

The heterojunction structure in HEMTs uses a carbon-free buffer layer and composite substrate to enhance electrical isolation and lattice compatibility, addressing performance issues in existing HEMTs by improving voltage resistance and reliability.

WO2025180926A1PCT designated stage Publication Date: 2025-09-04ALPSEMI
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Patent Information

Application Number
PCT/EP2025/054510
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-02-29
Filing Date
2025-02-20
Publication Date
2025-09-04

AI Technical Summary

Technical Problem

Existing high electron mobility transistors (HEMTs) face issues with crystalline quality degradation and charge trapping due to carbon doping, and the complexity of forming superlattices for lattice mismatch compensation, leading to performance degradation and operational delays.

Method used

A heterojunction structure using a nucleation layer of monocrystalline silicon or aluminum nitride with a buffer layer of aluminum nitride or aluminum-gallium nitride, devoid of carbon, to form a composite substrate that enhances electrical isolation and lattice compatibility, allowing for a thick buffer layer without a superlattice, and includes a bonding layer for substrate detachment.

Benefits of technology

The solution provides improved electrical isolation, reduced thermal losses, and better confinement of two-dimensional electron gas, enabling higher voltage resistance and reliability in HEMTs without the drawbacks of carbon doping and superlattice formation.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention relates to a heterojunction structure for a high-electron-mobility transistor, consecutively comprising: - a substrate (1); - a nucleation layer (2), made of a material selected from among monocrystalline silicon, Si, having a "111" crystal orientation, and monocrystalline aluminium nitride, AlN, having a 2H hexagonal crystal structure; - a buffer layer (3) free of carbon atoms, made of a material selected from among aluminium nitride, AlN, and aluminium gallium nitride AlxGa1-xN, where x>0,5; - first and second semiconductor layers (4, 5), respectively made of first and second III-N alloys selected such that the first and second semiconductor layers (4, 5) have a heterojunction (H) suitable for generating a two-dimensional electron gas.
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Description

[0001] HETEROJUNCTION STRUCTURE FOR A HIGH ELECTRONIC MOBILITY TRANSISTOR

[0002] Technical field

[0003] The invention relates to the technical field of power electronics, more particularly to high electron mobility transistors (HEMT).

[0004] The invention finds its application in particular in:

[0005] - components for high voltage power conversion, for example in the range [600 V — 1770 V], and at high frequency;

[0006] - components for electrical protection, for example in the voltage range [600 V

[0007] - 1770 V].

[0008] State of the art

[0009] A hetero]unction structure for a high electron mobility transistor HEMT successively comprises:

[0010] - a substrate;

[0011] - a nucleation layer;

[0012] - a buffer layer;

[0013] - first and second semiconductor layers, made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers have a hetero] junction suitable for forming a two-dimensional electron gas (2DEG for “2-Dimensional Electron Gas” in English).

[0014] The first semiconductor layer is called the channel layer. The second semiconductor layer is called the barrier layer.

[0015] The buffer layer is a thick layer (typically with a thickness greater than

[0016] 1 pm) allowing in particular:

[0017] (i) electrically insulating the channel layer from the substrate;

[0018] (ii) to ensure compatibility in terms of physical properties between the substrate material and the channel layer material.

[0019] Point (i) allows for good vertical voltage resistance. This electrical insulation is essential, especially when the substrate is semiconductor, for example for a silicon Si substrate. Point (ii) mainly allows for compatibility in terms of lattice mismatch in order to avoid the formation of crystalline defects that are detrimental in terms of reliability and performance.

[0020] It is known from the state of the art to use a silicon Si substrate and a gallium nitride GaN buffer layer. In order to satisfy points (i) and (ii), it is known:

[0021] - to introduce carbon doping into the buffer layer in order to obtain good electrical insulation;

[0022] - to form a superlattice of the AIN / GaN type for the buffer layer, in order to compensate for a strong crystal lattice mismatch between the silicon substrate and the channel layer (generally in GaN).

[0023] Such a structure based on heterogeneity of the state of the art is not entirely satisfactory insofar as:

[0024] - carbon doping degrades the crystalline quality, and introduces charge trapping which can cause harmful dynamic effects, such as control delays

[0025] ("gate-lag", "drain-lag" in English) or a collapse of the current;

[0026] - the formation of a super-network is complex to implement and consumes operating time.

[0027] Statement of the invention

[0028] The invention aims to remedy all or part of the aforementioned drawbacks. To this end, the invention relates to a heterojunction structure for a high electron mobility transistor, successively comprising:

[0029] - a substrate;

[0030] - a nucleation layer, made of a material different from the substrate and chosen from monocrystalline silicon Si having a crystalline orientation of the “111” type and monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the type

[0031] “2H”;

[0032] - a buffer layer, made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ x N with x>0.5; the buffer layer being devoid of carbon atoms;

[0033] - first and second semiconductor layers, made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers have a hetero] junction suitable for forming a two-dimensional electron gas.

[0034] Thus, such a hetero] junction structure according to the invention makes it possible to dispense with carbon doping of the state of the art thanks to the buffer layer made of aluminum nitride AIN or made of an aluminum-gallium nitride AlGaN enriched in aluminum, that is to say of the empirical formula Al x Cheerful_ xN with x>0.5. Aluminum nitride AIN and aluminum-enriched aluminum-gallium nitride AlGaN each have a larger band gap than gallium nitride GaN, so that the channel layer (i.e. the first semiconductor layer) is better electrically isolated from the substrate compared to the state of the art, which allows for better confinement of the two-dimensional electron gas.

[0035] The nucleation layer is made of a different material than the substrate, so that the substrate and the nucleation layer can form a so-called composite substrate. Monocrystalline silicon Si, having a crystal orientation of the "111" type, and monocrystalline aluminum nitride AIN, having a hexagonal crystal structure of the "2H" type, are materials of the nucleation layer having a small lattice mismatch with the buffer layer made of AIN or aluminum-enriched AlGaN.

[0036] A composite substrate allows the choice of substrate material not to be restricted based on its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the substrate material according to other criteria, for example its coefficient of thermal expansion (GTE), its transparency to electromagnetic radiation (e.g. in the presence of a bonding layer to detach it), etc.

[0037] The heterojunction structure according to the invention may comprise one or more of the following characteristics.

[0038] According to a characteristic of the invention:

[0039] - the material from which the buffer layer is made has a first coefficient of thermal expansion, noted CTE1;

[0040] - the substrate is made of a material having a second coefficient of thermal expansion, noted CTE2; the material from which the substrate is made being chosen so that Thus, an advantage provided is to be able to form a thick buffer layer (thickness greater than 1 pm) of good crystalline quality (typically of the order of or less than 10 9 dislocations per cm 2 ) by organometallic vapor phase epitaxy (MOCVD) or by molecular beam epitaxy (MBE), while avoiding the formation of a superlattice for the buffer layer.

[0041] According to a characteristic of the invention, the substrate is made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN.

[0042] Thus, an advantage provided by such materials is their low difference in GTE with the buffer layer.

[0043] According to a characteristic of the invention, the hetero-unction structure comprises a bonding layer extending between the substrate and the nucleation layer, the bonding layer being designed to detach the substrate from the hetero-unction structure when the bonding layer is subjected to electromagnetic radiation; the substrate being made of a material transparent to electromagnetic radiation.

[0044] Thus, one advantage provided is being able to recycle the substrate.

[0045] According to a characteristic of the invention, the bonding layer comprises:

[0046] - a first adhesive underlayer, preferably made of a material chosen from amorphous silicon and polycrystalline silicon;

[0047] - a second release sub-layer, designed to detach the substrate from the heterojunction structure when the second release sub-layer is subjected to electromagnetic radiation; the second release sub-layer preferably being made of a metallic material such as aluminum Al, tin Sn or zinc Zn, or preferably made of a carbon material such as carbon nanotubes or graphene.

[0048] Thus, an advantage provided by such materials for the second release sub-layer is that they can detach from the substrate when subjected to infrared electromagnetic radiation, thanks to their strong absorption in the infrared.

[0049] According to a characteristic of the invention, the buffer layer has a thickness greater than or equal to 1 μm.

[0050] Thus, an advantage provided is to improve the vertical electrical isolation of the channel layer (i.e. the first semiconductor layer). The absence of carbon atoms in the buffer layer also makes it possible to perfectly electrically isolate two adjacent transistors without having to manage their electrical potential on the back side (i.e. under the buffer layer). Such a thick buffer layer greatly limits, or even eliminates, the back barrier problem encountered when placing high voltage transistors on the same substrate (same chip). This problem is known with a state-of-the-art GaN gallium nitride buffer layer and is exacerbated with the increase in voltage (in particular from 100 V).Finally, this electrical insulation obtained by the buffer layer is not achieved at the expense of significant thermal losses, particularly when the buffer layer is made of aluminum nitride AIN, to a lesser extent when the buffer layer is made of aluminum-gallium nitride AlGaN enriched with aluminum. For example, electrical insulation obtained by a silicon-on-insulator (SOI) substrate has significant thermal resistance due to the presence of the insulator, typically a layer of silicon dioxide SiO2.

[0051] According to a characteristic of the invention, the material in which the buffer layer is made is monocrystalline.

[0052] Thus, an advantage provided is to obtain a buffer layer of good crystalline quality as well as good thermal conductivity (i.e. does not form a thermal barrier), particularly when the buffer layer is made of aluminum nitride AIN.

[0053] According to a characteristic of the invention:

[0054] - the first type III-N alloy is an alloy with the empirical formula Al x Cheerful_ x N, with x>0;

[0055] - the second type III-N alloy is an alloy with the empirical formula Al y Cheerful_ y N, with y>x.

[0056] Thus, one advantage provided is to obtain a hetero] junction allowing the formation of a two-dimensional electron gas.

[0057] The invention also relates to a high electron mobility transistor, comprising:

[0058] - a heterojunction structure according to the invention;

[0059] - first and second metal zones, each extending through the second semiconductor layer so as to form an ohmic contact with the heterojunction;

[0060] - a source electrode and a drain electrode, respectively electrically connected to the first and second metal zones;

[0061] - a third metal zone, the first and second metal zones extending on either side of the third metal zone;

[0062] - a grid electrode, electrically connected to the third metal zone.

[0063] According to a characteristic of the invention, the third metal zone is arranged to:

[0064] - extend over the second semiconductor layer so as to form a Schottky contact with the second semiconductor layer; or

[0065] - extend over a dielectric layer covering the second semiconductor layer; or

[0066] - extend over a p-type doped gallium nitride GaN layer or over a p-type doped aluminum-gallium nitride AlGaN layer, covering the second semiconductor layer; or

[0067] - extend inside the second semiconductor layer so as to form a recessed gate electrode.

[0068] When the third metal zone extends over the second semiconductor layer (i.e. the barrier layer) so as to form a Schottky contact with the second semiconductor layer, the HEMT transistor is generally of the normally on type (“Normalyl-On” in English).

[0069] When the third metal zone extends over a dielectric layer (the dielectric layer covering the second semiconductor layer), the HEMT transistor is also of the normally on type ("Normalyl-On" in English).

[0070] When the third metal region extends over a p-doped GaN layer (the p-doped GaN layer covering the second semiconductor layer), the HEMT is a normally off (Normal-Off) type.

[0071] When the third metal zone extends inside the second semiconductor layer so as to form a recess gate electrode, the HEMT transistor is of the normally off type.

[0072] According to a characteristic of the invention, the transistor comprises at least one field plate arranged to form a lateral extension of the third metal zone, the lateral extension being oriented towards the second metal zone.

[0073] Thus, an advantage provided is to improve the lateral voltage resistance between the gate electrode and the drain electrode. The invention also relates to a method for manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive steps: a) using a donor substrate, made of monocrystalline silicon Si having a crystal orientation of the "111" type; b) assembling the donor substrate to a receiving substrate; c) thinning the donor substrate so as to obtain a nucleation layer; d) forming a buffer layer on the nucleation layer, the buffer layer being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride ALGai-xN with x>0.5; the buffer layer being devoid of carbon atoms;e) successively forming first and second semiconductor layers on the buffer layer, the first and second semiconductor layers being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers have a hetero] junction suitable for forming a two-dimensional electron gas.;

[0074] Thus, such a method according to the invention makes it possible to obtain a composite substrate (receiving substrate / nucleation layer) at the end of step c), allowing the formation of a buffer layer of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its GTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc.

[0075] According to a characteristic of the invention, step b) comprises the steps: bi) forming a bonding layer on the receiving substrate or on the donor substrate; b2) assembling the donor substrate to the receiving substrate via the bonding layer; the bonding layer formed during step bi) preferably being designed to detach the receiving substrate from the hetero-unction structure obtained at the end of step e) when the bonding layer is subjected to electromagnetic radiation; the receiving substrate being made of a material transparent to electromagnetic radiation.

[0076] Thus, an advantage provided is to obtain a composite substrate (receiving substrate / bonding layer / nucleation layer) at the end of step c), allowing the formation of a buffer layer of aluminum nitride AIN or aluminum-gallium nitrate AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its GTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc. Such a bonding layer makes it possible to recycle the receiving substrate after step e).

[0077] The invention finally relates to a method for manufacturing a hetero] junction structure for a high electron mobility transistor, comprising the successive steps: a') forming a nucleation layer on a growth substrate, the nucleation layer being made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type, the nucleation layer having:

[0078] - a first, free face, having an aluminum Al type polarity;

[0079] - a second face, opposite the first face, having a nitrogen N type polarity; b') assembling the growth substrate to a temporary substrate on the side of the first face of the nucleation layer; then removing the growth substrate so as to expose the second face of the nucleation layer; c') assembling the temporary substrate to a receiving substrate on the side of the second face of the nucleation layer; then removing the temporary substrate so as to expose the first face of the nucleation layer; d) forming a buffer layer on the nucleation layer, the buffer layer being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGai-xN with x>0.5; the buffer layer being devoid of carbon atoms;e) successively forming first and second semiconductor layers on the buffer layer, the first and second semiconductor layers being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers have a hetero] junction suitable for forming a two-dimensional electron gas.;

[0080] Thus, such a method according to the invention makes it possible to obtain a composite substrate (receiving substrate / nucleation layer) at the end of step c'), allowing the formation of a buffer layer of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its CTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc.

[0081] Since a bulk substrate of monocrystalline AlN is not commercially available in a sufficient diameter and quality, it is not currently feasible to use a donor substrate of monocrystalline AlN and then thin it to form a nucleation layer, in which case a single transfer to a receiving substrate would be necessary. The nucleation layer of monocrystalline AlN is obtained by epitaxial growth on a growth substrate. Performing steps b') and c') results in a double transfer making it possible to recover the aluminum-type polarity on the free surface of the nucleation layer before step d), in order to obtain a satisfactory crystalline quality for the buffer layer formed during step d).

[0082] According to a characteristic of the invention, step c') comprises the steps: c'i) forming a bonding layer on the receiving substrate or on the second face of the nucleation layer; c' 2) assembling the temporary substrate to the receiving substrate via the bonding layer; the bonding layer formed during step c'i) preferably being designed to detach the receiving substrate from the hetero-unction structure obtained at the end of step e) when the bonding layer is subjected to electromagnetic radiation; the receiving substrate being made of a material transparent to electromagnetic radiation.

[0083] Thus, an advantage provided is to obtain a composite substrate (receiving substrate / bonding layer / nucleation layer) at the end of step c'), allowing the formation of a buffer layer of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its CTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc. Such a bonding layer makes it possible to recycle the receiving substrate after step e).

[0084] Definitions

[0085] - By "comprising successively an element A, an element B etc.", we mean that the elements A and B are arranged consecutively in an order defined according to the normal to a surface receiving the elements A and B, that is to say the vertical direction (from bottom to top) in normal conditions of use.

[0086] - By "substrate" is meant a self-supporting physical medium made of a crystalline material. A substrate can be a "slice", also called a "wafer" which is generally in the form of a disc cut from an ingot of a crystalline material.

[0087] - By “nucleation layer” we mean a layer forming a crystalline seed allowing epitaxial growth.

[0088] - By “different material” we mean that a material A is different from a material B when:

[0089] (i) material A has a qualitative chemical composition different from that of material B; or

[0090] (ii) material A has a qualitative chemical composition identical to that of material B but a quantitative chemical composition different from that of material B; or

[0091] (iii) material A has a qualitative chemical composition identical to that of material B but in a different crystalline form.

[0092] As non-limiting examples, (i) polycrystalline silicon carbide SiC is different from monocrystalline aluminum nitride AIN and monocrystalline silicon Si; (ii) the alloy Al x Cheerful_ X N is different from the alloy Al y Cheerful_ y N when y^x; (iii) monocrystalline aluminum nitride AIN is different from polycrystalline aluminum nitride AIN.

[0093] - By "111-type crystal orientation" is meant a crystal orientation defined by the Miller indices (111).

[0094] - By "hexagonal crystal structure of the 2H type" we mean that the hexagonal crystal structure has a 2H polytype.

[0095] - By “buffer layer” we mean a layer designed to:

[0096] (i) electrically insulating the channel layer (i.e. the first semiconductor layer) from the substrate, and

[0097] (ii) improve the crystalline quality of the layers formed above the buffer layer through the thickness of the buffer layer and the smoothing of the mesh parameters.

[0098] - By "semiconductor layer" is meant a layer made of a material having an electrical conductivity at 300 K of between 10 6 S / cm and 10 3 S / cm.

[0099] - "Type III-N alloy" means an alloy between at least one element from column III of the periodic table of elements (TPE) and nitrogen N. The alloy can be binary in the presence of a single element from column III of the TPE and nitrogen N. The alloy can be ternary in the presence of two elements from column III of the TPE and nitrogen N. The alloy can be quaternary in the presence of three elements from column III of the TPE and nitrogen N etc.

[0100] - By "hetero] junction" we mean a junction between two semiconductor materials whose forbidden band widths are different.

[0101] - By "transparent" is meant that the substrate has an intensity transmission coefficient greater than 80%, preferably greater than 85%, more preferably greater than 90% averaged over the spectrum of the electromagnetic radiation to which the bonding layer is subjected, for example an infrared domain.

[0102] - By "thickness" is meant the dimension along the normal to the surface of the substrate over which the nucleation layer, or where appropriate the bonding layer, extends, i.e. the vertical direction under normal conditions of use.

[0103] - By "dielectric" we mean that the layer is made of a material having an electrical conductivity at 300 K less than or equal to 10 6 S / cm.

[0104] - By "p-type doped" we mean that the gallium nitride GaN layer contains p-type dopants, i.e. species (e.g. impurities) which, when introduced into the gallium nitride GaN matrix, generate a hole in the valence band.

[0105] - By "field plate" is meant a metal plate arranged to reduce the intensity of the electric field near the grid electrode.

[0106] - By "aluminum-like polarity" we mean that the Al-N bond starts with an aluminum atom Al along the vertical direction. The first face of the nucleation layer has an aluminum-like polarity, i.e. with aluminum atoms Al on the surface.

[0107] - By "nitrogen-like polarity" we mean that the Al-N bond starts with a nitrogen atom N along the vertical direction. The second face of the nucleation layer has nitrogen-like polarity, i.e. with nitrogen atoms N on the surface.

[0108] - By "exposing" we mean an action of exposing a face of the nucleation layer so that said face becomes a free face.

[0109] - By "crystal lattice mismatch" we mean the quantitative difference between the lattice parameters of the materials concerned.

[0110] Brief description of the drawings

[0111] Other features and advantages will become apparent in the detailed description of various embodiments of the invention, the description being accompanied by examples and references to the attached drawings. Figure 1 is a schematic sectional view, illustrating a first embodiment of a hetero-unction structure according to the invention.

[0112] Figure 2 is a schematic sectional view, illustrating a second embodiment of a hetero-unction structure according to the invention, with the presence of a bonding layer.

[0113] Figure 3 is a schematic sectional view, illustrating a first embodiment of a high electron mobility transistor according to the invention, with the presence of a gate surmounting a dielectric layer (gate insulator).

[0114] Figure 4 is a schematic sectional view, illustrating a second embodiment of a high electron mobility transistor according to the invention, with the presence of a gate surmounting a p-type doped gallium nitride GaN layer.

[0115] Figure 5 is a schematic view similar to Figure 3, with the presence of a bonding layer.

[0116] Figure 6 is a schematic view similar to Figure 4, with the presence of a bonding layer.

[0117] Figure 7 includes schematic sectional views, illustrating a first embodiment of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer produced in a monocrystalline silicon Si having a crystalline orientation of the “111” type.

[0118] Figure 8 includes schematic sectional views, illustrating a second embodiment of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer produced in a monocrystalline silicon Si having a crystalline orientation of the “111” type, and with the presence of a bonding layer.

[0119] Figure 9 is a schematic sectional view, illustrating a step a') of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0120] Figure 10 is a schematic sectional view, illustrating an assembly of a growth substrate to a temporary substrate during a step b') of a method for manufacturing a heterojunction structure according to the invention.

[0121] Figure 11 is a schematic sectional view, illustrating a removal of the growth substrate during a step b') of a method for manufacturing a heterojunction structure according to the invention.

[0122] Figure 12 is a schematic sectional view, illustrating an assembly of a temporary substrate to a receiving substrate during a step c') of a method for manufacturing a heterojunction structure according to the invention. Figure 12bis is a schematic view similar to Figure 12, with the presence of a bonding layer.

[0123] Figure 13 is a schematic sectional view, illustrating a removal of the temporary substrate during a step c') of a method for manufacturing a hetero-unction structure according to the invention.

[0124] Figure 13bis is a schematic view similar to Figure 13, with the presence of a bonding layer.

[0125] Figure 14 is a schematic sectional view, illustrating a step d) of a method for manufacturing a hetero-unction structure according to the invention, with a nucleation layer made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0126] Figure 14bis is a schematic view similar to Figure 14, with the presence of a bonding layer.

[0127] Figure 15 is a schematic sectional view, illustrating a step e) of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0128] Figure 15bis is a schematic view similar to Figure 15, with the presence of a bonding layer.

[0129] It should be noted that the drawings described above are schematic, and are not necessarily to scale for the sake of readability and to simplify their understanding. The sections are made along the normal to the surface of the substrate(s) shown in the corresponding figure, that is to say along a vertical axis in normal conditions of use.

[0130] Detailed description of the implementation methods

[0131] Identical elements or those providing the same function will bear the same references for the different embodiments, for the sake of simplification.

[0132] Heterojunction structure

[0133] An object of the invention is a heterojunction structure for a high electron mobility transistor, successively comprising:

[0134] - a substrate 1;

[0135] - a nucleation layer 2, made of a material different from the substrate 1 and chosen from monocrystalline silicon Si having a crystalline orientation of the “111” type and monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the type

[0136] “2H”;

[0137] - a buffer layer 3, made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ x N with x>0.5; buffer layer 3 being devoid of carbon atoms;

[0138] - first and second semiconductor layers 4, 5, made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers 4, 5 have a hetero] junction H suitable for forming a two-dimensional electron gas.

[0139] Substrate

[0140] The substrate 1 is made of a material having a coefficient of thermal expansion, noted CTE2. The material from which the substrate 1 is made is advantageously chosen so that - < 10%, where CTE1 is the coefficient of thermal expansion of the material in which the buffer layer 3 is made.

[0141] The substrate 1 is advantageously made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN. The substrate 1 is advantageously a bulk substrate (in English). By "bulk substrate" is meant a substrate whose volume is homogeneous from the point of view of its crystalline structure (monocrystalline or polycrystalline). Thus, contrary to a usual meaning, the term "bulk" is not reserved in the present description for the monocrystalline form of a substrate, and can therefore refer to the polycrystalline form of a substrate.

[0142] The substrate 1 is advantageously made of a material transparent to electromagnetic radiation to which a CC bonding layer interposed between the substrate 1 and the nucleation layer 2 can be subjected (see paragraph “Bonding layer”). By way of non-limiting example, the material from which the substrate 1 is made is advantageously transparent in the infrared.

[0143] Substrate 1 may have a diameter of 200 mm or 300 mm. Substrate 1 may have a thickness of the order of 500 pm.

[0144] Nucleation layer

[0145] The nucleation layer 2 is made of a different material from the substrate 1 so that the substrate 1 and the nucleation layer 2 form a composite substrate.

[0146] According to a first embodiment, the nucleation layer 2 is made in a monocrystalline silicon Si having a crystal orientation of the “111” type. According to a second embodiment, the nucleation layer 2 is made in a monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the “2H” type.

[0147] The nucleation layer 2 may have a thickness of between a few hundred nanometers and around ten microns. By way of non-limiting example, the nucleation layer 2 may have a thickness of between 100 nm and 5 pm.

[0148] Buffer layer

[0149] Buffer layer 3 extends over nucleation layer 2. Buffer layer 3 is devoid of carbon-type dopants. Buffer layer 3 is a monolithic layer. In other words, buffer layer 3 does not have separate sub-layers made of different materials. In other words, buffer layer 3 does not form a multi-layer structure, as in a superlattice.

[0150] According to a first embodiment, the buffer layer 3 is made of aluminum nitride AIN. According to a second embodiment, the buffer layer 3 is made of aluminum-gallium nitride Al x Cheerful_ x N with x>0.5. The material from which the buffer layer 3 is made is advantageously monocrystalline. In other words, according to the first embodiment, the aluminum nitride AIN is advantageously monocrystalline. According to the second embodiment, the aluminum-gallium nitride Al x Cheerful_ xN, with x>0.5, is advantageously monocrystalline.

[0151] The buffer layer 3 advantageously has a thickness greater than or equal to 1 μm. The buffer layer 3 may have a thickness of the order of a few microns, and is generally less than 10 μm. By way of non-limiting example, the buffer layer 3 may have a thickness of the order of 4 μm.

[0152] First and second semiconductor layers

[0153] The first semiconductor layer 4 extends over the buffer layer 3. The first semiconductor layer 4 is made of a first III-N type alloy. The first semiconductor layer 4 may have a thickness of the order of 500 nm.

[0154] The second semiconductor layer 5 extends over the first semiconductor layer 4. The second semiconductor layer 5 is made of a second III-N type alloy. The second semiconductor layer may have a thickness of the order of 20 nm.

[0155] The first and second III-N type alloys are designed such that the first and second semiconductor layers 4, 5 have a hetero] junction H adapted to form a two-dimensional electron gas. By way of non-limiting example, the first III-N type alloy may be an alloy of empirical formula Al x Cheerful_ x N, with x>0, while the second type III-N alloy can be an alloy of empirical formula Al y Cheerful_ y N, with y>x. When x=0, the first type III-N alloy is a binary alloy of gallium nitride GaN. When x^O, the first type III-N alloy is a ternary alloy of aluminum-gallium nitride AlGaN.

[0156] Bonding layer

[0157] The hetero-unction structure advantageously comprises a CC bonding layer extending between the substrate 1 and the nucleation layer 2, the CC bonding layer being designed to detach the substrate 1 from the hetero-unction structure when the CC bonding layer is subjected to electromagnetic radiation. The electromagnetic radiation may be from laser irradiation.

[0158] For this purpose, the CC bonding layer may comprise a first adhesive sub-layer which is advantageously made of a material chosen from amorphous silicon and polycrystalline silicon. The CC bonding layer may comprise a second release sub-layer which is designed to detach the substrate 1 from the heterojunction structure when the second release sub-layer is subjected to electromagnetic radiation. The second release sub-layer is advantageously made:

[0159] - in a metallic material such as aluminum Al, tin Sn, zinc Zn; or

[0160] - in a carbon material such as carbon nanotubes or graphene.

[0161] Such materials for the second release sublayer absorb in the infrared so as to separate the substrate 1 from the heterojunction structure when these materials are subjected to infrared radiation.

[0162] Of course, it is conceivable to use a CC bonding layer extending between the substrate 1 and the nucleation layer 2 which is not designed to detach the substrate 1 from the heterojunction structure. As non-limiting examples, the CC bonding layer can be made of a material chosen from amorphous silicon, polycrystalline silicon and polycrystalline aluminum nitride AIN.

[0163] On-board diode(s)

[0164] The heterojunction structure advantageously comprises at least a first diode, intended to be reverse biased. The first diode comprises a p / n junction which can extend:

[0165] (i) within substrate 1; Or

[0166] (ii) within the CC bonding layer where applicable; or

[0167] (iii) within the nucleation layer 2; or (iv) at the interface between the substrate 1 and the nucleation layer 2, in the absence of a CC bonding layer; or

[0168] (v) at the interface between the substrate 1 and the CC bonding layer where applicable; or

[0169] (vi) at the interface between the CC bonding layer and the nucleation layer 2.

[0170] Such a first diode, intended to be reverse biased, provides additional electrical insulation to that provided by the buffer layer 3. The electrical insulation obtained can be both vertical and lateral. Lateral electrical isolation is advantageous in the presence of future adjacent high electron mobility transistors.

[0171] The p / n junction of the first diode is located according to the p-type and n-type dopants chosen and according to the properties of the substrate 1, the nucleation layer 2 and the CC bonding layer if applicable. For example, a nucleation layer 2 made in a monocrystalline silicon Si having a crystal orientation of the “111” type can be easily doped with p-type or doped with n-type, which is not the case for a nucleation layer 2 made in a monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the “2H” type. Of course, the CC bonding layer must not be designed to detach the substrate 1 from the heterojunction structure when the CC bonding layer comprises dopants in order to form all or part of the first diode.

[0172] According to a first exemplary embodiment, the substrate 1 is made of p-type doped polycrystalline silicon carbide SiC and the bonding layer CC is made of n-type doped polycrystalline silicon. According to a second exemplary embodiment, the bonding layer CC is made of p-type doped polycrystalline silicon and the nucleation layer 2 is made of n-type doped monocrystalline silicon Si, having a crystal orientation of the “111” type.

[0173] The heterojunction structure advantageously comprises at least one second diode, intended to be forward biased, mounted in series and head-to-tail (i.e. in anti-series) with the first diode. Such an anti-series assembly of the first and second diodes makes it possible to limit the reverse voltage of the second diode in the off state, so as not to damage it. Indeed, significant electrical potential differences may exist between the substrate 1 and the nucleation layer 2 (or with the CC bonding layer if applicable). In addition, such an anti-series assembly makes it possible to guarantee that one of the two diodes is in the off state. High electron mobility transistor

[0174] An object of the invention is a high electron mobility transistor (HEMT), comprising:

[0175] - a hetero]unction structure in accordance with the invention;

[0176] - first and second metal zones ZM1, ZM2, each extending through the second semiconductor layer 5 so as to form an ohmic contact with the heterojunction H;

[0177] - a source electrode S and a drain electrode D, respectively electrically connected to the first and second metal zones ZM1, ZM2;

[0178] - a third metal zone ZM3, the first and second metal zones ZM1, ZM2 extending on either side of the third metal zone ZM3;

[0179] - a grid electrode G, electrically connected to the third metal zone ZM3.

[0180] First and second metal zones

[0181] The first metal zone ZM1 extends through the second semiconductor layer 5 so as to form an ohmic contact with a first lateral edge of the heterojunction H. The second metal zone ZM2 extends through the second semiconductor layer 5 so as to form an ohmic contact with a second lateral edge of the heterojunction H. The first and second lateral edges of the heterojunction H, facing each other, delimit an active zone of the heterojunction H extending between the first and second metal zones ZM1, ZM2. The first and second metal zones ZM1, ZM2 extend on either side of the third metal zone ZM3.

[0182] The source electrode S is electrically connected to the first metal area ZML The drain electrode D is electrically connected to the second metal area ZM2.

[0183] Third metal zone

[0184] The third metal zone ZM3 is advantageously arranged for:

[0185] - extend over the second semiconductor layer 5 so as to form a Schottky contact with the second semiconductor layer 5; or

[0186] - extend over a dielectric layer 6 covering the second semiconductor layer 5; or

[0187] - extend over a layer 7 of p-type doped gallium nitride GaN or over a layer 7 of p-type doped aluminum-gallium nitride AlGaN, covering the second semiconductor layer 5; or

[0188] - extend inside the second semiconductor layer 5 so as to form a recessed gate electrode G. According to a first embodiment, the third metal zone ZM3 extends over the second semiconductor layer 5 so as to form a Schottky contact with the second semiconductor layer 5. The HEMT transistor is then generally of the normally on type (“Normalyl-On” in English).

[0189] According to a second embodiment, the third metal zone ZM3 extends over a dielectric layer 6 covering the second semiconductor layer 5. The HEMT transistor in question is then of the normally on type (y Normalyl -On in English). As non-limiting examples, the dielectric layer 6 may be made of silicon dioxide SiO2, silicon nitride SijN^, aluminum nitride AIN or alumina AI2O3. The dielectric layer 6 also makes it possible to passivate the surface of the second semiconductor layer 5.

[0190] According to a third embodiment, the third metal zone ZM3 extends over a layer 7 of p-type doped gallium nitride GaN (or over a layer 7 of p-type doped aluminum-gallium nitride AlGaN), covering the second semiconductor layer 5. The HEMT transistor is of the normally blocked type (“Normalyl-Off” in English).

[0191] According to a fourth embodiment, the third metal zone ZM3 extends (partially) inside the second semiconductor layer 5 so as to obtain a recessed gate electrode G. The HEMT transistor is of the normally blocked type (“Normalyl-Off” in English).

[0192] The gate electrode G is electrically connected to the third metal zone ZM3.

[0193] The first, second and third metal zones ZM1, ZM2, ZM3 are advantageously made from aluminum Al and / or copper Cu.

[0194] Field plate(s)

[0195] The transistor advantageously comprises at least one field plate FP arranged to form a lateral extension of the third metal zone ZM3. The lateral extension is advantageously oriented towards the second metal zone ZM2.

[0196] The field plate(s) FP are made of a metallic material, preferably aluminum Al or copper Cu. The field plate(s) FP allow for a better distribution of the electric field, i.e. to reduce the intensity of the electric field near the gate electrode G, in order to obtain good lateral voltage resistance, and therefore a high breakdown voltage. Manufacturing process with a Si “111” nucleation layer

[0197] An object of the invention is a method for manufacturing a hetero] junction structure for a high electron mobility transistor, comprising the successive steps: a) using a donor substrate SD, made of monocrystalline silicon Si having a crystal orientation of the "111" type; b) assembling the donor substrate SD to a receiver substrate 1; c) thinning the donor substrate SD so as to obtain a nucleation layer 2; d) forming a buffer layer 3 on the nucleation layer 2, the buffer layer 3 being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride ALGai-xN with x>0.5; the buffer layer 3 being devoid of carbon atoms;e) successively forming first and second semiconductor layers 4, 5 on the buffer layer 3, the first and second semiconductor layers 4, 5 being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers 4, 5 have a hetero] junction H suitable for forming a two-dimensional electron gas.;

[0198] Step a)

[0199] Step a) consists of using an SD donor substrate, made of monocrystalline silicon Si with a crystal orientation of the “111” type. The SD donor substrate can have a thickness of the order of a few hundred microns.

[0200] According to one embodiment, it is possible to form by epitaxy a bilayer structure on the donor substrate SD. The bilayer structure successively comprises a layer of monocrystalline silicon Si (future nucleation layer 2) and a stop layer. The stop layer is made of a material allowing selective chemical etching relative to the silicon of the future nucleation layer 2. In this respect, the material of the stop layer may have a doping rate and / or a chemical composition (eg Ge, SiGe, SiC) suitable for obtaining selective chemical etching.

[0201] Step b)

[0202] Step b) consists of assembling the donor substrate SD to a receiving substrate 1. Step b) can be performed by direct bonding. By "direct bonding" is meant a spontaneous bonding resulting from the direct contact of two surfaces, i.e. in the absence of an additional element such as an adhesive, a wax or a solder. The adhesion mainly comes from the van der Waals forces resulting from the electronic interaction between the atoms or molecules of two surfaces, from the hydrogen bonds due to the surface preparations or from the covalent bonds established between the two surfaces. Direct bonding can be activated (i.e. activation of the surfaces) with a plasma. Direct bonding can be performed under vacuum or under ultra-high vacuum. The bonding can be direct between the donor substrate SD and the receiving substrate 1. When the donor substrate SD and / or the receiving substrate 1 are coated with a dielectric layer (e.g.an oxide layer, preferably amorphous) before bonding, the bonding can be direct between a dielectric layer and a substrate, or between two dielectric layers. The thickness of the dielectric layer(s) (e.g. of the order of 100 nm) is adapted so as not to induce a significant thermal barrier.

[0203] The receiving substrate 1 is advantageously made of a material having a coefficient of thermal expansion, noted CTE2. The material from which the substrate is made

[0204] . . . . \CTE2— CTE1\ n / ' -'•ii ' -ii recipient 1 is advantaged

[0205] & ously chosen so that - < 10%, or Cl L1 is the CTEI ' coefficient of thermal expansion of the material in which the buffer layer 3 is made during step d).

[0206] The receiving substrate 1 is advantageously made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN. The receiving substrate 1 is advantageously a bulk substrate.

[0207] The receiving substrate 1 is advantageously made of a material transparent to electromagnetic radiation to which a CC bonding layer interposed between the substrate 1 and the nucleation layer 2 can be subjected. By way of non-limiting example, the material from which the receiving substrate 1 is made is advantageously transparent in the infrared.

[0208] Indeed, step b) may comprise the steps: bi) forming a CC bonding layer on the receiving substrate 1 or on the donor substrate SD; b2) assembling the donor substrate SD to the receiving substrate 1 via the CC bonding layer.

[0209] The CC bonding layer formed during step bi) is advantageously designed to detach the receiving substrate 1 from the hetero-unction structure obtained at the end of step e) when the CC bonding layer is subjected to electromagnetic radiation. The electromagnetic radiation may come from laser irradiation.

[0210] The CC bonding layer formed during step bi) may comprise:

[0211] - a first adhesive underlayer, advantageously made from a material chosen from amorphous silicon and polycrystalline silicon;

[0212] - a second release sub-layer, designed to detach the receiving substrate 1 from the hetero-unction structure obtained at the end of step e) when the second release sub-layer is subjected to electromagnetic radiation.

[0213] The second release sub-layer is advantageously carried out:

[0214] - in a metallic material such as aluminum Al, tin Sn, zinc Zn; or

[0215] - in a carbon material such as carbon nanotubes or graphene.

[0216] Such materials for the second release sub-layer absorb in the infrared so as to separate the receiving substrate 1 from the hetero-unction structure obtained at the end of step e) when these materials are subjected to infrared radiation.

[0217] When the CC bonding layer is not designed to detach the receiving substrate 1, step b) may comprise a step consisting of doping the CC bonding layer (by implantation or by diffusion of dopants) so as to obtain a p / n junction within it, or with the receiving substrate 1 (in which case the receiving substrate 1 is doped).

[0218] Step b) is advantageously followed by thermal annealing adapted to strengthen the bonding interface between the donor substrate SD and the recipient substrate 1. By “thermal annealing” is meant a heat treatment comprising:

[0219] (i) a phase of gradual temperature increase (rise ramp) until a temperature called the annealing temperature is reached;

[0220] (ii) a holding phase (plateau) at the annealing temperature, for a period called the annealing time;

[0221] (iii) a cooling phase.

[0222] Thermal annealing is performed according to a thermal budget adapted to strengthen the bonding interface between the donor substrate SD and the receiving substrate 1. By "thermal budget" is meant an input of energy of a thermal nature, determined by the choice of a value of the annealing temperature and the choice of a value of the annealing duration. The annealing temperature can be between 300°C and 500°C. The annealing duration is of the order of a few minutes to a few hours.

[0223] Step c)

[0224] Step c) consists of thinning the SD donor substrate so as to obtain a nucleation layer 2. The term "thinning" is understood as making the SD donor substrate less thick, without limitation to a technique of a particular nature as a means of obtaining a reduced thickness for the SD donor substrate.

[0225] By way of non-limiting example, step c) may comprise a grinding step of the SD donor substrate, followed by a chemical mechanical polishing (CMP) step of the SD donor substrate. Other techniques are conceivable, involving for example a Smart-cut™ of the SD donor substrate in order to allow its recycling. Thus, it is possible to carry out a species implantation (e.g. ionic implantation of hydrogen atoms) or a species coimplantation (e.g. ionic implantation of hydrogen atoms and helium atoms) through the SD donor substrate so as to form a weakening zone. The nucleation layer 2 is then obtained by fracturing the SD donor substrate along the weakening zone, for example by thermal annealing carried out at a temperature between 250°C and 400°C, or by mechanical fracturing.The co-implantation of species makes it possible to reduce the total dose and thereby limit the damage to the nucleation layer 2. By way of non-limiting example, the implanted or co-implanted species may comprise ionized hydrogen atoms, ionized helium atoms and ionized boron atoms. Advantageously, the species are co-implanted successively across the donor substrate SD according to different doses. The boron dose is advantageously high (e.g. between 2 10. 14 at. cm 2 and 5 10 14 at. cm 2 ; in order to reduce the thermal annealing temperature of the weakening zone.

[0226] The final thickness of the nucleation layer 2 can be adjusted by applying thermal annealing, under an oxidizing or neutral atmosphere. The annealing temperature can be between 1100°C and 1200°C. The annealing time can be of the order of a few hours.

[0227] Step c) may include a step consisting of doping the nucleation layer 2 (by implantation or by diffusion of dopants) so as to obtain a p / n junction:

[0228] - within it, or

[0229] - with the receiving substrate 1 (in which case the receiving substrate 1 is doped), or

[0230] - with the CC bonding layer (in which case the CC bonding layer is doped and is not designed to detach the receiving substrate 1).

[0231] In the embodiment where a bilayer structure is formed by epitaxy on the donor substrate SD, step c) successively comprises mechanical thinning of a portion of the barrier layer, followed by selective chemical etching of the remaining portion of the barrier layer, so as to expose the nucleation layer 2 (i.e. the first layer of the bilayer structure, underlying the barrier layer).

[0232] Step d)

[0233] Step d) consists of forming a buffer layer 3 on the nucleation layer 2. Step d) advantageously comprises a prior step of cleaning the surface of the nucleation layer 2. In this regard, the surface of the nucleation layer 2 can be smoothed and deoxidized under a reducing atmosphere. Step d) is advantageously carried out by organometallic vapor phase epitaxy MOCVD, by molecular beam epitaxy MBE, or by hybrid vapor phase epitaxy HVPE.

[0234] The buffer layer 3 is made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ x N with x>0.5.

[0235] The buffer layer 3 formed during step d) is advantageously made of a monocrystalline material. To do this, as mentioned previously, step d) can be carried out by MOCVD epitaxy, by MBE epitaxy or by HVPE epitaxy. It is also possible, in order to limit the operating time, to form a polycrystalline material by physical vapor deposition (PVD) and then possibly crystallize this material (this is called recrystallization). Step d) can combine MOCVD epitaxy with recrystallized PVD deposition. Recrystallization can be carried out by thermal annealing. It is also possible to successively apply MOCVD epitaxy, PVD deposition, and then MOCVD epitaxy to form the buffer layer 3 on the nucleation layer 2.

[0236] The buffer layer 3 formed during step d) advantageously has a thickness greater than 1 μm.

[0237] Step e)

[0238] Step e) consists of successively forming the first and second semiconductor layers 4, 5 on the buffer layer 3. Step e) can be carried out by MOCVD epitaxy or by MBE epitaxy.

[0239] The first semiconductor layer 4 extends over the buffer layer 3. The first semiconductor layer 4 is made of a first III-N type alloy.

[0240] The second semiconductor layer 5 extends over the first semiconductor layer 4. The second semiconductor layer 5 is made of a second III-N type alloy.

[0241] The first and second III-N type alloys are designed such that the first and second semiconductor layers 4, 5 have a hetero] junction H adapted to form a two-dimensional electron gas. By way of non-limiting example, the first III-N type alloy may be an alloy of empirical formula Al x Cheerful_x N, with x>0, while the second type III-N alloy can be an alloy of empirical formula Al y Cheerful_ y N, with y>x. When x=0, the first III-N alloy is a binary alloy of gallium nitride GaN. When x^O, the first III-N alloy is a ternary alloy of aluminum-gallium nitride AlGaN. Manufacturing process with a 2H AIN nucleation layer

[0242] An object of the invention is a method for manufacturing a hetero] junction structure for a high electron mobility transistor, comprising the successive steps: a') forming a nucleation layer 2 on a growth substrate SC, the nucleation layer 2 being made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type, the nucleation layer 2 having:

[0243] - a first face 20, free, having an aluminum Al type polarity;

[0244] - a second face 21, opposite the first face 20, having a nitrogen N type polarity; b') assembling the growth substrate SC to a temporary substrate ST on the side of the first face 20 of the nucleation layer 2; then removing the growth substrate SC so as to expose the second face 21 of the nucleation layer 2; c') assembling the temporary substrate ST to a receiving substrate 1 on the side of the second face 21 of the nucleation layer 2; then removing the temporary substrate ST so as to expose the first face 20 of the nucleation layer 2; d) forming a buffer layer 3 on the nucleation layer 2, the buffer layer 3 being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGai-xN with x>0.5; the buffer layer 3 being devoid of carbon atoms;e) successively forming first and second semiconductor layers 4, 5 on the buffer layer 3, the first and second semiconductor layers 4, 5 being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers 4, 5 have a hetero] junction H suitable for forming a two-dimensional electron gas.;

[0245] Step a')

[0246] Step a') consists of forming a nucleation layer 2 on a growth substrate SC. As a non-limiting example, the growth substrate SC can be made of silicon Si. Step a') can be carried out by MOCVD epitaxy or by MBE epitaxy.

[0247] Nucleation layer 2 is made of monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the “2H” type.

[0248] Nucleation layer 2 presents:

[0249] - a first face 20, free, having an aluminum Al type polarity;

[0250] - a second face 21, opposite the first face 20, having a nitrogen N type polarity. Step b')

[0251] Step b') comprises the successive steps: b'i) assembling the growth substrate SC to a temporary substrate ST on the side of the first face 20 of the nucleation layer 2; b'2) removing the growth substrate SC so as to expose the second face 21 of the nucleation layer 2.

[0252] Step b'i) can be performed by direct bonding. The bonding can be direct between the growth substrate SC and the temporary substrate ST. When the growth substrate SC and / or the temporary substrate ST are coated with a dielectric layer (e.g. an oxide layer, preferably amorphous) before bonding, the bonding can be direct between a dielectric layer and a substrate, or between two dielectric layers. The thickness of the dielectric layer(s) (e.g. of the order of 100 nm) is adapted so as not to induce a significant thermal barrier.

[0253] As a non-limiting example, the temporary substrate ST can be made of silicon Si.

[0254] Step b'2) can be performed by engraving. The engraving can be dry or wet, possibly in combination with grinding and chemical-mechanical polishing.

[0255] Step c)

[0256] Step c') includes the successive steps:

[0257] - assembling the temporary substrate ST to a receiving substrate 1 on the side of the second face 21 of the nucleation layer 2, preferably by direct bonding;

[0258] - removing the temporary substrate ST so as to expose the first face 20 of the nucleation layer 2, preferably by etching (dry or wet, possibly in combination with grinding and chemical-mechanical polishing).

[0259] The bonding can be direct between the temporary substrate ST and the receiving substrate 1. When the temporary substrate ST and / or the receiving substrate 1 are coated with a dielectric layer (e.g. an oxide layer, preferably amorphous) before bonding, the bonding can be direct between a dielectric layer and a substrate, or between two dielectric layers. The thickness of the dielectric layer(s) (e.g. of the order of 100 nm) is adapted so as not to induce a significant thermal barrier.

[0260] The bonding may not be direct between the temporary substrate ST and the receiving substrate 1. For this purpose, it is possible to use a polymer layer to assemble the temporary substrate ST to the receiving substrate 1 on the side of the second face 21 of the nucleation layer 2. If necessary, it is possible to remove the temporary substrate ST with a laser source. Tl

[0261] The receiving substrate 1 is advantageously made of a material having a coefficient of thermal expansion, noted CTE2. The material from which the substrate is made receiver 1 is advantageously chosen so that - < 10%, where CTE1 is the coefficient of thermal expansion of the material in which the buffer layer 3 is made during step d).

[0262] The receiving substrate 1 is advantageously made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN. The receiving substrate 1 is advantageously a bulk substrate.

[0263] The receiving substrate 1 is advantageously made of a material transparent to electromagnetic radiation to which a CC bonding layer interposed between the substrate 1 and the nucleation layer 2 can be subjected. By way of non-limiting example, the material from which the receiving substrate 1 is made is advantageously transparent in the infrared.

[0264] Indeed, step c') may comprise the steps: ci) forming a bonding layer CC on the receiving substrate 1 or on the second face 21 of the nucleation layer 2; c' 2) assembling the temporary substrate ST to the receiving substrate 1 via the bonding layer CC.

[0265] The CC bonding layer formed during step c'i) is advantageously designed to detach the receiving substrate 1 from the hetero-unction structure obtained at the end of step e) when the CC bonding layer is subjected to electromagnetic radiation. The electromagnetic radiation may come from laser irradiation.

[0266] The CC bonding layer formed during step c'i) may comprise:

[0267] - a first adhesive underlayer, advantageously made from a material chosen from amorphous silicon and polycrystalline silicon;

[0268] - a second release sub-layer, designed to detach the receiving substrate 1 from the hetero-unction structure obtained at the end of step e) when the second release sub-layer is subjected to electromagnetic radiation.

[0269] The second release sub-layer is advantageously carried out:

[0270] - in a metallic material such as aluminum Al, tin Sn, zinc Zn; or

[0271] - in a carbon material such as carbon nanotubes or graphene.

[0272] Such materials for the second release sub-layer absorb in the infrared so as to separate the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when these materials are subjected to infrared radiation. When the CC bonding layer is not designed to detach the receiving substrate 1, step c') may comprise a step consisting of doping the CC bonding layer (by implantation or by diffusion of dopants) so as to obtain a p / n junction within it, or with the receiving substrate 1 (in which case the receiving substrate 1 is doped).

[0273] Step c') advantageously includes a thermal annealing step adapted to reinforce the bonding interface between the temporary substrate ST and the receiving substrate 1.

[0274] Step d)

[0275] Step d) consists of forming a buffer layer 3 on the nucleation layer 2. More precisely, step d) consists of forming a buffer layer 3 on the first face 20 of the nucleation layer 2 exposed at the end of step c'). Step d) advantageously comprises a prior step consisting of cleaning the surface of the nucleation layer 2.

[0276] Step d) is advantageously carried out by organometallic vapor phase epitaxy MOCVD, by molecular beam epitaxy MBE or by hybrid vapor phase epitaxy HVPE.

[0277] The buffer layer 3 is made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ x N with x>0.5.

[0278] The buffer layer 3 formed during step d) is advantageously made of a monocrystalline material. To do this, as mentioned previously, step d) can be carried out by MOCVD epitaxy, by MBE epitaxy or by HVPE epitaxy. It is also possible, in order to limit the operating time, to form a polycrystalline material by physical vapor deposition (PVD) and then to crystallize this material (this is called recrystallization). Step d) can combine MOCVD epitaxy with recrystallized PVD deposition. Recrystallization can be carried out by thermal annealing.

[0279] The buffer layer 3 formed during step d) advantageously has a thickness greater than 1 μm.

[0280] Step e)

[0281] Step e) consists of successively forming the first and second semiconductor layers 4, 5 on the buffer layer 3. Step e) can be carried out by MOCVD epitaxy or by MBE epitaxy.

[0282] The first semiconductor layer 4 extends over the buffer layer 3. The first semiconductor layer 4 is made of a first III-N type alloy. The second semiconductor layer 5 extends over the first semiconductor layer 4. The second semiconductor layer 5 is made of a second III-N type alloy.

[0283] The first and second III-N type alloys are designed such that the first and second semiconductor layers 4, 5 have a hetero] junction H adapted to form a two-dimensional electron gas. By way of non-limiting example, the first III-N type alloy may be an alloy of empirical formula Al x Cheerful_ xN, with x>0, while the second type III-N alloy can be an alloy of empirical formula Al y Cheerful_ y N, with y>x. When x=0, the first type III-N alloy is a binary alloy of gallium nitride GaN. When x^O, the first type III-N alloy is a ternary alloy of aluminum-gallium nitride AlGaN.

[0284] The invention is not limited to the embodiments disclosed. Those skilled in the art are able to consider their technically effective combinations and to substitute equivalents for them.

Claims

CLAIMS 1. Hetero-functional structure for a high electron mobility transistor, successively comprising: - a substrate (1); - a nucleation layer (2), made of a material different from the substrate (1) and chosen from monocrystalline silicon Si having a crystalline orientation of the “111” type and monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type; - a buffer layer (3), made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ x N with x>0.5; the buffer layer (3) being devoid of carbon atoms; - first and second semiconductor layers (4, 5), made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a hetero] junction (H) suitable for forming a two-dimensional electron gas.

2. Heterojunction structure according to claim 1, in which: - the material from which the buffer layer (3) is made has a first coefficient of thermal expansion, noted CTE1; - the substrate (1) is made of a material having a second coefficient of thermal expansion, noted CTE2; the material from which the substrate (1) is made being chosen so that 3. Heterojunction structure according to claim 1 or 2, in which the substrate (1) is made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN.

4. Heterojunction structure according to one of claims 1 to 3, comprising a bonding layer (CC) extending between the substrate (1) and the nucleation layer (2), the bonding layer (CC) being designed to detach the substrate (1) from the heterojunction structure when the bonding layer (CC) is subjected to electromagnetic radiation; the substrate (1) being made of a material transparent to electromagnetic radiation.

5. Hetero-unction structure according to claim 4, in which the bonding layer (CC) comprises: - a first adhesive underlayer, preferably made of a material chosen from amorphous silicon and polycrystalline silicon; - a second release sub-layer, designed to detach the substrate (1) from the hetero-unction structure when the second release sub-layer is subjected to electromagnetic radiation; the second release sub-layer preferably being made of a metallic material such as aluminum Al, tin Sn or zinc Zn, or preferably made of a carbon material such as carbon nanotubes or graphene.

6. Heterojunction structure according to one of claims 1 to 5, in which the buffer layer (3) has a thickness greater than or equal to 1 μm.

7. Heterojunction structure according to one of claims 1 to 6, in which the material in which the buffer layer (3) is made is monocrystalline.

8. Heterojunction structure according to one of claims 1 to 7, in which: - the first type III-N alloy is an alloy with the empirical formula Al x Cheerful_ xN, with x>0; - the second type III-N alloy is an alloy with the empirical formula Al y Cheerful_ y N, with y>x.

9. High electron mobility transistor, comprising: - a heterojunction structure according to one of claims 1 to 8; - first and second metal zones (ZM1, ZM2), each extending through the second semiconductor layer (5) so as to form an ohmic contact with the heterojunction (H); - a source electrode (S) and a drain electrode (D), respectively electrically connected to the first and second metal zones (ZM1, ZM2); - a third metal zone (ZM3), the first and second metal zones (ZM1, ZM2) extending on either side of the third metal zone (ZM3); - a grid electrode (G), electrically connected to the third metal zone (ZM3).

10. Transistor according to claim 9, in which the third metal zone (ZM3) is arranged to: - extend over the second semiconductor layer (5) so as to form a Schottky contact with the second semiconductor layer (5); or - extend over a dielectric layer (6) covering the second semiconductor layer (5); or - extend over a layer (7) of p-type doped gallium nitride GaN or over a layer (7) of p-type doped aluminum-gallium nitride AlGaN, covering the second semiconductor layer (5); or - extend inside the second semiconductor layer (5) so as to form a recessed gate electrode (G).

11. Transistor according to claim 9 or 10, comprising at least one field plate (FP) arranged to form a lateral extension of the third metal zone (ZM3), the lateral extension being oriented towards the second metal zone (ZM2).

12. Method for manufacturing a hetero] junction structure for a high electron mobility transistor, comprising the successive steps: a) using a donor substrate (SD), made of monocrystalline silicon Si having a crystal orientation of the “111” type; b) assembling the donor substrate (SD) to a receiving substrate (1); c) thinning the donor substrate (SD) so as to obtain a nucleation layer (2); d) forming a buffer layer (3) on the nucleation layer (2), the buffer layer (3) being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ xN with x>0.5; the buffer layer (3) being devoid of carbon atoms; e) successively forming first and second semiconductor layers (4, 5) on the buffer layer (3), the first and second semiconductor layers (4, 5) being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a hetero] junction (H) suitable for forming a two-dimensional electron gas.

13. Method according to claim 12, wherein step b) comprises the steps: bi) forming a bonding layer (CC) on the receiving substrate (1) or on the donor substrate (1); b2) assembling the donor substrate (SD) to the receiving substrate (1) via the bonding layer (CC); the bonding layer (CC) formed during step bi) preferably being designed to detach the receiving substrate (1) from the hetero-unction structure obtained at the end of step e) when the bonding layer (CC) is subjected to electromagnetic radiation; the receiving substrate (1) being made of a material transparent to electromagnetic radiation.

14. Method for manufacturing a hetero] junction structure for a high electron mobility transistor, comprising the successive steps: a') forming a nucleation layer (2) on a growth substrate (SC), the nucleation layer (2) being made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type, the nucleation layer (2) having: - a first face (20), free, having an aluminum Al type polarity; - a second face (21), opposite the first face (20), having a nitrogen N type polarity; b') assembling the growth substrate (SC) to a temporary substrate (ST) on the side of the first face (20) of the nucleation layer (2); then removing the growth substrate (SC) so as to expose the second face (21) of the nucleation layer (2); c') assembling the temporary substrate (ST) to a receiving substrate (1) on the side of the second face (21) of the nucleation layer (2); then removing the temporary substrate (ST) so as to expose the first face (20) of the nucleation layer (2); d) forming a buffer layer (3) on the nucleation layer (2), the buffer layer (3) being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride Al x Cheerful_ xN with x>0.5; the buffer layer (3) being devoid of carbon atoms; e) successively forming first and second semiconductor layers (4, 5) on the buffer layer (3), the first and second semiconductor layers (4, 5) being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a heterojunction (H) adapted to form a two-dimensional electron gas.

15. Method according to claim 14, in which step c') comprises the steps: ci) forming a bonding layer (CC) on the receiving substrate (1) or on the second face (21) of the nucleation layer (2); c'2) assembling the temporary substrate (ST) to the receiving substrate (1) via the bonding layer (CC); the bonding layer (CC) formed during step c'i) preferably being designed to detach the receiving substrate (1) from the hetero-unction structure obtained at the end of step e) when the bonding layer (CC) is subjected to electromagnetic radiation; the receiving substrate (1) being made of a material transparent to electromagnetic radiation.

Citation Information

Patent Citations

  • Semiconductor structures and method for fabricating the same

    US20190288099A1

  • Semiconductor devices and methods for fabricating the same

    US20200365718A1