Method and device for an integrated circuit

Abstract

The invention relates to a method for a first integrated circuit, which can be arranged or is arranged together with at least one further, for example second, integrated circuit on a substrate and is designed to exchange first information with the second integrated circuit via a first communication interface, wherein the method comprises: exchanging second information, which is different from the first information, for example, with the at least one further, for example second, integrated circuit via a second communication interface, which is different from the first communication interface.

Description

[0001] Description

[0002] title

[0003] Method and device for an integrated circuit

[0004] State of the art

[0005] The disclosure relates to at least one method for an integrated circuit.

[0006] The disclosure further relates to at least one device for an integrated circuit.

[0007] Disclosure of the invention

[0008] Some examples relate to a method, for example a computer-implemented method, for a first integrated circuit that can be arranged or is arranged together with at least one further, for example second, integrated circuit on a substrate and is designed to exchange first information with the second integrated circuit via a first communication interface, the method comprising: exchanging second information, which is different from the first information, for example, with the at least one further, for example second, integrated circuit, via a second communication interface that is different from the first communication interface.

[0009] In some examples, the method comprises: evaluating an operating state of at least one component of the at least one further integrated circuit based on at least a portion of the second information.

[0010] In some examples, it is provided that the method comprises at least one of the following elements: a) deactivating at least one component of a communication module of the first integrated circuit, which is designed for the exchange of information with the at least one further integrated circuit via the first communication interface, or b) activating at least one component of the communication module of the first integrated circuit, which is designed for the exchange of information with the at least one further integrated circuit via the first communication interface.

[0011] In some examples, it is provided that the first integrated circuit and the at least one further, for example second, integrated circuit are each designed as a chip, for example chiplet, wherein, for example, the first integrated circuit and the at least one further, for example second, integrated circuit form a multi-chiplet system.

[0012] In some examples, the method comprises: sending a question via the second communication interface to the at least one further integrated circuit, optionally, for example if necessary, receiving an answer to the question via the second communication interface from the at least one further integrated circuit, evaluating an operating state of at least one component of the at least one further integrated circuit based on the answer, for example based on at least one of: a) content of the answer, or b) absence of a answer. In some examples, the evaluation of the operating state can thus also take into account the absence of a answer, which can be the case, for example, if a function of the at least one further integrated circuit is impaired in such a way that it cannot provide the answer.

[0013] In some examples, it is provided that the question is designed such that determining the answer to the question by the at least one further integrated circuit causes a predeterminable, for example functional, load on at least one component of the at least one further integrated circuit.

[0014] In some examples, the method comprises: receiving information characterizing a workload, for example workload, of at least one component of the at least one further integrated circuit via the second communication interface from the at least one further integrated circuit, and, optionally, evaluating an operating state of at least one component of the at least one further integrated circuit based on the information.

[0015] In some examples, it is provided that the evaluation comprises at least one of the following elements: a) determining whether a functional error is present in at least one component of the at least one further integrated circuit, or b) determining whether a workload, for example workload, of at least one component of the at least one further integrated circuit exceeds a predefinable first threshold value, or c) determining whether a workload, for example workload, of at least one component of the at least one further integrated circuit falls below a predefinable second threshold value, or d) determining whether a response time for answering a question or the question exceeds a predefinable third threshold value.

[0016] Some examples relate to a method for a second integrated circuit which can be arranged or is arranged together with at least one further integrated circuit, for example the first integrated circuit already described above, on a substrate and is designed to exchange first information with the first integrated circuit via a first communication interface, the method comprising: exchanging second information, which is different from the first information, for example, with the first integrated circuit, via a second communication interface which is different from the first communication interface.

[0017] In some examples, as already described, it is provided that the first integrated circuit and the second integrated circuit are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit and the second integrated circuit form a multi-chiplet system.

[0018] In some examples, the method comprises: receiving a question via the second communication interface from the first integrated circuit, and, optionally, determining an answer to the question, and, optionally, sending the answer to the question via the second communication interface to the first integrated circuit, wherein, for example, the question is designed such that determining the answer to the question by the at least one further integrated circuit causes a predeterminable, for example functional, load on at least one component of the at least one further integrated circuit.

[0019] In some examples, the method comprises: determining information that characterizes a workload, for example workload, of at least one component of the second integrated circuit, sending the information to the first integrated circuit via the second communication interface.

[0020] In some examples, the first communication interface is provided to be a, e.g., unified, chiplet interface, e.g. of the type Universal Chiplet Interconnect Express, UCIe.

[0021] In some examples, it is provided that the second communication interface is used dedicated to the exchange of the second information, for example not for the exchange of the first information.

[0022] Some examples relate to an apparatus for carrying out the method according to the disclosure.

[0023] Some examples relate to an integrated circuit, for example for a multi-chiplet system comprising a plurality of chiplets, comprising at least one device according to the disclosure, wherein, for example, the device or a functionality of the device is integrated into the integrated circuit.

[0024] Some examples relate to a system, for example a multi-chiplet system, comprising at least one device according to the disclosure or at least one integrated circuit according to the disclosure.

[0025] In some examples, the system is contemplated to include more than two integrated circuits, such as chiplets, such as a plurality of chiplets, wherein at least two chiplets each include a device according to the disclosure.

[0026] Some examples relate to a product, for example a control unit, for example for a motor vehicle, comprising at least one device according to the disclosure. Some examples relate to a vehicle, for example a motor vehicle, comprising at least one device according to the disclosure and / or at least one product, for example a control unit, according to the disclosure.

[0027] Some examples relate to a computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to perform the method according to the disclosure.

[0028] Some examples relate to a computer program comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the disclosure.

[0029] Some examples relate to a data carrier signal that characterizes and / or transmits the computer program according to the disclosure.

[0030] Some examples relate to a use of the method according to the disclosure and / or the device according to the disclosure and / or the integrated circuit according to the disclosure and / or the system according to the disclosure and / or the product according to the disclosure and / or the vehicle according to the disclosure and / or the computer-readable storage medium according to the disclosure and / or the computer program according to the disclosure and / or the data carrier signal according to the disclosure for at least one of the following elements: a) checking at least one integrated circuit for functionality, or b) checking at least one integrated circuit for a workload, for example workload, or c) evaluating an operating state of at least one component of at least one integrated circuit, or d) blocking the first communication interface, e) increasing a security of the system.

[0031] Further features, possible applications, and advantages of the invention will become apparent from the following description of examples of the invention, which are illustrated in the figures of the drawing. All described or illustrated features, individually or in any combination, constitute the subject matter of the invention, regardless of their summary in the claims or their references, as well as regardless of their wording or representation in the description or in the drawing. The drawing shows:

[0032] Fig. 1 schematically shows a simplified flow diagram,

[0033] Fig. 2 schematically shows a simplified block diagram,

[0034] Fig. 3 schematically shows a simplified flow diagram,

[0035] Fig. 4 schematically shows a simplified flow diagram,

[0036] Fig. 5 schematically shows a simplified block diagram,

[0037] Fig. 6 schematically shows a simplified flow diagram,

[0038] Fig. 7 schematically shows a simplified flow diagram,

[0039] Fig. 8 schematically shows a simplified flow diagram,

[0040] Fig. 9 schematically shows a simplified block diagram,

[0041] Fig. 10 schematically shows a simplified block diagram,

[0042] Fig. 11 schematically shows a simplified block diagram,

[0043] Fig. 12 schematically shows a simplified block diagram,

[0044] Fig. 13 schematic examples of uses.

[0045] Some examples, Fig. 1, 2, relate to a method, for example a computer-implemented method, for a first integrated circuit 110, which can be arranged or is arranged together with at least one further, for example second, integrated circuit 120 on a substrate 102 and is designed to exchange first information 1-1 with the second integrated circuit 120 via a first communication interface 131, the method comprising: exchanging 202 second information I-2, which is different, for example, from the first information 1-1, with the at least one further, for example second, integrated circuit 120, via a second communication interface 132, which is different from the first communication interface 131. Optionally, for example before exchanging 202 the second information I-2, an exchange 200 of the first information 1-1 can take place.

[0046] In some examples, Fig. 2, the method comprises: evaluating 204 an operating state of at least one component of the at least one further integrated circuit 120 based on at least a portion of the second information I-2. In some examples, the evaluation BEW can be used for controlling and / or regulating the operation of at least one component, for example, of at least one of the integrated circuits 110, 120.

[0047] In some examples, Fig. 1 , 2, it is provided that the method comprises at least one of the following elements: a) deactivating 206a at least one component of a communication module 112 of the first integrated circuit 110, which is designed for the exchange of information with the at least one further integrated circuit 120 via the first communication interface 131, for example based on the evaluation BEW, 204, or b) activating 206b at least one component of the communication module 112 of the first integrated circuit 110, which is designed for the exchange of information with the at least one further integrated circuit 120 via the first communication interface 131, for example based on the evaluation BEW, 204.

[0048] Element 122 according to Fig. 2 symbolizes a communication module of the second integrated circuit 120 according to some examples, which is designed for the exchange of information with the first integrated circuit 110 via the first communication interface 131.

[0049] Element 114 according to Fig. 2 symbolizes a communication module of the first integrated circuit 110 according to some examples, which is designed for the exchange of information with the second integrated circuit 120 via the second communication interface 132.

[0050] Element 124 according to Fig. 2 symbolizes a communication module of the second integrated circuit 120 according to some examples, which is designed for exchanging information with the first integrated circuit 110 via the second communication interface 132. In some examples, Fig. 2, it is provided that the first integrated circuit 110 and the at least one further, for example second, integrated circuit 120 are each designed as a chip, for example a chiplet, wherein, for example, the first integrated circuit 110 and the at least one further, for example second, integrated circuit 120 form a multi-chiplet system 100, e.g., together with the common substrate 102.

[0051] In some examples, at least one chiplet 110, 120 may be associated with a device 300 for executing aspects according to the examples, e.g., integrated into the respective chiplet and / or arranged on the substrate 102.

[0052] In some examples, Fig. 3, it is provided that the method comprises: sending 210 a question FR via the second communication interface 132 to the at least one further integrated circuit 120, optionally, for example if necessary (e.g. when the second integrated circuit 120 sends a response AW), receiving 212 one or the response AW to the question FR via the second communication interface 132 from the at least one further integrated circuit 120, evaluating 214 an operating state of at least one component of the at least one further integrated circuit 120 based on the response AW, for example based on at least one of: a) content of the response AW, or b) absence of the response AW.In some examples, the evaluation 214 of the operating state may thus also take into account the absence of a response AW, which may be the case, for example, if a function of the at least one further integrated circuit 120 is impaired in such a way that it cannot provide and / or send the response AW.

[0053] In some examples, it is provided that the question FR is designed such that determining the answer AW to the question FR by the at least one further integrated circuit 120 causes a predeterminable, for example functional, load (e.g. characterizable by computing resources and / or memory resources and / or an electrical energy consumption) of at least one component of the at least one further integrated circuit 120.

[0054] In some examples, Fig. 4, it is provided that the method comprises:

[0055] Receiving 220 information l-WL characterizing a workload, for example workload, of at least one component of the at least one further integrated circuit 120, via the second communication interface 132 from the at least one further integrated circuit 120, and, optionally, evaluating 222 an operating state of at least one component of the at least one further integrated circuit 120 based on the information l-WL.

[0056] In some examples, Fig. 5, it is provided that the evaluation 204, 214, 222 comprises at least one of the following elements: a) determining 230 whether a functional error is present in at least one component of the at least one further integrated circuit 120, or b) determining 232 whether a workload, for example workload, of at least one component of the at least one further integrated circuit 120 exceeds a predefinable first threshold value, or c) determining 234 whether a workload, for example workload, of at least one component of the at least one further integrated circuit 120 falls below a predefinable second threshold value, or d) determining 236 whether a response time for answering a question FR or the question FR exceeds a predefinable third threshold value.

[0057] In some examples, the at least one component of the second circuit 120 is, for example, a computing device, e.g., a processor.

[0058] Some examples, Fig. 6, relate to a method for a second integrated circuit 120 (Fig. 2), which can be arranged or is arranged together with at least one further integrated circuit, for example the first integrated circuit 110 already described above, on a substrate 102 and is designed to exchange 250 first information 1-1 with the first integrated circuit 110 via a or the first communication interface 110, the method comprising: exchanging 252 second information I-2, which is different, for example, from the first information 1-1, with the first integrated circuit 110, via a second communication interface 132, which is different from the first communication interface 131.

[0059] In some examples, as already described, it is provided that the first integrated circuit 110 and the second integrated circuit 120 are each formed as a chip, for example a chiplet, wherein, for example, the first integrated circuit and the second integrated circuit form a multi-chiplet system 100. In some examples, Fig.7, it is provided that the method comprises: receiving 260 a question FR via the second communication interface 132 from the first integrated circuit 110, and, optionally, determining 262 an answer AW to the question FR, and, optionally, sending 264 the answer AW to the question FR via the second communication interface 132 to the first integrated circuit 110, wherein, for example, the question FR is designed such that determining 262 the answer AW to the question FR by the at least one further integrated circuit 120 brings about a predeterminable, for example functional, load on at least one component of the at least one further integrated circuit 120.

[0060] In some examples, Fig. 8, it is provided that the method comprises: determining 270 information l-WL that characterizes a workload, for example workload, of at least one component of the second integrated circuit 120, sending 272 the information l-WL via the second communication interface 132 to the first integrated circuit 110.

[0061] In some examples, Fig. 2, it is provided that the first communication interface 131 is a, e.g., unified, chiplet interface, e.g., of the type Universal Chiplet Interconnect Express, UCIe.

[0062] In some examples, the second communication interface 132 is dedicated to exchanging the second information I-2, for example, not for exchanging the first information I-1. For example, the second communication interface 132 can be physically separated from the first communication interface 131, with individual transmitting and / or receiving devices 114, 124 also being provided for the chiplets 110, 120, for example. For example, the components 114, 124 are also physically separated from the components 112, 122.

[0063] Fig. 9 schematically shows a simplified block diagram according to some examples. Reference numeral 100' symbolizes a multi-chiplet system comprising a first chiplet 110' and a second chiplet 120'.

[0064] The first chiplet 110' has a communication module 112' for communication with the second chiplet 120' via a first communication interface 131'. For example, the first communication interface 131' is of the UCI type, e.g. UCIe, where the arrows a1, a2 symbolize an exchange of information via a main band channel of the first communication interface 131', and where the arrows a3, a4 symbolize an exchange of information via a side band channel of the first communication interface 131'. Element 112-1 according to Fig. 9 symbolizes a transmitting device, e.g. of the UCIe MB type, element 112-2 symbolizes a receiving device, e.g. of the UCIe MB type. Element 112-3 according to Fig. 9 symbolizes a transmitting device, e.g. of the UCIe SB type, element 112-4 symbolizes a receiving device, e.g. of the UCIe SB type.

[0065] The second chiplet 120' has a communication module 122' for communicating with the first chiplet 110' via the first communication interface 131'. Element 122-1 symbolizes a transmitting device, e.g., of the UCIe MB type. Element 122-2 symbolizes a receiving device, e.g., of the UCIe MB type. Element 122-3 symbolizes a transmitting device, e.g., of the UCIe SB type. Element 122-4 symbolizes a receiving device, e.g., of the UCIe SB type.

[0066] Element 132' of Fig. 9 symbolizes aspects of an information exchange between the chiplets 110', 120' via the second communication interface (see element 132 of Fig. 2) according to some examples, which is different from the first communication interface 131'.

[0067] Element E1 symbolizes the formation and / or transmission of at least one question a5 to the second chiplet 120', and element E2 symbolizes the formation and / or transmission of at least one answer a6 to the question a5.

[0068] Element E3 symbolizes a determination of a workload, for example workload, of at least one component of the second chiplet 120', and element E4 symbolizes an evaluation, for example monitoring, of the information a7 relating to the workload transmitted by the second chiplet 120' via the second communication interface.

[0069] In some examples, an exchange of information can take place between the elements E2, E3 or E1, E4, see the unlabeled further arrows between the relevant components in Fig. 9.

[0070] Element E5 symbolizes an evaluation of information a8 determined by at least one of the elements E1, E2, E3, E4 regarding the second chiplet 120', for example, with regard to static and / or dynamic operating behavior. In some examples, based on the evaluation E5, for example, at least one component 112-1, 112-2, 112-3, 112-4 of the communication module 112' can be deactivated or activated, see arrow a9.

[0071] In some examples, this allows the first chiplet 110' to evaluate, e.g., proper operation of the second chiplet 120' and, based on the evaluation, to at least temporarily deactivate communication via the first communication interface 131'. In some examples, this may increase the security and / or reliability of the system 100'.

[0072] Fig. 10 schematically shows a simplified block diagram according to some examples. Reference numeral 100 symbolizes a multi-chiplet system comprising a plurality of chiplets 110, 120, 120a, 120b, 120c arranged on a common substrate 102. Chiplet 110 can, for example, be configured to exchange information or data with the other chiplets via respective communication interfaces 131, 132, 131a, 132a, 131b, 132b, 135. For example, chiplet 110 is configured to manage or monitor at least one further chiplet 120, 120a, 120b, 120c, e.g., as a system management chiplet (SMC).

[0073] For example, chiplet 120 is a hardware-based accelerator device, e.g., for executing artificial intelligence algorithms, e.g., machine learning. For example, chiplet 120a is configured as a processing device, e.g., a processor, e.g., a CPU. For example, chiplet 120b is configured as a graphics processor, GPU. For example, chiplet 120c is configured as a memory device.

[0074] Optionally, a (further) graphics processor 140 may be present, which is connected to the CPU chiplet 120a via an interface 141, e.g. of the PCIe type.

[0075] The communication interfaces 131, 132, 131a, 132a, 131b, 132b are, for example, die-to-die interfaces, e.g., of the UCIe type. Optionally, at least some of the chiplets 120, 120a, 120b can also be connected, e.g., to each other, to further communication interfaces 133, 134 (e.g., of the UCIe type). In some examples, at least one chiplet 110, 120, 120a, 120b can be assigned a device 300 for executing aspects according to the examples, e.g., integrated into the respective chiplet.

[0076] For example, the SMC 110 can thereby evaluate and / or monitor the operation of at least one additional chiplet 120, 120a, 120b, and, if necessary, at least temporarily prevent or enable communication with the at least one additional chiplet, e.g., via a respective UCIe interface. For example, the SMC 110 can also be used as a central backbone.

[0077] The multi-chiplet system 100" according to Fig. 10 can be used in further examples, e.g. for applications in the vehicle sector, for example in the motor vehicle sector.

[0078] Some examples, Fig. 11 , relate to an apparatus 300 for carrying out the method according to the disclosure.

[0079] In some examples, Fig. 11 , it is provided that the device 300 comprises: a computing device ("computer") 302 having at least one computing core 302a, a memory device 304 assigned to the computing device 302 for at least temporarily storing at least one of the following elements: a) data DAT (e.g. data associated with the second information I-2 and / or a question or answer and / or a workload and / or an assessment), b) computer program PRG, for example for carrying out the method according to the disclosure.

[0080] In further examples, the storage device 304 comprises a volatile memory (e.g., random access memory (RAM)) 304a, and / or a non-volatile (NVM) memory (e.g., flash EEPROM) 304b, or a combination thereof or with other memory types not explicitly mentioned.

[0081] In further examples, the device 300 is implemented as a hardware circuit, for example a pure hardware circuit (not shown).

[0082] In further examples, Figs. 2, 9, 10, the device 300 can be provided for at least one chiplet, e.g., integrated into the chiplet in question (or arranged outside the chiplet, e.g., on the substrate). Further examples, Fig. 11, relate to a computer-readable storage medium SM comprising instructions PRG that, when executed by a computer 302, cause the computer 302 to perform the method according to the disclosure.

[0083] Further examples relate to a computer program PRG comprising instructions which, when the program PRG is executed by a computer 302, cause the computer 302 to carry out the method according to the disclosure.

[0084] Further examples relate to a data carrier signal DCS that characterizes and / or transmits the computer program PRG according to the disclosure. The data carrier signal DCS can be received, for example, via an optional data interface 306 of the device 300.

[0085] Some examples relate to an integrated circuit, e.g., a chiplet 110, 120, for example for a multi-chiplet system 100, 100', 100", comprising several chiplets, comprising at least one device 300 according to the disclosure, wherein, for example, the device 300 or a functionality of the device 300 is integrated into the integrated circuit 110, 120.

[0086] Some examples relate to a system 100, 100', 100", for example a multi-chiplet system, comprising at least one device 300 according to the disclosure or at least one integrated circuit 110, 120 according to the disclosure.

[0087] In some examples, Fig. 10, the system is contemplated to include more than two integrated circuits, e.g., chiplets, e.g., a plurality of chiplets, wherein at least two chiplets each include a device 300 according to the disclosure.

[0088] Some examples, Fig. 12, relate to a product, for example control unit, 12, for example for a motor vehicle 10, comprising at least one device 300 according to the disclosure.

[0089] Some examples, Fig. 12, relate to a vehicle, for example motor vehicle, 10, comprising at least one device 300 according to the disclosure and / or at least one product, for example control unit, 12 according to the disclosure.

[0090] Some examples, Fig. 13, relate to a use 400 of the method according to the disclosure and / or the device 300 according to the disclosure and / or the integrated circuit 110, 120 according to the disclosure and / or the system 100, 100', 100" according to the disclosure and / or the product 12 according to the disclosure and / or the vehicle 10 according to the disclosure and / or the computer-readable storage medium SM according to the disclosure and / or the computer program PRG according to the disclosure and / or the data carrier signal DCS according to the disclosure for at least one of the following elements: a) checking 401 at least one integrated circuit for functionality, or b) checking 402 at least one integrated circuit for a workload, for example, workload, or c) evaluating 403 an operating state of at least one component of at least one integrated circuit, or d) blocking 404 the first communication interface,e) Increasing 405 a security of the system 100, 100', 100".,

[0091] Further aspects and examples are described below, which - in the case of further examples - can each be combined individually or in any combination with at least one of the aspects and / or examples described above.

[0092] In some examples, the second communication interface 132 can be used, for example, as a dedicated transmission path, e.g., for complex and / or time-varying question and answer functions, for example, independently of operation of the first communication interface 131.

[0093] In some examples, a workload measurement can be executed, e.g., on a functional chiplet 120, and results of the workload measurement can be evaluated, e.g., on the first chiplet, e.g., SMC, 110, e.g., in the sense of workload monitoring.

[0094] In some examples, a (function of an) evaluation unit, e.g., regarding the static and / or dynamic correctness of at least one chiplet, can be implemented by means of device 300. In some examples, enabling or disabling communication, e.g., between SMC 110 and functional chiplets 120, e.g., via first communication interface 131, can be controlled.

[0095] In some examples, several different monitoring types are possible, e.g.: a) In some examples, a general function is similar to a stress check on a human, in which, among other things, rest phases, stress phases and recovery phases are stimulated and the reaction of the "human" system is checked. By knowing the system behavior of a chiplet 120, e.g. through testing and analysis, the target and actual status can be compared and, if necessary, countermeasures can be taken, e.g. up to and including switching off the chiplet 120, for example by an SMC 110. b) In some examples, a dynamic check, e.g. in the sense of a closed control loop, is possible, e.g. "Dynamic closed loop check": The "Question" module E1 (Fig. 9) of the SMC 110' sends different questions to the functional chiplet 120', e.g. depending on the operating state, which load various modules (not shown) on the chiplet 120'.The load of questions can, for example, depending on the question, place a significant functional load on the functional chiplet 120' or it can be imperceptible. This means that, as the functional chiplet 120' is stimulated in some examples, the functional chiplet 120' should either show no response or show a response in the workload or utilization. c) In some examples, a robustness check is possible: When the functional chiplet 120' is heavily utilized, for example, questions are asked that expect answers in a short time. If the response times exceed the expected value and / or answers are skipped or are incorrect, it can be assumed that the functional chiplet is at its performance limit and countermeasures, e.g. in the form of load reduction, should be implemented.d) In some examples, a recovery check is enabled: After being loaded by functional requirements or questions, the system should return to a state where short answers and complex questions can be answered quickly. If this is not the case, there are problems with capacity or software / hardware errors. e) In some examples, detection of denial-of-service attacks is enabled: this can be achieved by overloading and / or compromising (e.g., by a virus infection) the functional chiplet; ie, due to a security issue.

[0096] In some examples, the principle according to the disclosure enables efficient monitoring of one or more chiplets 110, 120, ... on a multi-chiplet system, for example by at least one of the chiplets, e.g. an SMC 110, whereby, for example, system behavior can be improved, for example optimized, e.g. with respect to at least one of the following aspects: • Error detection of HW, SW and system errors, • Detection of inadmissible SW due to security and / or faulty programming, • Robustness, • Indications of future and performance limitations, • Availability.

Claims

Claims 1 . Method for a first integrated circuit (110) which can be arranged or is arranged together with at least one further, for example second, integrated circuit (120) on a substrate (102) and is designed to exchange (200) first information (1-1) with the second integrated circuit (120) via a first communication interface (131), the method comprising: exchanging (202) second information (1-2), which is different, for example, from the first information (1-1), with the at least one further, for example second, integrated circuit (120), via a second communication interface (132) which is different from the first communication interface (131).

2. The method according to claim 1, comprising: evaluating (204) an operating state of at least one component of the at least one further integrated circuit (120) based on at least a portion of the second information (I-2).

3. The method according to claim 2, comprising at least one of the following elements: a) deactivating (206a) at least one component of a communication module (112) of the first integrated circuit (110) which is designed for the information exchange (200) with the at least one further integrated circuit (120) via the first communication interface (131), or b) activating (206b) at least one component of the communication module (112) of the first integrated circuit (110) which is designed for the information exchange (200) with the at least one further integrated circuit (120) via the first communication interface (131) 4. Method according to at least one of the preceding claims, wherein the first integrated circuit (110) and the at least one further, for example second, integrated circuit (120) are each designed as a chip, for example a chiplet, wherein for example the first integrated Circuit (110) and the at least one further, for example second, integrated circuit (102) form a multi-chiplet system (100).

5. The method according to at least one of the preceding claims, comprising: sending (210) a question (FR) via the second communication interface (132) to the at least one further integrated circuit (120), optionally, for example if necessary, receiving (212) a response (AW) to the question (FR) via the second communication interface (132) from the at least one further integrated circuit (120), evaluating (214) an operating state of at least one component of the at least one further integrated circuit (120) based on the response (AW), for example based on at least one of: a) content of the response (AW), or b) absence of the response (AW).

6. The method according to claim 5, wherein the question (FR) is designed such that determining the answer (AW) to the question (FR) by the at least one further integrated circuit (120) causes a predeterminable, for example functional, load on at least one component of the at least one further integrated circuit (120).

7. The method according to at least one of the preceding claims, comprising: receiving (220) information (l-WL) characterizing a workload, for example workload, of at least one component of the at least one further integrated circuit (120) via the second communication interface (132) from the at least one further integrated circuit (120), and, optionally, evaluating (222) an operating state of at least one component of the at least one further integrated circuit (120) based on the information (l-WL).

8. The method according to at least one of claims 2 to 7, wherein the evaluation (204; 214; 222) comprises at least one of the following elements: a) determining (230) whether a functional error is present in at least one component of the at least one further integrated circuit (120), or b) determining (232) whether a workload, for example workload, of at least one component of the at least one further integrated circuit (120) exceeds a predeterminable first threshold value, or c) determining (234) whether a workload, for example workload, of at least one component of the at least one further integrated circuit (120) falls below a predeterminable second threshold value, or d) determining (236) whether a response time for answering one or the question (FR) exceeds a predeterminable third threshold value.

9. Method for a second integrated circuit (120) which can be arranged or is arranged together with at least one further, for example first, integrated circuit (110) on a substrate (102) and is designed to exchange (250) first information (1-1) with the first integrated circuit (110) via a first communication interface (131), the method comprising: exchanging (252) second information (1-2), which is different, for example, from the first information (1-1), with the first integrated circuit (110) via a second communication interface (132) which is different from the first communication interface (131).

10. The method according to claim 9, wherein the first integrated circuit (110) and the second integrated circuit (120) are each designed as a chip, for example a chiplet, wherein for example the first integrated circuit (110) and the second integrated circuit (102) form a multi-chiplet system (100).

11. Method according to at least one of claims 9 to 10, comprising: receiving (260) a question (FR) via the second communication interface (132) from the first integrated circuit (120), and, optionally, determining (262) an answer (AW) to the question (FR), and, optionally, sending (264) the answer (AW) to the question (FR) via the second communication interface (132) to the first integrated circuit (120), wherein, for example, the question (FR) is designed such that determining the answer (AW) to the question (FR) by the at least one further integrated circuit (120) causes a predeterminable, for example functional, load on at least one component of the at least one further integrated circuit (120).

12. The method according to at least one of the preceding claims, comprising: determining (270) information (l-WL) which characterizes a workload, for example workload, of at least one component of the second integrated circuit (120), sending (272) the information (l-WL) via the second communication interface (132) to the first integrated circuit (120).

13. The method according to at least one of the preceding claims, wherein the first communication interface (131) is a, e.g., unified, chiplet interface, e.g., of the Universal Chiplet Interconnect Express, UCIe, type.

14. The method according to at least one of the preceding claims, wherein the second communication interface (132) is used dedicatedly for the exchange of the second information (I-2), for example not for the exchange of the first information (1-1).

15. Device (300) for carrying out the method according to at least one of the preceding claims.

16. Integrated circuit (110; 120), for example for a multi-chiplet system (100) comprising a plurality of chiplets, comprising at least one device (300) according to claim 15, wherein, for example, the device (300) or a functionality of the device (300) is integrated into the integrated circuit (110; 120).

17. System, for example multi-chiplet system, (100; 100'; 100"), comprising at least one device (300) according to claim 15 or at least one integrated circuit (110; 120) according to claim 16.

18. System (100; 100'; 100") according to claim 17, wherein the system (100; 100'; 100") comprises more than two integrated circuits, for example chiplets, (110, 120), for example a plurality (110, 120, 120a, 120b, 120c, ...) of chiplets, wherein at least two chiplets (110, 120, 120a, 120b) each comprise a device (300) according to claim 15.

19. Product, for example a control unit (12), for example for a motor vehicle (10), comprising at least one device (300) according to claim 15.

20. Vehicle, for example a motor vehicle, (10), comprising at least one device (300) according to claim 15 and / or at least one product, for example a control unit, (12) according to claim 19.

21. Computer-readable storage medium (SM) comprising instructions (PRG) which, when executed by a computer (302), cause the computer to carry out the method according to at least one of claims 1 to 14.

22. Computer program (PRG) comprising instructions which, when the computer program (PRG) is executed by a computer (302), cause the computer (302) to carry out the method according to at least one of claims 1 to 14.

23. Data carrier signal (DCS) that characterizes and / or transmits the computer program (PRG) according to claim 22.

24. Use (400) of the method according to at least one of claims 1 to 14 and / or of the device (300) according to claim 15 and / or of the integrated circuit (110; 120) according to claim 16 and / or of the system (100; 100';100") according to at least one of claims 17 to 18 and / or the product (12) according to claim 19 and / or the vehicle (10) according to claim 20 and / or the computer-readable storage medium (SM) according to claim 21 and / or the computer program (PRG) according to claim 22 and / or the data carrier signal (DCS) according to claim 23 for at least one of the following elements: a) checking (401) at least one integrated circuit (120) for functionality, or b) checking (402) at least one integrated circuit (120) for a workload, for example workload, or c) evaluating (403) an operating state of at least one component of at least one integrated circuit (120), or d) blocking (404) the first communication interface (131), e) increasing (405) a security of the system (100; 100'; 100").

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