Drive circuit for semiconductor element

Abstract

This drive circuit for a semiconductor element comprises: a resistance circuit provided in a gate signal line of the semiconductor element; an added capacitor provided between the resistance circuit and a reference potential of the semiconductor element; a switch circuit provided between the resistance circuit and the added capacitor and connected in series with the added capacitor; and a switch control circuit that controls, when switching the semiconductor element, the switch circuit so as to adjust the rising and / or falling slope of the gate voltage waveform of the semiconductor element.

Description

Semiconductor element drive circuit

[0001] The present disclosure relates to a drive circuit for a semiconductor device.

[0002] It has been known that there is a trade-off between switching loss and noise generation in switching elements constituting a power conversion circuit such as an inverter. That is, reducing switching loss increases noise, and vice versa. Various gate control techniques have been proposed to resolve the trade-off between noise and loss (see, for example, Patent Document 1).

[0003] JP 2009-55696 A

[0004] However, the technology described in Patent Document 1 mentioned above has the problem that it is a control method only for turn-off and that the timing of the switch for switching the capacitance cannot be set arbitrarily. In addition, other conventional drive circuits also have problems such as large circuit scale.

[0005] Therefore, there is a demand for a semiconductor element drive circuit that can suppress the amount of noise generated while suppressing switching loss and can solve the problems associated with drive circuits of the prior art.

[0006] One aspect of the present disclosure is a drive circuit for a semiconductor element, comprising: a resistance circuit provided on a gate signal line of the semiconductor element; an additional capacitor provided between the resistance circuit and a reference potential of the semiconductor element; a switch circuit provided between the resistance circuit and the additional capacitor and connected in series with the additional capacitor; and a switch control circuit that controls the switch circuit to adjust the slope of the rising and / or falling edges of a gate voltage waveform of the semiconductor element when switching the semiconductor element.

[0007] 1 is a circuit diagram showing an overview of a motor drive device according to an embodiment of the present invention. 2 is a circuit diagram showing the configuration of a drive circuit according to an embodiment of the present invention. 3 is a diagram showing the operating principle when the drive circuit is turned on. 4 is a diagram showing an example of a change in voltage over time when the drive circuit shown in FIG. 3 is operating. 5 is a diagram showing the operating principle when the drive circuit is turned off. 6 is a diagram showing an example of a change in voltage over time when the drive circuit shown in FIG. 5 is operating. 7 is an example of a circuit configuration when the switch circuit is configured with an n-channel MOSFET. 8 is an example of a circuit configuration when the switch circuit is configured with an n-channel MOSFET and a p-channel MOSFET. 9 is another example of a circuit configuration when the switch circuit is configured with an n-channel MOSFET and a p-channel MOSFET. 10 is an example of a circuit configuration in which the charge / discharge circuit is a source follower with the input of the semiconductor element as the circuit input. 11 is a diagram showing the relationship between the voltage of an additional capacitor and the gate voltage of the semiconductor element. 12 is an example of a circuit configuration in which the switch control circuit shown in FIG. 9 is configured with a delay circuit and a pulse waveform generation circuit. 13 is an example of a circuit configuration in which the switch control circuit is configured with a digital circuit. 14 is an example of a circuit configuration in which the switch control circuit is configured with a CPU and an insulating interface IC. 1 is a diagram showing another configuration example of circuit configuration examples 2 and 3. FIG. 2 is a diagram showing an example of a simulation result of a switching waveform at the time of turn-off in the drive circuit according to the present embodiment. FIG. 3 is a simulation result showing the trade-off relationship between switching loss and noise in the drive circuit according to the present embodiment.

[0008] An example of an embodiment of the present disclosure will now be described. Fig. 1 is a circuit diagram showing an overview of a motor drive device 100 according to this embodiment. The motor drive device 100 drives a motor 114 mounted on industrial equipment such as a robot, a machine tool, etc. The motor drive device 100 includes a power circuit 101, a drive circuit 102, and a control circuit 103.

[0009] The power circuit 101 is a circuit that supplies power to the motor 114 and drives the motor 114. The power circuit 101 is composed of a power supply 110, a reactor 111, a diode rectifier 112, a smoothing capacitor 113, and semiconductor elements (switching elements) 17. The power supply 110 supplies a high voltage such as AC 200 V. The multiple semiconductor elements 17 function as an inverter circuit.

[0010] The drive circuit 102 is a circuit that drives the semiconductor element 17 of the power circuit 101 in response to a switching command from the control circuit 103. The drive circuit 102 is composed of a gate drive circuit 121, an insulating element 122, an insulating power supply 123, etc. Since the power circuit 101 and the control circuit 103 have different voltage levels, reference potentials, etc., an insulating element 122 is required to transmit signals from the control circuit 103 to the power circuit 101 while providing insulation. The insulating element 122 is composed of a pulse transformer, a photocoupler, etc. The drive circuit 102 is a circuit that can output a large current to drive the semiconductor element 17.

[0011] The control circuit 103 is a circuit that generates and outputs a switching command for switching the semiconductor element (switching element) 17 of the power circuit 101. The control circuit 103 operates at a low voltage, such as DC 24 V. The control circuit 103 is configured by, for example, a CPU 131, an arithmetic circuit 132, etc. The reference potential of the control circuit 103 is 0 V.

[0012] 2 is a circuit diagram showing the configuration of a drive circuit 102 according to this embodiment. As shown in Fig. 2, the drive circuit 102 includes a voltage source 11, resistors 12 and 13, diodes 14 and 15, a semiconductor element 17, an input capacitance 16 of the semiconductor element 17, resistors 21 and 41, diodes 22 and 42, switch circuits 23 and 43, and additional capacitors 24 and 44.

[0013] The voltage source 11 is configured by, for example, a gate driving IC, etc. The semiconductor element 17 is, for example, a power semiconductor such as an IGBT (Insulated Gate Bipolar Transistor).

[0014] The resistors 12 and 13 and the diodes 14 and 15 function as a resistance circuit provided on the gate signal line of the semiconductor element 17 .

[0015] The drive circuit 102 also includes a switch control circuit 91. The switch control circuit 91 controls the switch circuits 23 and 43 so as to adjust the rising and / or falling slope of the gate voltage waveform of the semiconductor element 17 when switching the semiconductor element 17.

[0016] The resistors 21 and 41 and the diodes 22 and 42 function as a charge / discharge circuit that charges the additional capacitors 24 and 44 and / or discharges the additional capacitors 24 and 44 .

[0017] That is, the resistance circuit has resistors 12 and 13 and diodes 14 and 15 connected in series, and the charge / discharge circuit has resistors 21 and 41 and diodes 22 and 42 connected in series.

[0018] More specifically, the resistance circuit includes a first resistance circuit 131 having a resistor 13 and a diode 15, and a second resistance circuit 132 having a resistor 12 and a diode 14. That is, the first resistance circuit 131 includes a diode 15 that is turned on when the gate drive signal to the semiconductor element 17 is high. The second resistance circuit 132 includes a diode 14 that is turned on when the gate drive signal to the semiconductor element 17 is low. The first resistance circuit 131 and the second resistance circuit 132 are connected in parallel with each other.

[0019] The additional capacitors 24 and 44 include an additional capacitor 24 provided between the first resistor circuit 131 and the reference potential of the semiconductor element 17, and an additional capacitor 44 provided between the second resistor circuit 132 and the reference potential of the semiconductor element 17.

[0020] The switch circuits 23 and 43 include a switch circuit 23 that is provided between the first resistor circuit 131 and the additional capacitor 24 and connected in series with the additional capacitor 24, and a switch circuit 43 that is provided between the second resistor circuit 132 and the additional capacitor 44 and connected in series with the additional capacitor 44.

[0021] A circuit in which the switch circuit 23 and the additional capacitor 24 are connected in series is connected to a node between the resistor 13 and the diode 15 in the first resistor circuit 131. A circuit in which the switch circuit 43 and the additional capacitor 44 are connected in series is connected to a node between the resistor 12 and the diode 14 in the second resistor circuit 132.

[0022] The charge / discharge circuit includes a first discharge circuit 141 having a resistor 21 and a diode 22, and a second charge circuit 142 having a resistor 41 and a diode 42. That is, the first discharge circuit 141 includes a diode 22 that is turned on when the gate drive signal to the semiconductor element 17 is low. The second charge circuit 142 includes a diode 42 that is turned on when the gate drive signal to the semiconductor element 17 is high.

[0023] The additional capacitor 24 is connected to the first discharge circuit 141, and the additional capacitor 44 is connected to the second charge circuit 142. The first resistance circuit 131, the additional capacitor 24, and the switch circuit 23 operate when the semiconductor device 17 is turned on. The second resistance circuit 132, the additional capacitor 44, and the switch circuit 43 operate when the semiconductor device 17 is turned off.

[0024] Fig. 3 is a diagram showing the operating principle of the drive circuit 102 according to this embodiment when it is turned on. For ease of explanation, the resistors and diodes that form the path when it is turned off are omitted. Fig. 4 shows an example of the change in voltage over time when the drive circuit 102 shown in Fig. 3 is operating. Reference numeral 31 denotes the voltage of the voltage source 11, reference numeral 32 denotes the voltage of the switch control signal, reference numeral 33 denotes the gate voltage of the semiconductor element 17, and reference numeral 34 denotes the voltage of the additional capacitor 24.

[0025] When the voltage source 11 is low, the additional capacitor 24 and the input capacitance 16 are not charged. Reference numerals 33 and 34 in Fig. 4 are in a 0 V state. When the voltage source 11 goes high, the input capacitance 16 is charged via the resistor 13 and the diode 15, and the gate voltage rises. Therefore, the voltage at reference numeral 33 rises.

[0026] During the transition period while the gate voltage is rising, the switch control circuit 91 turns on the switch circuit 23 at the appropriate timing, and charging of the additional capacitor 24 also begins. In FIG. 4, when the voltage of the switch control signal 32 turns on, the voltage of the additional capacitor 24 (reference numeral 34) rises. When the voltage of the input capacitor 16 and the voltage of the additional capacitor 24 become the same due to charging, the two capacitors (capacitor 24 and input capacitor 16) are charged simultaneously. Because the capacitance value increases, the rise of the gate voltage after the switch circuit 23 is turned on becomes slower.

[0027] In this way, the drive circuit 102 can control the rise speed of the gate voltage, making it possible to more appropriately set the trade-off between loss and surge. The switch control circuit 91 then switches the switch circuit 23 off, but if this is left as is, the additional capacitor 24 will remain charged, and the additional capacitor 24 will have no effect the next time the switch is turned on. Therefore, the resistor 21 and diode 22 discharge the additional capacitor 24 when the voltage source 11 is low.

[0028] 5 is a diagram showing the operating principle of the drive circuit 102 according to this embodiment when it is turned off. For convenience of explanation, the resistors and diodes that form the paths when it is turned on are omitted.

[0029] Fig. 6 shows an example of the change in voltage over time when the drive circuit 102 shown in Fig. 5 is operating. Reference numeral 51 denotes the voltage of the voltage source 11, reference numeral 52 denotes the voltage of the switch control signal, reference numeral 53 denotes the gate voltage of the semiconductor element 17, and reference numeral 54 denotes the voltage of the additional capacitor 44.

[0030] During turn-off operation, when the voltage source 11 is high, the additional capacitor 44 and the input capacitance 16 are charged. The additional capacitor 44 is charged by the resistor 41 and the diode 42. In FIG. 6, reference numerals 53 and 54 are in a high state. When the voltage source 11 goes low, the input capacitance 16 is discharged via the resistor 12 and the diode 14, and the gate voltage drops. In FIG. 6, the voltage at reference numeral 53 drops.

[0031] During the transition period while the gate voltage is decreasing, the switch control circuit 91 turns on the switch circuit 43 at an appropriate timing, which causes the additional capacitor 44 to start discharging as well. In FIG. 5, when the voltage of the switch control signal 52 turns on, the voltage of the additional capacitor 44 (54) decreases. When the voltage of the input capacitor 16 and the voltage of the additional capacitor 44 become the same due to the discharge, the two capacitors (the additional capacitor 44 and the input capacitor 16) are discharged simultaneously. Because the capacitance value increases, the decrease in the gate voltage after the switch circuit 43 is turned on is slowed down.

[0032] In this way, the drive circuit 102 can control the rate at which the gate voltage falls, making it possible to more appropriately set the trade-off between loss and surge. After that, the switch circuit 43 is turned off, but if this is left as it is, the additional capacitor 44 will remain discharged, and the additional capacitor 44 will have no effect the next time the device is turned off. Therefore, the resistor 41 and the diode 42 charge the additional capacitor 44 when the voltage source 11 is High.

[0033] It should be noted that, for example, if there is a large amount of noise when the drive circuit 102 is turned off, it is possible to perform control only when the drive circuit 102 is turned off and use a conventional circuit when the drive circuit 102 is turned on. Also, in the above-mentioned drive circuit 102, the gate drive IC is replaced with the voltage source 11, but in an actual motor drive device, a pre-driver using a bipolar transistor or a pre-driver using a MOSFET can be used.

[0034] In the above-described embodiment, an IGBT is used as an example of the semiconductor element 17, but semiconductor elements such as a power MOSFET, SiC, or GaN can also be applied. Furthermore, the drive circuit 102 according to this embodiment can be applied even if the low level voltage of the gate drive IC is a negative voltage.

[0035] Furthermore, the on / off timing of the switch circuits 23 and 43 can be arbitrarily set by the switch control circuit 91. For example, the on / off timing can be controlled as off-on-off, or the switch circuits can be turned on and off several times at the rising edge of the gate signal.

[0036] As described above, according to this embodiment, the drive circuit 102 includes a resistance circuit (i.e., the resistors 12, 13 and the diodes 14, 15) provided on the gate signal line of the semiconductor element 17, additional capacitors 24, 44 provided between the resistance circuit and the reference potential of the semiconductor element 17, switch circuits 23, 43 provided between the resistance circuit and the additional capacitors 24, 44 and connected in series with the additional capacitors 24, 44, and a switch control circuit 91 that controls the switch circuits 23, 43 so as to adjust the slope of the rising and / or falling edges of the gate voltage waveform of the semiconductor element 17 when switching the semiconductor element 17.

[0037] With this configuration, the drive circuit 102 controls the on / off of the switch circuits 23 and 43 at the appropriate timing when turning on or off the semiconductor element 17, thereby suppressing switching loss and reducing noise generation. Furthermore, the drive circuit 102 eliminates the need for multiple gate drive ICs and can select appropriate gate resistance and capacitance values ​​for turn-on and turn-off, respectively. Furthermore, the drive circuit 102 can arbitrarily set the optimal switching timing of the switch circuits 23 and 43. Furthermore, the drive circuit 102 increases the input capacitance of the semiconductor element 17 by adding the capacitors 24 and 44, thereby achieving a high noise suppression effect. For example, the parasitic capacitance of the gate of the semiconductor element 17 and the additional capacitors 22 and 44 act equivalently to adding a capacitor between the output of the semiconductor element 17 and the reference potential, thereby suppressing ringing and lowering the circuit's cutoff frequency, thereby achieving noise suppression effects based on a principle different from adjusting the switching speed.

[0038] The drive circuit 102 further includes a charge / discharge circuit (21, 22, 41, 42) that charges and / or discharges the additional capacitors 24, 44. With this configuration, the drive circuit 102 can slow down the rise and / or fall of the gate voltage by charging and discharging the additional capacitors 24, 44. This allows the drive circuit 102 to control the rise rate and / or fall rate of the gate voltage.

[0039] The resistance circuit has resistors 12 and 13 and diodes 14 and 15 connected in series, and the charge / discharge circuit has resistors 21 and 41 and diodes 22 and 42 connected in series for charge / discharge. With this configuration, the drive circuit 102 can preferably drive the semiconductor element 17 and charge / discharge the additional capacitors 24 and 44.

[0040] 2-6, the first resistance circuit 131, the additional capacitor 24, and the switch circuit 23 operate when the semiconductor element 17 is turned on, and the second resistance circuit 132, the additional capacitor 44, and the switch circuit 43 operate when the semiconductor element 17 is turned off. By having such a configuration, the drive circuit 102 can suitably control the rise rate and / or fall rate of the gate voltage.

[0041] 7 shows a circuit configuration example in which the switch circuits 23, 43 shown in FIG. 4 are configured with n-channel MOSFETs 61, 63. The switch circuit 23 on the turn-on side has an n-channel MOSFET 61 and a diode 60, and the anode of the diode 60 is connected to a resistor 13. The drain of the n-channel MOSFET 61 is connected to the cathode of the diode 60. An additional capacitor 24 is connected to the source of the n-channel MOSFET 61. The diode 60 prevents backflow due to the parasitic diode of the n-channel MOSFET 61.

[0042] The switch circuit 43 on the turn-off side has an n-channel MOSFET 63 and a diode 62, and the cathode of the diode 62 is connected to the resistor 12. The anode of the diode 62 is connected to the source of the n-channel MOSFET 63. The drain of the n-channel MOSFET 63 is connected to the additional capacitor 44. The diode 62 prevents backflow due to the parasitic diode of the n-channel MOSFET 63. In addition, the drain of the n-channel MOSFET 63 is connected to the additional capacitor 44 in order to pass a current in a direction that draws charge from the additional capacitor 44.

[0043] By configuring in this way, the drive circuit 102 shown in FIG. 7 can be configured using n-channel MOSFETs 61 and 63, which are readily available and have good performance.

[0044] <Circuit Configuration Example 2> Fig. 8 shows a circuit configuration example in which the switch circuit 23 is configured with an n-channel MOSFET 231 and the switch circuit 43 is configured with a p-channel MOSFET 431. In the circuit configuration example shown in Fig. 8, when the input signal transitions from low to high, the parasitic diode of the p-channel MOSFET 431 becomes conductive, charging the additional capacitor 44. The additional capacitor 44 is also charged through the resistor 21 and diode 22 which function as a charging circuit.

[0045] When the input signal transitions from High to Low, the parasitic diode of the n-channel MOSFET 231 becomes conductive, discharging the capacitor 44. The additional capacitor 24 is also discharged through the resistor 41 and diode 42 that function as a discharge circuit.

[0046] By configuring in this manner, the drive circuit 102 shown in FIG. 8 does not require a special circuit to drive the MOSFET, compared to circuit configuration example 1, and the overall scale of the drive circuit 102 can be made smaller.

[0047] <Circuit Configuration Example 3> Fig. 9 shows another circuit configuration example in which switch circuit 23 is configured with an n-channel MOSFET 232 and switch circuit 43 is configured with a p-channel MOSFET 432. In the circuit configuration example shown in Fig. 9, as described in the example shown in Fig. 8, when the input signal transitions from low to high, the parasitic diode of p-channel MOSFET 432 becomes conductive, and additional capacitor 44 is charged. In addition, drive circuit 102 shown in Fig. 9 has a switch control circuit 91, which outputs switching commands to n-channel MOSFET 232 and p-channel MOSFET 432.

[0048] On the other hand, when the input signal transitions from High to Low, the parasitic diode of the n-channel MOSFET 232 becomes conductive, discharging the additional capacitor 44. By configuring in this way, the circuit configuration example shown in Fig. 9 can charge and discharge using the parasitic diode, and therefore, compared to the example shown in Fig. 8, the resistor 21, diode 22, resistor 41, and diode 42 as part of the charge and discharge circuit are eliminated.

[0049] 9, the charge / discharge circuit is composed of resistors 12 and 13 of the resistance circuit and the parasitic diodes of n-channel MOSFET 232 and p-channel MOSFET 432, and does not have dedicated diodes and resistors in the charge / discharge circuit. By configuring in this way, the charge / discharge circuit (i.e., resistor 21, diode 22, resistor 41, and diode 42) can be eliminated from drive circuit 102 shown in FIG.

[0050] <Circuit Configuration Example 4> Fig. 10A shows a circuit configuration example in which the input of the charge / discharge circuit is the input of the semiconductor element 17. In other words, the charge / discharge circuit is a voltage follower (source follower) circuit in which the input of the charge / discharge circuit is the input of the semiconductor element 17. As shown in Fig. 10A, the voltage follower circuit has switching elements 81 and 82 and resistors 83, 84, 85, and 86. The outputs of the voltage follower circuits are connected to additional capacitors 24 and 44, respectively.

[0051] 10A, the voltages of the additional capacitors 24, 44 are always equal to the gate voltage of the semiconductor element 17. Therefore, the drive circuit 102 shown in FIG. 10A can suppress fluctuations in the gate voltage that occur when the switch circuits 23, 43 are turned on and the additional capacitors 24, 44 are connected.

[0052] 10B is a diagram showing the relationship between the voltages of the additional capacitors 24 and 44 and the gate voltage of the semiconductor element 17. In FIG. 10B, the capacitances of the additional capacitors 24 and 44 are C ａ (Voltage V １ ), and the parasitic capacitance of the semiconductor element 17 is C ｇｅ (Voltage V ２ 10B, when the switch circuits 23 and 43 are turned on in a state where the voltages of the additional capacitors 24 and 44 and the gate voltage of the semiconductor element 17 are different, the gate voltage of the semiconductor element 17 is disturbed for a moment and then returns to its original state.

[0053] 10A and 10B, the voltage of the additional capacitors 24, 44 becomes the same as the gate voltage of the semiconductor element 17, and therefore fluctuations in the gate voltage of the semiconductor element 17 when switching between the additional capacitors 24, 44 can be suppressed. Note that the voltage follower circuit may be any circuit that makes the additional capacitor voltage and the gate voltage the same, and may be an emitter follower circuit using a bipolar transistor, a voltage follower circuit using an operational amplifier, or the like.

[0054] <Circuit Configuration Example 5> Fig. 11 shows a circuit configuration example in which the switch control circuit 91 shown in Fig. 9 is configured by a delay circuit 71 and a pulse waveform generating circuit 72. As shown in Fig. 11, the drive circuit 102 has the delay circuit 71 and the pulse waveform generating circuit 72. The delay circuit 71 includes resistors 711, 712, and 713, a diode 714, switching elements 715 and 716, and a capacitor 717.

[0055] When the rising edge or falling edge of an input signal is input to the delay circuit 71, a rising waveform or falling waveform delayed by a certain time is input to the pulse waveform generating circuit 72. When the rising waveform or falling waveform is input, the pulse waveform generating circuit 72 outputs a pulse of a desired pulse width. Therefore, when the rising edge or falling edge of the input signal is input to the delay circuit 71, a switch control signal of a desired pulse width is output from the pulse waveform generating circuit 72 after a certain time delay.

[0056] 9 is configured by the delay circuit 71 and pulse waveform generating circuit 72, the delay circuit 71 delays a fixed period from the transition of the gate drive signal of the semiconductor element 17, and the pulse waveform generating circuit 72 outputs a pulse waveform of a desired pulse width after the fixed period of delay. With this configuration, the drive circuit 102 can generate the switching signal using the power circuit portion, eliminating the need to add an insulating element for the switch control signal.

[0057] 12 shows a circuit configuration example in which the switch control circuit 91 shown in FIG. 9 is configured by a digital circuit 93. The digital circuit 93 includes a clock 931 and a logic circuit 932. The logic circuit 932 is configured by an edge detection circuit, a counter circuit, etc.

[0058] 12 , a signal with a fixed pulse width is output as a switch control signal by a digital circuit 93 after a fixed delay time from the rising or falling edge of a switching command for the semiconductor element 17. The switching command is supplied to switch circuits 231 and 431 via an insulating element 122.

[0059] As described above, the drive circuit 102 shown in Fig. 12 is configured by using a digital circuit 93, which is the switch control circuit 91 shown in Fig. 9, and includes a clock 931 and a logic circuit 932 including an edge detection circuit and a counter. The digital circuit 93 delays a certain period from the transition of the gate drive signal of the semiconductor element 17, and outputs a pulse waveform of a desired pulse width after the certain period of delay. By configuring in this manner, the drive circuit 102 shown in Fig. 12 can more easily adjust the delay time and change the waveform than the circuit configuration example shown in Fig. 11.

[0060] 13 shows a circuit configuration example in which the switch control circuit 91 shown in FIG. 9 is configured by a CPU 911 and insulating interface ICs 921, 922, and 923. The CPU 911 outputs a switching signal and an optimum switching command for the semiconductor element 17. The command output from the CPU 921 is input to the insulating interface ICs 921, 922, and 923, and becomes a drive signal for the semiconductor element 17 and a control signal for the switch circuits 231 and 431.

[0061] 9 is configured by a CPU 911 and insulating interface ICs 921, 922, and 923, and the drive circuit 102 shown in FIG. 13 generates and outputs a drive signal for the semiconductor element 17. The drive signal is supplied to the semiconductor element 17 via the insulating interface IC 921. A command (switch command) to switch the capacitor 44 is supplied to the switch circuit 231 via the insulating interface IC 922, and a command (switch command) to switch the capacitor 24 is supplied to the switch circuit 431 via the insulating interface IC 923. With this configuration, the drive circuit 102 shown in FIG. 13 can easily adjust the delay time and change the waveform.

[0062] 14 is a diagram showing another example of the configuration of circuit configuration examples 2 and 3. In the drive circuit 102 shown in FIG. 14, the connection position between the switch circuit 233 and the capacitor 24 and the connection position between the switch circuit 433 and the capacitor 44 are different from those in circuit configuration examples 2 and 3.

[0063] In the circuit configuration examples 2 and 3, the switch circuit is turned off when the charging or discharging of the additional capacitor 24, 44 is completed. In the circuit configuration example 8 shown in Fig. 14, the switch circuits 233, 433 are always on while a switch command is being input.

[0064] <Simulation Results> Fig. 15 is a diagram showing an example of a simulation result of switching waveforms at the time of turn-off in the drive circuit 102 according to this embodiment. In the example shown in Fig. 15, control is performed to turn on the command for the additional capacitor switch after the gate voltage command changes from on to off. Fig. 15 shows the collector voltage and emitter current waveforms of the conventional and proposed IGBTs.

[0065] As shown in Figure 15, the simulation results for the proposed type (drive circuit 102 according to this embodiment) show that the maximum value of the collector voltage is smaller and the amplitude of the ringing is also smaller than those for the conventional type. It is also clear that the amplitude of the ringing of the emitter current is smaller. Furthermore, the rising slopes of the collector voltage and emitter current are the same as those for the conventional type, indicating that the switching loss is about the same.

[0066] 16 shows simulation results showing the trade-off relationship between switching loss and noise in the drive circuit 102 according to this embodiment. For the conventional type, the values ​​of switching loss and noise are plotted when the gate resistance value is changed. For the proposed type, the values ​​of switching loss and noise are plotted when the timing of switching on the additional capacitor is changed. These results show that the proposed type can eliminate the trade-off between switching loss and noise compared to the conventional type.

[0067] Although the present disclosure has been described in detail, the present disclosure is not limited to the individual embodiments described above. Various additions, substitutions, modifications, partial deletions, etc. are possible in these embodiments without departing from the gist of the present disclosure or the spirit of the present disclosure derived from the content of the claims and their equivalents. These embodiments can also be implemented in combination. For example, in the above-described embodiments, the order of each operation and the order of each process are shown as examples and are not limited to these. The same applies when numerical values ​​or mathematical expressions are used in the description of the above-described embodiments.

[0068] The following supplementary notes are further disclosed regarding the above embodiments and modifications. (Supplementary Note 1) A drive circuit (102) for a semiconductor element (17), comprising: a resistance circuit (12, 13, 14, 15) provided on a gate signal line of the semiconductor element; an additional capacitor (24, 44) provided between the resistance circuit and a reference potential of the semiconductor element; a switch circuit (23, 43) provided between the resistance circuit and the additional capacitor and connected in series with the additional capacitor; and a switch control circuit (91) that controls the switch circuit to adjust the slope of the rising and / or falling edges of a gate voltage waveform of the semiconductor element when switching the semiconductor element. (Supplementary Note 2) The drive circuit for a semiconductor element according to Supplementary Note 1, further comprising a charge / discharge circuit (21, 22, 41, 42) that charges the additional capacitor and / or discharges the additional capacitor. (Supplementary Note 3) The semiconductor element drive circuit according to Supplementary Note 2, wherein the resistance circuit (12, 13, 14, 15) has resistors (12, 13) and diodes (14, 15) connected in series, and the charge / discharge circuit (21, 22, 41, 42) has resistors (21, 41) and diodes (22, 42) connected in series for charge / discharge. (Supplementary Note 4) The resistance circuit includes a first resistance circuit (13, 15) having a first diode (15) that is turned on when a gate drive signal to the semiconductor element is High, and a second resistance circuit (12, 14) having a second diode (14) that is turned on when the gate drive signal to the semiconductor element is Low, and the first resistance circuit (13, 15) and the second resistance circuit (12, 14) are connected in parallel with each other; the additional capacitors (24, 44) include a first additional capacitor (24) provided between the first resistance circuit and a reference potential of the semiconductor element, and a second additional capacitor (44) provided between the second resistance circuit and a reference potential of the semiconductor element; and the switch circuits (23,a first switch circuit (23) provided between the first resistor circuit and the first additional capacitor and connected in series with the first additional capacitor, and a second switch circuit (43) provided between the second resistor circuit and the second additional capacitor and connected in series with the second additional capacitor, a circuit in which the first switch circuit (23) and the first additional capacitor (24) are connected in series is connected to a node between a resistor (13) and a diode (14) in the first resistor circuit, and a circuit in which the second switch circuit (43) and the second additional capacitor (44) are connected in series is connected to a node between a resistor (12) and a diode (14) in the second resistor circuit, The charge / discharge circuits (21, 22, 41, 42) include a first discharge circuit (21, 22) having a diode (22) that turns on when the gate drive signal to the semiconductor element is Low, and a second charge circuit (41, 42) having a diode (42) that turns on when the gate drive signal to the semiconductor element is High, the first additional capacitor (24) is connected to the first discharge circuit (21, 22), the second additional capacitor (44) is connected to the second charge circuit (41, 42), the first resistor circuit (13, 15), the first additional capacitor (24), and the first switch circuit (23) operate when the semiconductor element (17) is turned on, and the second resistor circuit (12, 42)The drive circuit for a semiconductor element according to Supplementary Note 2 or 3, wherein the first switch circuit (23) has a first n-channel MOSFET (61) and a third diode (60), and the cathode of the third diode (60) is connected to the drain of the first n-channel MOSFET (61), and the second switch circuit (43) has a second n-channel MOSFET (63) and a fourth diode (62), and the anode of the fourth diode (62) is connected to the source of the second n-channel MOSFET (63). (Supplementary Note 6) The semiconductor element drive circuit according to Supplementary Note 4, wherein the first switch circuit (23) has an n-channel MOSFET (231), and the second switch circuit (43) has a p-channel MOSFET (431). (Supplementary Note 7) The semiconductor element drive circuit according to Supplementary Note 2 or 3, wherein the charge / discharge circuit is composed of resistors (12, 13) of the resistor circuit and parasitic diodes of the switch circuits (232, 432), and does not have dedicated diodes and resistors in the charge / discharge circuit. (Supplementary Note 8) The charge / discharge circuit is a voltage follower circuit (81, 82, 83, 84, 85, 86) in which the input of the charge / discharge circuit is an input of the semiconductor element, and the output of the voltage follower circuit is connected to the additional capacitor (24,44). (Supplementary Note 9) The drive circuit for a semiconductor element according to Supplementary Note 1 or 2, wherein the switch control circuit has a delay circuit (71) and a pulse waveform generation circuit (72), wherein the delay circuit (71) delays a fixed period from a transition of a gate drive signal for the semiconductor element, and the pulse waveform generation circuit (72) outputs a pulse waveform of an arbitrary pulse width after the delay of the fixed period. (Supplementary Note 10) The drive circuit for a semiconductor element according to Supplementary Note 1 or 2, wherein the switch control circuit is composed of a digital circuit (93) including an edge detection circuit, a counter, and a clock (931), and wherein the switch control circuit delays a fixed period from a transition of a gate drive signal for the semiconductor element, and outputs a pulse waveform of an arbitrary pulse width after the delay of the fixed period. (Supplementary Note 11) The drive circuit for a semiconductor element according to Supplementary Note 1 or 2, wherein the switch control circuit has an element including a CPU (911) that generates and outputs a switching command for the semiconductor element, and the switching command is supplied to the switch circuit (231, 431) via an insulating element (922, 923).

[0069] 100 Motor drive device 101 Power circuit 102 Drive circuit 103 Control circuit 11 Voltage source 12 Resistor 13 Resistor 14 Diode 15 Diode 131 First resistor circuit 132 Second resistor circuit 16 Input capacitance 17 Semiconductor element 21 Resistor 22 Diode 23 Switch circuit 24 Additional capacitor 31 Voltage of voltage source 32 Voltage of switch control circuit 33 Gate voltage of semiconductor element 34 Voltage of additional capacitor 41 Resistor 42 Diode 43 Switch circuit 44 Additional capacitor 60 Diode 61 n-channel MOSFET 62 Diode 63 p-channel MOSFET 231 n-channel MOSFET 431 p-channel MOSFET 232 n-channel MOSFET 432 p-channel MOSFET 81 MOSFET 82 MOSFET 83, 84, 85, 86 Resistance

Claims

1. A drive circuit for a semiconductor element, comprising: a resistance circuit provided on a gate signal line of the semiconductor element; an additional capacitor provided between the resistance circuit and a reference potential of the semiconductor element; a switch circuit provided between the resistance circuit and the additional capacitor and connected in series with the additional capacitor; and a switch control circuit that controls the switch circuit to adjust the slope of the rising and / or falling edges of the gate voltage waveform of the semiconductor element when switching the semiconductor element.

2. The semiconductor device drive circuit according to claim 1, further comprising a charge / discharge circuit for charging and / or discharging the additional capacitor.

3. The semiconductor element drive circuit according to claim 2, wherein the resistance circuit has a resistor and a diode connected in series, and the charge / discharge circuit has a resistor and a diode for charge / discharge connected in series.

4. The resistance circuit comprises a first resistance circuit having a first diode that is turned on when a gate drive signal to the semiconductor element is High, and a second resistance circuit having a second diode that is turned on when the gate drive signal to the semiconductor element is Low, the first resistance circuit and the second resistance circuit being connected in parallel with each other, the additional capacitor comprises a first additional capacitor provided between the first resistance circuit and a reference potential of the semiconductor element, and a second additional capacitor provided between the second resistance circuit and the reference potential of the semiconductor element, the switch circuit comprises a first switch circuit provided between the first resistance circuit and the first additional capacitor and connected in series with the first additional capacitor, and a second switch circuit provided between the second resistance circuit and the second additional capacitor and connected in series with the second additional capacitor, the circuit in which the first switch circuit and the first additional capacitor are connected in series is connected to a node between a resistor and a diode in the first resistance circuit, 4. The drive circuit for a semiconductor element according to claim 2 or 3, wherein: a circuit in which the second switch circuit and the second additional capacitor are connected in series is connected to a node between a resistor and a diode in the second resistance circuit; the charge / discharge circuit includes a first discharge circuit having a diode that turns on when the gate drive signal to the semiconductor element is Low, and a second charge circuit having a diode that turns on when the gate drive signal to the semiconductor element is High; the first additional capacitor is connected to the first discharge circuit; and the second additional capacitor is connected to the second charge circuit; the first resistance circuit, the first additional capacitor, and the first switch circuit operate when the semiconductor element is turned on; and the second resistance circuit, the second additional capacitor, and the second switch circuit operate when the semiconductor element is turned off.

5. The semiconductor device drive circuit according to claim 4, wherein the first switch circuit has a first n-channel MOSFET and a third diode, the cathode of which is connected to the drain of the first n-channel MOSFET, and the second switch circuit has a second n-channel MOSFET and a fourth diode, the anode of which is connected to the source of the second n-channel MOSFET.

6. The semiconductor device drive circuit according to claim 4, wherein the first switch circuit has an n-channel MOSFET, and the second switch circuit has a p-channel MOSFET.

7. A semiconductor element drive circuit according to claim 2 or 3, wherein the charge / discharge circuit is composed of a resistor in the resistor circuit and a parasitic diode in the switch circuit, and the charge / discharge circuit does not have a dedicated diode or resistor.

8. A semiconductor element drive circuit according to claim 2 or 3, wherein the charge / discharge circuit is a voltage follower circuit in which the input of the charge / discharge circuit is the input of the semiconductor element, and the output of the voltage follower circuit is connected to the additional capacitor.

9. The semiconductor element drive circuit according to claim 1 or 2, wherein the switch control circuit has a delay circuit and a pulse waveform generation circuit, the delay circuit delays a fixed period from the transition of the gate drive signal of the semiconductor element, and the pulse waveform generation circuit outputs a pulse waveform of a given pulse width after the fixed period of delay.

10. A drive circuit for a semiconductor element according to claim 1 or 2, wherein the switch control circuit is composed of a digital circuit including an edge detection circuit, a counter, and a clock, and the switch control circuit delays a fixed period from the transition of the gate drive signal for the semiconductor element, and outputs a pulse waveform of an arbitrary pulse width after the fixed period of delay.

11. A drive circuit for a semiconductor element according to claim 1 or 2, wherein the switch control circuit has an element including a CPU that generates and outputs a switching command for the semiconductor element, and the switching command is supplied to the switch circuit via an insulating element.

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