Drive circuit for semiconductor device and power conversion device

Abstract

A drive circuit (100) for a semiconductor device is characterized by: during turn-off, increasing and holding the voltage of a gate drive device (120) at an intermediate voltage (Vint_com) larger than an off voltage, which is lower than a drive voltage, for a second period (Tint) after a first period (Tdraw) in which an instruction logic unit (110) issues an instruction for the off voltage; and temporarily increasing and holding a gate voltage (Vg) of an element at a voltage (Vint) larger than the off voltage and smaller than a threshold voltage (Vth). The drive circuit is characterized in that the end timing of the first period (Tdraw) is later than the start of a mirror period and earlier than the end of the mirror period, and the end timing of the second period (Tint) is later than a timing when the element reaches a surge voltage (Vsurge).

Description

Semiconductor device driver circuit and power converter

[0001] The present invention relates to a drive circuit for a semiconductor device and a power conversion device.

[0002] The global trend toward realizing a decarbonized society is driving steady market growth in electric vehicles (EVs), power grids, and railways. These applications use power conversion devices that output AC current based on DC power supplied from a DC power source to drive electric motors. Key components of power conversion devices include semiconductor switching elements and the gate drive circuits that drive them. Insulated gate bipolar transistors (IGBTs), one type of semiconductor switching element, are required to have high current densities and high tolerance to interrupt large currents flowing through them without damaging the element. As the current density of IGBTs increases, a decrease in tolerance when the IGBT is turned off is becoming a problem.

[0003] To address this issue, there are methods to increase the breakdown resistance of the IGBT itself, as well as methods to increase the breakdown resistance of the gate drive system or gate circuit that drives the IGBT. For example, there are methods that perform soft shutdown by controlling the gate voltage and current at turn-off, as shown in Patent Documents 1, 2, and 3.

[0004] Patent Document 1 describes a method for preventing oscillation of a semiconductor device by raising the gate voltage above the threshold voltage again when the device is turned off.

[0005] Patent Document 2 describes a method for suppressing surge voltage by appropriately controlling the gate current when a semiconductor device is turned off.

[0006] Patent Document 3 describes a method for suppressing surge voltage by appropriately controlling the gate current when a semiconductor device is turned off.

[0007] This section explains how to improve the interruption capability and reduce losses in an IGBT. Figure 13 is a cross-sectional view of a side-gate IGBT. The side-gate IGBT 10 includes a collector electrode 11, a p-type collector layer 12, an n-drift layer 13, a p-base layer 14, an n+ emitter layer 15, a gate electrode 16, a gate oxide film (interlayer insulating film) 17, an emitter electrode 18, and a gate electrode terminal 19. The side-gate IGBT 10 has a structure in which the gate electrodes 16 are provided on both sides of the emitter electrode 18.

[0008] 14 is a diagram showing the effect of turning off the side-gate IGBT 10 (hereinafter referred to as IGBT 10) shown in FIG. 13 when the gate is negative. In FIG. 14, when the IGBT 10 is on, a gate voltage (Vg) equal to or greater than the threshold voltage (Vth) is applied to the gate electrode 16. When turning off, the IGBT 10 is turned off by setting the gate voltage (Vg) equal to or less than the threshold voltage (Vth). At this time, negatively biasing Vg not only improves the carrier extraction speed and reduces turn-off loss (Eoff), but also ensures redundancy against the IGBT turning on again due to noise, etc.

[0009] However, if the gate resistance (Rg) is reduced to increase the speed at which Vg is negatively biased in order to speed up turn-off, Vg will be negatively biased faster than the holes (accumulated holes 20) accumulated inside the device can be discharged. When the gate is negatively biased, a hole accumulation layer 21 (see hatching in FIG. 14 ) is formed under the gate electrode 16, as shown in FIG. 14 . If holes are discharged in this state, the current flowing through the IGBT 10 will concentrate in the region where the hole accumulation layer 21 is formed, increasing the electric field strength and current density in that region and inducing a dynamic avalanche (see arrow a in FIG. 14 ). When a dynamic avalanche is induced, the generated avalanche current increases the current flowing through the p-base layer 14 below the n+ emitter layer 15 (see arrow b in FIG. 14 ), activating the parasitic npn transistor 22 (see dashed box in FIG. 14 ). This causes latch-up breakdown of the IGBT 10. In other words, the IGBT breakdown tolerance is reduced. To summarize, the following applies:

[0010] When the potential at point A determined by the voltage drop when the avalanche current flows through p base layer 14 below n+ emitter layer 15 becomes greater than the built-in potential of the pn junction consisting of p base and n+ emitter, parasitic npn transistor 22 turns on.

[0011] The above problem is not limited to the side-gate IGBT 10, but is similar to other IGBT structures, such as trench-gate IGBTs. However, in the case of the side-gate IGBT 10, it is difficult to deepen the trench to reduce the step, so the depth of the p-base layer 14 is inevitably shallow. As a result, the potential at point A in FIG. 14 , which is determined by the potential drop caused by the avalanche current (see symbol b in FIG. 14 ) generated by the dynamic avalanche (see symbol a in FIG. 14 ) flowing through the p-base layer 14, is higher when the trench is shallower than when the trench is deep. Therefore, there is a concern that the parasitic npn transistor 22 is more likely to operate in the side-gate IGBT 10 than in a deep trench-gate IGBT. For this reason, the side-gate IGBT 10 has been used as an example.

[0012] JP 2017-70164 A JP 2023-013594 A JP 2021-141662 A

[0013] Patent Document 1 describes a technology for reducing vibration by raising the gate voltage above the threshold voltage again after the surge voltage peak (Vds peak) when a semiconductor switching element is turned off. However, with the method described in Patent Document 1, the gate voltage rises above the threshold voltage again after turn-off, causing the semiconductor switching element to turn on again, increasing loss.

[0014] Patent Document 2 describes a method for softening the turn-off of a semiconductor switching element by controlling the gate current to adjust the switching speed when the element is turned off. However, the method described in Patent Document 2 increases turn-off loss by slowing down the switching speed.

[0015] Patent Document 3 describes an example of active gate drive using current control by switching gate resistors. However, the method described in Patent Document 3 involves switching gate resistors, so although the gate drive speed can be changed during switching, it is difficult to control (or design) the gate voltage to a desired level so as to prevent inversion under the gate electrode 16 (see FIG. 14). Furthermore, because changes in gate resistance change the turn-off loss, it is not possible to achieve both reduced loss and improved tolerance.

[0016] The following summarizes the issues involved in improving the breakdown voltage and reducing losses in IGBTs. As shown in Figure 14, preventing the formation of a hole accumulation layer 21 under the gate electrode 16 and suppressing dynamic avalanche (see symbol a in Figure 14) are important for improving the breakdown voltage of the IGBT itself.

[0017] Figure 15 illustrates the trade-off between power dissipation performance (Eoff) and the reverse bias safe operating area (RBSOA), which indicates breakdown immunity. RBSOA is the range of current and voltage that an IGBT can use when turned off without degradation or breakdown. As shown in Figure 15, increasing the gate resistance (Rg) to prevent breakdown slows down the speed at which the gate voltage (Vg) is negatively biased. This reduces the formation of a hole accumulation layer 21 (see Figure 14) under the gate electrode 16 when holes accumulated inside the device are discharged. This prevents strong inversion under the gate around the time when the product of the collector current (Ic) and the collector-emitter voltage (Vce) (= IGBT power consumption) reaches its maximum, thereby improving the IGBT's breakdown immunity. However, adjusting the gate resistance (Rg) has the problem of increasing power dissipation performance (Eoff) due to a slower switching speed. In other words, there is a trade-off between improving power dissipation performance (RBSOA) and reducing power dissipation performance (Eoff), as shown in Figure 15, and achieving both is the challenge.

[0018] The present invention has been made in view of the above circumstances, and has as its object to provide a drive circuit for a semiconductor device and a power conversion device that improves breakdown resistance without increasing the switching loss of a semiconductor switching element, thereby achieving both low loss performance Eoff and high breakdown resistance performance RBSOA.

[0019] In order to solve the above problem, a drive circuit for a semiconductor device of the present invention is provided, which includes a command logic unit that issues a drive command signal for a semiconductor switching element, and a gate drive device that drives the gate of the semiconductor switching element based on the drive command signal from the command logic unit, wherein, when the semiconductor switching element is turned off, after a first period (Tdraw) during which the command logic unit issues a command for an off voltage lower than the drive voltage, the gate drive device raises and holds the voltage of the gate drive device to an intermediate voltage (Vint_com) that is higher than the off voltage for a second period (Tint), and temporarily raises and holds the gate voltage (Vg) of the semiconductor switching element to a voltage (Vint) that is higher than the off voltage and lower than a threshold voltage (Vth), and the end timing of the first period (Tdraw) is later than the start timing of a mirror period and earlier than the end timing of the mirror period, and the end timing of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

[0020] According to the present invention, it is possible to provide a drive circuit for a semiconductor device and a power conversion device that improves breakdown resistance without increasing the switching loss of a semiconductor switching element, thereby achieving both low loss performance (Eoff) and high breakdown resistance performance (RBSOA).

[0021] 14 is a diagram illustrating an overall configuration of a power conversion device including a semiconductor device drive circuit according to a first embodiment of the present invention. FIG. 15 is a circuit diagram of a gate drive device of the semiconductor device drive circuit according to the first embodiment of the present invention. FIG. 16 is a circuit diagram of a power supply for the gate drive device of the semiconductor device drive circuit according to the first embodiment of the present invention. FIG. 17 is a diagram illustrating an example of switching waveforms of the gate drive device of the semiconductor device drive circuit according to the first embodiment of the present invention. FIG. 18 is a diagram illustrating an effect of the semiconductor device drive circuit according to the first embodiment of the present invention. FIG. 19 is a circuit diagram of a gate drive device of the semiconductor device drive circuit according to the first embodiment of the present invention. FIG. 19 is a diagram illustrating a schematic configuration of a semiconductor switching element according to the first embodiment of the present invention. FIG. 19 is a diagram illustrating an operation waveform of a general dual gate drive. FIG. 19 is a diagram illustrating switching waveforms during operation of the gate drive device of the semiconductor device drive circuit according to a second embodiment of the present invention. FIG. 19 is a diagram illustrating a switching waveform during operation of the gate drive device of a first modified example of the second embodiment of the present invention. FIG. 19 is a diagram illustrating a schematic configuration of a semiconductor switching element according to a second modified example of the second embodiment of the present invention. FIG. 19 is a diagram illustrating a schematic configuration of a semiconductor switching element according to a third modified example of the second embodiment of the present invention. FIG. 19 is a cross-sectional view of a side-gate IGBT. FIG. 19 is a diagram illustrating the effect of turn-off when the gate of the side-gate IGBT shown in FIG. 13 is negative. FIG. 19 is a diagram illustrating the trade-off between loss performance Eoff and RBSOA, which indicates breakdown resistance performance.

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (First Embodiment) A semiconductor device drive circuit according to a first embodiment of the present invention will be described. This embodiment is an example in which a power conversion device including a semiconductor device drive circuit is applied to a control system for an inductive load using a three-phase inverter. Furthermore, the semiconductor device is suitably applied to not only trench-gate IGBTs but also side-gate IGBTs, which are difficult to suppress the occurrence of dynamic avalanches.

[0023] [Overall Configuration] Figure 1 is an overall configuration diagram of a power conversion device including a semiconductor device drive circuit according to a first embodiment. The power conversion device 200 shown in Figure 1 outputs AC current based on DC power supplied from a DC power supply 30 to drive an electric motor 50. The semiconductor device drive circuit 100 includes a command logic unit 110 and a gate drive device 120, and drives a semiconductor switching element 140 (semiconductor device; semiconductor element; element). The gate drive device 120 and the semiconductor switching element 140 constitute an inverter circuit 160. The power conversion device 200 includes the inverter circuit 160 and the command logic unit 110. A smoothing capacitor 40 is provided between the DC power supply 30 (power supply voltage = Vcc) and the positive electrode connection line 160a and negative electrode connection line 160b of the inverter circuit 160.

[0024] The inverter circuit 160 includes three UVW phase series circuits of semiconductor switching elements 140, each consisting of an upper arm and a lower arm. In FIG. 1 , the semiconductor switching elements 140 of the upper and lower arms are each configured with an IGBT. The high-potential terminal of the upper arm IGBT of each phase is connected to a first end (positive electrode connection wire 160a) of the smoothing capacitor 40. The low-potential terminal of the upper arm IGBT of each phase is connected to a high-potential terminal of the lower arm IGBT of each phase. The low-voltage terminal of the lower arm IGBT of each phase is connected to a second end (negative electrode connection wire 160b) of the smoothing capacitor 40.

[0025] In each phase, the connection point between the low potential side terminal of the IGBT in the upper arm and the high potential side terminal of the IGBT in the lower arm is connected to one end of a winding of the motor 50. The other end of the winding of each phase is connected to a neutral point. The motor 50 is, for example, an induction motor.

[0026] Each IGBT is connected in anti-parallel to a freewheeling diode 150. Various types of diodes can be used as the freewheeling diode 150, such as a pn junction diode, a Schottky barrier diode, or a diode that uses both a pn junction and a Schottky junction.

[0027] The command logic unit 110 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate driver 120 as an ON / OFF drive command signal P for the semiconductor switching elements 140. In response to this, the command logic unit 110 alternately turns ON the semiconductor switching elements 140 of the upper arm and the semiconductor switching elements 140 of the lower arm in each phase in order to control the control variable of the electric motor 50 to the command value. The control variable is, for example, the torque of the electric motor 50.

[0028] The gate driver 120 is provided for each semiconductor switching element 140, receives an on / off drive command signal P from the command logic unit 110, and turns the semiconductor switching element 140 on or off based on the received on / off drive command signal P.

[0029] Each semiconductor switching element 140 controls the power and torque supplied to the connected electric motor 50 by repeatedly turning on and off at high speed.

[0030] In this embodiment, the command logic unit 110 is provided outside the inverter circuit 160, but the command logic unit 110 may be incorporated into the inverter circuit 160. In this case, the semiconductor device driver circuit 100 is also incorporated into the inverter circuit 160.

[0031] [Gate Drive Device] FIG. 2 is a circuit diagram of the gate drive device 120 of the drive circuit 100 for the semiconductor device of FIG. 1. FIG. 3 is a circuit diagram of the power supply for the gate drive device 120 of FIG. 2. FIG. 2 shows the semiconductor switching element 140 and its gate drive device 120 associated with the lower arm of the U-phase in the inverter circuit 160 of FIG. 1. In FIG. 2, the semiconductor switching elements 140 and their gate drive devices 120 in the upper arm of the U-phase and the upper and lower arms of the V-phase and W-phase also have the same configuration as in FIG. 2. While FIG. 2 describes the configuration and operation of the semiconductor switching element 140 and its gate drive device 120 in the lower arm of the U-phase, the semiconductor switching elements 140 and their gate drive devices 120 in the upper and lower arms of the V-phase and W-phase also have the same configuration as in FIG. 2.

[0032] As shown in FIG. 2 , the gate driver 120 includes an intermediate voltage control unit (gate voltage control unit) 121, an on / off control unit 122, a positive-side power supply (power supply voltage=Vp) 123, a first PMOSFET (PMOSFET<1>) 124 (PMOSFET<1>), a second PMOSFET (PMOSFET<2>) 125, an on-side gate resistor (Rgon) 126, a negative-side power supply (power supply voltage=Vm) 127, an off-side gate resistor (Rgoff) 128, an NMOSFET 129, an auxiliary power supply (power supply voltage=Vaux) 130, and an auxiliary gate resistor (Rgaux) 131.

[0033] The output section of the gate driver 120 is connected to the gate electrode G of the semiconductor switching element 140 via a terminal G. The reference potential 132 of the gate driver 120 is connected to the emitter terminal E of the semiconductor switching element 140. Furthermore, the input section of the gate driver 120 is connected to the P output and Q output of the command logic unit 110 via input terminals P and Q.

[0034] The source of the PMOSFET<1> 124 is connected to the positive-side power supply 123, and the source of the PMOSFET<2> 125 is connected to the auxiliary power supply 130. The drain of the PMOSFET<1> 124 is connected to one end of the on-side gate resistor (Rgon) 126, and the drain of the PMOSFET<2> 125 is connected to one end of the auxiliary gate resistor (Rgaux) 131. The drain of the NMOSFET 129 is connected to one end of the off-side gate resistor (Rgoff) 128, and the source of the NMOSFET 129 is connected to the negative-side power supply 127. The other end of the on-side gate resistor (Rgon) 126, the other end of the auxiliary gate resistor (Rgaux) 131, and the other end of the off-side gate resistor (Rgoff) 128 are all connected to the output terminal G of the output section of the gate driver 120. The gates of the PMOSFET<1> 124 and the NMOSFET 129 are all connected to the output section of the on / off control section 122. The gate of the PMOSFET<2> 125 is connected to the output of the intermediate voltage control unit 121 .

[0035] 3 is a power supply circuit diagram of the gate driver 120. The gate driver 120 is supplied with power from a positive power supply 123 (power supply voltage=Vp), a negative power supply 127 (power supply voltage=Vm), and an auxiliary power supply 130 (power supply voltage=Vaux).

[0036] As described above, the gate driver 120 is configured to include an on / off control unit 122, a positive power supply (power supply voltage = Vp) 123, a first PMOSFET (PMOSFET<1>) 124 (PMOSFET<1>), an on-side gate resistor (Rgon) 126, a negative power supply (power supply voltage = Vm) 127, an NMOSFET 129, and an off-side gate resistor (Rgoff) 128, all of which are operated in response to a conventional on / off drive command signal P. In addition, the gate driver 120 further includes an on / off control unit 122, an auxiliary power supply (power supply voltage = Vaux) 130, a second PMOSFET (PMOSFET<2>) 125, and an auxiliary gate resistor (Rgaux) 131, which are operated in response to an intermediate voltage drive command signal Q from the command logic unit 110. As a result, in addition to the conventional positive power supply (power supply voltage = Vp) 123 and negative power supply (power supply voltage = Vm) 127, a new power supply, the auxiliary power supply (power supply voltage = Vaux) 130, is added.

[0037] [Operation Description] The operation of the gate driver 120 of this embodiment will now be described. <Operation upon Input of ON / OFF Drive Command Signal P> The ON / OFF drive command signal P is input from the command logic unit 110 to the ON / OFF control unit 122 of the gate driver 120. The ON / OFF control unit 122 of the gate driver 120 operates to turn on the PMOSFET<1> 124 and turn off the NMOSFET 129 while the ON / OFF drive command signal P is being input from the command logic unit 110. This causes a current (gate current) to flow from the positive-side power supply 123 to the gate of the semiconductor switching element 140 via the ON-side gate resistor (Rgon) 126.

[0038] At this time, the capacitance between the gate and emitter of the semiconductor switching element 140 is charged and a voltage (for example, +15 V) exceeding the threshold voltage of the semiconductor switching element 140 is applied, turning on the semiconductor switching element 140 and causing a current to flow (turn on) through the semiconductor switching element 140. The turn-on switching speed is controlled by adjusting the resistance value (Rgon) of the on-side gate resistor (Rgon) 126.

[0039] Furthermore, the on / off control unit 122 of the gate driver 120 operates to turn off the PMOSFET<1> 124 and turn on the NMOSFET 129 while the on / off drive command signal P is not input from the command logic unit 110. This causes a gate current to flow from the gate of the semiconductor switching element 140 through the off-side gate resistor (Rgoff) 128 toward the negative power supply.

[0040] At this time, the capacitance between the gate and emitter terminals of the semiconductor switching element 140 is discharged and a voltage (for example, −15 V) lower than the threshold voltage of the semiconductor switching element 140 is applied, turning off the semiconductor switching element 140 and cutting off (turning off) the current through the semiconductor switching element 140. The turn-off switching speed is controlled by adjusting the resistance value (Rgoff) of the off-side gate resistor (Rgoff) 128.

[0041] <dV / dt During Switching Transition> The semiconductor switching element 140 is turned on / off by charging and discharging the gate capacitance. At that time, the gate-collector capacitance Cgc changes due to fluctuations dV / dt in the collector-emitter voltage Vce, and a Miller period occurs in which the gate-emitter voltage Vge becomes flat in order to charge and discharge Cgc.

[0042] However, the mirror period defined in this embodiment does not refer to the mirror period in the narrow sense in which the gate-emitter voltage Vge becomes flat, but refers to the period that begins when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes greater than the on-voltage (Vce(sat)) and ends when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes the same as the power supply voltage Vcc of the element (Vce=Vcc).

[0043] <Intermediate Voltage Drive Operation by Input of Intermediate Voltage Drive Command Signal Q> Basic Concept This embodiment is characterized in that, during the mirror period, an intermediate voltage drive command signal Q is input, the second PMOSFET (PMOSFET<2>) 125 is turned on, the auxiliary power supply (power supply voltage=Vaux) 130 is connected, and the auxiliary gate resistor (Rgaux) 131 is connected to the gate of the semiconductor switching element 140, thereby changing the gate voltage (Vg) to an intermediate voltage Vint shown in (Equation 1) described later, and further maintaining this intermediate voltage Vint for the Tint period.

[0044] Fig. 4 is a diagram showing an example of the switching waveforms of the gate driver 120. The upper part of Fig. 4 shows a gate drive command (= the output waveform of the drive circuit of the semiconductor device), the middle part of Fig. 4 shows the gate-emitter voltage waveform of the IGBT, and the lower part of Fig. 4 shows the collector-emitter voltage and current waveforms of the IGBT.

[0045] Tdraw is the time (first period) during which the gate drive command shown in the upper part of Figure 4 initially issues a command for a voltage (off voltage) lower than the drive voltage. Tint is the time during which the gate drive command shown in the upper part of Figure 4 issues a voltage command for an intermediate voltage Vint_com higher than the off voltage. Vint is the gate voltage (Vg) applied to the gate of the semiconductor switching element 140 (hereinafter referred to as the element) in the gate-emitter voltage waveform of the IGBT shown in the middle part of Figure 4. Vint is the second period during which the gate voltage (Vg) of the element is temporarily raised and maintained at a voltage (Vint) higher than the off voltage but lower than the threshold voltage (Vth). Vsuege is the surge voltage generated in the voltage and current waveforms between the collector and emitter of the IGBT shown in the lower part of Figure 4. The reasons for the constraints on the values ​​of Tdraw, Tint, and Vint are as follows.

[0046] <tdraw>If the Vint_com command is issued earlier than Vce > Vce(sat), the gate voltage rises before the carriers have been sufficiently discharged, slowing down the switching of the device and increasing Eoff. If the Vint_com command is issued after Vce = Vcc, the gate begins to rise when the collector current Ic begins to decrease. IGBTs break down when dI / dt is applied due to current concentration caused by the discharge of carriers, so the effect of improving the withstand capability cannot be obtained.

[0047] <tint>By issuing the Vint_com command (continuing to issue the Vint_com command) until the surge voltage Vsuege is exceeded, it is possible to prevent strong inversion under the gate when strong power is applied to the device. This suppresses dynamic avalanche near the gate, which can cause latch-up, improving the withstand voltage. Ideally, it is preferable to maintain the gate voltage (Vg) at Vint until the IGBT current becomes zero, as this prevents strong inversion throughout the entire carrier discharge period and improves the withstand voltage.

[0048] <vint>If Vint > Vth, not only will the IGBT turn on again and the collector current Ic increase, which not only increases Eoff, but an excessive current will flow when a voltage higher than the on-voltage (Vce(sat)) is applied to the element, which creates a risk of destruction due to the heat generated, so Vint < Vth is necessary. Therefore, Vint_com < Vth is necessary. However, if the condition Vint < Vth can be met by adjusting the length of Tint, Vint_com < Vth is not necessarily necessary.

[0049] <Features of this embodiment> The end of Tdraw (symbol c in FIG. 4) is later than the timing (symbol d in FIG. 4) when Vce > Vce(sat) (the start of the mirror period) and earlier than the time (symbol e in FIG. 4) when Vce = Vcc of the element (the end of the mirror period). Therefore, Tdraw is a fixed period indicated by arrow f in FIG. 4.

[0050] The timing at which Tint ends (symbol g in FIG. 4) is later (period indicated by arrow i in FIG. 4) than the timing at which the element experiences a surge voltage (Vsurge) (symbol h in FIG. 4).

[0051] <Explanation of Operation> When the IGBT is turned off, an intermediate voltage drive command signal Q is input from command logic unit 110 to intermediate voltage control unit 121 (FIG. 2) of gate driver 120 between the time when the collector-emitter voltage Vce of the element becomes greater than the on-voltage (Vce(sat)) (start of the mirror period) and the time when the collector-emitter voltage Vce of the element becomes the same as the power supply voltage Vcc of the element (Vce=Vcc) (end of the mirror period). The mirror period is the period from when the collector-emitter voltage Vce becomes greater than the on-voltage (Vce(sat)) to the time when Vce=Vcc (symbol e in FIG. 4) and the collector current Ic begins to drop.

[0052] The on-voltage (Vce(sat)) is a common name and is more accurately called the collector-emitter saturation voltage, which is the voltage value between the collector and emitter when a specified voltage is applied between the gate and emitter and a specified current flows through the collector. The collector-emitter voltage Vce is sometimes simply called the collector voltage Vce.

[0053] As shown in the upper part of Figure 4, during turn-off, the gate voltage (Vg) is first biased to an off-state voltage lower than the drive voltage, and then biased again to a positive voltage below the threshold voltage for a certain period (Tdraw) (first period). The positive bias begins during the period when the collector-emitter voltage Vce fluctuates dV / dt (i.e., the Miller period), and is returned to the off-state voltage after the collector-emitter voltage Vce reaches a surge voltage (Vsuege). This prevents strong inversion under the gate around the time when the product of the collector current Ic and the collector-emitter voltage Vce (= IGBT power consumption) reaches its maximum, thereby improving the RBSOA.

[0054] At the time of the above-mentioned turn-off, the intermediate voltage drive command signal Q is input from the command logic unit 110 to the intermediate voltage control unit 121 (FIG. 2) of the gate driver 120 between the timing when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes greater than the on-voltage (Vce(sat)) (start of the mirror period) and the time when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes the same as the power supply voltage Vcc of the element (Vce=Vcc) (end of the mirror period).

[0055] The intermediate voltage control unit 121 generates an intermediate voltage control signal based on the intermediate voltage drive command signal Q and applies it to the gate of the PMOSFET<2> 125 to turn on the PMOSFET<2> 125. When the PMOSFET<2> 125 is turned on, the auxiliary power supply (power supply voltage=Vaux) 130 is connected to one end of the ON-side gate resistor (Rgon) 126 and one end of the OFF-side gate resistor (Rgoff) 128 through the auxiliary gate resistor (Rgaux) 131.

[0056] The gate voltage (Vg) of the element is maintained at a voltage (Equation 1) determined by the auxiliary power supply (power supply voltage = Vaux) 130, the negative power supply (power supply voltage = Vm) 127, the off-side gate resistance (Rgoff) 128, and the auxiliary gate resistance (Rgaux) 131.

[0057]

[0058] Vint_com: Design voltage of the gate driver Vaux: Auxiliary power supply voltage Vm: Negative power supply voltage Rgoff: Gate resistance between the negative power supply and the semiconductor switching element Rgaux: Gate resistance between the auxiliary power supply and the semiconductor switching element

[0059] As shown in the middle of Figure 4, by inputting the intermediate voltage drive command signal Q, the gate voltage (Vg) of the element is changed from being negative (symbol j in Figure 4) to a voltage Vint_com (Equation 1) determined by the auxiliary power supply (power supply voltage = Vaux) 130, the negative-side power supply (power supply voltage = Vm) 127, the off-side gate resistance (Rgoff) 128, and the auxiliary gate resistance (Rgaux) 131, and then rises sharply (symbol k in Figure 4), and is maintained at the intermediate voltage Vint.

[0060] The timing relationship between the period in which the gate voltage (Vg) changes from negative to positive and transitions to an intermediate voltage Vint that is lower than the threshold voltage Vth (symbol j→k in FIG. 4) and the end of the mirror period, Vce=Vcc (symbol e in FIG. 4), is an important timing specification. In other words, one of the timing conditions is that the timing when the gate voltage (Vg) starts to rise to the intermediate voltage Vint (symbol j→k in FIG. 4) is earlier than the timing when the collector current Ic starts to fall (when Vce=Vcc) (symbol e in FIG. 4).

[0061] In other words, the intermediate voltage drive command signal Q is input before the collector current Ic begins to drop and at a timing that anticipates that the gate voltage (Vg) will be maintained at the intermediate voltage Vint and completed. As can be seen from Equation 1, the slope of the voltage rise as the gate voltage (Vg) transitions to the intermediate voltage Vint is determined by the auxiliary power supply voltage Vaux, the negative power supply voltage Vm, the gate resistance Rgoff between the negative power supply and the device, and the gate resistance Rgaux between the auxiliary power supply and the device. If the auxiliary power supply voltage Vaux, the negative power supply voltage Vm, and the gate resistance Rgoff are assumed to be constants (constant values), the slope of the voltage rise of the gate voltage (Vg) is determined by the value of the gate resistance Rgaux. Note that the end of Tdraw is not controlled by the on / off drive command signal P; after issuing an off command, the on / off drive command signal P continues to issue an off command. The period from when the on-off drive command signal P becomes an OFF command until the intermediate voltage drive command signal Q issues a Vint_com command is Tdraw, and the period from when the intermediate voltage drive command signal Q issues an OFF command is Tint.

[0062] The above has described the timing of the start of the intermediate voltage drive command signal Q. The intermediate voltage drive command signal Q changes the gate voltage (Vg) to the intermediate voltage Vint shown in (Equation 1) during the mirror period and then maintains this intermediate voltage Vint for the Tint period. The end of the Tint period is determined by the intermediate voltage drive command signal Q issuing an OFF command.

[0063] As shown in the collector-emitter voltage and current waveforms of the IGBT in the lower part of Figure 4, it is known from experience that dynamic avalanche occurs in the device when the collector current Ic is ramping (reference symbol l in Figure 4). Therefore, when the collector current Ic is ramping (when dI / dt is applied), the intermediate voltage Vint is maintained for the Tint period. Furthermore, the Vint_com command continues to be issued until the surge voltage Vsuege (reference symbol h in Figure 4) is passed. Therefore, the end of Tint (reference symbol g in Figure 4) is later (period indicated by arrow i in Figure 4) than when the device experiences the surge voltage (Vsurge) (reference symbol h in Figure 4). The timing at which the element experiences a surge voltage (Vsurge) is the point at which the risk of destruction is highest, and by making the timing at which Tint ends (symbol g in FIG. 4) later (later) than the timing at which the surge voltage (Vsurge) occurs (symbol h in FIG. 4), the element is protected from destruction by the surge voltage.

[0064] After the semiconductor switching element 140 (hereinafter referred to as the semiconductor element or the element as appropriate) experiences a surge voltage (Vsurge), the command logic unit 110 inputs an OFF drive command signal P to the gate driver 120, turning off the PMOSFET<2> 125, and the gate voltage Vg is controlled by the negative power supply (power supply voltage=Vm) 127.

[0065] <Modification> In the circuit diagram of the gate driver 120 in FIG. 2 , the auxiliary power supply 130 (power supply voltage = Vaux) and the positive power supply 123 (power supply voltage = Vp) may be common (Vp = Vaux). By commonizing the power supply voltage Vaux and the positive power supply voltage Vp, the auxiliary power supply 130 (power supply voltage = Vaux) can be omitted (reducing the size of the power supply circuit in FIG. 3 ). When the power supply voltage Vaux and the positive power supply voltage Vp are common, the gate voltage (Vg) only needs to satisfy Equation 1. However, when the power supply voltage Vaux and the positive power supply voltage Vp are common, increasing the power supply voltage Vaux to the positive power supply voltage Vp increases the threshold voltage Vth. To avoid this, the value of Rgaux must be increased. This slows down the speed at which the gate voltage (Vg) is increased (from j to k in FIG. 4 ), thereby increasing turn-off loss. For this reason, from the viewpoint of reducing losses, it is preferable to provide an auxiliary power supply 130 (power supply voltage=Vaux) and reduce the value of Rgaux to quickly raise the gate voltage (Vg).

[0066] Incidentally, as shown in the voltage and current waveforms between the collector and emitter of the IGBT in the lower part of Figure 4, as Vg increases, the carrier discharge speed slows down, and the slope of Vce becomes somewhat gentler at the timing of symbol c in Figure 4.

[0067] For the above reasons, the "auxiliary power supply" in claim 1 also includes the "positive power supply voltage" in the case of the common use.

[0068] Effect of First Embodiment As described above, the drive circuit 100 ( FIG. 2 ) for a semiconductor device according to the first embodiment includes a command logic unit 110 that issues a drive command signal for the semiconductor switching element 140, and a gate drive device 120 that drives the gate of the semiconductor switching element 140 based on the drive command signal (ON / OFF drive command signal P) from the command logic unit 110. When the semiconductor switching element 140 is turned off, the gate drive device 120 changes the voltage of the gate drive device 120 to an intermediate voltage (Vint in FIG. 4 ) that is higher than the OFF voltage after a first period (Tdraw in FIG. 4 ) during which the command logic unit 110 issues a command for an OFF voltage that is lower than the drive voltage. The voltage is raised and maintained for the second period (Tint in FIG. 4 ), and the gate voltage (Vg) of the semiconductor switching element 140 is temporarily raised and maintained at a voltage (Vint in FIG. 4 ) that is greater than the off-voltage and less than the threshold voltage (Vth) (symbol k in FIG. 4 ). The timing at which the first period (Tdraw in FIG. 4 ) ends (symbol g in FIG. 4 ) is later than the start (symbol d in FIG. 4 ) of the mirror period (arrow f in FIG. 4 ) and earlier than the end (symbol e in FIG. 4 ) of the mirror period, and the timing at which the second period (Tint in FIG. 4 ) ends (symbol g in FIG. 4 ) is later than the timing (symbol h in FIG. 4 ) at which the semiconductor switching element 140 experiences a surge voltage (Vsurge in FIG. 4 ).

[0069] With this configuration, the semiconductor device driver circuit 100 (FIG. 2) improves switching speed and prevents an increase in loss performance Eoff by quickly biasing the gate voltage (Vg) negative (symbol j in FIG. 4) during the first half of the dV / dt period during which loss performance Eoff occurs, while raising the gate voltage (Vg) to a positive intermediate voltage Vint (symbol j→k in FIG. 4) only during the dI / dt period during which the risk of device breakdown is high, thereby preventing the accumulation of positive charge (hole accumulation layer) and preventing strong inversion. Furthermore, by positioning the end of the intermediate voltage Vint (symbol g in FIG. 4) at Tint after the timing of the surge voltage (Vsurge) (symbol h in FIG. 4), the device can be protected from damage by surge voltage.

[0070] Therefore, it is possible to realize a waveform in which the gate voltage is maintained positive at the timing when a high Ic × Vce product (conduction loss) occurs without compromising the switching speed (dV / dt).As a result, it is possible to realize an internal state of the device in which dynamic avalanche (symbol a in FIG. 14) under the gate electrode 16 (FIG. 14) is suppressed by the drive circuit 100 of this semiconductor device, without increasing the gate resistance (Rg) for preventing breakdown.

[0071] FIG. 5 illustrates the effects of this embodiment in terms of the trade-off between loss performance Eoff and RBSOA, which indicates breakdown immunity. As described above, the semiconductor device driver circuit 100 can achieve an internal device state in which dynamic avalanche (symbol a in FIG. 14 ) under the gate electrode 16 ( FIG. 14 ) is suppressed without increasing the gate resistance (Rg). As indicated by the hollow arrow m in FIG. 5 , this embodiment achieves advantages by moving away from the Eoff-RBSOA trade-off while maintaining the Eoff-RBSOA trade-off relationship (see the solid line in FIG. 5 ) achieved by adjusting Rg. For example, focusing on a turn-off loss of 100% (%), the breakdown immunity can be improved by increasing the maximum interruption current by 50% or more without increasing Rg. Therefore, the breakdown immunity can be improved without increasing the IGBT's switching loss, achieving both low loss performance Eoff and high breakdown immunity performance RBSOA.

[0072] In the semiconductor device driver circuit 100 (FIG. 2), the gate driver 120 controls the gate voltage (Vg) to the intermediate voltage (Vint_com) shown in (Equation 1) during the turn-off operation of the semiconductor switching element 140.

[0073] In this way, the design voltage (Vint_com) of the gate driver 120 when the intermediate voltage Vint is introduced can be designed based on the auxiliary power supply voltage Vaux, the negative power supply voltage Vm, the gate resistance Rgoff, and the gate resistance Rgaux. In particular, optimal values ​​for the gate resistance Rgaux and the auxiliary power supply voltage Vaux can be designed.

[0074] In addition, in the drive circuit 100 (FIG. 2) of the semiconductor device, the semiconductor switching element 140 includes an IGBT, and the length of the second period (Tint) is variable depending on the breakdown voltage and interruption current (Ic) of the IGBT (the current obtained by viewing the collector current Ic from the interruption characteristics).

[0075] By doing this, the higher the breakdown voltage (i.e., the thicker the chip) or the larger the cutoff current (Ic) of the semiconductor device drive circuit 100, the more carriers are stored inside the chip at turn-off, so by extending the gate lift time, it is possible to expect a reliable improvement in the breakdown voltage.

[0076] In the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), after a first period (Tdraw in FIG. 4) in which the command logic unit 110 issues a command for an off-voltage lower than the drive voltage, when the semiconductor switching element 140 is turned off, the gate drive device 120 raises and holds the voltage of the gate drive device 120 to an intermediate voltage (Vint_com in FIG. 4) higher than the off-voltage for a second period (Tint in FIG. 4) and holds the gate voltage (Vg) of the semiconductor switching element 140 higher than the off-voltage. The voltage is temporarily raised and maintained at a voltage (Vint in FIG. 4) that is lower than the threshold voltage (Vth) that the semiconductor switching element 140 can tolerate (symbol k in FIG. 4), and gate drive control is performed such that the end timing (symbol g in FIG. 4) of the first period (Tdraw in FIG. 4) is later than the start (symbol d in FIG. 4) of the mirror period (arrow f in FIG. 4) and earlier than the end timing (symbol e in FIG. 4) of the mirror period, and the end timing (symbol g in FIG. 4) of the second period (Tint in FIG. 4) is later than the timing (symbol h in FIG. 4) at which the semiconductor switching element 140 experiences a surge voltage (Vsurge in FIG. 4).

[0077] By doing so, the driving circuit 100 of the semiconductor device can be driven at a higher speed by simplifying the driving under conditions other than overcurrent, where the risk of breakdown is low.

[0078] Furthermore, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), it increases the resistance value (Rgoff) of the OFF-side gate resistor.

[0079] In this way, the semiconductor device driver circuit 100 can reliably cut off the power supply so that the system does not break down when an overcurrent occurs by increasing the gate resistance while ignoring the increase in loss.

[0080] Furthermore, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), it switches off the gate voltage in multiple stages.

[0081] In this way, the semiconductor device driver circuit 100 can reliably cut off the power so that the system does not break down when an overcurrent occurs by driving the gate while ignoring the increase in loss.

[0082] Furthermore, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), it detects the inflection point of the collector-emitter voltage Vce (dynamic avalanche due to the overcurrent) when dV / dt falls below a predetermined value.

[0083] When an overcurrent occurs, a dynamic avalanche occurs, causing a phenomenon in which dV / dt becomes small during turn-off. The drive circuit 100 for the semiconductor device can detect the current and transition to an operation to protect the system.

[0084] Second Embodiment A semiconductor device driver circuit according to a second embodiment of the present invention will be described. This embodiment is an example of application to a semiconductor device driver circuit for a dual-gate IGBT having two independently controllable gates. FIG. 6 is a circuit diagram of a gate driver 120A of a semiconductor device driver circuit 100A according to the second embodiment. Components identical to those in FIG. 2 are designated by the same reference numerals. FIG. 6 shows a semiconductor switching element 140 and its gate driver 120A associated with the lower arm of the U-phase in the inverter circuit 160 of FIG. 1. While FIG. 6 describes the configuration and operation of the semiconductor switching element 140 and its gate driver 120A in the lower arm of the U-phase, the semiconductor switching elements 140 and their gate drivers 120A in the upper and lower arms of the V-phase and W-phase also have similar configurations.

[0085] 2, the semiconductor device driver circuit 100A shown in Fig. 6 has two gate terminals of the semiconductor switching element 140A, a control gate Gc and a switching gate Gs, and accordingly, the on / off control unit 122 shown in Fig. 2 is replaced by a delay control unit 122A in Fig. 6. The gate resistances (Rgcon, Rgcoff) on the Gc side, the NMOSFET <2> , PMOSFET <3> has increased. Therefore, the gate resistances Rgon and Rgoff in the first embodiment are now Rgson and Rgsoff, respectively. The auxiliary power supply is connected to the Gc side. The detailed configuration is as follows. The symbol Gc is used as the control gate Gc, the second gate electrode Gc, and the terminal Gc. Similarly, the symbol Gs is used as the switching gate, the first gate electrode, and the terminal.

[0086] As shown in FIG. 6 , the gate driver 120A includes an intermediate voltage control unit 121, a delay control unit 122A, a positive-side power supply (power supply voltage=Vp) 123, a PMOSFET<1> 124A, a third PMOSFET (PMOSFET<3>) 124B, a PMOSFET<2> 125, an ON-side gate resistance (Rgcon) 126A, an ON-side gate resistance (Rgson) 126B, a negative-side power supply (power supply voltage=Vm) 127, an OFF-side gate resistance (Rgcoff) 128A, an OFF-side gate resistance (Rgsoff) 128B, a first NMOSFET (NMOSFET<1>) 129A, a second NMOSFET (NMOSFET<2>) 129B, an auxiliary power supply (power supply voltage=Vaux) 130, and an auxiliary gate resistance (Rgaux) 131.

[0087] The output section of the gate driver 120A is connected to the first gate electrode Gs and the second gate electrode Gc of the semiconductor switching element 140A via terminals Gs and Gc. The reference potential of the gate driver 120A is connected to the emitter terminal E of the semiconductor switching element 140A. The input section of the gate driver 120A is connected to the Pd output and the Q output of the command logic unit 110 via input terminals Pd and Q.

[0088] The sources of the PMOSFET<1> 124A and PMOSFET<3> 124B are connected to the positive-side power supply 123, and the source of the PMOSFET<2> 125 is connected to the auxiliary power supply 130. The drains of the PMOSFET<1> 124A and PMOSFET<3> 124B are connected to one end of the on-side gate resistors (Rgcon) 126A and (Rgson) 126B, the drain of the PMOSFET<2> 125 is connected to one end of the auxiliary gate resistor (Rgaux) 131, and the drains of the NMOSFET<1> 129A and NMOSFET<2> 129B are connected to one end of the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B, respectively.

[0089] The other ends of the on-side gate resistors (Rgcon) 126A and (Rgson) 126B, the other end of the auxiliary gate resistor (Rgaux) 131, and the other ends of the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B are all connected to the output of the gate driver 120A. The sources of the NMOSFET<1> 129A and the NMOSFET<2> 129B are connected to the negative power supply 127. The gates of the PMOSFET<1> 124A and the PMOSFET<3> 124B and the gates of the NMOSFET<1> 129A and the NMOSFET<2> 129B are all connected to the output of the delay control unit 122A, and the gate of the PMOSFET<2> 125 is connected to the output of the intermediate voltage control unit (gate voltage control unit) 121.

[0090] 7 is a diagram showing a schematic configuration of the semiconductor switching element 140 A. The semiconductor cell 240 of the semiconductor switching element 140 A has an outer periphery region cell 240 a, a central region cell 240 b, a gate (Gc) electrode pad 241, and a gate (Gs) electrode pad 242.

[0091] The semiconductor switching element 140A drives and controls the central region cell 240b with different gate electrodes (Gc) and (Gs). Here, the control gate electrode (Gc) is turned off prior to turn-off (FIG. 8). By turning off the control gate electrode (Gc) prior to the switching gate electrode (Gs), some of the carriers accumulated in the central region cell 240b are discharged, preventing current concentration in the peripheral portion of the active region during turn-off, thereby improving the turn-off interruption capability.

[0092] [Operation Description] The operation of the gate driver 120A of this embodiment will now be described. In FIG. 6 , a drive command signal Pd is input from the command logic unit 110 to the delay control unit 122A of the gate driver 120A. While the drive command signal Pd is being input, the gate driver 120A operates the delay control unit 122A to turn on the PMOSFET<1> 124A and the PMOSFET<3> 124B and turn off the NMOSFET<1> 129A and the NMOSFET<2> 129B. This causes a gate current to flow from the positive-side power supply 123 to the control gate (Gc) (first gate) and switching gate (Gs) (second gate) of the semiconductor switching element 140A via the on-side gate resistors (Rgcon) 126A and (Rgson) 126B.

[0093] At this time, the capacitance between the gate and emitter of the semiconductor switching element 140A is charged, and a voltage (for example, +15 V) exceeding the threshold voltage of the semiconductor switching element 140A is applied, turning on the semiconductor switching element 140A and causing a current to flow through the semiconductor switching element 140A (turn-on). The turn-on switching speed is controlled by adjusting the resistance values ​​(Rgcon, Rgson) of the on-side gate resistors (Rgcon) 126A and (Rgson) 126B.

[0094] Normally, the first and second gate electrodes are turned on simultaneously at the time of turn-on. That is, at the time of turn-on, the time difference set by the delay control unit 122A is set to zero, but a delay may be provided.

[0095] Furthermore, the gate driver 120A operates the intermediate voltage control unit 121 to turn off the PMOSFET<1> 124A and the PMOSFET<3> 124B and turn on the NMOSFET<1> 129A and the NMOSFET<2> 129B while the drive command signal Pd is not being input from the command logic unit 110. This causes a gate current to flow from the gate (Gc and Gs) of the semiconductor switching element 140A toward the negative power supply 127 via the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B.

[0096] At this time, the capacitance between the gate and emitter terminals of the semiconductor switching element is discharged and a voltage (for example, −15 V) lower than the threshold voltage of the semiconductor switching element 140A is applied, turning off the semiconductor switching element 140A and cutting off the current through the semiconductor switching element 140A (turning off). The turn-off switching speed is controlled by adjusting the resistance values ​​(Rgcoff, Rgsoff) of the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B.

[0097] 8 shows the operating waveforms of a typical dual gate drive. Typically, at turn-off, the first gate electrode (Gc) is turned off before the second gate electrode (Gs). That is, at turn-off, the time difference (Tpre_off) set by the delay control unit 122A is set to Tpre_off (≧0). In situations where all gates need to be shut off urgently due to a system malfunction, the delay may be set to zero (Tpre_off ≒ 0).

[0098] Returning to FIG. 6 , by increasing the number of gate terminals of the semiconductor switching element 140A to two and setting the time difference (Tpre_off) set by the delay control unit 122A to Tpre_off (≧0), the carriers accumulated inside the semiconductor when the element is turned off are reduced compared to the semiconductor switching element 140 of the first embodiment, resulting in an improved turn-off speed (=reduced Eoff). It is important to note that this configuration, in principle, causes a negative bias on the first gate electrode (Gc) during turn-off, which leads to strong inversion under the first gate electrode. Below, we will explain why the configuration of the second embodiment can improve the issue of strong inversion under the first gate electrode.

[0099] In the second embodiment, at the time of turn-off, an additional voltage is applied to the Gc side in addition to the normal turn-off of the general dual gate drive shown in Fig. 8. Specifically, when Tdraw has elapsed since Gc was turned off, an on / off drive command signal P is input from the command logic unit 110 to the gate driver 120A, turning on the PMOSFET<2> 125, and the gate voltage Vg of the semiconductor switching element 140A (semiconductor element) is maintained at a voltage (Equation 2) determined by the auxiliary power supply (power supply voltage = Vaux) 130, the negative power supply (power supply voltage = Vm) 127, the off-side gate resistance (Rgoff) 128, and the auxiliary gate resistance (Rgaux) 131.

[0100]

[0101] Vint_com: Design voltage of the gate driver Vaux: Auxiliary power supply voltage Vm: Negative power supply voltage Rgcoff: Gate resistance between the negative power supply and the semiconductor switching element Rgaux: Gate resistance between the auxiliary power supply and the semiconductor switching element

[0102] At this time, Tdraw must be a positive value and shorter than Tpre_off (Tdraw < Tpre_off). After the semiconductor switching element 140A (semiconductor element) encounters a surge voltage (Vsurge), an on / off drive command signal P is input from the command logic unit 110 to the gate drive device 120A, causing the PMOSFET<2> 125 to turn off, and the gate voltage (Vg) of the semiconductor switching element 140A (semiconductor element) is controlled to the negative power supply voltage. An example of the waveform when the above operation is performed is shown in FIG. 9.

[0103] FIG. 9 is a diagram showing the switching waveforms during the operation of the gate drive device 120A of the second embodiment. The upper diagram in FIG. 9 shows the first gate (Gc) command and the second gate (Gs) command, the middle diagram in FIG. 9 shows the first gate voltage (Vgc) and the second gate voltage (Vgs), and the lower diagram in FIG. 9 shows the collector current Ic and Vce.

[0104] The drive circuit 100A of the semiconductor device of this embodiment is an IGBT in which the semiconductor switching element 140A is driven and controlled by two gates, and has a preparation period (= charge reduction time: Tpre_off) for turning off the first gate (Gc) prior to the turn-off of the second gate (Gs). After a certain period (Tdraw) when the first gate turns off first, the gate drive device 120A is provided to raise and hold the voltage of the gate drive circuit of the first gate to an intermediate voltage (Vint_com) greater than the off voltage for a certain period (Tint). The gate drive device 120A temporarily raises and holds the first gate voltage (Vgc) of the semiconductor switching element 140A to a voltage (Vint) greater than the off voltage and less than the threshold voltage (Vth) (reference numeral n in FIG. 9), and is characterized in that the length of Tdraw at this time is shorter than Tpre_off (reference numeral o in FIG. 9).

[0105] The reasons for setting Tdraw shorter than Tpre_off (symbol o in FIG. 9 ) and Vgc<Vth (symbol n in FIG. 9 ) are as follows: The semiconductor switching element 140A continues to conduct through only the second gate Gs even after the first gate Gc is turned off, and is turned off when Gs is turned off. Therefore, dV / dt and dI / dt occur, and the risk of breakdown arises only after the Gs off command is issued. Therefore, by raising the Gc gate earlier (Tdraw<Tpre_off) before the Gs off command is issued, it is possible to eliminate the strong inversion layer of holes generated under the Gc gate at turn-off. Furthermore, setting the Gc gate voltage (Vgc) below Vth prevents the device from re-turning on and prevents an increase in Eoff.

[0106] Effect of Second Embodiment A semiconductor device drive circuit 100A ( FIG. 6 ) according to the second embodiment is a semiconductor device drive circuit 100A including a gate drive device 120A that drives and controls a dual-gate IGBT having two gates, and the gate drive device 120 has a preparation period (= time for reducing accumulated charge: Tpre_off) for turning off the first gate (Gc) prior to turning off the second gate (Gs), and after a certain period (Tdraw) after the first gate is turned off first, the gate voltage of the first gate (Gc) is raised and held at an intermediate voltage (Vint) that is higher than the off-voltage for a certain period (Tint), and the first gate voltage (Vgc) of the IGBT is temporarily raised and held at a voltage (Vint) that is higher than the off-voltage and lower than the threshold voltage (Vth), and the length of the certain period (Tdraw) is shorter than the preparation period (Tpre_off).

[0107] With this configuration, the semiconductor device driver circuit 100A (FIG. 6) considers that the risk of breakdown of the semiconductor switching element 140A occurs after an OFF command is issued to the second gate (Gs). By raising the Gc gate voltage (Tdraw<Tpre_off) before the OFF command is issued to the second gate (Gs), the strong inversion layer of holes generated under the first gate (Gc) can be eliminated at turn-off. Furthermore, by setting the voltage (Vgc) of the first gate (Gc) below Vth, the device does not re-turn on, preventing an increase in the loss performance Eoff. As a result, similar to the first embodiment, the breakdown tolerance can be improved without increasing the IGBT's switching loss, achieving both low loss performance Eoff and high breakdown tolerance performance RBSOA.

[0108] [Variation 1 of the Second Embodiment] FIG. 10 shows switching waveforms during operation of a gate driver according to Variation 1 of the second embodiment. The same timing as in FIG. 9 is denoted by the same reference numerals. Variation 1 of the second embodiment adds the gate driver 120 of the first embodiment (FIG. 4) to the second gate (Gs) side. For example, the drive shown in FIG. 10 can be achieved by introducing a circuit connected to the auxiliary power supply 130 between the gate resistors Rgsoff and Rgson on the Gs side in FIG. 6, similar to the first gate (Gc) side. The operation is the same as in the second embodiment up until an OFF command is received by the second gate (Gs). After the OFF command is received by the second gate (Gs), the drive according to the first embodiment is added to the second gate (Gs). This eliminates the strong hole inversion layer on the second gate (Gs) side, further improving the reliability of the entire device.

[0109] [Modification 2 of Second Embodiment] Figure 11 is a diagram showing a schematic configuration of a semiconductor switching element according to Modification 2 of the second embodiment. Components identical to those in Figure 7 are designated by the same reference numerals, and redundant descriptions will be omitted. The semiconductor switching element according to Modification 2 includes a semiconductor cell 240 and a semiconductor cell 250. The semiconductor cell 250 has an outer periphery region cell 250a, a central region cell 250b, and two first gate (Gc) electrode pads 251 connected to the outer periphery region cell 250a.

[0110] The semiconductor switching element of the second modification is configured by connecting the collector electrodes of a chip Hc with a high hole injection efficiency from the collector side (low on-state voltage) and a chip Hs with a low hole injection efficiency from the collector side (high on-state voltage) in parallel, and connecting the emitter electrodes of the chips Hc and Hs in parallel. Gate electrodes Gc and Gs connected to the gates of Hc and Hs are connected to the output terminals Gc and Gs of the gate driver 120A shown in FIG. 6, respectively. The Hs chip, which has high conductivity and low conduction loss, and the Hs chip, which has high speed and low switching loss, are spatially separated. This configuration, when combined with the gate driver 120A of the second embodiment, which provides a delay (Tpre_off) between Gc and Gs off, further enhances the effect of reducing losses generated in the semiconductor switching element 140A.

[0111] [Modification 3 of Second Embodiment] Figure 12 is a diagram showing a schematic configuration of a semiconductor switching element according to Modification 3 of the second embodiment. Components identical to those in Figure 7 are designated by the same reference numerals, and redundant description will be omitted. The semiconductor switching element according to Modification 3 includes a semiconductor cell 260 and a semiconductor cell 270. The semiconductor cell 260 includes a periphery region cell 260a, a central region cell 260b, and a gate (Gs) electrode pad 262 connected to the central region cell 260b. The semiconductor cell 270 includes a periphery region cell 270a, a central region cell 277b, and a gate (Gc) electrode pad 271 connected to the periphery region cell 260a.

[0112] The semiconductor switching element of Variation 3 is configured by connecting the collector electrodes of a chip Hc with a high hole injection efficiency from the collector side (low on-state voltage) and a chip Hs with a low hole injection efficiency from the collector side (high on-state voltage) in parallel, and by connecting the emitter electrodes of these chips. Gate electrodes Gc and Gs connected to the gates of Hc and Hs are connected to terminals Gc and Gs of the output section of the gate driver 120A shown in FIG. 6, respectively. By configuring the Hs chip with high conductivity and low conduction loss and the Hs chip with high speed and low switching loss as separate chips, the configuration is more spatially separated than the configuration shown in FIG. 11. This configuration, when combined with the gate driver 120A of the second embodiment, which provides a delay (Tpre_off) between Gc and Gs off, has the advantage of further reducing losses generated in the semiconductor switching element 140A.

[0113] [Fourth Modification of Second Embodiment] In addition, in a drive circuit 100A ( FIG. 6 ) for a semiconductor device, two or more semiconductor switching elements each having different on-voltages and capable of being driven and controlled by two or more gates are mounted on the same substrate with their collector electrodes and emitter electrodes connected in parallel, and the drive circuit 100A includes a gate drive device that drives the operation of each gate with a time lag (Tpre_off), in which the gate drive device 120A may be configured such that, after a certain period (Tdraw) after a preceding gate that turns off prior to a switching gate that is to be turned off last is turned off, the gate voltage of the preceding gate is raised and held at an intermediate voltage (Vint_com) that is higher than the off-voltage for the certain period (Tint), and the preceding gate voltage of the semiconductor switching element is temporarily raised and held at a voltage (Vint) that is higher than the off-voltage and lower than a threshold voltage (Vth), and the length of the certain period (Tdraw) during the temporary raised and held state may be shorter than the time lag (Tpre_off).

[0114] [Fifth Modification of Second Embodiment] In the drive circuit 100A ( FIG. 6 ) for a semiconductor device, the gate drive device 120A may have the same configuration as the gate drive device 120 in FIG. 2 , that is, when the semiconductor switching element 140A is turned off, after a first period (Tdraw) during which the command logic unit 110 ( FIG. 6 ) issues a command for an off-voltage lower than the drive voltage, the voltage of the gate drive device is raised and maintained at an intermediate voltage (Vint_com) higher than the off-voltage for a second period (Tint), and the gate voltage (Vg) of the semiconductor switching element 140A is temporarily raised and maintained at a voltage (Vint) that is higher than the off-voltage and lower than a threshold voltage (Vth), so that the end timing of the first period (Tdraw) is later than the start timing of the mirror period and earlier than the end timing of the mirror period, and the end timing of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

[0115] [Sixth Modification of the Second Embodiment] The drive circuit 100A (FIG. 6) for a semiconductor device monitors the collector-emitter voltage (Vce), which is the element voltage of the semiconductor switching element 140A, during the time difference (Tpre_off). If the value exceeds the threshold value (Vce_th) (Vce>Vce_th), the gate drive device 120A changes the voltage of the gate drive device 120A to an intermediate voltage (Vint_c) greater than the off voltage after a first period (Tdraw) during which the command logic unit 110 (FIG. 6) issues a command for an off voltage lower than the drive voltage when the semiconductor switching element is turned off. and temporarily raising and holding the second gate voltage (Vgs) of the semiconductor switching element to a voltage (Vint) that is greater than the off-voltage and less than the threshold voltage (Vth), and operating gate drive such that the timing of the end of the first period (Tdraw) is later than the start of the mirror period and earlier than the end of the mirror period, and the timing of the end of the second period (Tint) is later than the timing at which the semiconductor switching element 140A experiences the surge voltage (Vsurge).

[0116] The present invention is not limited to the above-described embodiments and modifications, and includes other modifications and applications as long as they do not deviate from the gist of the present invention as set forth in the claims. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0117] The semiconductor devices (semiconductor switching elements) of the semiconductor device drive circuits 100 and 100A may be MOSFETs, unipolar devices such as JFETs (Junction Field Effect Transistors), or bipolar devices such as IGBTs. Depending on the device, the main terminals and sense terminals may be called "collector" and "emitter" instead of the above-mentioned "drain" and "source."

[0118] Furthermore, the power conversion device 200 to which the drive circuits 100, 100A of this semiconductor device are applied can be applied to motor drive systems for various types of moving objects, including railway cars and electric vehicles, as well as industrial systems, PCSs (Power Conditioning Systems) in solar power generation devices and wind power generation devices, smart grids (power distribution systems), and the like.

[0119] 100, 100A Semiconductor device drive circuit 110 Command logic unit 120, 120A Gate drive device 140, 140A Semiconductor switching element (semiconductor device; semiconductor element; element) 160 Inverter circuit 160a Positive electrode connecting wire of inverter circuit 160b Negative electrode connecting wire of inverter circuit 121 Intermediate voltage control unit (gate voltage control unit) 122 On / off control unit 122A Delay control unit 123 Positive side power supply (power supply voltage = Vp) 124 PMOSFET<1> 125 PMOSFET<2> 126 On side gate resistance (Rgon) 127 Negative side power supply (power supply voltage = Vm) 128 Off side gate resistance (Rgoff) 129 NMOSFET 130 Auxiliary power supply (power supply voltage = Vaux) 131 Auxiliary gate resistance (Rgaux) 200 Power conversion device 240, 250 Semiconductor cell 250a, peripheral region cell 250b, central region cell 251, first gate (Gc) electrode pad, Tdraw, first period, Tint, second period< / vint> < / tint> < / tdraw>

Claims

1. A drive circuit for a semiconductor device comprising: a command logic unit that issues a drive command signal for a semiconductor switching element; and a gate drive device that drives the gate of the semiconductor switching element based on the drive command signal from the command logic unit, wherein, when the semiconductor switching element is turned off, after a first period (Tdraw) during which the command logic unit issues a command for an off voltage lower than the drive voltage, the gate drive device raises and holds the voltage of the gate drive device to an intermediate voltage (Vint_com) that is higher than the off voltage for a second period (Tint), and temporarily raises and holds the gate voltage (Vg) of the semiconductor switching element to a voltage (Vint) that is higher than the off voltage and lower than a threshold voltage (Vth), the end timing of the first period (Tdraw) is later than the start of a mirror period and earlier than the end of the mirror period, and the end timing of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

2. The gate driver controls the gate voltage (Vg) to an intermediate voltage (Vint_com) expressed by the following formula during the turn-off operation of the semiconductor switching element:

2. The semiconductor device drive circuit according to claim 1, wherein Vint_com is a design voltage of the gate drive device, Vaux is an auxiliary power supply voltage, Vm is a negative power supply voltage, Rgoff is a gate resistance between the negative power supply and the semiconductor switching element, and Rgaux is a gate resistance between the auxiliary power supply and the semiconductor switching element.

3. The semiconductor device drive circuit according to claim 1, characterized in that the semiconductor switching element comprises an IGBT, and the length of the second period (Tint) is variable depending on the breakdown voltage and interruption current (Ic) of the IGBT.

4. The drive circuit for a semiconductor device according to claim 1, wherein, when an overcurrent is detected, the gate drive device, when turning off the semiconductor switching element, after a first period (Tdraw) during which the command logic unit issues a command for an off voltage lower than the drive voltage, raises and holds the voltage of the gate drive device to an intermediate voltage (Vint_com) higher than the off voltage for a second period (Tint), and temporarily raises and holds the gate voltage (Vg) of the semiconductor switching element to a voltage (Vint) higher than the off voltage and lower than a threshold voltage (Vth), wherein the end timing of the first period (Tdraw) is later than the start timing of a mirror period and earlier than the end timing of the mirror period, and the end timing of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

5. The drive circuit for a semiconductor device according to claim 2, characterized in that the gate drive device increases the resistance value (Rgoff) of the OFF-side gate resistor when an overcurrent is detected.

6. The drive circuit for a semiconductor device according to claim 1, wherein the gate drive device switches the gate voltage in multiple stages and turns it off when an overcurrent is detected.

7. The semiconductor device drive circuit according to claim 1, wherein when the gate drive device detects an overcurrent, it detects an inflection point of the collector-emitter voltage Vce when dV / dt falls below a predetermined value.

8. A drive circuit for a semiconductor device including a gate drive device that drives and controls a dual-gate IGBT having two gates, wherein the gate drive device has a preparation period (Tpre_off) in which a first gate (Gc) is turned off prior to the turning off of a second gate (Gs), and a certain period (Tdraw) after the first gate is turned off first, the gate voltage of the first gate is raised and held at an intermediate voltage (Vint_com) greater than the off-voltage for a certain period (Tint), and the first gate voltage (Vgc) of the IGBT is temporarily raised and held at a voltage (Vint) greater than the off-voltage and less than a threshold voltage (Vth), and the length of the certain period (Tdraw) during which the voltage is temporarily raised and held is shorter than the preparation period (Tpre_off).

9. The drive circuit for a semiconductor device according to claim 8, further comprising a command logic unit that issues a drive command signal for a semiconductor switching element, wherein the gate drive device, when the semiconductor switching element is turned off, operates to raise and maintain the voltage of the gate drive device at an intermediate voltage (Vint_com) that is higher than the off-voltage for a second period (Tint) after a first period (Tdraw) during which the command logic unit issues a command for an off-voltage that is lower than the drive voltage, and to temporarily raise and maintain a second gate voltage (Vgs) of the semiconductor switching element at a voltage (Vint) that is higher than the off-voltage and lower than a threshold voltage (Vth), and the timing of the end of the first period (Tdraw) is later than the start of a mirror period and earlier than the end of the mirror period, and the timing of the end of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

10. A power conversion device comprising a drive circuit for a semiconductor device according to any one of claims 1 to 9.

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