Failing bit node systems for circuit design, test and diagnosis

Abstract

Techniques for generating a failing bit node system for a circuit design (330). The failing bit node system comprise equivalent fault group information extracted from a huge amount of fault simulation data for the circuit design. The related equivalent fault group information allows the failing bit node system to shrink or expand under certain conditions. Based on the failing bit node system, diagnosis coverage values are be predicted for various constraints, which can be employed to make circuit designs diagnosis friendly (350). The failing bit node system can be converted into a fault partition node system. Dictionary-like diagnosis are performed based on the failing bit node system (360).

Description

[0001] Failing Bit Node Systems for Circuit Design, Test and Diagnosis

[0002] FIELD OF THE DISCLOSED TECHNOLOGY

[0003]

[0001] The present disclosed technology relates to the field of circuit test and diagnosis. Various implementations of the disclosed technology may be particularly useful for diagnosis coverage prediction, design for diagnosis, and dictionary-like diagnosis.

[0004] BACKGROUND OF THE DISCLOSED TECHNOLOGY

[0005]

[0002] Modem integrate circuits are complex. At leading technology nodes, feature sizes have shrunk to a few nm wide. Non-planar or “three-dimensional” transistors (FinFET and GAA (gate-all-around)) are being used to achieve higher performance with lower power consumption. The non-planar transistors and transistor connections have more complicated structures with more layers and thus require more process steps. More process steps and smaller feature sizes can result in more root causes of defects. For these integrate circuits to be commercially viable, the manufacture yield needs to reach and maintain above a certain threshold. Therefore, accurately identifying yield-limiting root causes becomes highly critical. In the past, bitmapping static random-access memories (SRAMs) has been employed as a “yield learning vehicle”. For leading technology nodes, however, being capable of manufacturing these regular structures does not guarantee that a product with irregular structures can be successfully manufactured.

[0006]

[0003] Software-based diagnosis of scan test failures has proven to be of enormous value for yield learning. Scan testing is commonly used in a manufacture process to ensure that integrated circuits are fabricated correctly. Diagnosis uses failure data from scan testing along and circuit design information to determine the most likely defect locations and mechanisms for failing circuits (dies). The diagnosis results can guide physical failure analysis (PF A) to focus on a much smaller area in a failing circuit, leading to higher success rates of PFA with reduced turnaround time and costs. Based on the yield loss mechanism obtained by PFA, circuit design or manufacture process can be adjusted to improve manufacture yields.

[0007]

[0004] The PFA process is destructive to integrated circuits. It is thus important for diagnosis to provide a target area for PFA as precise as possible. Fault simulation has been employed to help solve test quality problems. In a similar way, fault simulation may be used to improve diagnosis quality. Diagnosis quality can be affected by insufficient data collected by a tester, low-quality test pattern sets, or circuit design issues. If the problems are identified earlier, remedies to improve diagnosis resolution could be applied before silicon tape-out or manufacture testing.

[0008]

[0005] Fault simulation for diagnosis can generate a huge amount of data. A typical modern circuit design can have hundreds of scan chains, each scan chain can have hundreds of scan cells, and the number of faults can reach half a million. As such, full failing bit information for all faults obtained through fault simulation for diagnosis would not only demand unrealistic amounts of computer storage but could also result in unacceptably slow computing speeds. Signature-based methods may be employed to reduce the amount of information to be stored. But a lot of useful information is often lost during the signature generation process, limiting their applications.

[0009] BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY

[0010]

[0006] Various aspects of the present disclosed technology relate to techniques for generating a failing bit node system for a circuit design. In one aspect, there is a method comprising: receiving a circuit design, a plurality of faults, and one or more test patterns, the circuit design comprising one or more test response output channels; performing fault simulation for each of the one or more test patterns in a sequence to determine a test response bit at each of observation clock cycles from each of the one or more test response output channels, the sequence being the same as a sequence in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design, test response bits derived from the fault simulation comprising passing bits and failing bits; generating a failing bit node system for the circuit design based on the test response bits, the failing bit node system comprising failing bit nodes and equivalent fault groups, each of the equivalent fault groups comprising one or more faults in the plurality of faults and being associated with one of the failing bit nodes, the generating comprising: creating one new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has at least one failing bit at one of the observation clock cycles but is not separated into two or more new equivalent fault groups based on one or more test response bits at the one of the observation clock cycles, and changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node, creating (TV - 1) new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if one of the N new equivalent fault group has no failing bit, associating the N new equivalent fault groups with the (TV - 1) new failing bit nodes and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node, and creating TV new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into TV new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if each of the TV new equivalent fault groups has at least one failing bit, associating each of the TV new failing bit nodes with one of the TV new equivalent fault groups, and removing the association of the existing equivalent fault group with the existing failing bit node; and storing information of the failing bit node system.

[0011]

[0007] The one or more test patterns may be a sub-group of test patterns in an original group of test patterns. The method may further comprises: updating the plurality of faults by removing, from the plurality of faults, faults of which each becomes a fault in an equivalent fault group alone; repeating the performing and the generating for a next sub- group of test patterns in the original group of test patterns to expand the failing bit node system; and iterating the updating and the repeating until all test patterns in the original group of test patterns are used or no fault is left in the plurality of faults, the sequence of test patterns simulated being the same as a sequence in which the original group of test patterns would be used to test the circuit.

[0012]

[0008] A failing bit node in the failing bit node system may be further associated with failing bit information, observation clock cycle information, or both.

[0013]

[0009] The failing bit node system may be generated for each of the one or more test response output channels, a number of failing bit node systems generated being equal to a number of the one or more test response output channels, wherein N = 2 and the generating comprising: creating a new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has a failing bit at one of the observation clock cycles; if the failing bit does not separate the existing equivalent fault group into two new equivalent fault groups, changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node; and if the failing bit separates the existing equivalent fault group into two new equivalent fault groups, associating the two new equivalent fault groups with the new failing bit node and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node.

[0014]

[0010] The plurality of faults may be divided into preliminary equivalent fault groups. The preliminary equivalent fault groups may be derived based on results of preliminary fault simulation for some test patterns.

[0015]

[0011] The method may further comprise: determining a diagnosis coverage value based on the failing bit node system and a constraint associated with a limited size of a failing bit buffer of a tester. The determining may comprise: removing failing bit nodes having cumulated failing bit counts above a threshold associated with the limited size; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

[0016]

[0012] The method may further comprise: determining a diagnosis coverage value based on the failing bit node system and a constraint associated with an observation clock cycle limit or a subgroup of test patterns in the one or more test patterns. The determining may comprise: removing failing bit nodes with which observation clock cycles associated are greater than the observation clock cycle limit or a largest observation clock cycle for the subgroup of test patterns; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

[0017]

[0013] The method may further comprise: converting the failing bit node system into a fault partition node system for the circuit design. The converting may comprise: removing failing bit nodes that do not separate an equivalent fault group into two or more groups; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

[0018]

[0014] The method may further comprise: performing dictionary-like diagnosis by mapping test response bits obtained from a tester to the failing bit node system.

[0019]

[0015] In another aspect, there is one or more computer-readable media storing computerexecutable instructions for causing one or more processors to perform the above method.

[0016] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0020]

[0017] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0021] BRIEF DESCRIPTION OF THE DRAWINGS

[0022]

[0018] Figure 1 illustrates an example of a computing device that may be used to implement various embodiments of the disclosed technology.

[0023]

[0019] Figure 2 illustrates an example of a failing bit node system generation tool that may be implemented according to various embodiments of the disclosed technology.

[0024]

[0020] Figure 3 illustrates a flowchart showing a process of failing bit node system generation that may be implemented according to various examples of the disclosed technology.

[0025]

[0021] Figure 4A illustrates an example of test response output channels that are coupled to outputs of scan chains.

[0026]

[0022] Figure 4B illustrates an example of test response output channels in a test compression environment.

[0023] Figure 5 illustrates a flowchart showing an example process for creating new failing bit nodes for a failing bit node system for a circuit design that may be implemented according to various examples of the disclosed technology.

[0027]

[0024] Figure 6A uses a diagram as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for a circuit design corresponding to the operation 540 shown in Fig. 5.

[0028]

[0025] Figure 6B uses a diagram as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for a circuit design corresponding to the operation 550 shown in Fig. 5.

[0029]

[0026] Figure 6C uses a diagram as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for a circuit design corresponding to the operation 560 shown in Fig. 5.

[0030]

[0027] Figure 7 illustrates an example profile of diagnosis coverage vs per-pin failing bit limit.

[0031]

[0028] Figure 8 A uses a diagram as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for one test response output channel when existing equivalent fault groups are divided into new equivalent fault groups that may be implemented according to various examples of the disclosed technology.

[0032]

[0029] Figure 8B uses a diagram as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for one test response output channel when existing equivalent fault groups cannot be divided into new equivalent fault groups that may be implemented according to various examples of the disclosed technology.

[0033]

[0030] Figure 9 illustrates a flow chart showing a process of failing bit node system generation that may be implemented according to various examples of the disclosed technology.

[0031] Figure 10 illustrates a simple circuit which is used to show the relationships between binary decision trees (BDTs), reduced binary decision trees (RBDTs), asymmetric binary decision trees (ABDTs), and asymmetric partition binary decision trees (APTs).

[0034]

[0032] Figure 11 A illustrates a binary decision tree (BDT) for Pin A of the design shown in Fig. 10.

[0035]

[0033] Figure 1 IB illustrates a binary decision tree (BDT) for Pin B of the design shown in Fig. 10.

[0036]

[0034] Figure 12 illustrates a multiple decision tree for the design shown in Fig. 10.

[0037]

[0035] Figure 13 A illustrates a reduced binary decision tree (RBDT) for Pin A of the design shown in Fig. 10.

[0038]

[0036] Figure 13B illustrates a reduced binary decision tree (RBDT) for Pin B of the design shown in Fig. 10.

[0039]

[0037] Figure 14A illustrates an asymmetric binary decision tree (ABDT) for Pin A of the design shown in Fig. 10.

[0040]

[0038] Figure 14B illustrates an asymmetric binary decision tree (ABDT) for Pin B of the design shown in Fig. 10.

[0041]

[0039] Figure 15A illustrates an asymmetric partition binary decision tree (APT) for Pin A of the design shown in Fig. 10.

[0042]

[0040] Figure 15B illustrates an asymmetric partition binary decision tree (APT) for Pin B of the design shown in Fig. 10.

[0043]

[0041] Figure 16A illustrates an asymmetric partition binary decision tree (APT) for Pin A of the design shown in Fig. 10 under an observation clock cycle limit of Cl.

[0042] Figure 16B illustrates an asymmetric partition binary decision tree (APT) for Pin B of the design shown in Fig. 10 under an observation clock cycle limit of Cl.

[0044]

[0043] Figure 17 illustrates a table comparing between the sizes of the binary decision trees (BDTs), the reduced binary decision trees (RBDTs), the asymmetric binary decision trees (ABDTs), and the asymmetric partition binary decision trees (APTs) for a real circuit design.

[0045] DETAILED DESCRIPTION OF THE DISCLOSED TECHNOLOGY

[0046] General Considerations

[0047]

[0044] Various aspects of the present disclosed technology relate to techniques for generating a failing bit node system for a circuit design. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosed technology.

[0048]

[0045] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0049]

[0046] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. The detailed description sometimes uses terms like “perform”, “generate,” “create,” and “associate” to describe the disclosed methods / systems. Such terms are high-level descriptions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0050]

[0047] As used in this disclosure, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not affecting the intended operation of the circuit.

[0051]

[0048] Also, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device, however, such as a portion of an integrated circuit device. Still further, the term “design” also is intended to encompass data describing more than one microdevice, such as data to be used to form multiple microdevices on a single wafer.

[0052] Design For Test, Test Pattern Generation, And Testing

[0053]

[0049] The reduction in feature size increases the probability that a manufacture defect in an integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnecting wire. Even a single faulty transistor or wire can cause the entire chip to function improperly. Manufacture defects are unavoidable nonetheless, no matter whether the manufacturing process is at the prototype stage or the high-volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Diagnosing faulty chips is also needed to ramp up and to maintain the manufacturing yield.

[0050] Testing typically includes applying a set of test stimuli (test patterns) to the circuit-under- test and then analyzing responses generated by the circuit-under-test. Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly. Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions.

[0054]

[0051] To make it easier to develop and apply test patterns, certain testability features are added to circuit designs, which is referred to as design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers for shifting in test patterns and shifting out test responses. A scan cell can operate as originally intended for functional purposes (functional / mission mode) and as a unit in a scan chain for scan testing (scan mode). A widely used type of scan cell includes an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port. The scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic. Scan cells can serve as both a control point and an observation point. Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting (activating) a fault and propagating the incorrect value to an observation point. Scan testing allows the test equipment to access gates deeply embedded through the primary inputs / outputs and / or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element.

[0055]

[0052] In a typical scan test, a series of known values (test stimuli or test pattern) are shifted-in (or loaded into) scan cells through their sequential inputs. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be called as test mode.

[0056]

[0053] Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process. ATPG usually focuses on a set of faults derived from a gatelevel fault model. A defect is a flaw or physical imperfection caused in a device during the manufacturing process. A fault model (or briefly a fault) is a description of how a defect alters design behavior. For a given target fault, ATPG comprises two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault (e.g., for a stuck-at-0 fault, the fault activation process will try to establish a logic T at that site). Fault propagation propagates the fault effect (e.g., stuck at 0) forward by sensitizing a path from a fault site to a scan cell or a primary output. A fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time. Here, the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults.

[0057]

[0054] A popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Cell internal fault models can be derived using transistor-level circuit simulations (analog simulations). This approach can pinpoint the defect location within a cell for various cell internal defects.

[0058]

[0055] During the circuit design and manufacturing process, a manufacturing test screens out chips (dies) containing defects. The test itself, however, does not identify the reason for the unacceptable low or fluctuating yield that may be observed. Physical failure analysis (PF A) can inspect the faulty chip to locate the defect location(s) and to discover the root cause. The process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also referred to as scan diagnosis) is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file). The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses. The layout information of the circuit design may also be employed to further reduce the number of defect suspects.

[0059]

[0056] Diagnosis includes logic diagnosis (sometimes referred to as scan diagnosis) and chain diagnosis. Logic diagnosis may employ a fault dictionary or directly examine the syndrome (i.e., the effect) of the failing chip to determine likely defect locations (defect suspects). The latter approach may include structural pruning (back tracing), fault injection and evaluation (fault simulation for both failing and passing test patterns).

[0060]

[0057] Chain diagnosis determines scan cells that are likely to be defective. Scan elements and related clocking circuitry can take up about 30% of silicon area of an IC chip. It has been reported that scan chain failures account for almost 50% of chip failure in some cases. Chain diagnosis is thus important to guide physical failure analysis and yield learning process. In a chain diagnosis process, two types of test patterns may be used. The first type is called chain patterns. A chain pattern is a pattern used in a process comprising shift-in and shift-out without pulsing capture clocks. The other type is often referred to as scan patterns. A scan pattern is a pattern used in a process comprising shift-in, one or multiple capture clock cycles, and shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, special chain diagnostic patterns generated only for scan chain diagnosis purpose and some special functional patterns. Chain patterns can be used to test the integrity of scan chains and / or determine fault models associated with faulty scan chains while scan patterns can be used to inject certain values to some scan cells for locating defective scan cells.

[0058] The quality of diagnosis can be measured by diagnostic resolution (the number of the real defects vs. the number of the defect suspects). Diagnostic resolution is linked not only to the algorithm used for diagnosis but also to the test patterns used for the manufacturing test (manufacturing test patterns). The quality of diagnosis can also be measured by diagnosis coverage. Diagnosis coverage may be determined in several ways. A simple way is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group cannot be separated or distinguished under a certain condition by a diagnosis technique. To enhance the quality of diagnosis, a diagnostic test pattern generation process may be employed. This process generates test patterns that can increase the number of equivalent fault groups or reduce the average number of faults in the equivalent fault groups.

[0061]

[0059] Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in / out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit.

[0062]

[0060] Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can not only reduce the amount of data stored on the tester but also reduce the test time for a given test data bandwidth.

[0063] Illustrative Operating Environment

[0064]

[0061] Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Fig. 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory 107 may include both a readonly memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0065]

[0062] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 115, a removable magnetic disk drive 117, an optical disk drive 119, or a flash memory card 121. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computer 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0066]

[0063] With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0067]

[0064] It should be appreciated that the computer 101 is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer 101 illustrated in Fig. 1, which include only a subset of the components illustrated in Fig. 1, or which include an alternate combination of components, including components that are not shown in Fig. 1. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0068] Failing Bit Node System Generation Tool

[0069]

[0065] Fig. 2 illustrates an example of a failing bit node system generation tool 200 that may be implemented according to various embodiments of the disclosed technology. As seen in this figure, the failing bit node system generation tool 200 includes a fault simulation unit 210 and a failing bit node creation unit 220. Various implementations of the failing bit node system generation tool 200 may cooperate with (or incorporate) one or more of a fault list updating unit 230, an application tool 240, a fault partition node system conversion unit 250, an input database 205 and an output database 255. The application tool 240 can be a diagnosis tool or a diagnosis coverage prediction tool.

[0070]

[0066] As will be discussed in more detail below, the failing bit node system generation tool 200 can receive, from the input database 205, a circuit design, a plurality of faults, and one or more test patterns. The circuit design has one or more test response output channels. The simulation unit 210 can perform fault simulation for each of the one or more test patterns in a sequence to determine a test response bit at each of observation clock cycles from each of the one or more test response output channels. The sequence is the same as one in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design. The test response bits derived from the fault simulation comprise passing bits and failing bits. The failing bit node creation unit 220 can generate a failing bit node system for the circuit design based on the test response bits. The failing bit node system comprises failing bit nodes and equivalent fault groups. Each of the equivalent fault groups comprises one or more faults in the plurality of faults and is associated with one of the failing bit nodes, creating one new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has at least one failing bit at one of the observation clock cycles but is not separated into two or more new equivalent fault groups based on one or more test response bits at the one of the observation clock cycles, and changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node; creating (N - 1) new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if one of the N new equivalent fault group has no failing bit, associating the N new failing bit nodes with the (N - 1) new equivalent fault group and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node; and creating N new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if each of the N new equivalent fault group has at least one failing bit, associating each of the N new failing bit nodes with one of the N new equivalent fault groups, and removing the association of the existing equivalent fault group with the existing failing bit node.

[0071]

[0067] The failing bit node system generation tool 200 can store information of the failing bit node system in the output database 255. The fault list updating unit 230 can update the plurality of faults by removing, from the plurality of faults, faults of which each becomes the only fault in an equivalent fault group after the new equivalent fault groups are derived. The fault partition node system conversion unit 250 can convert the failing bit node system into a fault partition node system for the circuit design. The converting may comprise: removing failing bit nodes that do not separate an equivalent fault group into two or more groups; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

[0072]

[0068] The application tool 240 as a diagnosis coverage prediction tool can determine a diagnosis coverage value under various constraints based on the failing bit node system. The application tool 240 as a diagnosis tool can perform fault diagnosis based on the failing bit node system.

[0073]

[0069] As previously noted, various examples of the disclosed technology may be implemented by one or more computing systems, such as the computing system illustrated in Fig. 1. Accordingly, one or more of the fault simulation unit 210, the failing bit node creation unit 220, the fault list updating unit 230, the application tool 240, the fault partition node system conversion unit 250 may be implemented by executing programming instructions on one or more processors in one or more computing systems, such as the computing system illustrated in Fig. 1. Correspondingly, some other embodiments of the disclosed technology may be implemented by software instructions, stored on a non-transitory computer-readable medium, for instructing one or more programmable computers / computer systems to perform the functions of one or more of the fault simulation unit 210, the failing bit node creation unit 220, the fault list updating unit 230, the application tool 240, the fault partition node system conversion unit 250. As used herein, the term “non-transitory computer-readable medium” refers to computer-readable medium that are capable of storing data for future retrieval, and not propagating electromagnetic waves. The non-transitory computer-readable medium may be, for example, a magnetic storage device, an optical storage device, or a solid state storage device.

[0074]

[0070] It also should be appreciated that, while the fault simulation unit 210, the failing bit node creation unit 220, the fault list updating unit 230, the application tool 240, the fault partition node system conversion unit 250 are shown as separate units in Fig. 1, a single computer (or a single processor within a master computer) or a single computer system may be used to implement some or all of these units at different times, or components of these units at different times.

[0075]

[0071] With various examples of the disclosed technology, the input database 205 and the output database 255 may be implemented using any suitable computer readable storage device. That is, either of the input database 205 and the output database 255 may be implemented using any combination of computer readable storage devices including, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable storage devices may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, holographic storage devices, or any other non-transitory storage medium that can be used to store desired information. While the input database 205 and the output database 255 are shown as separate units in Fig. 2, a single data storage medium may be used to implement some or all of these databases.

[0076] Failing Bit Node System Generation

[0077]

[0072] Fig. 3 illustrates a flowchart 300 showing a process of failing bit node system generation that may be implemented according to various examples of the disclosed technology. For ease of understanding, methods of failing bit node system generation that may be employed according to various embodiments of the disclosed technology will be described with reference to the failing bit node system generation tool 200 in Fig. 2 and the flow chart 300 illustrated in Fig. 3. It should be appreciated, however, that alternate implementations of a failing bit node system generation tool may be used to perform the methods of failing bit node system generation illustrated by the flow chart 300 according to various embodiments of the disclosed technology. Likewise, the failing bit node system generation tool 200 may be employed to perform other methods of failing bit node system generation according to various embodiments of the disclosed technology.

[0078]

[0073] In operation 310 of the flow chart 300, the failing bit node system generation tool 200 receives, from the input database 205, a circuit design, a plurality of faults, and one or more test patterns. According to some embodiments of the disclosed technology, the plurality of faults may be separated into a number of equivalent fault groups. Faults in an equivalent fault group are faults that cannot be distinguished under a certain condition. The certain condition can be related to a group of test patterns. Equivalent fault groups can be changed with the condition. When test patterns in addition to the group of test patterns are used, for example, some or all of the existing equivalent fault groups may be divided into new equivalent fault groups, resulting in more equivalent fault groups. On the other hand, when some test patterns in the group of test patterns are removed from being considered, some or all of the existing equivalent fault groups may be merged into new equivalent fault groups, resulting in fewer equivalent fault groups.

[0079]

[0074] The received circuit design has one or more test response output channels. Test response output channels, sometimes referred to as output pins, may be coupled to outputs of scan chains in the circuit design. Fig. 4A illustrates an example of test response output channels 400 that are coupled to outputs of scan chains 410. As described previously, the scan chains 410, formed by connecting scan cells in serial, can be used not only to shift in and launch test stimuli but also to capture and shift out test response bits. As also described previously, various test compression techniques are often employed to address challenges related to the continuously increasing volume of test data. Thus, test response output channels may be coupled to outputs of a test response compactor rather than directly to scan chains. Fig. 4B illustrates an example of test response output channels 420 in a test compression environment. In this setup, the test response output channels 420 are coupled to outputs of a test response compactor 430. The test response compactor 430 is configured to compact test responses captured by scan chains 440. The scan chains 440 is configured to load decompressed test patterns from a decompressor 450. The embedded deterministic test (EDT) is one example test compression technique. If this technique is employed, the decompressor 450 comprises a ring generator and an associated phase shifter, and the test response compactor 430 comprises one or more XOR gate networks. In some cases where an on-chip comparator is used to compare captured test response bits with good-machine test response bits, test response output channels may be coupled to outputs of the on-chip comparator.

[0080]

[0075] Referring back to Fig. 3, in operation 320, the fault simulation unit 210 performs fault simulation for each of the one or more test patterns in a sequence to determine a test response bit at each of observation clock cycles from each of the one or more test response output channels. In a typical fault simulation process, a fault is injected into the circuit, and then a test pattern is applied to the fault-injected circuit by launching bits of the test pattern from scan cells to functional circuitry of the circuit. Test response bits 1 generated by the functional circuitry of the circuit are captured by the scan cells and are shifted out either directly from the scan chains or from a compactor after being compacted. The test response bits shifted out of the test response output channels are referred to as observed test response bits, or simply test response bits. The test response bits may also be ones that are derived by comprising observed test response bits with good-machine test response bits The test response bits can comprise passing bits (the same as the corresponding good-machine bits) and failing bits (different from the corresponding good-machine bits). During the shift-out operation, the test response bits come out of each test response output channel one bit per observation clock cycle.

[0081]

[0076] As noted previously, test patterns are shifted into scan chains and applied to the circuit one at a time. After test response bits for the current test pattern are captured, they are being shifted out while the next test pattern is being shifted in. As such, test patterns are applied to the circuit in a particular sequence during scan testing. The sequence in which the one or more test patterns is used for the fault simulation in the operation 320 is the same as the one in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design.

[0082]

[0077] In operation 330, the failing bit node creation unit 220 generates a failing bit node system for the circuit design based on the test response bits. The failing bit node system comprises failing bit nodes and equivalent fault groups. Each of the equivalent fault groups comprises one or more faults in the plurality of faults. Each of the equivalent fault groups is associated with one of the failing bit nodes. Here, a root node may also be referred to as a failing bit node. When the circuit design has more than one test response output channels, the failing bit node system can be a failing bit node system for the circuit design (or multiple test response output channels) or a failing bit node system for each of the test response output channels. The failing bit node systems generated for individual test response output channels can be combined into the failing bit node system for the circuit design.

[0078] The operation 330 can comprise a series of suboperations for creating new failing bit nodes and for associating new equivalent fault groups with the new failing bit nodes and the existing failing bit nodes. Fig. 5 illustrates a flowchart 500 showing an example process for creating new failing bit nodes for a failing bit node system for a circuit design that may be implemented according to various examples of the disclosed technology.

[0083]

[0079] In operation 510, the failing bit node creation unit 220 determines whether an existing equivalent fault group has a failing bit at the current observation clock cycle. If the answer is yes, the flow chart 500 will proceed to an operation 520. Otherwise, the flow chart 500 will proceed to an operation 570.

[0084]

[0080] In operation 520, the failing bit node creation unit 220 determines whether the existing equivalent fault group can be separated into N (N > 1) equivalent fault groups based on one or more test response bits at the current observation clock cycle. If two faults in the existing equivalent fault group have different test response bits, then they can be placed into two new equivalent fault groups. This shows a major difference between fault simulation for circuit testing and fault simulation for diagnosis. The former focuses on whether a fault is detectable by comparing test response bits with good-machine test response bits, while the latter focuses on whether faults can be separated by comparing test response bits among themselves (these test response bits may be ones that are derived by comprising with good-machine test response bits). Another difference involves updating a list of faults for fault simulation. For circuit testing purposes, a fault that can be detected by one or more test patterns may be removed from the list of faults and would not be involved in further fault simulation for other test patterns. For diagnosis purposes, on the other hand, a fault that is alone in an equivalent fault group may be removed from the list of faults and would not be involved in further fault simulation for other test patterns. This property may be employed to speed up the process of failing bit node system generation as will be discussed in more detail below.

[0081] If the failing bit node creation unit 220 determines in the operation 520 that the existing equivalent fault group can be separated into N(N> 1) new equivalent fault groups based on the one or more test response bits at the current observation clock cycle, the flow chart 500 will proceed to an operation 530. Otherwise, the flow chart 500 will proceed to an operation 560. In operation 560, the failing bit node creation unit 220 creates a new failing bit node for an existing failing bit node associated with the existing equivalent fault group and changes the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node.

[0085]

[0082] In operation 530, the failing bit node creation unit 220 determines whether there is a new equivalent fault group in the N new equivalent fault groups that has only passing bits at the current observation clock cycle. If the answer is yes, the flow chart 500 will proceed to an operation 540. Otherwise, the flow chart 500 will proceed to an operation 550. In operation 540, the failing bit node creation unit 220 creates (N - 1) new failing bit nodes for an existing failing bit node associated with the existing equivalent fault group, associates the N new equivalent fault groups with the (TV - 1) new failing bit nodes and the existing failing bit node, respectively, and removes the association of the existing equivalent fault group with the existing failing bit node.

[0086]

[0083] In operation 550, which can be reached if each of the N new equivalent fault groups has at least one failing bit determined in the operation 530, the failing bit node creation unit 220 creates N new failing bit nodes for an existing failing bit node associated with the existing equivalent fault group, associates each of the N new equivalent fault groups with one of the N new failing bit nodes, and removes the association of the existing equivalent fault group with the existing failing bit node.

[0087]

[0084] After either the operation 540, or the operation 550, or the operation 560, the flow chart 500 proceeds to the operation 570. In operation 570, which can also be reached from the operation 510, the failing bit node creation unit 220 moves to the next observation clock cycle at which the test response bits include at least a failing bit. The operations 510-570 can be repeated for each of the new equivalent fault groups by treating it as an existing equivalent fault groups unless a new equivalent fault group has only one fault. The reason to skip observation clock cycles at which the test response bits include no failing bit is because that faults cannot be separated based on the test response bits that are all passing bits. The process illustrated by the flow chart 500 may be terminated when the test response bits for all of the test patterns (i.e., for all of the observation clock cycles) are analyzed or each fault in the existing equivalent fault group is placed alone in a new equivalent fault group.

[0088]

[0085] It should be noted that, for each existing equivalent fault group, the process illustrated by the flow chart 500 can be performed independently. Therefore, the failing bit node creation unit 220 can perform the process illustrated by the flow chart 500 for multiple existing failing bit nodes in parallel, which can significantly increase the overall processing speed.

[0089]

[0086] Fig. 6A uses a diagram 600 as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for a circuit design corresponding to the operation 540 shown in Fig. 5. In the diagram 600, an existing failing bit node 610 is initially associated with an equivalent fault group 630. Based on one or more test response bits 670 at an observation clock cycle, the equivalent fault group 630 is divided into (N - 1) new equivalent fault groups 640 and a new equivalent fault group 650. One of the new equivalent fault groups 640-650 has only passing bits at the observation clock cycle. Accordingly, (N - 1) new failing bit nodes 620 are created. Each of the (N - 1) new equivalent fault groups 640 is associated with one of the (N - 1) new failing bit nodes 620. The new equivalent fault group 650 is associated with the existing failing bit node 610, replacing the equivalent fault group 630. According to various embodiments of the disclosed technology, the new equivalent fault group 650 can be the one that has the number of failing bits smaller than any of the new equivalent fault groups 640. Each failing bit node, either existing or new, may further be associated with failing bit information, observation clock cycle information, or both, as shown as “Clk. cycle info. / Failing bit info.” 660 in the figure. The process illustrated in Fig. 6 can be repeated to create further new failing bit nodes for the newly-created failing bit nodes.

[0090]

[0087] Fig. 6B uses a diagram 605 as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for a circuit design corresponding to the operation 550 shown in Fig. 5. In the diagram 605, an existing failing bit node 615 is initially associated with an equivalent fault group 635. Based on one or more test response bits 675 at an observation clock cycle, the equivalent fault group 635 is divided into N new equivalent fault groups 645. Each of the N new equivalent fault groups has at least one failing bit. Accordingly, N new failing bit nodes 625 are created. Each of the N new equivalent fault groups 645 is associated with one of the N new failing bit nodes 625. The association of the existing failing bit node 615 with the existing equivalent fault group 635 is removed. Each failing bit node, either existing or new, may further be associated with failing bit information, observation clock cycle information, or both, as shown as “Clk. cycle info. / Failing bit info.” 665 in the figure. The process illustrated in Fig. 6B can be repeated to create further new failing bit nodes for the newly-created failing bit nodes.

[0091]

[0088] Fig. 6C uses a diagram 607 as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for a circuit design corresponding to the operation 560 shown in Fig. 5. In the diagram 607, an existing failing bit node 617 is initially associated with an equivalent fault group 637. One or more test response bits 677 at an observation clock cycle have at least one failing bit, but the equivalent fault group 637 cannot be not divided into two or more new equivalent fault groups. Accordingly, a new failing bit node 627 is created, the association of the existing equivalent fault group 637 is changed from with the existing failing bit node 617 to with the new failing bit node 627. Each failing bit node, either existing or new, may further be associated with failing bit information, observation clock cycle information, or both, as shown as “Clk. cycle info. / Failing bit info.” 667 in the figure. The process illustrated in Fig. 6C can be repeated to create further new failing bit nodes for the newly-created failing bit nodes.

[0089] The term “failing bit node system” is a high-level description of a set of related equivalent fault groups created based on test response bits derived by fault simulation up to a certain observation clock cycle or a test pattern. Accordingly, a process of the failing bit node system generation can be used to derive equivalent fault groups under a particular condition for a particular circuit design. Moreover, a generated failing bit node system can show the family relationship between the created equivalent fault groups. Some faults are separated from each other at an early stage while others are separated from each other at a late stage. As described previously, the failing bit node system can also include other information such as the failing bit information, the observation clock cycle information, or both. Combining the family relationship information with some additional information, the failing bit node system can be shrunk or grown further to a new failing bit node system that takes account of some constraint such as the tester storage limit and the number of test patterns applied without redoing the generation process. This is useful for predicting diagnosis coverage values under various constraints. As noted above, a failing bit node may further be associated with failing bit information, observation clock cycle information, or both. The failing bit information may include cumulative failing bit counts for a particular failing bit node. This can allow generation of a new failing bit node system for predicting the diagnosis coverage under a constraint associated with a tester. For example, a tester usually only store failing bits and its failing bit buffer has a limited size. To generate a new failing bit node system meeting the constraint, the failing bit nodes having cumulated failing bit counts above a threshold can be merged recursively with corresponding parent failing bit nodes. Using the above process, a profile of diagnosis coverage vs failing bit limit can be derived. Fig. 7 illustrates an example profile of diagnosis coverage vs per-pin failing bit limit.

[0092]

[0090] The observation clock cycle information with which the failing bit nodes may be associated can show observation clock cycles at which the failing bit nodes are created. This can allow generation of a new failing bit node system for predicting the diagnosis coverage under a constraint associated with a threshold observation clock cycle or a subgroup of test patterns in the one or more test patterns. To generate the new failing bit node system, the failing bit nodes with which observation clock cycles associated are greater than the threshold observation clock cycle or a largest observation clock cycle for the subgroup of test patterns can be merged recursively with corresponding parent failing bit nodes. Using the above process, a profile of diagnosis coverage vs number of test patterns can be derived.

[0093]

[0091] As noted previously, a failing bit node system can be generated for each of the one or more test response output channels. Fig. 8A uses a diagram 800 as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for one test response output channel when existing equivalent fault groups are divided into new equivalent fault groups that may be implemented according to various examples of the disclosed technology. In the diagram 800, an existing failing bit node 810 is initially associated with an equivalent fault group 830. A single test response output channel can output only one test response bit per observation clock cycle. Only a failing test response bit may separate faults in an existing equivalent fault group into two new equivalent fault groups. In Fig. 8 A, a single failing test response bit 870 at an observation clock cycle divides the equivalent fault group 830 is divided into two new equivalent fault groups 840 and 850. Accordingly, a new failing bit node 820 is created. The new equivalent fault group 840 is associated with the new failing bit node 820 and the new equivalent fault group 850 is associated with the existing failing bit node 810, replacing the equivalent fault group 830. This can be repeated to create further new failing bit nodes for the newly - created failing bit nodes. Here, the new equivalent fault group 840 associated with the existing failing bit node 810 is the one that has a passing bit according to some embodiments of the disclosed technology. Similar to Figs. 6A, 6B, 6C, failing bit information and observation clock cycle information 860 can be associated with the existing failing bit node 810 and the new failing bit node 820.

[0094]

[0092] Fig. 8B uses a diagram 805 as an example to illustrate a process for creating new failing bit nodes for a failing bit node system for one test response output channel when existing equivalent fault groups cannot be divided into new equivalent fault groups that may be implemented according to various examples of the disclosed technology. In the diagram 805, an existing failing bit node 815 is initially associated with an equivalent fault group 835. A single failing test response bit 875 at an observation clock cycle cannot not divide the equivalent fault group 835 is divided into two new equivalent fault groups. Due to the failing test response bit 875, a new failing bit node 825 is created. The existing equivalent fault group 845 changes the association from with the existing failing bit node 815 to with the new failing bit node 825. This can be repeated to create further new failing bit nodes for the newly-created failing bit nodes. Similar to Figs. 6A, 6B, 6C, failing bit information and observation clock cycle information 865 can be associated with the existing failing bit node 815 and the new failing bit node 825.

[0095]

[0093] It should be noted that the equivalent fault groups derived for a test response output channel may not be the final equivalent fault groups if the circuit design has more than one test response output channel. The final equivalent fault groups can be obtained by comparing faults in an equivalent fault group in one failing bit node system for one test response output channel with faults in other equivalent fault groups in other failing bit node systems for other test response output channels. This may further separate faults in the equivalent fault groups derived for individual test response output channels.

[0096]

[0094] Referring back to Fig. 3, it should be noted that the operations 320 and 330 do not need to be performed in serial for all of the one or more test patterns. In another word, the fault simulation unit 210 does not need to perform fault simulation for all of the one or more test patterns before the failing bit node creation unit 220 starts to generate the failing bit node system. The two operations may be performed “concurrently.” Fig. 9 illustrates a flow chart 900 showing a process of failing bit node system generation that may be implemented according to various examples of the disclosed technology. In operation 910, the failing bit node system generation tool 200 selects a sub-group of test patterns in an original group of test patterns. In operation 920, the fault simulation unit 210 performs fault simulation of a plurality of faults for each test pattern in the sub-group of test patterns to determine a test response bit at each of observation clock cycles from each of one or more test response output channels. In operation 930, the failing bit node creation unit 220 generates a failing bit node system if none exists or expands the existing failing bit node system for the circuit design based on test response bits derived from the fault simulation. In operation 940, the fault list updating unit 230 updates the plurality of faults by removing, from the plurality of faults, faults of which each becomes an only fault in an equivalent fault group and then repeat the above operations by selecting a different sub-group of test patterns following a particular sequence in the operation 910. The process can be terminated when either no fault is left in the plurality of faults or no test pattern is not used in the original group of test patterns.

[0097]

[0095] By updating the fault list after each iteration, the process illustrated by the flow chart 900 allows the number of faults for fault simulation for subsequent test patterns to be reduced and thus greatly speed up the process for generating a failing bit node system for a circuit design. As noted previously, another way to speed up the process that may be employed according to various examples of the disclosed technology is to perform preliminary fault simulation for some test patterns at the beginning. Based on the results of preliminary fault simulation, the plurality of faults can be divided into multiple equivalent fault groups. In this operation, the formation of these equivalent fault groups over observation clock cycles or test patterns may not need to be not tracked. By starting with equivalent fault groups, test response bits for a fault are compared only with those for faults within the same equivalent fault group, leading to significant savings of computation time. Moreover, this allows the computation for each of the equivalent fault groups to be operated in parallel, further speeding up the process.

[0098]

[0096] Referring back to Fig. 3, in operation 340, the failing bit node system generation tool 200 stores information of the failing bit node system in the output database 255. Optionally, in operation 350, the application tool 240, if it functions as a diagnosis coverage prediction tool, determines a diagnosis coverage value under various constraints based on the failing bit node system. The application tool 240 can use the observation clock cycle information or the failing bit information for this purpose. For example, a tester may not record test response bits when the observation clock cycle is larger than an observation clock cycle limit. The application tool 240 can generate a new failing bit node system by merging failing bit nodes with which observation clock cycles associated are greater than the observation clock cycle limit recursively with corresponding parent failing bit nodes. The diagnosis coverage value can be readily determined using the new failing bit node system.

[0099]

[0097] Each test pattern typically has the same number of test cycles, so converting from a cyclebased limit to a pattern-based limit is straightforward. The application tool 240 can generate a new failing bit node system by merging failing bit nodes with which observation clock cycles associated are greater than the largest observation clock cycle for a subgroup of test patterns. This can allow the application tool 240 to determine test pattern count limit impact on diagnosis coverage. In another example, a tester may have a limited size of a failing bit buffer. The application tool 240 can generate a new failing bit node system by merging failing bit nodes having cumulated failing bit counts above a threshold associated with the limited size recursively with corresponding parent failing bit nodes. The limited size may be a per-pin failing buffer limit or an all-pin failing buffer limit. For the former, a failing bit node system for each pin can be generated; and for the latter, a failing bit node system for the circuit design can be created.

[0100]

[0098] Optionally, in operation 360, the application tool 240, if it functions as a diagnosis tool, performs dictionary-like diagnosis based on the failing bit node system. For example, if the failing bit node system for each of the test response output channels is available, the application tool 240 may match the failing bits obtained from the tester from the first failing bit node downward to trace the failing bit node systems to identify the matching equivalent fault group(s).

[0101]

[0099] Optionally, in operation 370, the fault partition node system conversion unit 250 can convert the failing bit node system into a fault partition node system for the circuit design. In the process of failing bit node system generation, a large number of test response bits observed do not contribute to diagnosis. Even a large number of failing bits cannot distinguish known faults. Therefore, the fault partition node system conversion unit 250 may remove failing bit nodes that do not separate an equivalent fault group into two or more groups and move equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively. The moving comprises merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group. The resultant system is referred to as a fault partition node system. The fault partition node system comprises fault partition nodes and equivalent fault groups. Each of the fault partition nodes is associated with one of the equivalent fault groups.

[0102]

[0100] A failing bit node system may also be referred to as an asymmetric binary / multiple decision tree, while a fault partition node system may also be referred to as an asymmetric partition tree (APT). An asymmetric partition tree can be related to a binary / multiple decision tree, a reduced binary / multiple decision tree, and an asymmetric binary / multiple decision tree. A binary / multiple decision tree is straightforward to be generated based on fault simulation. Generating a binary / multiple decision tree, however, take an exceptionally long time and a vast memory. A binary / multiple decision tree can be converted into a reduced binary / multiple decision tree with a smaller size, and a reduced binary / multiple decision tree can be converted into an even smaller asymmetric binary / multiple decision tree. An asymmetric binary / multiple decision tree, as discussed above, can be converted into an asymmetric partition tree with a still smaller size.

[0103]

[0101] To show the above-mentioned conversions, a simple circuit design 1000 illustrated in Fig. 10 is used. The circuit design 1000 has two scan chains coupled to two test response output channels, Pin A (1010) and Pin B (1020). Each of the scan chains has three scan cells. As such, each test pattern has only three observation clock cycles, corresponding to three observation points (bits). Assume that the circuit design 1000 has only ten faults with one test pattern. The test response bits for the ten faults are shown in a table 1005. In the table 1005, a value of “1” indicates that the fault produces a failing bit at that observation point, and a value of “0” indicates that the fault does not make a failing bit at that observation point, which can be referred to as a passing bit. The left bit of a set of test response bits in the table 1005 corresponds to the first observation clock cycle (CO), the middle bit corresponds to the second observation clock cycle (Cl), and the right bit corresponds to the second observation clock cycle (C2). If all test response bits of a test pattern have values 000 of a fault, this test pattern is called a passing test pattern for this fault. Otherwise, this pattern is called a failing test pattern for this fault.

[0104]

[0102] Fig. 11 A illustrates a binary decision tree (BDT) for Pin A of the design 1000 shown in Fig. 10. In the figure, each node has two children. The left child is a failing bit node, and the right child is a passing bit node. For a specific fault, if it has a failing bit at the observation point (observation clock cycle), it goes to the left child node; otherwise, it goes to the right child node. Each fault starts from the top and follows its failing bit information of Pin A to reach a leaf node of the binary decision tree. All faults that reach the same leaf node are equivalent. Six equivalent fault groups in total are derived as shown in the figure: {F0}, {Fl, F2}, {F3, F9}, {F4, F5}, {F6}, and {F7, F8}. Within them, F0 and F6 are in an equivalent fault group alone, referred to as unique faults. Fig. 1 IB illustrates a binary decision tree (BDT) for Pin B of the design 1000 shown in Fig. 10. Five equivalent fault groups in total are derived as shown in the figure: {F0, F3}, {Fl, F2}, {F6}, {F4, F5, F7}, and {F8, F9}. Here, F6 is the only unique fault. By combining them together, the final equivalent fault groups for the circuit design 1000 shown in Fig. 10 after three observation clock cycles are: {F0}, {Fl, F2}, {F3}, {F4, F5}, {F6}, {F7}, {F8}, and {F9}. Thus, a simple diagnose coverage value can be calculated as 8 equivalent fault groups / 10 faults = 80%. In Figs. 11 A and 1 IB, C2 means the second observation clock cycle.

[0105]

[0103] Another way to derive the final equivalent fault groups is to generate a multiple decision tree directly for the circuit design 1000. In this tree, each observation clock cycle has multiple observation points from all pins and thus multiple failing conditions. Fig. 12 illustrates a multiple decision tree for the design 1000 shown in Fig. 10. For each observation clock cycle, it has four decisions: three failing conditions (“11”, “10”, “01”) and one passing condition (“00”). For example, fault group {F0} has three failing observation clock cycles: CO (“11”), Cl (“10”), and C2 (“11”), and fault group {F3} has two failing observation clock cycles and one passing observation clock cycle: CO (“11”), Cl (“00”), and C2 (“11”). The final equivalent fault groups are: {F0}, {Fl, F2}, {F3}, {F4, F5}, {F6}, {F7}, {F8}, and {F9}, which are the same as those derived by combining the equivalent fault groups derived for each test response output channel.

[0106]

[0104] A reduced binary decision tree can be obtained by removing nodes that are not visited by any faults in a binary decision tree. Removing them does not impact diagnosis coverage calculation. Fig. 15A illustrates a reduced binary decision tree (RBDT) for Pin A of the design 1000 shown in Fig. 10. Fig. 15B illustrates a reduced binary decision tree (RBDT) for Pin B of the design 1000 shown in Fig. 10. Again, in Figs. 15A and 15B, C2 means the second observation clock cycle. A reduction like the one from binary decision trees to reduced binary decision trees can be performed on multiple decision trees to create reduced multiple decision trees.

[0107]

[0105] Binary decision trees are symmetric, but the failing bit information is asymmetric. Most faults have much fewer failing bits than passing bits in real circuit designs. As such, most nodes in the reduced binary decision tree are used for passing bits. A reduced binary decision tree may be further condensed by removing these passing bit nodes and by moving the equivalent fault information of (equivalent fault groups associated with) all passing bit nodes to their parents recursively. The resultant systems are referred to as asymmetric binary decision trees (ABDT) or failing bit node systems. The moving action is needed because passing bit nodes have some information needed in a merging process. When a node does not survive due to a constraint, its sibling does not survive either. Fig. 15A illustrates an asymmetric binary decision tree (ABDT) for Pin A of the design 1000 shown in Fig. 10. Fig. 15B illustrates an asymmetric binary decision tree (ABDT) for Pin B of the design 1000 shown in Fig. 10.

[0106] Unlike the binary decision trees shown in Figs. 11 A, 1 IB and the reduced binary decision trees shown in Figs. 15 A, 15B, each node in the asymmetric binary decision trees in Figs. 15 A, 15B is shown with the number of accumulative failing bits next to the observation clock cycle. This accumulative failing bit information can also be added to the other types of trees. Another difference is that the root node in the asymmetric binary decision trees is not associated with the first observation clock cycle “CO”, and the observation clock cycles are moved to match the failing bit for all nodes.

[0108]

[0107] The asymmetric binary decision tree has a smaller tree size than but can carry the same information as the corresponding reduced binary decision tree. For example, in Fig. 15A, fault F0 has three failing bits at C2, Cl, and CO by tracing backward from its fault group node to the root. Fault F6, on the other hand, has one failing bit at C2 according to the asymmetric binary decision tree in Fig. 15 A. This also means it has passing bits at Cl and CO. In other words, if all the failing bit locations are known, all the passing bit locations can be derived easily.

[0109]

[0108] A reduction like the one from reduced binary decision trees to asymmetric binary decision trees can be performed on reduced multiple decision trees to create asymmetric multiple decision trees.

[0110]

[0109] In modern circuit designs, many scan cells provide both test input points for control and test response points for observation. It has been shown that not all scan cells are used for detecting target faults. The test input points needed to detect faults are called stimulus care bits. Modern test compression techniques explore this to reduce test costs significantly. Similarly, not all scan cell observation points are needed to distinguish faults to improve diagnosis resolution, which can be employed to remove some failing bit nodes of asymmetric binary decision trees. The failing bit nodes that do not partition any fault groups have no impact on diagnosis coverage calculation. Thus, only failing bit nodes that can partition an equivalent fault group into new equivalent fault groups need to be kept. These failing bit nodes are referred to as fault partition nodes. The equivalent fault information of (the equivalent fault group associated with) each non-partition failing bit node can be moved to its parent. The resultant systems are referred to as asymmetric partition binary decision trees (APBDT or APT) or fault partition node systems. Fig. 15A illustrates an asymmetric partition binary decision tree (APT) for Pin A of the design 1000 shown in Fig. 10. Fig. 15B illustrates an asymmetric partition binary decision tree (APT) for Pin B of the design 1000 shown in Fig. 10. For Pin B, the asymmetric partition binary decision tree (APT) is the same as the asymmetric binary decision trees (ABDT).

[0111] [HO] A reduction like the one from asymmetric binary decision trees to asymmetric partition binary decision trees can be performed on asymmetric multiple decision trees to create asymmetric partition multiple decision trees.

[0112] [Ill] Assume that a tester has an observation clock cycle limit: all nodes with an observation clock cycle larger than Cl will not survive. The new asymmetric partition binary decision tree (APT) (fault partition node system) can be derived by shrinking the original asymmetric partition binary decision tree (APT) (fault partition node system): removing the nodes with an observation clock cycle larger than Cl and move the equivalent fault information of these nodes to their parents recursively. Fig. 16A illustrates an asymmetric partition binary decision tree (APT) for Pin A of the design 1000 shown in Fig. 10 under the observation clock cycle limit of Cl. As shown in the figure, the fault partition nodes 1610 and 1640, associated with an observation clock cycle larger than C2, are removed. The equivalent fault groups associated with these two fault partition nodes are moved up to merge with the equivalent fault groups associated with their parent fault partition nodes 1620 and 1650, respectively. Here the root note 1650 is also referred to as a fault partition node. If the observation clock cycle limit is CO, the resultant equivalent fault group will be moved up one more level to be merged with the equivalent fault group associated with the fault partition node 1630. This shows how the equivalent fault is moved recursively. Fig. 16B illustrates an asymmetric partition binary decision tree (APT) for Pin B of the design 1000 shown in Fig. 10 under the observation clock cycle limit of Cl. For this pin, only the fault partition node 1660 is removed, and its equivalent fault information is moved up and merged with the equivalent fault information associated with its parent fault partition node 1670.

[0113]

[0112] Figs 16A, 16B illustrates a new asymmetric partition binary decision tree (APT) (fault partition node system) can be derived by shrinking an original asymmetric partition binary decision tree (APT) (fault partition node system). A process with minor revisions can be used to shrink an original asymmetric binary decision tree (ABDT) (failing bit node system) into a new asymmetric binary decision tree (ABDT) (failing bit node system).

[0114]

[0113] An experiment is conducted for an actual circuit design, which is a core embedded in a circuit, to demonstrate the benefits of the disclosed technology. This core has no primary input / output pins (channels) and has 27019 scan cells in 58 chains with 2 EDT compactor output channels. It has 498 observation clock cycles per test patterns. This core design has 1366 test patterns for manufacture testing. The total number of observation bits is 1,360,536 (680,268 bits per EDT channel). For fault simulation for diagnosis, there are 564,646 logic faults and 54,038 chain faults. Logic faults include all stuck-at faults. Chain faults are stuck-at faults with two fault types (stuck-at-0 and stuck-at- 1) at the output of each scan cell. The total number of failing bits from these logic faults is 180,043,133 (average: 0.25 bits per fault per test pattern). The total number of failing bits from these chain faults is 17,195,002,600 (average, 233 bits per fault per pattern).

[0115]

[0114] Fig. 17 illustrates a table comparing between the sizes of the binary decision trees (BDTs), the reduced binary decision trees (RBDTs), the asymmetric binary decision trees (ABDTs), and the asymmetric partition binary decision trees (APTs) for the above real circuit design. The BDT per pin has a node count of about 6.15xlO205339, a huge decimal number with 205,340 digits. It will take an exceptionally long time and a vast memory to build the BDT tree. With 564,646 logic faults, the RBDT of Pin 1 derived after removing the unused nodes from the BDT has 133,672,202,801 nodes, and the RBDT of Pin 2 has 104,292,284,131 nodes. With 54038 chain faults, the RBDT of Pin 1 has 23,021,634,209 nodes, and the RBDT of Pin 2 has 18,647,396,056 nodes. Obviously, these RBDT trees are still too large to build.

[0116]

[0115] After removing the passing bit nodes from RBDT, with 564,646 logic faults, the ABDT of Pin 1 has 8,344,743 nodes (16,018X reduction), and the ABDT of Pin 2 has 8,091,510 nodes (12, 889X reduction). With 54038 chain faults, the ABDT of Pin 1 has 969,225,681 nodes (23X reduction), and the ABDT of Pin 2 has 1,323,345,661 nodes (14X reduction). The ABDT trees are still too big for chain diagnosis simulation applications, even after removing all passing bit nodes.

[0117]

[0116] By keeping only fault partition nodes, the reduction is over 25K for chain faults between APT and ABDT and is over 600K for either logic faults or chain faults between APT and RBDT. The reduction between APT and ABDT indicates that the number of diagnosis care bits is much smaller than the number of failing bits.

[0118] Conclusion

[0119]

[0117] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

What is claimed is:

1. A method, executed by at least one processor of a computer, comprising: receiving a circuit design, a plurality of faults, and one or more test patterns, the circuit design comprising one or more test response output channels; performing fault simulation for each of the one or more test patterns in a sequence to determine a test response bit at each of observation clock cycles from each of the one or more test response output channels, the sequence being the same as a sequence in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design, test response bits derived from the fault simulation comprising passing bits and failing bits; generating a failing bit node system for the circuit design based on the test response bits, the failing bit node system comprising failing bit nodes and equivalent fault groups, each of the equivalent fault groups comprising one or more faults in the plurality of faults and being associated with one of the failing bit nodes, the generating comprising: creating one new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has at least one failing bit at one of the observation clock cycles but is not separated into two or more new equivalent fault groups based on one or more test response bits at the one of the observation clock cycles, and changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node, creating (N - 1) new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of theobservation clock cycles and if one of the N new equivalent fault group has no failing bit, associating the N new equivalent fault groups with the (N - 1) new failing bit nodes and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node, and creating N new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if each of the N new equivalent fault groups has at least one failing bit, associating each of the N new failing bit nodes with one of the N new equivalent fault groups, and removing the association of the existing equivalent fault group with the existing failing bit node; and storing information of the failing bit node system.

2. The method recited in claim 1 , wherein the one or more test patterns are a sub-group of test patterns in an original group of test patterns, and wherein the method further comprises: updating the plurality of faults by removing, from the plurality of faults, faults of which each becomes a fault in an equivalent fault group alone; repeating the performing and the generating for a next sub-group of test patterns in the original group of test patterns to expand the failing bit node system; and iterating the updating and the repeating until all test patterns in the original group of test patterns are used or no fault is left in the plurality of faults, the sequence of test patternssimulated being the same as a sequence in which the original group of test patterns would be used to test the circuit.

3. The method recited in claim 1, wherein a failing bit node in the failing bit node system is further associated with failing bit information, observation clock cycle information, or both.

4. The method recited in claim 1, wherein the failing bit node system is generated for each of the one or more test response output channels, a number of failing bit node systems generated being equal to a number of the one or more test response output channels, wherein N = 2 and the generating comprising: creating a new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has a failing bit at one of the observation clock cycles; if the failing bit does not separate the existing equivalent fault group into two new equivalent fault groups, changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node; and if the failing bit separates the existing equivalent fault group into two new equivalent fault groups, associating the two new equivalent fault groups with the new failing bit node and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node.

5. The method recited in claim 1, wherein the plurality of faults are divided into preliminary equivalent fault groups.

6. The method recited in claim 5, wherein the equivalent fault groups are derived based on results of preliminary fault simulation for some test patterns.

7. The method recited in claim 1, further comprising: determining a diagnosis coverage value based on the failing bit node system and a constraint associated with a limited size of a failing bit buffer of a tester.

8. The method recited in claim 7, wherein the determining comprises: removing failing bit nodes having cumulated failing bit counts above a threshold associated with the limited size; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

9. The method recited in claim 1, further comprising:determining a diagnosis coverage value based on the failing bit node system and a constraint associated with an observation clock cycle limit or a subgroup of test patterns in the one or more test patterns.

10. The method recited in claim 9, wherein the determining comprises: removing failing bit nodes with which observation clock cycles associated are greater than the observation clock cycle limit or a largest observation clock cycle for the subgroup of test patterns; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

11. The method recited in claim 1, further comprising: converting the failing bit node system into a fault partition node system for the circuit design.

12. The method recited in claim 11, wherein the converting comprises: removing failing bit nodes that do not separate an equivalent fault group into two or more groups; andmoving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

13. The method recited in claim 1, further comprising: performing dictionary-like diagnosis by mapping test response bits obtained from a tester to the failing bit node system.

14. One or more computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: receiving a circuit design, a plurality of faults, and one or more test patterns, the circuit design comprising one or more test response output channels; performing fault simulation for each of the one or more test patterns in a sequence to determine a test response bit at each of observation clock cycles from each of the one or more test response output channels, the sequence being the same as a sequence in which the one or more test patterns would be used to test a circuit fabricated according to the circuit design, test response bits derived from the fault simulation comprising passing bits and failing bits; generating a failing bit node system for the circuit design based on the test response bits, the failing bit node system comprising failing bit nodes and equivalent fault groups, each of theequivalent fault groups comprising one or more faults in the plurality of faults and being associated with one of the failing bit nodes, the generating comprising: creating one new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has at least one failing bit at one of the observation clock cycles but is not separated into two or more new equivalent fault groups based on one or more test response bits at the one of the observation clock cycles, and changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node, creating (N - 1) new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if one of the N new equivalent fault group has no failing bit, associating the N new equivalent fault groups with the (N - 1) new failing bit nodes and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node, and creating N new failing bit nodes for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node is separated into N new equivalent fault groups based on one or more test response bits at one of the observation clock cycles and if each of the N new equivalent fault groups has at least one failing bit, associating each of the N new failing bit nodes with one of the N new equivalent fault groups, and removing the association of the existing equivalent fault group with the existing failing bit node; andstoring information of the failing bit node system.

15. The one or more computer-readable media recited in claim 14, wherein the one or more test patterns are a sub-group of test patterns in an original group of test patterns, and wherein the method further comprises: updating the plurality of faults by removing, from the plurality of faults, faults of which each becomes a fault in an equivalent fault group alone; repeating the performing and the generating for a next sub-group of test patterns in the original group of test patterns to expand the failing bit node system; and iterating the updating and the repeating until all test patterns in the original group of test patterns are used or no fault is left in the plurality of faults, the sequence of test patterns simulated being the same as a sequence in which the original group of test patterns would be used to test the circuit.

16. The one or more computer-readable media recited in claim 14, wherein a failing bit node in the failing bit node system is further associated with failing bit information, observation clock cycle information, or both.

17. The one or more computer-readable media recited in claim 14, wherein the failing bit node system is generated for each of the one or more test response output channels, a number of failing bit node systems generated being equal to a number of the one or more test response output channels, wherein N= 2 and the generating comprising:creating a new failing bit node for an existing failing bit node if an existing equivalent fault group associated with the existing failing bit node has a failing bit at one of the observation clock cycles; if the failing bit does not separate the existing equivalent fault group into two new equivalent fault groups, changing the association of the existing equivalent fault group from with the existing failing bit node to with the new failing bit node; and if the failing bit separates the existing equivalent fault group into two new equivalent fault groups, associating the two new equivalent fault groups with the new failing bit node and the existing failing bit node, respectively, and removing the association of the existing equivalent fault group with the existing failing bit node.

18. The one or more computer-readable media recited in claim 14, wherein the plurality of faults are divided into preliminary equivalent fault groups.

19. The one or more non-transitory computer-readable media recited in claim 18, wherein the equivalent fault groups are derived based on results of preliminary fault simulation for some test patterns.

20. The one or more non-transitory computer-readable media recited in claim 14, wherein the method further comprises: determining a diagnosis coverage value based on the failing bit node system and a constraint associated with a limited size of a failing bit buffer of a tester.

21. The one or more non-transitory computer-readable media recited in claim 20, wherein the determining comprises: removing failing bit nodes having cumulated failing bit counts above a threshold associated with the limited size; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

22. The one or more non-transitory computer-readable media recited in claim 14, wherein the method further comprises: determining a diagnosis coverage value based on the failing bit node system and a constraint associated with an observation clock cycle limit or a subgroup of test patterns in the one or more test patterns.

23. The one or more non-transitory computer-readable media recited in claim 22, wherein the determining comprises: removing failing bit nodes with which observation clock cycles associated are greater than the observation clock cycle limit or a largest observation clock cycle for the subgroup of test patterns; andmoving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

24. The one or more non-transitory computer-readable media recited in claim 14, wherein the method further comprises: converting the failing bit node system into a fault partition node system for the circuit design.

25. The one or more non-transitory computer-readable media recited in claim 24, wherein the converting comprises: removing failing bit nodes that do not separate an equivalent fault group into two or more groups; and moving equivalent fault groups associated with the removed failing bit nodes to corresponding parent failing bit nodes recursively, the moving comprising merging equivalent fault groups if a parent failing bit node is associated with an equivalent fault group and associating with a parent failing bit node if the parent failing bit node is not associated with an equivalent fault group.

26. The one or more non-transitory computer-readable media recited in claim 14, wherein the method further comprises: performing dictionary-like diagnosis by mapping test response bits obtained from a tester to the failing bit node system.

Images