Voltage regulator and electronic device

Abstract

A voltage regulator (10) comprises a first circuit portion (111) and a second circuit portion (112). The first circuit portion (111) is configured to generate a reference voltage, Vref, from a voltage provided by a voltage supply (110, 210) and to output Vref to the second circuit portion (112). The first circuit portion (111) further is configured to generate a replica of a target output voltage, Vout, replica, from the voltage provided by the voltage supply (110, 210). The second circuit portion (112) is configured to receive the reference voltage, and to output an output voltage, Vout, that is based on the reference voltage from an output node (114, 214). The voltage regulator (10) is configured to control Vout based on Vout, replica.

Description

[0001] VOLTAGE REGULATOR AND ELECTRONIC DEVICE

[0002] BACKGROUND

[0003] Voltage regulators are employed in a variety of electronic devices . A voltage regulator usually is connected to a voltage reference and supplies a supply voltage to a further component of the electronic device . Generally, attempts are being made to improve the stability of the supply voltage for di f ferent kinds of loads .

[0004] It is an obj ect of the present invention to provide an improved voltage regulator and an improved electronic device .

[0005] SUMMARY

[0006] According to embodiments , the above obj ect is achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0007] According to embodiments , a voltage regulator comprises a first circuit portion and a second circuit portion . The first circuit portion is configured to generate a reference voltage , Vre f , from a voltage provided by a voltage supply and to output Vref to the second circuit portion, the first circuit portion further being configured to generate a replica of a target output voltage , Vout, repl i ca , from the voltage provided by the voltage supply . The second circuit portion is configured to receive the reference voltage , and to output an output voltage , Vout , that is based on the reference voltage from an output node . The voltage regulator is configured to control Vout based on VOut, repl i ca • For example , the second circuit portion may comprise a source follower and a common source transistor . A source terminal of the source follower may be connected to the output node , and a drain terminal of the common source transistor may be connected to the output node .

[0008] For example , the voltage regulator may further comprise an error ampli fier comprising a first sense transistor . A source terminal of the first sense transistor may be connected to the output node , and a current at a drain terminal of the first sense transistor may be configured to control the output voltage .

[0009] According to embodiments , the current at the drain terminal of the first sense transistor may be subtracted from a first current applied to a gate electrode of the common source transistor .

[0010] For example , the voltage regulator may further comprise a repl ica transistor that is matched to the common source transistor, wherein the first current is applied to a gate electrode of the replica transistor, and a terminal of the replica transistor is connected to a node connected to a gate electrode of the source follower .

[0011] According to embodiments , the error ampli fier further comprises a second sense transistor . A source terminal of the second sense transistor is connected to the output node . A current at a drain terminal of the second sense transistor is mirrored to a gate terminal of the source follower, and a current at the drain terminal of the first sense transi stor is subtracted from a current applied to the gate terminal of the source follower .

[0012] For example , the first circuit portion comprises a reference transistor that is matched to the first sense transistor, wherein the reference voltage is applied to a gate terminal of the reference transistor and to the gate terminal of the first sense transistor .

[0013] According to embodiments , the first circuit portion comprises a reference transistor that is matched to the first sense transistor and to the second sense transistor wherein the reference voltage is applied to a gate terminal of the reference transistor, to the gate terminal of the first sense transistor, and to the gate terminal of the second sense transistor .

[0014] For example , the voltage regulator may further comprise a first driving transistor . A terminal of the first driving transistor is connected to a node connected to a gate terminal of the common source transistor .

[0015] According to embodiments , the voltage regulator may further comprise a third sense transistor . The third sense transistor is matched to the source follower, a source terminal of the third sense transistor is connected to the output node and a drain current of the third sense transistor is subtracted from a bias current at the gate terminal of the common source transistor .

[0016] For example , a current at a drain terminal of the reference transistor may be mirrored to the second circuit portion as a bias current .

[0017] According to embodiments , the source follower and the common source transistor are implemented as PMOS transistors . The drain terminal of the common source transistor is connected to the output node , and the source terminal of the source follower is connected to the output node , the common source transistor being arranged between the output node and an upper supply voltage level , and the source follower being arranged between the output node and a lower supply voltage level . According to further embodiments , the source follower and the common source transistor are implemented as NMOS transistors . The drain terminal of the common source transistor is connected to the output node , and the source terminal of the source follower is connected to the output node , the common source transistor being arranged between the output node and a lower supply voltage level , and the source follower being arranged between the output node and an upper supply voltage level .

[0018] An electronic device comprises the voltage regulator as described above .

[0019] For example , the electronic device may further comprise an image sensor .

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .

[0022] Fig . 1 is a schematic drawing of components of a voltage regulator according to embodiments . Fig. 2A is an equivalent circuit diagram of a voltage regulator according to embodiments.

[0023] Fig. 2B is an equivalent circuit diagram of a voltage regulator according to further embodiments.

[0024] Fig. 3A is an equivalent circuit diagram of a voltage regulator according to embodiments.

[0025] Fig. 3B is an equivalent circuit diagram of a voltage regulator according to further embodiments.

[0026] Fig. 4 shows an example of an electronic device.

[0027] DETAILED DESCRIPTION

[0028] In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

[0029] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments. As employed in thi s speci fication, the terms "coupled" and / or "electrically coupled" are not meant to mean that the elements must be directly coupled together - intervening elements may be provided between the "coupled" or "electrically coupled" elements . The term "electrically connected" may describe a low- ohmic electric connection between the elements electrically connected together .

[0030] According to further embodiments and where appropriate , the term "electrically connected" may mean that the respective elements are "directly connected" or are "directly and permanently connected" .

[0031] The term " electrically connected" may describe a permanent low- resistive connection between electrically connected elements , for example a direct contact between the concerned elements or a low-resistive connection via a metal and / or heavily doped semiconductor material . The term " electrically coupled" may include that one or more intervening element ( s ) adapted for signal and / or power transmi ssion may be connected between the electrically coupled elements , for example , elements that are controllable to temporarily provide a low-resistive connection in a first state and a high-resistive electric decoupling in a second state . An ohmic contact may be a non-recti fying electrical j unction .

[0032] Fig . 1 is a schematic drawing of components of a voltage regulator 10 according to embodiments . The voltage regulator 10 illustrated in Fig . 1 comprises a first circuit portion 111 and a second circuit portion 112 . The first circuit portion 111 is connected to a voltage supply 110 , e . g . a voltage reference circuit , such as a bandgap voltage reference . The first circuit portion 111 is configured to generate and to output a reference voltage Vref from a voltage provided by the voltage supply 110 . The first circuit portion is further configured to output Vre f to the second circuit portion 112 . Moreover, the first circuit portion 111 is configured to generate a replica of a target output voltage , Vout, replica, from the voltage provided by the voltage supply .

[0033] The second circuit portion 112 is configured to receive the reference voltage Vref and is further configured to output an output voltage that is based on the reference voltage Vref via an output node 114 . Further, the second circuit portion is configured to control Vout using the Vout, replica generated within the first circuit portion .

[0034] For example , as is illustrated in Fig . 1 , a reference current source 102 is connected to a replica node 105 . The current source 102 is connected to an upper supply voltage level VDD . The replica node 105 is connected to a source terminal of a reference transistor 103 . The reference transistor 103 may be implemented as a PMOS transistor, e . g . a p-channel transistor . The first circuit portion 111 may comprise a divider including a first resistor 101 and a second resistor 108 . A terminal of the second resistor 108 is connected to VSS , e . g . a lower voltage level which may be connected to GND .

[0035] A node of the first resistor 101 is connected to the repl ica node 105 . A node arranged between the first resistor 101 and the second resistor 108 may be connected to an input , e . g . an inverting input , of an amplifier 109 . The voltage provided by the voltage supply 110 is connected to another input of the ampli fier 109 . An output of the ampli fier 109 is connected to a reference node 107 . The reference node 107 is connected to a gate terminal of the reference transistor 103 . Further, a reference voltage Vref is suppl ied from the reference node 107 to the second circuit portion 112 . For example , the first circuit portion 111 may further comprise a first transistor M40 and a second transistor M39 which may be connected in series . A voltage V40 is applied to the gate terminal of M40 . Further, a voltage V41 is applied to the gate terminal of M39 . M39 is diode-connected to a node connected to a drain terminal of the reference transistor 103 .

[0036] The ampli fier 109 keeps the voltage provided by the voltage supply 110 over the second resistor 108 of the divider . Hence , the replica node 105 is at a voltage level Vout, replica of a repl ica of a target value of the output voltage . The replica node 105 i s disconnected from a load and, hence , remains a replica of the target Vout level . The ampli fier 109 generates the reference voltage Vref .

[0037] The reference transistor 103 is matched to sense transistors included in the second circuit portion 112 . The transistors M39 and M40 implement a portion of a current mirror . Accordingly, as will be explained in more detail with reference to Fig . 2A, since drain currents of the reference transistor 103 and of the sense transistors in the second circuit portion 112 will be matched, the source terminal of the reference transistor 103 and the source terminals of the sense transistors of the second circuit portion 112 will be at the same voltage level . Consequently, Vout is a scaled-up replica of the voltage supplied by the voltage supply 110 .

[0038] As will be explained in the following, the output node 114 of the second circuit portion 112 is a fast node in comparison to the reference node 107 and the replica node 105 . Due to the separation into two di f ferent circuit portions 111 , 112 , these circuit portions may operate independently from each other so that the second circuit portion 112 is configured to respond to fast load current spikes at the output node 114.

[0039] Fig. 2A shows an equivalent circuit diagram of a voltage regulator. For example, the voltage regulator 10 illustrated in Fig. 2A may be operated at output voltages that are close to VDD.

[0040] Elements of the first circuit portion 111 are similar to those explained with reference to Fig. 1. Therefore, a detailed description thereof will be omitted. As is illustrated in Fig. 2A, the second circuit portion 112 may comprise a source follower 122 and a common source transistor 125. According to embodiments, the source follower 122 is arranged at the low side, i.e. between the lower supply voltage level and the output node 114. The common source transistor 125 is arranged at the high side, i.e. between the output node 114 and the upper supply voltage level. A source terminal of the source follower 122 is connected to the output node 114. The second circuit portion may further comprise an error amplifier 116 which comprises a differential stage including a first sense transistor 117 and a second sense transistor 118. For example, the source follower 122, the common source transistor 125 and the first and the second sense transistors 117, 118 may be implemented as PMOS transistors, e.g. transistors comprising a p-channel. The first sense transistor 117 and the second sense transistor 118 are both matched to the reference transistor 103. A source terminal of the first sense transistor 117 and the source terminal of the second sense transistor 118 are connected to the output node

[0041] 114.

[0042] Further, a drain current of the second sense transistor 118 is mirrored via transistors M33 and M35 to the first node 124. The first node 124 is connected to the gate terminal of the source follower 122 . Moreover, the drain terminal of the first sense transistor 117 is connected to an eighth node 123 that is connected to transistor M41 . Transistor M41 may be implemented as an NMOS transistor . The current at transistor M41 is based on a drain current of transistor M39 of the first circuit portion 111 . A source terminal of an NMOS transistor 133 is connected to the eighth node 123 . The current at a drain terminal of transistor 133 is mirrored via transistors M25 and M26 to the first node 124 .

[0043] When the output voltage Vout is larger than the target output voltage , the drain currents of the first sense transistor 117 and of the second sense transistor 118 are increased . The drain current of the second sense transistor 118 is directly mirrored to the gate of the source follower 122 . Further, an increase of the drain current of the first sense transistor 117 results in a decrease of the current at transistor M26 . As a consequence , the gate electrode of the source follower 122 is pulled to a lower value , the source follower is turned on and the output node 114 is discharged back to the target output voltage value .

[0044] On the other hand, i f the output voltage Vout is lower than the target value , the drain currents of the first and the second sense transistor 117 , 118 are decreased . As a consequence , the current mirrored by the current mirror M33 / M35 is decreased whereas the current at transi stor M26 is increased . As a consequence , the source follower 122 is turned of f to recharge the output voltage Vout to the target output voltage . A voltage applied to the gate terminal of the source follower 122 may move from a lower voltage supply level VSS to a higher voltage supply level VDD . Consequently, the source follower 122 may sink to GND currents that are several orders of magnitude higher than a bias current of the source follower 122 . As is further illustrated in Fig . 2A, the reference voltage Vref is applied to the gate terminal of the reference transistor 103 which forms part of the first circuit portion . Moreover, Vref is also applied to the gate electrode of the first sense transistor 117 and to the gate electrode of the second sense transistor 118 . The source current of M39 is mirrored to transistors M45 , M41 and further M43 . Accordingly, a current at a drain terminal of the reference transistor 103 of the first circuit portion 111 may be mirrored to the second circuit portion 112 as a bias current . Transistors M41 and M43 are components of a current source for sensing the output voltage .

[0045] The second circuit portion 112 may further comprise a common source transistor 125 . The common source transistor 125 may be implemented as a PMOS transistor . A drain terminal of the common source transistor is connected to the output node 114 . The source follower 122 can sink a lot of current . Accordingly, controlling its static bias current results in a moderate quiescent current for the overall voltage regulator 10 . A gate terminal of the common source transistor 125 is connected to a second node 126 which is connected to a third node 127 and to the source terminal of a first driving transistor 128 . The first driving transistor 128 may be implemented as a PMOS transistor . A current delivered by the first driving transistor 128 determines the VGS of the common source transistor 125 and, hence , the static current of the source follower 122 . A gate voltage V128 applied to the first driving transistor 128 is derived from the upper supply level VDD and may be further derived using a series combination of scaled-down replicas of the common source transistor 125 and the first driving transistor 128 .

[0046] A drain terminal of transistor M38 is connected to the third node 127 . Transistor M38 forms part of a current mirror which additionally comprises transi stor M37 . A drain terminal of transistor M37 is connected to a drain terminal of transistor M44 . A voltage V40 is applied to the gate terminals of transistors M40 , M44 and further to the gate terminals of a second driving transistor 130 and transistor 133 . For example , V40 may be generated by inj ecting a current ( e . g . any bias current , for example the current of M39 and M41 ) into a transistor that is diode connected to the ground (VSS ) . V40 is intended to be the voltage bias for NMOS cascoding devices ( such as M40 , M44 , 130 and 133 ) . In particular, V40 is a reference voltage with respect to the lower voltage supply .

[0047] The second driving transistor 130 and the transistor 133 are both implemented as NMOS transistors . The second circuit portion 112 may further comprise a third sense transistor 129 that may be matched to the source follower 122 . For example , a drain current at the third sense transistor 129 is a scaled-down replica of the drain current at the source follower 122A. A source terminal of the third sense transistor 129 may be connected to the output terminal 114 . A drain terminal of the third sense transistor 129 is connected to a node that is connected to a drain terminal of transistor M43 .

[0048] Without any load, when the drain current of the common source transistor 125 is larger than a target current corresponding to a target output voltage , the current of the source follower 122 increases . In a corresponding manner, a current of the third sense transistor 129 also increases . As a consequence , a current at the third node 127 that is connected to the second driving transistor 130129 decreases . Since the third node 127 is connected to the second node 126 , the common source transi stor 125 is turned of f .

[0049] When a load is connected to the output node 114 and the current at the source follower 122 is decreased, also the current at the third sense transistor 129 is decreased, resulting in an increase of the current at the third node 127 . Since the gate electrode of the common source transistor 125 is connected to the third node via the second node 126 , the common source transistor 125 is turned on to pull the output voltage high . The increase of drain current of the source follower 122 may be several orders of magnitude .

[0050] On the other hand, when the source follower 122 conducts more current , also the current at the third sense transistor 129 grows resulting in a decrease at the third node 127 . Thi s turns the common source transistor 125 of f resulting in a decrease of the output voltage Vout •

[0051] As is further illustrated in Fig . 2A, a first current source for the common source transi stor 125 may comprise NMOS transi stor M43 which mirrors the current at M39 . A second current source for the common source transi stor 125 may comprise PMOS transi stor M38 which forms part of a current mirror that further comprises transistor M37 . For example , the design of transistors M43 and M38 may be chosen so that a current provided by transistor M43 is slightly bigger than the current provided by transistor M38 . In this way, when the current through the third sense transistor 129 is completely gone , the current of transistor M43 is applied directly to the gate of the common source transistor 125 . This saturates the transistors M43 and the transistor 130 . The gate of the common source transistor 125 is driven little above GND . When the common source transistor 125 is fully opened, it conducts a current which is several orders of magnitude higher than the static bias . Accordingly, the driving range of the common source transistor 125 may be enlarged .

[0052] As i s further il lustrated in Fig . 2A, a fourth node 134 may be arranged between the first node 124 and the gate terminal of the source follower 122 . The fourth node 134 may be connected to a source terminal of the transistor 131 . A voltage V131 is applied to the gate terminal of the transistor 131 . Further, the voltage V131 is applied to an electrode of reference capacitor 132 . A second electrode of the reference capacitor 132 may be connected to the reference node 105 .

[0053] The voltage V131 that is applied to the gate terminal of transistor 131 may be generated as a reference voltage in respect to replica node 105 , i . e . as a reference voltage in respect to the replica of Vout which is a static reference .

[0054] For example , a capacitance of the capacitor 132 may be approximately more than 100 femtofarad to approximately some picofarad . Due to this drive of the gate of the source follower 122 , the gate of the source follower 122 may be a low impedance node and the associated pole may be shi fted to higher frequencies . The voltage V131 may be generated in a simi lar manner as V128 . Di f fering from voltage V128 , voltage V131 is generated relative to Vout, replica instead of VDD . For example , the bias current of transistor 131 may be generated by the error ampli fier and may be based on a di f ference of the currents of M26 and M35 . Due to this configuration, the voltage regulator 10 may be used with a decoupling capacitor for the output node , wherein the decoupling capacitor may have a considerably large variation of the capacitance .

[0055] The voltage regulator 10 described with reference to Fig . 2A can both deliver a current spike to a load via the common source transistor 125 and may sink a current spike to ground via the source follower 122 . The voltage regulator 10 is stable in static conditions owing to a moderate voltage gain and to exclusive high frequency poles . The dominant pole is the output node 114 for a capacitive range of more than 1 pF down to 10 nF . For example , a decoupling capacitor having a capacitance of 10 nF may be feasible on-chip . Even smaller capacitors can be used for a padless supply generation but with a slightly di f ferent topology .

[0056] The voltage regulator 10 uses only a moderate bias current of approximately hundreds of pA for the source follower 122 and the common source transistor 125 which still allows them to operate well out of saturation to deliver high current spikes of hundreds of mA. The voltage regulator 10 may be distributed around a large pixel array . It is possible to use the same Vref as at the input of several sense transistors 117 , 118 , 129 , instances driving an equal number of common source transistors 125 and source followers 122 that are conveniently spread in and around a large pixel array . In this way, potential di f ferent of fsets of the output voltage are traded against a lower IR drop .

[0057] As has been described with reference to Fig . 2A, the error ampli fier 116 drives the gate of the source follower 122 . Instead, the error ampli fier may be used to drive the gate of the common source transistor 125. This may be useful in a case of applications when the voltage regulator 10 is intended to deliver more current spikes to load than to sink current spikes from the load . This will be illustrated with reference to Fig . 2B .

[0058] In Fig . 2B, elements of the first circuit portion 111 are similar to those illustrated with reference to Fig . 2A. Deviating from embodiments illustrated in Fig . 2A, the second circuit portion 112 comprises an error ampli fier 116 which only comprises a first sense transistor 117 . Further, the second circuit portion comprises a replica transistor 135 which is matched to the common source transistor 125 . A drain terminal of the replica transi stor is connected to a fourth node 134 that is connected to the gate terminal of the source follower 122 . A drain portion of the first sense transistor 117 is connected to the gate electrode of the replica transistor 135 and to the third node 127 via the transistor 133 . The third node is connected to the gate terminal of the common source transistor 125 . Accordingly, the error ampli fier 116 drives a gate of the common source transistor 125 using only the first sense transistor 117 . When the output voltage Vout is larger than the target value , the current of the first sense transistor 117 grows and the current at the transistor 133 drops . Consequently, the constant bias source M38 that is connected to the third node 127 pulls up the gate of the common source transistor 125 and, hence , the Vout node decreases back to target . The replica transistor 135 copies a scaled-down replica of the current of the common source transistor 125 . The replica transistor 135 directly drives the gate of the source follower 122 via the fourth node 134 .

[0059] When the output terminal 114 is to be discharged, the currents of the common source transistor 125 and of the replica transistor 135 are decreased . As a consequence , the transistor 131 pulls down the gate of the source follower 122 . As a consequence , the current of the source follower 122 is increased, thereby actively discharging the output node 114 .

[0060] The same is valid, when Vout is lower than the target voltage . In this case , the current of the first sense transistor 117 is reduced so that the current at the third node 127 is increased . As a consequence , the gate electrode of the common source transistor 125 is opened to pull the output voltage high . Further, using the replica transistor 135 replicating the current of the common source transistor 125 , the gate electrode of the source follower 122 is set to a higher level which helps the output voltage Vout to increase to the target voltage . According to embodiments illustrated in Fig. 2B, the error amplifier 116 drives the common source transistor 125whereas according to embodiments illustrated in FIG. 2A the error amplifier 116 drives the source follower 122.

[0061] Fig. 3A shows an example of a voltage regulator 10 according to further embodiments. Fig. 3A shows similar elements as illustrated in Fig. 2A, wherein the corresponding reference numbers are incremented by 100. The voltage regulator 10 illustrated in Fig. 3A may be used for an output voltage Vout which is close to GND, i.e. the lower supply range, e.g. less than IV. For example, an output voltage of the voltage regulator 10 illustrated in Fig. 3A may be in a range of approximately 0.4 V to 0.8 V. In comparison to the voltage regulator 10 illustrated in Figs. 2A and 2B, the positions of the source follower 222 and of the common source transistor 225 are interchanged. The source follower 222 is arranged at the high- side, i.e. between the upper supply voltage level and the output node 214. The common source transistor 225 is arranged at the low side, i.e. between the output node 214 and the lower supply voltage level. Further, the source follower 222 and the common source transistor 225 are implemented as NMOS transistor. A drain terminal of the source follower 222 is connected to the higher supply voltage level VDD, whereas a source terminal of the common source transistor 225 is connected to a lower supply level, VSS.

[0062] In Fig. 3A, differing from embodiments illustrated with reference to Figs. 2A and 2B, the voltage supply 110 is configured to deliver a fraction of the bandgap voltage.

[0063] In Fig. 3A, the reference transistor 203 is implemented as an NMOS transistor. A source terminal of the NMOS transistor 203 is connected to a replica node 205. The replica node 205 is connected to a drain terminal of transistor M39. A replica of the target output voltage is applied to the replica node 205 . Further, a control bias 208 is appl ied to a gate terminal of transistor M39 , M40 and further M55 . The first circuit portion 111 comprises the ampli fier 209 , the reference transistor 203 , the replica node 205 and transi stor M39 . The second circuit portion 112 comprises a source follower 222 and an error amp li fier 216 .

[0064] According to embodiments illustrated in Fig . 3A, the current of the reference transistor 203 does not need to be copied for the second circuit portion 112 . For example , the current for the second circuit portion 112 can be independently imposed from the exterior . According to implementations , the control bias 208 can result from a diode connected repl ica device of M39 . According to further implementations , the control bias anyhow can be generated externally .

[0065] The error ampli fier 216 comprises a first sense transistor 217 and a second sense transistor 218 . The sense transistors 217 , 218 are both implemented as NMOS transistors . A source terminal of the first sense transistor 217 and of the second sense transistor 218 is connected to Vout • A drain terminal of the first sense transistor 217 is connected to a seventh node 223 . The seventh node 223 is connected to a transistor M46 forming part of the current mirror compri sing transistors M43 and M46 which mirrors a current of M39 . A resulting current is supplied via a PMOS transistor 233 to a further current mirror comprising transistors M44 and M45 and, finally, to a sixth node 224 . The sixth node 224 is connected to a gate terminal of the source follower 222 .

[0066] A drain terminal of the second sense transistor 218 is connected to the sixth node 224 via a current mirror comprising transistors M37 and M38 . A source terminal of a first NMOS driving transistor 228 is connected to a fi fth node 226 which is also connected to a drain terminal of transistor M55 . The fi fth node 226 is connected to a gate terminal of the NMOS common source transistor 225 .

[0067] The functionality of the voltage regulator 10 is similar to the functionality of the voltage regulator 10 illustrated in Fig . 2A. In particular, the gate of the NMOS source follower 222 is driven by the error ampli fier 216 to regulate Vout in an analogous manner as has been described above with reference to Fig . 2A. Further, an electrode of the reference capacitor 232 is electrically coupled to the replica node 205 . Further V231 is a voltage reference built in respect or relative to the static replica node 205 or Vout, repiica •

[0068] Fig . 3B shows an example of a voltage regulator according to further embodiments . Elements of the voltage regulator in Fig . 3B are similar to the voltage regulator 10 illustrated in Fig . 2B, wherein the corresponding reference numbers are incremented by 100 . Further, in a similar manner as has been discussed above with reference to Fig . 3A, the voltage regulator 10 is suitable to be used in a lower supply voltage range , e . g . in a range of approximately 0 . 4 to 0 . 8 V . The voltage regulator in particular comprises a replica transistor 235 which is a replica of the common source transistor 225 . The drain terminal of the replica transistor 235 is connected to a ninth node 236 that is connected to the gate terminal of the source follower 222 .

[0069] In a similar manner as has been described above with reference to Fig . 2B, the voltage regulator comprises only one sense transistor 217 . Further, the repl ica transistor 235 copies a scaled-down replica of the current of the common source transistor 225. The replica transistor 35 directly drives the gate of the source follower 222 via the ninth node 236.

[0070] Fig. 4 shows an example of an electronic device 15 comprising the voltage regulator 10 as has been explained above. The electronic device 15 is suitable to be connected to a voltage supply 110, 210 that delivers a reference voltage, e.g. a bandgap voltage or a fraction of a bandgap voltage. The electronic device may for example comprise an image sensor 20 or another device. Due to the ability of the voltage regulator 10 to supply large currents and e.g. to sink to GND large currents, the voltage regulator 10 may be used in combination with an image sensor 20. In this case, for example, during a reset step approximately 200 mA may be sunk to GND, whereas a current of approximately 350 mA may be supplied in a further step.

[0071] As has been described, the voltage regulator is configured to be used when, e.g. a load is a time discontinuous current consumer, such as a digital circuit, a switch capacitor block, an S / H circuit or, for example, an array of pixels, e.g. an image sensor 20. As has been described, a reference voltage is first processed in a slow loop, e.g. the first circuit portion 111. The reference voltage is delivered to a second circuit portion 112 which comprises an error amplifier 116, 216 which is a fast amplifier and has only a limited DC gain but a widened bandwidth by placing the poles at high frequency. According to embodiments, the voltage regulator 10 may be used in combination with a decoupling capacitor which may be a slow capacitor having a capacitance of 10 nF or below.

[0072] The described topologies may support also a significant DC current. The DC gain may be increased by removing a "short" at the output of the error amplifier regardless of which gate is driven by the error ampli fier ( e . g . that of the CS device or that of the source follower device ) . A dominant pole for stability can be obtained either at the output with a larger decoupling capacitor or by making the output of the error ampli fier which is a high impedance node , the dominant pole of the internally compensated loop .

[0073] Increasing the gain by the output impedance of the error ampli fier makes it possible to operate even with decoupling capacitors , e . g . having a capacitance lower than nF values . In this case , the output is no longer the dominant pole . As has been described above , the trade of f between the gain and the output capacitance may be solved by using two circuit portions wherein a first circuit portion works at a lower speed and the second circuit portion works at a higher speed .

[0074] The voltage regulator 10 described can be operated at a high frame rate and may be used in combination with a larger pixel array in comparison with known concepts . For example , the voltage regulator 10 may support loads that vary the current over several decades of magnitude e . g . in a range of 0 to 350 mA. Further, there is a high flexibility in the choice of the decoupling capacitor . For example , a capacitance of the decoupling capacitor may be approximately 10 nF or less so that the decoupling capacitor may be arranged on-chip . The voltage regulator is able to cope with bidirectional current spikes .

[0075] While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein . LIST OF REFERENCES

[0076] 10 voltage regulator

[0077] 15 electronic device

[0078] 20 image sensor

[0079] 101 first resistor

[0080] 102 reference current source

[0081] 103 reference transistor

[0082] 105 replica node

[0083] 107 reference node

[0084] 108 second resistor

[0085] 109 amp 1 i f i e r

[0086] 110 voltage supply

[0087] 111 first circuit portion

[0088] 112 second circuit portion

[0089] 114 output node

[0090] 116 error ampli fier

[0091] 117 first sense transistor

[0092] 118 second sense transistor

[0093] 122 source follower

[0094] 123 eighth node

[0095] 124 first node

[0096] 125 common source transistor

[0097] 126 second node

[0098] 127 third node

[0099] 128 first driving transistor

[0100] 129 third sense transistor

[0101] 130 second driving transistor

[0102] 131 transistor

[0103] 132 reference capacitor

[0104] 133 transistor

[0105] 134 fourth node

[0106] 135 replica transistor

[0107] 203 reference transistor replica node control bias ampli fier voltage supply output node error ampli fier first sense transistor second sense transistor NMOS source follower seventh node sixth node NMOS common source transistor fi fth node first NMOS driving transistor second driving transistor NMOS transistor reference capacitor PMOS transistor replica transistor ninth node

Claims

CLAIMS1. A voltage regulator (10) comprising a first circuit portion (111) and a second circuit portion (112) , the first circuit portion (111) being configured to generate a reference voltage, Vref, from a voltage provided by a voltage supply (110, 210) and to output Vref to the second circuit portion (112) , the first circuit portion (111) further being configured to generate a replica of a target output voltage, Vout, replica, from the voltage provided by the voltage supply (110, 210) , the second circuit portion (112) being configured to receive the reference voltage, and to output an output voltage, Vout, that is based on the reference voltage, via an output node (114, 214) , the voltage regulator (10) being configured to control Vout based on Vout, replica, wherein the second circuit portion (112) comprises a source follower (122, 222) and a common source transistor (125, 225) , wherein a source terminal of the source follower (122, 222) is connected to the output node (114, 214) , and a drain terminal of the common source transistor (125, 225) is connected to the output node (114, 214the voltage regulator (10) further comprising an error amplifier (116, 216) comprising a first sense transistor (117, 217) , wherein a source terminal of the first sense transistor (117, 217) is connected to the output node (114, 214) , and a current at a drain terminal of the first sense transistor (117, 217) is configured to control the output voltage .

2. The voltage regulator (10) according to claim 1, wherein the current at the drain terminal of the first sense transistor(117, 217) is subtracted from a first current applied to a gate electrode of the common source transistor (125, 225) .

3. The voltage regulator (10) according to claim 2, further comprising a replica transistor (135, 235) that is matched to the common source transistor (125, 225) , wherein the first current is applied to a gate electrode of the replica transistor (135, 235) , and a terminal of the replica transistor (135, 235) is connected to a node (134, 236) connected to a gate electrode of the source follower (122, 222) .

4. The voltage regulator (10) according to claim 1, wherein the error amplifier (116, 216) further comprises a second sense transistor (118, 218) , wherein a source terminal of the second sense transistor (118, 218) is connected to the output node (114, 214) , a current at a drain terminal of the second sense transistor (118, 218) is mirrored to a gate terminal of the source follower (122, 222) , and a current at the drain terminal of the first sense transistor (117, 217) is subtracted from a current applied to the gate terminal of the source follower (122, 222) .

5. The voltage regulator (10) according to any of claims 1 to 3, wherein the first circuit portion (111) comprises a reference transistor (103, 203) that is matched to the first sense transistor (117, 217) , wherein the reference voltage is applied to a gate terminal of the reference transistor (103, 203) and to the gate terminal of the first sense transistor (117, 217) .

6. The voltage regulator (10) according to claim 4, wherein the first circuit portion (111) comprises a reference transistor (103, 203) that is matched to the first sense transistor (117,217) and to the second sense transistor (118, 218) wherein the reference voltage is applied to a gate terminal of the reference transistor (103, 203) , to the gate terminal of the first sense transistor (117, 217) , and to the gate terminal of the second sense transistor (118, 218) .

7. The voltage regulator (10) according to any of the preceding claims, further comprising a first driving transistor (128, 228) , wherein a terminal of the first driving transistor (128, 228) is connected to a node (126, 226) connected to a gate terminal of the common source transistor (125, 225) .

8. The voltage regulator (10) according to any of claims 4, 6 or 7, further comprising a third sense transistor (129, 229) , wherein the third sense transistor (129, 229) is matched to the source follower (122, 222) , a source terminal of the third sense transistor (129, 229) is connected to the output node (114, 214) and a drain current of the third sense transistor (129, 229) is subtracted from a bias current at the gate terminal of the common source transistor (125, 225) .

9. The voltage regulator (10) according to any of claims 5 to 8, wherein a current at a drain terminal of the reference transistor (103, 203) is mirrored to the second circuit portion(112) as a bias current.

10. The voltage regulator (10) according to any of the preceding claims, wherein the source follower (122) and the common source transistor (125) are implemented as PMOS transistors, and the drain terminal of the common source transistor (125) is connected to the output node (114) , and the source terminal of the source follower (122) is connected to the output node (114) , the common source transistor (125) being arranged between the output node (114) and an upper supplyvoltage level, and the source follower (122) being arranged between the output node (114) and a lower supply voltage level.

11. The voltage regulator (10) according to any of the preceding claims, wherein the source follower (222) and the common source transistor (225) are implemented as NMOS transistors, and the drain terminal of the common source transistor (225) is connected to the output node (214) , and the source terminal of the source follower (222) is connected to the output node (214) , the common source transistor (225) being arranged between the output node (214) and a lower supply voltage level, and the source follower (222) being arranged between the output node (214) and an upper supply voltage level.

12. An electronic device (15) comprising the voltage regulator (10) according to any of the preceding claims.

13. The electronic device (15) according to claim 12, further comprising an image sensor (20) .

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