Data rate conversion method and data rate conversion unit

Abstract

The invention relates to a method for converting a data rate from an input data rate into a predefined output data rate, comprising the steps of: generating an intermediate frequency depending on a multiple of an output data rate; constantly keeping (100) input samples at an input data rate for a period of the intermediate frequency; sampling (200) the input samples at the intermediate frequency, wherein an intermediate signal is generated; filtering (300) the intermediate signal, wherein the filter is designed to suppress multiples of the output data rate and has a smaller suppression between the multiples of the output data rate than for the multiples of the output data rate; determining filter coefficients (h(0), h(1), h(2)) for which samples on the intermediate frequency are not equal to zero by means of a phase-locked loop, wherein an output clock is synchronised with a system clock, which is a multiple of the input data rate, and is used as an input signal for the phase-locked loop; and down-clocking (400) the filtered intermediate signal to the output data rate.

Description

[0001] Description

[0002] title

[0003] DATA RATE CONVERSION METHOD AND DATA RATE CONVERSION UNIT

[0004] The invention relates to a data rate conversion unit and a method for converting a sampling rate.

[0005] State of the art

[0006] Implementing or converting the sample rate or data rate is a frequently required function, for example in the audio or communications sector, e.g. in software-defined radio. Data rate conversions are also required in sensor technology. For example, a MEMS gyroscope is often operated at its resonant frequency and all clock pulses are derived from this resonant frequency. If multiple sensors, e.g. gyroscope, accelerometer, etc. are implemented on a MEMS die, these sensors and their evaluation circuits often have to be operated at the frequency derived from the gyroscope. At the interface between the sensor and the outside world, on the other hand, a fixed data rate that is independent of the MEMS is often expected. For some interfaces, e.g. PDM interface, I2S, Soundwire, the expected data rate is even specified externally. For these use cases, data rate conversion is necessary.

[0007] Various implementations are known for converting a data rate.

[0008] Figure 1 conceptually shows the process of how a sample rate conversion is performed in state-of-the-art converters. The left side shows the time domain, and the right side the frequency domain. The data rate of the input signal is brought to a very high intermediate frequency by zero stuffing 500. Typical interpolation factors are on the order of 2 A16 for digital audio. In the frequency domain, this means a repetition of the spectrum of the input signal at multiples of the input sampling frequency. This signal at the high intermediate frequency is digitally filtered at 600. The filter's task is to sufficiently suppress the repeated images of the signal. The bandwidth of this filter is therefore smaller than this intermediate data rate by the interpolation factor of the zero stuffing. Filtering is typically performed with FIR filters. Therefore, very long FIR filters are required, and a large number of multiplications and additions must be performed for each output sample. The spectrum of a sampled signal always repeats at multiples of the respective sampling frequency. A digital filter cannot suppress these images at multiples of the high intermediate frequency. The ratio between the high intermediate frequency and the output data rate does not necessarily have to be an integer.To achieve the output data rate, the signal is held constant for one period of the intermediate frequency (700). In the frequency domain, this corresponds to filtering with a sinc function. This signal is sampled at the output sampling frequency (800). The sinc-suppressed images of the signal, at multiples of the intermediate frequency, are aliased into the signal frequency band. The suppression of these images depends on the ratio of the signal bandwidth to the intermediate frequency. The higher the intermediate frequency, the closer, relatively speaking, the signal images are to the zeros of the sinc function at the intermediate frequency, and thus the stronger the suppression of the sinc filter. From the requirement for a minimum suppression of the images, a requirement for the size of the intermediate frequency can be derived.

[0009] The described concept requires a significant amount of hardware. In particular, the long FIR filters at high intermediate frequencies require a large number of multiplications and additions for each individual output sample. Practical implementations therefore exploit the fact that many samples of the signal to be filtered are zero and therefore do not need to be included in the calculation. Only the non-zero samples of the signal need to be multiplied and added by the corresponding filter coefficients. The filter coefficients are usually stored in a read-only memory (ROM). Additional logic then determines the filter coefficients for the non-zero samples of the signal. These are different for each output sample and must be selected using additional logic.

[0010] Figure 2 shows a typical prior art implementation. The prior art data rate conversion unit shown uses a RAM 11 for buffering the input samples and a ROM 12 for the filter coefficients. The filter is implemented, for example, as a polyphase filter, with a RAM address generator 13 for reading a start address in the RAM 11 and a ROM address generator 14 for selecting the polyphase. The address generators 13, 14 are controlled by a write counter 15, a P-element 16 with gain K, and an integrator 17 that uses the clock signal Out Clk. The filtering process comprises a plurality of arithmetic operations, the results of which are accumulated in 18.

[0011] The object of the invention is to reduce the hardware effort for a sample rate converter by at least one order of magnitude, in particular for the special case that the input signal and possibly also the output signal is a delta-sigma modulated bitstream.

[0012] Disclosure of the invention

[0013] The invention enables simple and resource-efficient data rate conversion. For this purpose, the invention is particularly suitable for delta-sigma modulated bitstreams, and specific properties of the input and output signals used are utilized. The properties of the input and output signals utilized are explained below. The input signal is, in particular, delta-sigma modulated. This means that the bandwidth of the useful signal is smaller than the input data rate by the oversampling rate, and the bit width is very small, for example, only 1 bit. The output signal is also oversampled, meaning that the output data rate is also significantly larger than the bandwidth of the useful signal. Interference signals that occur outside the signal frequency band are less or not relevant. This hardware reduction enables the effective use of a sample rate converter in small, power-efficient sensors.

[0014] Considerable savings in hardware complexity can be expected if the requirements for the digital filter at the intermediate frequency could be reduced, thus reducing the filter length. This would reduce the overall number of multiplications. One approach to this is provided by the property of the output signal that the output signal is oversampled, making noise signals outside the signal frequency band less relevant and therefore requiring less suppression. In the signal frequency band, aliasing causes signals with frequencies (+ / - signal bandwidth) around the output sampling frequency to end up. Therefore, the attenuation of the digital filter only needs to be very high at these frequencies. In the ranges in between, the requirements are lower.

[0015] An exemplary choice for such a filter is an n-order sinc filter with n-order zeros at multiples of the output sampling frequency; but other filters are also conceivable.

[0016] One problem that arises when implementing such a filter function using the described prior art method is that the filtering occurs at a multiple of the input data rate, but the zeros of the selected transfer function are intended to be located at multiples of the output data rate. However, the zeros of a digital filter always track at the sampling frequency at which they are operated. Since the ratio of input data rate to output data rate is not fixed and can vary from device to device, the desired transfer function cannot be realized with the desired accuracy using the prior art method.

[0017] The method for converting a data rate from an input data rate to a predefined output data rate comprises the following steps. The method is particularly suitable for delta-sigma modulated bitstreams.

[0018] First, a step a) generates an intermediate frequency as a function of a multiple of an output data rate. Then, a step b) maintains input samples constant at an input data rate for one period of the intermediate frequency. The input samples originate, in particular, from an input bitstream, preferably from a delta-sigma modulated input bitstream.

[0019] Next, the input samples, as described in the previous step, are sampled at the intermediate frequency. This generates an intermediate signal. The data rate of the intermediate signal is still a multiple of the output data rate.

[0020] Furthermore, the intermediate signal is filtered. The filter is preferably an nth-order sinc filter with nth-order zeros. The filter is designed to suppress multiples of the output data rate. Furthermore, the filter has a smaller suppression between multiples of the output data rate than for multiples of the output data rate. Likewise, a step e. of determining filter coefficients for which samples at the intermediate frequency are not equal to zero is carried out. The filter coefficients are determined using a phase-locked loop, wherein an output clock is synchronized with a system clock that is a multiple of the input data rate and used as the input signal for the phase-locked loop.

[0021] Since the intermediate frequency is a multiple of the output data rate, the filter can be implemented simply and operates with minimal effort. In particular, it is intended that only delta-sigma modulated bitstreams are processed, allowing the filter to be adapted to these bitstreams.

[0022] Finally, a step f is performed to downclock the filtered intermediate signal to the output data rate. This provides a new data rate.

[0023] The subclaims contain preferred developments of the invention.

[0024] Advantageously, a gain is determined which results from the previous steps, in particular steps b to d. Furthermore, the gain in the downclocked signal is corrected to generate an output signal. The output signal thus corresponds to the input signal with the changed data rate. The gain results in particular from the fact that the input signal is only held constant for the relatively short period of one period of the intermediate frequency. For the rest of the time, the held signal is zero. In other words, a duty cycle is thus realized for the held signal, resulting in a gain over the entire transmission path. This gain depends in particular on said duty cycle, which results from the ratio of input frequency to output frequency.

[0025] To determine the gain, it is particularly advantageous to repeat at least the steps of holding, sampling, and filtering for an input signal of magnitude 1. The same filter coefficients are used for the filtering step as for filtering the intermediate signal. Thus, the constant signal 1 undergoes the same processing as the input signal. This means that the same gain occurs as in the input signal. Since the signal has the constant value 1, the resulting gain can be easily determined, allowing a simple gain correction to generate the output signal.

[0026] In a further advantageous embodiment of the method, the output signal is converted into a bitstream by analog-to-digital conversion. The conversion is performed, in particular, using delta-sigma modulation. The determined gain is used as the reference for the delta-sigma modulator. This allows for easy and minimal gain correction. The entire method is particularly effective and easy to implement for converting data rates of delta-sigma modulated bitstreams.

[0027] In an alternative advantageous embodiment, the gain is determined from a ratio of the input frequency to the output frequency. As previously described, the gain is realized in particular from the duty cycle effectively generated during the input signal holding step. This, in turn, means that a ratio of the input frequency to the output frequency determines the magnitude of the gain. This allows the gain to be easily determined and subsequently corrected.

[0028] The filtering step advantageously includes adding and / or subtracting the filter coefficients to or from the intermediate signal. In particular, this allows oversampled input signals with a bit width of one bit to be processed effectively and resource-efficiently. Such an application is particularly advantageous for sensor signals.

[0029] The invention also relates to a computer program. The computer program is configured to carry out the method as described above. In particular, the computer program is executed on a control device, for example, a computer or a control unit.

[0030] The invention further relates to a machine-readable storage medium. The computer program is stored on the machine-readable storage medium as described above. The storage medium is, in particular, an optical and / or magnetic and / or electronic storage medium.

[0031] Finally, the invention relates to a data rate conversion unit comprising a filter. The filter is preferably an n-order sinc filter with n-order zeros at multiples of the output sampling frequency. The data rate conversion unit is designed to generate an intermediate frequency as a function of a multiple of an output data rate. Furthermore, the data rate conversion unit is designed to keep input samples constant at an input data rate for one period of the intermediate frequency and to sample the input samples at the intermediate frequency, thereby generating an intermediate signal. The data rate conversion unit is also designed to filter the intermediate signal using the filter and to downclock the filtered intermediate signal to the output data rate.

[0032] The filter is designed to suppress multiples of the output data rate. Between multiples of the output data rate, the filter has a smaller suppression than for multiples of the output data rate. The data rate conversion unit also has a phase-locked loop designed to determine filter coefficients of the filter. The phase-locked loop serves to determine the filter coefficients such that the samples at the intermediate frequency are not equal to zero. For this purpose, an output clock is synchronized with a system clock that is a multiple of the input data rate as the input signal of the phase-locked loop. In particular, the phase-locked loop serves to determine the time difference between the input clock and the output clock, this difference being provided for selecting the filter coefficients. The filter coefficients are preferably predefined and stored, for example, in a read-only memory or ROM.

[0033] The data rate conversion unit preferably has an additional filter with the same filter coefficients as the filter. The data rate conversion unit is preferably designed to determine a gain that results in particular from holding the input samples and sampling and filtering. As described above, these processing steps result in an amplification factor or gain less than 1. To determine this gain, the data rate conversion unit is designed to hold and sample a signal of size 1 as described above and to filter it with the additional filter. Thus, the data rate conversion unit is designed to subject the signal of size 1 to the same processing as the input signal. Due to the constant size 1 of the signal, the resulting gain can be immediately recognized. The data rate conversion unit is designed to correct the gain in the down-clocked signal to generate an output signal.

[0034] Further advantages arise from the following description of embodiments and the dependent patent claims.

[0035] Short description of the drawings

[0036] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. They show:

[0037] Figure 1 shows a sample rate conversion in the time domain and in the frequency domain from the state of the art,

[0038] Figure 2 shows a state-of-the-art implementation of a sample-rate conversion,

[0039] Figure 3 shows an inventive sample rate conversion in the time domain and in the frequency domain, and Figure 4 shows an inventive implementation of a sample rate conversion.

[0040] Figure 3 schematically shows the flow of a method for converting the data rate from an input data rate to a predefined output data rate according to an exemplary embodiment of the invention. On the one hand, a schematic overview of the flow is shown, and on the other hand, the signal processing during the method is shown as an example in the time domain (left side) and the frequency domain (right side). Figure 4 shows an exemplary implementation of the method.

[0041] In a first step, the high intermediate frequency is selected not as a multiple of the input data rate, but as a multiple of the output data rate. To do this, the input samples are held constant at the input data rate for one period of the intermediate frequency (100) and then sampled at the intermediate frequency (200). In the frequency domain, the hold function again corresponds to filtering with a sinc function. The suppression of the sinc function at multiples of the intermediate frequency can again be adjusted via the size of the intermediate frequency. Aliasing occurs when sampling the held signal. However, the frequency components that are mirrored into the signal frequency band are sufficiently suppressed by the sinc function.

[0042] In a subsequent step, the signal is filtered 300 at the high intermediate frequency. For this purpose, a filter 2a is used with strong suppression at multiples of the output data rate and smaller suppression in between. However, since the intermediate frequency, contrary to the problems described above, is a multiple of the output data rate, it is possible to implement a filter 2a, for example, as an n-order sinc filter with n-order zeros at multiples of the output sampling frequency. Due to the relaxed requirements for filter 2a, significant hardware savings result. Further hardware savings arise from the properties of the input signal. It is an oversampled signal with a small bit width, often even only one bit. This reduces the effort required for multiplication by the filter coefficients. For 1-bit signals, the effort is reduced to simple addition or subtraction.In addition, the filter coefficients h(0), h(1), h(2) of the filter 2a are determined. The filter coefficients h(0), h(1), h(2) are predefined and stored in a read-only memory 8. Filter coefficients h(0), h(1), h(2) are selected for which the samples at the high intermediate frequency are not equal to zero. This is done with the aid of a digital phase-locked loop 3 having a phase detector 3a, a loop filter 3b, and a digital oscillator 3c. For this purpose, the output clock fso is synchronized with a system clock that is a multiple of the input data rate fsi and used as the input signal for the phase-locked loop 3. Synchronization is performed by means of a sampling element 7 with a multiple of the input clock k * fsi. The digital oscillator 3c in the phase-locked loop 3 integrates its control signal with each clock to form a phase ramp. If this counter exceeds a certain threshold, the oscillator generates an output pulse.This signal is kept synchronized with the output data rate by the phase-locked loop 3. The phase ramp of the digital oscillator 3c therefore contains the information about how much time has elapsed between the input clock fsi and the output clock fso. This information is used directly to select the corresponding filter coefficients.

[0043] The final step is to downclock 400 the filtered intermediate signal to the output data rate. This is performed, for example, by a sampling element 5 with the output clock f50. Modulation is then performed using the delta-sigma modulator 4 to generate the output bistream bitstream out. For the delta-sigma modulation of the delta-sigma modulator 4, a gain correction is also provided, which is explained below.

[0044] During the hold step 100, the input signal is held constant for the short duration of one period of the high intermediate frequency. For the rest of the time, the held signal is zero. Effectively, the signal is duty-cycled, resulting in a gain of less than 1 for the entire transmission path, which depends on this duty cycle—ultimately, the ratio of input to output frequency. Since this ratio is unknown and can vary from sample to sample, this gain must be determined and corrected.

[0045] In the embodiment shown, a constant signal of magnitude 1 is used to perform the previously described steps of holding 100, sampling 200, and filtering 300 on this signal. For filtering 300, an additional filter 2b is used, which has the same filter coefficients h(0), h(1), h(2) as filter 2a. Thus, the signal of magnitude 1 is subjected to the same processing as the actual input signal, and the magnitude of the resulting output signal is determined. Since the original signal is constantly 1, the gain can be easily determined. An alternative way of determining the gain is to determine the ratio of the input and output frequencies and calculate the gain from this. Since the input and output frequencies usually change only very slowly, this determination of the gain can be done at a lower frequency and with reduced effort.

[0046] The determined gain is filtered in a filter element 6 and fed to the delta-sigma modulator 4 as a reference. The delta-sigma modulator 4 thus outputs the final output signal of the data rate conversion unit 1. The output signal is again a bitstream, referred to as bistream out in Figure 4.

[0047] A significant advantage is the reduction in hardware complexity. While conventional sample rate converters require on the order of magnitude 60 to 70 multiplications and additions per output sample, a method according to the exemplary embodiment of the invention, or a data rate conversion unit 1 according to the exemplary embodiment of the invention, achieves this with three additions. Even with a parallel path for determining the gain running continuously, the total hardware complexity is reduced by an order of magnitude, with six additions.

[0048] A further advantage is the automatic tracking of the anti-aliasing filter. If a data rate is reduced using a sample rate converter, the frequency components above the new half data rate must be suppressed. If the data rate is increased, this filtering is neither necessary nor desired. In practice, this is achieved by switchable filter sets for the digital filter, depending on whether the new data rate is lower or higher than the old data rate. In a data rate conversion unit 1 according to the exemplary embodiment of the invention, the bandwidth of the filter 2a automatically tracks the new data rate. Switching the filter sets is not necessary.

Claims

Claims 1 . Method for converting a data rate from an input data rate to a predefined output data rate, comprising the steps of: a. generating an intermediate frequency as a function of a multiple of an output data rate, b. keeping input samples constant (100) at an input data rate for one period of the intermediate frequency, c. sampling (200) the input samples at the intermediate frequency, whereby an intermediate signal is generated, d. filtering (300) the intermediate signal, wherein the filter is designed to suppress multiples of the output data rate and has a smaller suppression between the multiples of the output data rate than for the multiples of the output data rate, e.Determining filter coefficients (h(0), h(1), h(2)) for which samples at the intermediate frequency are not equal to zero by means of a phase-locked loop, wherein an output clock is synchronized with a system clock which is a multiple of the input data rate and used as an input signal for the phase-locked loop, and f. down-clocking (400) the filtered intermediate signal to the output data rate.

2. Method according to claim 1, characterized by step g. Determining a gain resulting from the previous steps, in particular steps b to d, and correcting the gain in the downclocked signal to generate an output signal.

3. Method according to claim 2, characterized in that, to determine the gain, at least the steps of holding (100), sampling (200) and filtering (300) are repeated for an input signal of size 1, using the same filter coefficients as for filtering the intermediate signal.

4. Method according to claim 3, characterized in that the output signal is converted into a bitstream by analog-to-digital conversion, in particular by delta-sigma modulation, wherein the determined gain is used as a reference of the delta-sigma modulator (4).

5. Method according to claim 2, characterized in that the gain is determined from a ratio of input frequency and output frequency.

6. Method according to one of the preceding claims, characterized in that the filtering step (300) comprises adding and / or subtracting the filter coefficients to or from the intermediate signal.

7. Computer program configured to carry out the method according to claims 1 to 6.

8. A machine-readable storage medium on which the computer program according to claim 7 is stored.

9. Data rate conversion unit (1) comprising a filter (2a), in particular a sinc filter of n-th order with zeros of n-th order, and designed to • Generating an intermediate frequency as a function of a multiple of an output data rate, • Holding constant (100) input samples at an input data rate for one period of the intermediate frequency, and • Sampling (200) the input samples at the intermediate frequency, whereby an intermediate signal is generated, • Filtering (300) of the intermediate signal, • Clocking down (400) the filtered intermediate signal to the output data rate, wherein the filter (2a) is designed to suppress multiples of the output data rate and has a smaller suppression between the multiples of the output data rate than for the multiples of the output data rate, and wherein the data rate conversion unit (1) has a phase-locked loop (3) which is designed to determine filter coefficients (h(0), h(1), h(2)) in which samples on the intermediate frequency are not equal to zero, wherein an output clock is synchronized with a system clock which is a multiple of the input data rate and is provided as an input signal for the phase-locked loop.

10. Data rate conversion unit (1) according to claim 9, characterized in that the data rate conversion unit (1) has an additional filter (2b) with the same filter coefficients as the filter (2a) and is designed, • to determine a gain resulting in particular from holding (100) the input samples and sampling (200) as well as filtering (300), by holding (100), sampling (200) and filtering (300) a signal of size 1 with the additional filter (2b), and • correct the gain in the down-clocked signal to produce an output signal.

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