Multi-cellular HEMT layout

Abstract

A heterojunction device comprising: a Ill-nitride semiconductor region comprising a heterojunction, wherein the heterojunction comprises at least one two-dimensional carrier gas, a drain terminal (8) operatively connected to the Ill-nitride semiconductor region, a gate terminal (6) positioned over the Ill-nitride semiconductor region, the gate terminal surrounding and spaced apart from drain terminal in a lateral dimension, and a source terminal (7) surrounding and spaced apart from the gate terminal in the lateral dimension, the source terminal and operatively connected to the Ill-nitride semiconductor region. The source terminal is positioned about or proximate to a perimeter of the heterojunction device. A perimeter of the drain terminal is circular in the lateral dimension.

Description

[0001] MULTI-CELLULAR HEMT LAYOUT

[0002] Field of the Disclosure

[0003] The present disclosure relates to semiconductor devices. Particularly, but not exclusively, the disclosure relates to hetero-structure AIGaN / GaN high electron mobility transistors and / or rectifiers.

[0004] Background of the Disclosure

[0005] Gallium Nitride (GaN) is a wide band gap material with properties that make it a suitable candidate for use in several fields of application (e.g. radio-frequency electronics, optoelectronics, power electronics) which require or benefit from the use of solid-state devices.

[0006] GaN technology facilitates the design of transistors with a high electron mobility and a high saturation velocity. These properties of GaN have made it a good candidate for high-power and high-temperature microwave applications, for example radar and cellular communications systems. As systems expand in subscribers and desired capacity, interest in increasing their operating frequency and power has grown correspondingly. Higher frequency signals can carry more information (bandwidth) and allow for smaller antennas with relatively high or very high gain.

[0007] Additionally, GaN with its wide bandgap offers the potential for emitting light at higher frequencies, for example in the green (495-570 nm), blue (380-500 nm), violet (-380 nm), and ultraviolet (10-400 nm) portions of the electromagnetic spectrum.

[0008] In the last decade, GaN has increasingly been considered as a very promising material for use in the field of power devices. The application areas range from portable consumer electronics, solar power inverters, electric vehicles, and power supplies. The relatively wide band gap of the material (Eg=3.39 eV) results in a relatively high critical electric field (Ec=3.3 MV / cm) compared to alternative materials, which can facilitate the design of devices with a shorter drift region. This in turn may enable a lower on-state resistance compared to e.g. a silicon-based device with the same breakdown voltage. The use of an Aluminium Gallium Nitride (AIGaN) / GaN heterostructure also facilitates the formation of a two-dimensional electron gas (2DEG) at the hetero-interface, where charge carriers can reach very high mobility (p=2000 cm2 / (Vs)) values. In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure can result in a high electron density in the 2DEG layer (e.g. 1 xio13cm-2). These properties allow the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters.

[0009] For high voltage / power devices, several key parameters are generally considered to be important. The rated voltage (e.g. 600V) is the maximum allowable voltage in the off- state or during the transient modes that could be applied safely between the drain and the source terminals of the power device. The breakdown voltage, which is the largest reverse voltage that can be applied without causing an exponential increase in the leakage current, should exceed the rated voltage (e.g. 1 kV). In many designs, the breakdown voltage may be limited by lateral leakage between the drain terminal and the source terminal and / or vertical leakage between the drain terminal and the substrate. The specific on-state resistance (e.g. 2 mohmcm2) for a given rated voltage is another key static parameter. The smaller the specific on-state resistance the lower the on-state power losses. Other important components or parameters which may limit the speed and transient losses of the power device are the capacitances, for example the gate-source and gate-drain (Miller) and drain-source (output) capacitances. Generally speaking, the smaller these capacitances for a given area (or for given on-state resistance), the faster and more efficient the HEMT is in commutation. Finally, another important parameter is the leakage current in the off-state. This off-state leakage generally increases with temperature and with the applied off-state voltage. It has two components, a lateral component (drain terminal to source terminal or drain terminal to gate terminal) and a vertical component (drain terminal to substrate). The vertical component in particular may increase significantly at higher off-state, thereby blocking voltages.

[0010] In the past varied transistor structures have been proposed to optimise the layout area and the operation of power devices. For example, US5838050A and US5852315A each describe cell layouts for complementary metal-oxide-semiconductor (CMOS) devices for electrostatic discharge (ESD) protection.

[0011] State-of-the-art GaN based lateral devices such as HEMTs are commonly designed using inter-digitated fingers. Source and gate fingers are separated by a drift region from drain fingers. One or several field plates on the source / gate fingers (respectively connected to either source or gate terminals) and / or on the drain fingers (connected to drain terminals) are commonly used to shape the electric field inside the drift region, and thereby enhance the reliability of the device. The inter-digitated design is a relatively easy design to layout and effective in scaling to different currents (for example by adding or removing fingers)

[0012] However, inter-digitated designs also possess several drawbacks. For example, interdigitated designs generally have a relatively high channel resistance, as well as a relatively high resistance of the 2DEG under the field plates due to a low channel density. Further to this, these designs are typically characterised by a high output capacitance and a relatively slow speed of removing the 2DEG during the turn-off, while also possessing a relatively high vertical leakage current. The low channel density of the interdigitated design also limits the saturation current. The saturation current further reduces with the increase in temperature. In some applications, having a relatively high saturation current, such as applications utilising full load conditions or surge conditions, can be beneficial.

[0013] The Applicant have therefore recognised a need for an improved design for semiconductor devices, and in particular a need for improved designs for heterostructure AIGaN / GaN HEMTs.

[0014] Summary

[0015] It is the object of this invention to describe a lateral power semiconductor device, such as a power transistor or HEMT, that addresses some or all of the shortcomings of interdigitated GaN HEMT design as described above.

[0016] According to a first aspect of the present disclosure there is provided a heterojunction device comprising: a Ill-nitride semiconductor region comprising a heterojunction, wherein the heterojunction comprises at least one two-dimensional carrier gas; a drain terminal operatively connected to the Ill-nitride semiconductor region; a gate terminal positioned over the Ill-nitride semiconductor region, the gate terminal surrounding and spaced apart from drain terminal in a lateral dimension; and a source terminal surrounding and spaced apart from the gate terminal in the lateral dimension, the source terminal operatively connected to the Ill-nitride semiconductor region, wherein the source terminal is positioned about or proximate to a perimeter of the heterojunction power device; and a perimeter of the drain terminal is circular in the lateral dimension or a rounded polygon in the lateral dimension.

[0017] Generally speaking, the present disclosure provides at least one cell of a lateral semiconductor device, for example a HEMT based on GaN technology, with concentric source terminal and gate terminal rings (e.g. the gate ring being enclosed by the source ring, and the gate ring itself enclosing the drain terminal), with a circular or approximately circular drain. For example, the drain may have a circular or oval shape, or may have a square or rectangular (or other polygonal) shape with chamfered or rounded corners. The drain is enclosed and separated from the gate ring through a drift region. As used herein, a rounded polygon may refer to a polygon with rounded or chamfered corners. For example, a “rounded square” may refer to square with rounded corners ora “squircle” shape.

[0018] The device may be a heterojunction high voltage / power device. In one example, the device may comprise a multi-cellular design, to thereby facilitate the use of relatively high currents. As used herein, high voltage may refer to voltages of 20V to 1 .2 kV, and / or with corresponding current levels that may be in the range of 1A to hundreds of Amps. It will be understood that a lower power / lower voltage device may also be provided. For example, the device may have a current rating below 1A and / or a breakdown voltage below 20V. Such devices may be used in analogue or mix-signal circuits, for example. Lower power device may also form part of a power integrated circuit. Such a device may retain advantages over convention structures such as a larger channel density, and thereby provide better overall performance than a conventional device.

[0019] Thus, in implementations the power device is a power transistor, and optionally the power device is a HEMT. The Ill-nitride semiconductor region may comprise a GaN layer and an AIGaN, wherein the heterojunction is formed at an interface between the GaN layer and the AIGaN layer.

[0020] In implementations, the heterojunction power device may form a rectangular (e.g. square), hexagonal, octagonal or a polygonal structure such that the perimeter of the device may be square or hexagonal or octagonal or polygonal in the lateral dimension. The source terminal may similarly form a rectangular (e.g. square), hexagonal, octagonal or a polygonal structure , in the lateral dimension about the perimeter of the device. However, other source terminal shapes may also be provided. Similarly, the gate terminal may additionally or alternatively form a rectangular (e.g. square), hexagonal, octagonal or a polygonal structure in the lateral dimension. In implementations, the gate terminal and source terminal may be the same shape such that they form concentric structures, wherein a separation between an edge of the gate terminal and a corresponding edge of the source terminal the same or is approximately the same for all edges of the terminals. In implementations, the gate terminal may be enclosed by the source terminal in the lateral dimension. The drain terminal may be enclosed by both the gate and source terminals in the lateral dimension, with a drift region separating the drain terminal from the gate terminal. For example, an outer perimeter of the drain, source and gate terminals may have the same shape such that the terminals form a concentric structure in the lateral dimension. The gate terminal may contain a p doped Gallium nitride layer. Alternatively a metal on insulated gate can be provided.

[0021] In some implementations, a hexagonal device structure (e.g. with hexagonal gate and source rings) may facilitate a very high packing density, thus minimising the channel resistance and the source resistance of the device. The high channel density may also help to facilitate an increased saturation current of the device.

[0022] Alternatively, a square-shaped source terminal is simpler to manufacture than a hexagonal-shaped source terminal, but generally provides a poorer packing density (and therefore a reduced channel density).

[0023] An octagonal device structure may provide better packing density than a square shaped device and a greater channel perimeter than a hexagon shaped device, thereby reducing the channel resistance. It may also facilitate simpler designs and manufacturing, for example by facilitating the use of simpler patterns or designs of a metal interdigitation above the semiconductor layers.

[0024] The source and gate terminals may also be provided in other (non-hexagonal or rectangular) shapes. For example, the gate terminal may comprise a “flower-shape” or undulating design. This may further increase the perimeter of the gate terminal for a given area, and thus further reduce the channel resistance and increase the saturation current. Other polygon shaped structures may also be provided. In particular, polygonal shapes with an even number of sides may facilitate higher packing densities than structures with an odd number of sides. As such, in some implementations the device, gate terminal and / or source terminal may be polygonal shapes with an even number of sides, such as but not limited to squares, hexagons and octagons.

[0025] In implementation, the gate terminal is positioned above a p-type GaN (pGaN) region. The pGaN region may have the same shape as the gate terminal.

[0026] The drain terminal may be provided with a closed circular contact plate and / or a circular field plate, to thereby reduce or minimise the electric fields around the drain contact. A drain field plate may be provided with a circular shape (or a regular polygon shape mimicking or closed to a circular shape, for example with angles more than 120 degrees), to reduce the electric field due to the presence of the sharp corners. Similarly, the drain terminal itself may be a circle or approximately circular, e.g. a regular polygon with angles more than 120 degrees. In implementations, the drain field plate may have the same shape as the drain terminal. For example, the drain terminal and drain field plate may both be a square with rounded corners, a square with keyhole corners or any other shape with keyhole or otherwise rounded corners. In implementations, any polygonal shaped drain terminal may be used, and in particular polygonal shapes with rounded corners. In some implementations, the drain terminal may form an even-numbered polygonal structure in the lateral dimension, such as a square, hexagon, octagon, or other shapes..

[0027] A field plate may be provided for and connected to the source or gate terminal. The source / gate field plate is preferably circular or approximately circular on an internal edge, or alternatively it can have a similar hex or square or octagon or polygon design to the source terminal or the gate terminal. In implementations, a circular or rounded cornered source / gate field plate design may facilitate improved field distribution. As with the drain field plate, the source and / or gate field plates may have the same shape as the corresponding source and / or gate terminals.

[0028] As such, in implementations the device comprises a field plate connected to the source terminal or the gate terminal, wherein a lateral internal edge of the field plate is circular. A drift region may therefore be formed in an active area of the Ill-nitride semiconductor region between the drain terminal and field plate. The device may additionally or alternatively comprise a second field plate connected to the drain terminal, wherein the second field plate is circular in the lateral dimension or similar to (or the same as) the shape of the drain terminal in the lateral dimension and comprises a diameter greater than a diameter of the drain terminal. The drift region may therefore be formed in the Ill- nitride semiconductor region between the field plate and the second field plate.

[0029] The drift region may have a doughnut or torus shape, i.e. due to the shape of the edges of the field plates. For example, the drift region may be formed between the drain-side edge of the source-connected or gate-connected field plate (or the source or gate terminal) and the source or gate-side edge of the drain-connected field plate (or the drain terminal). In one example therefore, the drift region may extend from an edge of a drain- connected field plate (at a laterally inner edge of the drift region) to an edge of a source- connected or gate-connected field plate (at a laterally outer edge of the drift region). In the drift region, a surface field may be present during the off-state or voltage blocking mode of the device. This is also the region where the field builds up from the gate towards the drain during the turn-off of the device, by gradually depleting the 2DEG between the drain edge of the gate and the drain.

[0030] In implementations, the device comprises one or more isolation regions located inside an active area of the heterojunction power device. The one or more isolation regions may be configured to prevent the formation of the two-dimensional carrier gas inside the one or more isolation regions. The one or more isolation regions may be formed at a corner of the gate terminal or a corner of the source terminal, or both.

[0031] According to a second aspect of the invention, there is provided a system comprising a plurality of heterojunction devices according to the first aspect, wherein each heterojunction device is positioned adjacent to at least one other of the heterojunction device.

[0032] Thus, and generally speaking, multiple HEMT cells according to the present disclosure can be packed together in a multicellular array in a tessellating pattern such as a honeycomb structure, to thereby increase the current of the device and lower its on-state resistance. The multicellular array may form a regular tessellating pattern, semi-regular tessellating pattern or an irregular tessellating pattern. Alternatively, the HEMT cells may be arranged in an MxN matrix multicellular array, where M and N are integers and at least one of M and N is greater than 1.

[0033] In implantations, the concentric rings of the source and gate terminals of the heterojunction devices may not be closed within each cell. For example, the terminals may be “shared” between cells such that they continue from one cell to other (e.g. adjacent) cells and loop around the overall array. The continuation of the terminals across the cells may be beneficial for connecting any field plates to the source and / or gate terminals.

[0034] Various metal layers may be provided to connect the source and / or drain terminal of the heterojunction devices. For example, upper metal interconnections on the source, gate, drain (e.g. using vias or metal pillars) may be connected to the hexagonal / octagonal / circular patterns below. If the upper metal layers follow the cellular layout of the semiconductor layers, then the metal lengths required may increase and pose additional challenges for device design and / or manufacture. As used herein, the cellular layout may refer to the arrangement of devices in a multi-cell structure.

[0035] For example, the overall gate metal length in a cellular layout may be much larger than the overall gate metal length in an interdigitated structure, potentially resulting in higher gate resistance. Therefore, the upper metal connections may advantageously be formed with inter-digitated fingers, to provide connections from the power device cells to the terminal pads (i.e. source, gate and drain) and / or to facilitate easier connection of the redistribution layers such as upper metal layers. Moving from a cellular design at semiconductor level to an interdigitated design at metal level may provide an efficient design benefitting from the high packing density of cellular layout and low metal resistance due to decreased length of metal layers. Landing “contacts” may be provided at the intersection of hex shapes for forming interpillars, to connect the source and / or drain terminals to an upper redistribution metal layer. The redistribution metal layer (e.g. such as an upper metal layer) may comprise of copper or other suitable metals for effective transport of current.

[0036] Thus, the system may comprise a source layer provided along an edge region of the heterojunction power devices, wherein the source layer is connected to the source terminals of the heterojunction power devices. Contacts regions for the source layer may be provided at intersections of heterojunction power devices, for example in cases where hexagonal structure are provided. Alternatively, the contact regions for the source layer may be provided in the source region between the two devices, for example in cases where octagon structures is provided. It will be understood that the preferred location for the contact regions may depend on the specific structure and intended use of the device.

[0037] Additionally or alternatively, the system may comprise a drain layer connected to the drain terminals of the heterojunction power devices. Additionally or alternatively, the system may comprise a gate layer connected to the gate terminals of the heterojunction power devices, to thereby route the gate signals across the cells.

[0038] The source layer and the drain layer may be interdigitated, or the system may comprise an upper drain layer and an upper source layer, wherein the source layer is connected to the upper source layer and the drain layer is connected to the upper drain layer, and wherein the upper source layer and upper drain layer are interdigitated.

[0039] In an implementation, adjacent heterojunction power devices share a source terminal along their adjacent edge.

[0040] In summary therefore, the present disclosure provides a cell level device that may comprise a polygonal source ring such as a hexagonal or octagonal source ring, enclosing a polygonal gate ring such as a hexagonal or octagonal gate ring, which itself encloses at least one circular or rounded square source-connected or gate-connected field plate enclosing a doughnut (circular) type drift region, circular or rounded square drain field plate enclosing a circular or rounded square drain plate. The present disclosure further provides a multi-cell device level, comprising interconnections from the source, gate and drain terminals to upper metal layers. The upper metal layers may comprise interdigitated fingers. Pads for source, drain and gate may be provided on a metal layer above the interdigitated metal layer structure, to provide connections points for the package.

[0041] Implementations of the present disclosure provide various advantages, some of which are listed below:

[0042] - A higher channel density due to a high perimeter over surface area, and a higher packing density. This may facilitate reduced channel resistance and therefore reduced on-state resistances.

[0043] - A higher source contact density resulting in lower on-state resistance.

[0044] The fast and efficient depletion of the 2DEG during the turn-off. This may be facilitated by the circular shape of the drift region where the 2DEG is present, as this favours a faster depletion and higher electric field towards the drain terminal (i.e. the inside of the doughnut shaped drift region) rather than gate (i.e. the outside of the doughnut shape). As the voltage between the drain and source is increased, for example during the turn-off of the device, the depletion region may advance faster towards the drain terminal (when compared to existing an interdigitated designs), as the 2DEG area and therefore the 2DEG charge diminishes towards the drain terminal because of the circular or near-circular (doughnut) drift region geometry.

[0045] - A lower field pressure on the drain edge of the gate terminal, thereby redistributing the electric field towards the drain. This can reduce the effect of the field on the dynamic Ron or the on the stability of the threshold voltage.

[0046] - A lower drain to substrate current leakage and lower output (drain to substrate) capacitance. This may be facilitated by the positioning of the drain terminal on the inside of the cell structure. As a result, its surface area and contact area to the 2DEG is significantly smaller than in an equivalent interdigitated design.

[0047] - A higher saturation current for the same gate to source voltage, e.g. due to the increased channel density. This may be of benefit in full load conditions and / or surge conditions.

[0048] - A higher endurance time during short-circuit events. During the short-circuit a hotspot may be formed near a field plate, for example next to the gate terminal. As the electric field is lower in that region because of the cellular geometry, the hotspot may have a lower temperature and be more extended in dimensions during short-circuit events, thereby reducing the risk of further damage to the device.

[0049] According to a third aspect of the invention, there is provided a method of making a heterojunction device comprising: forming a Ill-nitride semiconductor region above a substrate, the Ill-nitride semiconductor region comprising a heterojunction, wherein the heterojunction comprises at least one two-dimensional carrier gas; forming a drain terminal operatively connected to the Ill-nitride semiconductor region; forming a gate terminal positioned over the Ill-nitride semiconductor region, the gate terminal surrounding and spaced apart from drain terminal in a lateral dimension; and forming a source terminal surrounding and spaced apart from the gate terminal in the lateral dimension, the source terminal and operatively connected to the Ill-nitride semiconductor region; wherein a perimeter of the heterojunction power device forms a hexagonal or octagonal shape in the lateral dimension; and a perimeter of the drain terminal is circular or a rounded square in the lateral dimension.

[0050] The method may further comprise forming a at least a first heterojunction power device and a second heterojunction power device such that the first and second heterojunction power device are adjacent to one another such that they share an adjoining edge.

[0051] Brief Description of the Drawings

[0052] The present disclosure will be understood more fully from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only.

[0053] Figures 1a and 1b show example semiconductor device structures according to the present disclosure.

[0054] Figures 2a and 2b show example multi-cell structures according to the present disclosure.

[0055] Figure 3 shows an example metallisation layer structure according to the present disclosure.

[0056] Figure 4 shows a further example metallisation layer structure according to the present disclosure.

[0057] Figures 5a and 5b show example semiconductor device structures according to the present disclosure. Figures 6a-c show a further example semiconductor device structure according to the present disclosure.

[0058] Figures 7a and b shows further example semiconductor device structures according to the present disclosure.

[0059] Figure 8 shows a further example semiconductor device structure according to the present disclosure.

[0060] Figure 9 shows a further example semiconductor device structure according to the present disclosure.

[0061] Detailed Description of the Preferred Embodiments

[0062] Figure 1a illustrates a schematic diagram of a semiconductor device 100 according to the present disclosure. The semiconductor device 100 is a hexagonal (hex) HEMT cell and may be combined with one or more other hex HEMT cells to form a multi-cell structure. The hex cell is provided with a source terminal or ring 7 provided along or proximate to a perimeter of the hex cell, such that it laterally surrounds the hex cell. A drain terminal 8 is provided in the centre of the hex cell, and is formed in a circular shape, i.e. such that a perimeter of the drain terminal in the lateral dimension is a circular. As used herein, “laterally” or the “lateral dimension” may refer to the direction of separation between the drain terminal and the source terminal of the semiconductor device.

[0063] A gate terminal or ring 6 is formed on a pGaN layer 5, which itself is formed above a 2DEG. The gate terminal 6 is formed between the source terminal 7 and the drain terminal 8. While the gate terminal 6 and pGaN layer 5 are depicted with a hexagonal shape (e.g. formed parallel to and inside of the source terminal 7), the gate terminal 6 may be formed in any shape. The gate terminal 6 is positioned between the source terminal 7 and the drain terminal 8, such that it laterally surrounds the drain terminal 8 and is in turn laterally surrounded by the source terminal 7. More generally, the hex cell may be provided with any closed-loop shape design for the source terminal 7 and the gate terminal 6, for example hexagonal, circular, flower etc. Other implementations may be provided with terminals (including but not limited to the drain terminal) formed in other circular (e.g. oval) shapes or approximately circular shapes, such as a regular polygon with more than 6 corners and angles larger than 120 degrees. In some implementations, the source terminal and gate terminal may not form a closed loop, and may have openings or breaks in certain areas along their perimeter. This for example may facilitate easier or more convenient connections to any field plates.

[0064] Generally speaking, lateral high voltage / power HEMTs such as device 100 are provided with three terminals: a source terminal, a drain terminal and a gate terminal, with the gate terminal configured in use to modulate the current between the drain terminal and the source terminal. The current between the source and drain terminals may flow through a 2DEG, e.g. provided at a GaN / AIGaN heterojunction. For example, the source 7 and the drain 8 terminals may make an ohmic contact to the 2DEG. As such, the gate the p- type GaN layer 5 (upon which the gate terminal 6 is formed) may be placed above the AIGaN layer. Alternatively, the gate terminal 6 may be a Schottky type or an insulated type gate. In the off-state, the voltage is blocked between the drain 8 and the source 7, as the gate-source voltage is less than a threshold value which ensures that at least a portion of the 2DEG under the gate 6 is depleted. As the voltage between the drain 8 and the source 7 is increased, the 2DEG becomes increasingly depleted. Thus, during the turn-off and in the off-state of the device, the depletion of the 2DEG between the gate 6 and the drain 8 allows a high electric field to be sustained in the drift region. It will be understood that references to source, drain and gate terminals herein are references to terminals of the transistor device configured for use as respective source, drain and gate terminals.

[0065] The hexagonal structure of device 100 may provide an increased ratio of the size of the perimeters of the source terminal 7 and the perimeter of the gate terminal 6 relative to an interdigitated structure. This increased perimeter ratio for the gate 6 can facilitate an improved channel resistance per unit area of the device 100. It will be understood that the on-state resistance of the device 100 may comprise the resistance of the drift region and the channel region, and as such minimising the resistance of the channel region may result in a lower overall on-state resistance.

[0066] Moreover, the hex / circular geometry of the cell may result in lower capacitances and a steeper decrease of such capacitances with the voltage. This is the result of the generally circular geometry providing a faster advance of depletion region and the electric field towards the drain terminal, and lower field pressures on the drain edge of the gate terminal. As such, the structure of the device 100 may also facilitate improved reliability and increased stability against dynamic on state resistances (Ron) or threshold shift problems. Additionally, the use of a circular (or approximately circular) drain terminal structure may avoid or reduce unwanted or undesirable electric field effects at the corners of the drain region.

[0067] The structure of device 100 may further facilitate a lower field pressure on the drain edge of the gate terminal, redistributing the field towards the drain. This can reduce the effect of the field on the dynamic Ron and / or the on the stability of the threshold voltage.

[0068] Further to this, the hexagonal structure depicted in Figure 1 may reduce a current leakage in an off-state between the drain terminal and a substrate terminal attached to the backside of the chip of the semiconductor device. This may be facilitated by the smaller effective physical contact of the drain terminal to the active area compared to an interdigitated design. The smaller contact area of the drain contact may also lead to a reduced drain to substrate capacitance, which may in turn facilitate faster switching and smaller transient losses.

[0069] Figure 1b illustrates a schematic diagram of an alternative semiconductor device 101 according to the present disclosure. The semiconductor device 101 is structurally similar to semiconductor device 100, and like reference numerals are provided. In contrast to device 100, device 101 comprises an octagonal (termed here “octo”) HEMT cell, and may be combined with one or more other octo HEMT cells to form a multi-cell structure. The octo cell is provided with a source terminal or ring 7 provided along or proximate to a perimeter of the octo cell, such that it laterally surrounds the octo cell. The inner edge of the source terminal is octagonal in shape. A drain terminal 8 is provided in the centre of the octo cell. In this example, the drain terminal 8 comprises a square or approximately square shape with rounded corners (sometimes referred to as a “rounded square” or “squircle”), i.e. such that a perimeter of the drain terminal in the lateral dimension has rounded corners. It will be understood that the drain terminal may instead form any polygonal shape in the lateral dimension, and in particular a polygonal shape with rounded corners. In some implementations, the drain terminal may form a polygonal shape with an even number of sides, such as a square, hexagon or octagon.

[0070] A gate terminal or ring 6 is formed on a pGaN layer 5, which itself is formed on an AIGaN layer above a 2DEG formed at the interface between a GaN layer and the AIGaN layer. Above the p GaN layer a Schottky or ohmic gate metal can be provided. Alternatively, to the gate metal / pGaN layer a metal / oxide layer can be provided to form an insulated gate (not shown). The gate terminal 6 is formed between the source terminal 7 and the drain terminal 8. While the gate terminal 6 and pGaN layer 5 are depicted with an octagonal shape (e.g. formed parallel to and inside of the source terminal 7), the gate terminal 6 may be formed in any shape. The gate terminal 6 is positioned between the source terminal 7 and the drain terminal 8, such that it laterally surrounds the drain terminal 8 and is in turn laterally surrounded by the source terminal 7.

[0071] It will be understood that semiconductor devices utilising other polygonal cell shapes, and in particular polygonal shapes with an even number of sides, may also be provided.

[0072] Figure 2a shows a multi-cell system or structure 200 comprising a plurality of cells 200a- d. In an example, each cell may be a hex cell such as semiconductor device 100 of Figure 1a. However, it will be understood that other cell shapes may also be utilised in equivalent array arrangements. While structure 200 is depicted with four cells 200a-d, it will be understood that any number of cells may be provided according to the needs and desired functionality of the structure. The hex structure of each cell 200a-d facilitates an increased packing density of the cells, and therefore a higher perimeter of the channel for a given area than an inter-digitated design.

[0073] As such, the multi-cell structure 200 may provide an enhanced channel density and thus smaller channel resistance and a lower ratio of channel resistance to drift region resistance. Moreover, each cell of the structure 200 may be provided with a wider gate width per given unit area compared to known HEMT structures.

[0074] Figure 2b shows an alternative multi-cell system or structure 201 comprising a plurality of cells. In an example, each cell may be an octo cell such as semiconductor device 101 of Figure 1b. However, it will be understood that other cell shapes may also be utilised in equivalent array arrangements. While structure 201 is depicted with eight cells, it will be understood that any number of cells may be provided according to the needs and desired functionality of the structure. The octo structure of each cell facilitates an increased packing density of the cells, and therefore a higher perimeter of the channel for a given area than an inter-digitated design.

[0075] Adjacent cells in structure 201 may be provided with overlapping source regions, i.e. such that a laterally outer edge of the source region of a cell is adjacent to or is shared with a laterally outer edge of the source region of the adjacent cell. As such, the multi-cell structure 201 may provide an enhanced channel density and thus smaller channel resistance and a lower ratio of channel resistance to drift region resistance. The enhanced channel density also increases the saturation current in the device. Moreover, each cell of the structure 201 may be provided with a wider gate width per given unit area compared to known HEMT structures.

[0076] Figure 3 illustrates a further example multi-cell structure 300 comprising a plurality of octo cells, such as devices 101 of Fig. 1b. Structure 300 is provided with the source metallization layer 302 and drain metallization layer 304. The source of each cell is connected with an upper metal layer (i.e. source metallization layer 302) along the edges of the octo cells. The drain of each cell is likewise connected to an upper metal layer (i.e. drain metallization layer 304) and interdigitated with the source metal layer. The upper metal layers may be connected to source / drain terminals through vias or contacts 306. In this example, the gate terminal of each cell is connected to an upper gate metal layer through the vias. The gate signal may be routed through these upper metal layers across the cells. In some implementations, if the gate metal is to be connected at the terminal level then the source terminal region may need to be discontinued between cells to provide an open region for the gate metal layer to pass and connect the cells together.

[0077] Figure 4 illustrates an alternative layout for the source metallization layer 402 and drain metallization layer 404 of a multi-cell hexagonal structure 400 such as structure 200. The drain and source layers 402, 404 are interdigitated, and may form an upper metallisation layer connected respectively to the source and drain terminals via one or more contacts (e.g. vias). In implementations, the multi-cell structure may comprise both a lower source / drain metal layer 302, 304 and an upper source / drain metal layer 402, 404, wherein the respective lower and upper source / drain layers are electrically connected to one another via one or more contact points such as contact points 306 / 406.

[0078] Figure 5a illustrates a semiconductor device 600 corresponding to semiconductor device 100 of Figure 1. Like reference numerals are provided.

[0079] Figure 5b illustrates a schematic cross-section of the device 600 along line A-A of device 600. The device 600 comprises a transition layer 3 formed on a first surface substrate 4. A metal backplate layer 9 may be provided on a second, opposite, side of the substrate 4. A heterojunction layer comprising a 2DEG 10 is formed above the transition layer 3. The heterojunction layer comprises a GaN layer 2 and an AIGaN layer 1 , and the 2DEG 10 is formed at the interface of these layers. It will be understood that the heterojunction layer may comprise other materials in addition to or in place of the GaN 2 and AIGaN 1 layers. A source field plate 12 (which may be, for example, source metallization layer 302 or a separate metal layer) extends over the gate 6 terminal, and a drain field plate 16 (e.g. drain metallization layer 304 or a separate metal layer) is connected to the drain terminal 8. The edge of the source field plate 12 and the edge of the drain field plate 16 may define a drift region between the gate terminal 6 and the drain terminal 8, as shown in Figure 6a, 7a, 7b. It will be understood that Figure 5b is merely an example configuration, and that the field plate dimensions may be designed laterally and vertically for a better optimised potential distribution in the off-state of the device, and / or for improved ease of use of the device. As depicted in Figure 5b, the source and drain terminals 7, 8 may be laterally separated, i.e. spaced apart in a dimension that is perpendicular to the separation of these terminals from the substrate 9. Alternatively, source field plate 12 may be a gate field plate, and be connected to the gate terminal 6 rather than the source terminal 7. In this case, the drift region may still be formed in the active area of the device between the gate field plate and the drain terminal 8 or the drain field plate 16.

[0080] Figure 6a depicts a schematic top view of an example semiconductor device 500. Figure 6a shows an example drift region 15 between a laterally internal edge (e.g. a drain-side edge) of a source field plate and an edge (e.g. gate-side edge) of a drain field plate. As depicted in Figure 6a, the source and / or drain field plates may be provided with a rounded square shape, such that the lateral electric field between the source and drain field plates is confined between the near circular internal edge of the source field plate and the near circular outer edge of the drain terminal 8 or drain field plate. As shown, the drift region may therefore be formed in a ring torus shape. However, it will be understood that other shapes of drift region 15 may also be provided based on the selection of the drain and / or source field plate shapes, or alternatively based on the shapes of the source and / or drain terminals. For example, any polygonal shape, and in particular polygons with rounded corners, may be utilised. For example, the drift region may be provided such that its laterally inner and outer edges form (rounded) square, hexagonal or octagonal shapes.

[0081] Figure 6b illustrates the depletion of 2DEG in a structure 501 comprising an octagonal HEMTs, such as device 201 as shown in Figure 2b. Cell 501a illustrates the shape of the drift region while cell 501b illustrates the moving edge of the depletion region 18 during turn-off. After each step increase in the voltage between the drain and source, the edge of the depletion region moves incrementally closer to the drain. The convergence of the shape of drift region from an octagonal shape to a rounded square shape may facilitate a faster and more efficient depletion of 2DEG during the turn-off. This may in turn be facilitated by the approximately circular (e.g. squircle, rounded square or other rounded polygonal) shape of the drift region where the 2DEG is present, as this shape favours a faster depletion and higher electric field towards the drain terminal (i.e. the inside of the doughnut shaped drift region) rather than gate (i.e. the outside of the doughnut shape). As the voltage between the drain and source is increased, for example during the turn-off of the device, the depletion region may advance faster towards the drain terminal (when compared to existing interdigitated designs), as the 2DEG area and therefore the 2DEG charge diminishes towards the drain terminal as a result of the nearcircular (doughnut) drift region geometry.

[0082] Figure 6c illustrates example lateral Field distributions from source to drain in an interdigitated design and cellular design at the same high voltage level, when the 2DEG is depleted. In a cellular design, the field advances towards the drain, lowering the peaks at the edge of the pGan gate and the field plate and redistributing the field inside the drift region towards the drain side.

[0083] Figure 7a depicts a schematic top view of a semiconductor device 700a. Figure 7a shows an example drift region 15 between a laterally internal edge (e.g. a drain-side edge) of a source field plate 12 and an edge (e.g. gate-side edge) of a drain field plate 16. As depicted in Figure 7a, the source and / or drain field plates may be provided with a circular shape, such that the lateral electric field between the field plates 12, 16 is confined between the circular internal edge of the source field plate 12 and the circular outer edge of the drain terminal 8 or drain field plate 16. As shown, the drift region 15 may therefore be formed in a ring torus shape. However, it will be understood that other shapes of drift region 15 may also be provided based on the selection of the drain and / or source field plate shapes, or alternatively based on the shapes of the source and / or drain terminals.

[0084] Figure 7b depicts a schematic top view of an alternative semiconductor device 700b. Device 700b is similar to device 700a shown in Fig. 7a. However, the device 700b, the source terminal 7 and gate terminal 6 are formed in a square shape in a lateral dimension. The drain terminal 8 and the field plates 12, 16 may be formed and function similarly to those of the device 600a (i.e. with generally circular inner or outer edges respectively). As such, the drift region of the device may still be formed in a ring torus shape. Figure 8 illustrates a further example semiconductor device structure 800. Semiconductor device 800 is largely identical to semiconductor device 700, and like reference numerals are provided. Relative to device 700, the pGaN and gate terminal 17 of device 800 is provided in the shape of a flower, or otherwise in an undulating shape laterally surrounding the drain terminal 8, to thereby provide a uniform gate channel around the drain terminal 8. It will be understood that Figure 8 is a schematic diagram and is not to scale. For example, the gate channel width may be uniform throughout the gate region 17. The “flower-shaped” or undulating design may further increase the perimeter of the gate terminal for a given area, and thus further reduce the channel resistance. While device 800 is depicted as a hex cell structure, it will be understood that the undulating gate terminal shape may also be used in combination with a square cell structure, such as that depicted in Fig. 7b, an octagonal cell structure, such as depicted in Fig. 6a, or any other polygonal device structure as described above.

[0085] Figure 9 illustrates invention further example semiconductor device 900. Relative to e.g. semiconductor device 700, semiconductor device 900 comprises isolation regions 11 provided at the corners of the gate terminal 6, to thereby segment the hexagonal gate terminal 6. The isolation regions 11 may be configured to remove the 2DEG from the isolation area, such that the isolation region 11 does not form part of the active area of the device 900. The isolation regions 11 may have a circular, or at least rounded (e.g. rounded corners) shape, which may assist with the current spreading from the channel into the drift region and avoid any possible concentration of current flow lines or high electric fields.

[0086] The dimensions of these isolation regions 11 adjust the trade-off between the saturation current (short-circuit capability) and the on-state resistance of the structure. The larger these isolation regions 11 are, the lower the perimeter of the active gate region 13, and therefore the lower the saturation current and hence the better the short-circuit endurance. However, if the remaining perimeter of the active gate region 13 is too small, the channel resistance may be increased, potentially leading to higher on-state resistance. It will be understood that isolation regions 11 can be located at other positions (i.e. not necessarily at the corners of the gate 6), or only at some corners of the gate terminal 6. Other possible placements of the isolation regions 11 may include: on the sides of the p-GaN hexagon, or between the gate hexagon and the source hexagon, or on the corners of source hexagon, thus increasing the source resistance. An increased source resistance also results in a lower saturation current and therefore improved short- circuit endurance. Furthermore, the isolation regions 11 facilitate a better trade-off between an increased channel perimeter and increased gate to source and gate to drain capacitances. It will be further understood that the isolation regions may be provided in combination with other gate terminal, source terminal and cell shapes, for example square, octagonal, circular or flower / undulating structures as described above. In some implementations, the terminals above the isolation regions may be discontinuous or segmented. This arrangement may be particularly advantageous where power transistors according to the present disclosure are manufactured by forming the isolation regions after forming the gate regions (i.e. the doped Ill-nitride regions), for example where the isolation regions may be formed by implantation that would otherwise take place through the gate region. The isolation regions may still need to be formed with partial overlap between the gate region and the isolation region (where in the isolation region the two-dimensional carrier gas is prevented from forming), to suppress any 2DEG path between the source 7 and drain 8 terminals when the gate is off.

[0087] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘above’, ‘below’ and ‘lateral’ are made with reference to conceptual illustrations such as those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to the positioning of the components as shown in the accompanying schematic drawings.

[0088] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

[0089] Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.

Claims

CLAIMS:1 . A heterojunction device comprising: a Ill-nitride semiconductor region comprising a heterojunction, wherein the heterojunction comprises at least one two-dimensional carrier gas; a drain terminal operatively connected to the Ill-nitride semiconductor region; a gate terminal positioned over the Ill-nitride semiconductor region, the gate terminal surrounding and spaced apart from drain terminal in a lateral dimension; and a source terminal surrounding and spaced apart from the gate terminal in the lateral dimension, the source terminal operatively connected to the Ill-nitride semiconductor region, wherein the source terminal is positioned about or proximate to a perimeter of the heterojunction device; and a perimeter of the drain terminal is circular in the lateral dimension or a rounded polygon in the lateral dimension.

2. The heterojunction device of claim 1 , wherein the perimeter of the heterojunction device forms a hexagonal shape in the lateral dimension.

3. The heterojunction device of claim 1 , wherein the perimeter of the heterojunction device forms a square shape in the lateral dimension.

4. The heterojunction device of claim 1 , wherein the perimeter of the heterojunction device forms an octagonal shape in the lateral dimension.

5. The heterojunction device of any preceding claim, wherein the gate terminal forms a hexagonal, octagonal or square structure in the lateral dimension.

6. The heterojunction device of claim 5, wherein a separation between an edge of the gate terminal and a corresponding edge of the source terminal is approximately constant.

7. The heterojunction device of any one of claims 1 to 4, wherein the gate terminal forms an undulating structure in the lateral dimension.

8. The heterojunction device of any preceding claim, wherein the gate terminal is positioned above a p-type GaN (pGaN) region.

9. The heterojunction device of any preceding claim, wherein the Ill-nitride semiconductor region comprises a GaN layer and a AIGaN layer, wherein the heterojunction is formed at an interface between the GaN layer and the AIGaN layer.

10. The heterojunction device of any preceding claim, comprising a field plate connected to the source terminal or the gate terminal, wherein a laterally internal edge of the field plate is circular, and wherein a drift region is formed in an active area of the Ill-nitride semiconductor region between the drain terminal and field plate.11 . The heterojunction device of claim 10, comprising a second field plate connected to the drain terminal, wherein the second field plate is circular in the lateral dimension and comprises a diameter greater than a diameter of the drain terminal, wherein the drift region is formed in the Ill-nitride semiconductor region between the field plate and the second field plate.

12. The heterojunction device of any preceding claim, comprising one or more isolation regions located inside an active area of the heterojunction device, the one or more isolation regions being configured to prevent the formation of the two-dimensional carrier gas inside the one or more isolation regions.

13. The heterojunction device of claim 12, wherein the one or more isolation regions are positioned along a perimeter of the gate terminal.

14. The heterojunction device of claim 13, wherein at least one of the one or more isolation regions is formed at a corner of the gate terminal.

15. The heterojunction device of claim 12, wherein the one or more isolation regions are positioned along a perimeter of the source terminal.

16. The heterojunction device of claim 15, wherein at least one of the one or more isolation regions is formed at a corner of the source terminal.

17. The heterojunction device of any preceding claim, wherein the perimeter of the drain terminal is circular in the lateral dimension.

18. The heterojunction device of any one of claims 1 to 16, wherein the perimeter of the drain terminal forms a rounded polygon in the lateral dimension, optionally wherein the polygon is a square.

19. A system comprising a plurality of heterojunction devices according to any preceding claim, wherein each heterojunction device is positioned adjacent to at least one other of the plurality of heterojunction devices.

20. The system according to claim 19, comprising a source layer provided along an edge region of each of the heterojunction devices, wherein the source layer is connected to the source terminals of the heterojunction devices.21 . The system according to claim 20, comprising contacts for the source layer at a laterally outer edge of the source region of each of the heterojunction devices.

22. The system according to any one of claims 19 to 21 , comprising a drain layer connected to the drain terminals of the heterojunction devices.

23. The system according to claim 22 when dependent upon claim 20 or 21 , wherein the source layer and the drain layer are interdigitated.

24. The system according to claim 23 or 22 when dependent upon claim 20 or 21 , comprising an upper drain layer and an upper source layer, wherein the source layer is connected to the upper source layer and the drain layer is connected to the upper drain layer, and wherein the upper source layer and upper drain layer are interdigitated.

25. The system according to claim 19, comprising: a drain metallisation layer connected to the drain terminal of each heterojunction device; a source metallisation layer connected to the source terminal of each heterojunction device; and a gate metallisation layer connected to the gate terminal of each heterojunction device; wherein the source, drain and gate metallization layers are interdigitated.

26. The system according to any one of claims 19 to 25, wherein the plurality of heterojunction devices are arranged in an MxN grid, where M and N are integers and at least one of M and N is greater than 1.

27. The system according to any one of claims 19 to 25, wherein the plurality of heterojunction devices are arranged in a tessellating pattern.

28. A method of making a heterojunction device comprising: forming a Ill-nitride semiconductor region above a substrate, the Ill-nitride semiconductor region comprising a heterojunction, wherein the heterojunction comprises at least one two-dimensional carrier gas; forming a drain terminal operatively connected to the Ill-nitride semiconductor region; forming a gate terminal positioned over the Ill-nitride semiconductor region, the gate terminal surrounding and spaced apart from drain terminal in a lateral dimension; and forming a source terminal surrounding and spaced apart from the gate terminal in the lateral dimension, the source terminal and operatively connected to the Ill-nitride semiconductor region; wherein a perimeter of the heterojunction device forms a hexagonal shape in the lateral dimension; and a perimeter of the drain terminal is circular in the lateral dimension, or a rounded polygon in the lateral dimension.

29. A method of making a system comprising a plurality of heterojunction devices, comprising: forming a first heterojunction device according to the method claim 28; and forming a second heterojunction device according to the method claim 28; wherein the first and second heterojunction device are adjacent to one another such that they share an adjoining edge.

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