Semiconductor storage device

Abstract

An SRAM cell according to the present invention comprises: an active region (N3) in which a read drive transistor (RPD) is formed; and a power supply line (13) which is formed in a backside wiring layer, which has an overlap with the active region (N3) in plan view, and which supplies a power supply voltage VSS. A line (63) corresponding to a read bit line (RBL) is formed in a metal wiring layer.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device equipped with a nanosheet FET (Field Effect Transistor), and in particular to a layout structure of a two-port SRAM (Static Random Access Memory) cell (hereinafter, also referred to simply as a cell, as appropriate) using a nanosheet FET.

[0002] SRAMs are widely used in semiconductor integrated circuits, and include two-port SRAMs that have one write port and one read port.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Documents 1 to 3 disclose layouts of two-port SRAM cells using nanosheet FETs.

[0005] US Patent Application Publication No. 2022 / 0328499 US Patent Application Publication No. 2023 / 0017584 International Publication No. 2023 / 171452

[0006] In Patent Documents 1 and 2, the read bit line and the write bit line are provided in the same wiring layer, so the wiring width of the bit line cannot be increased. This increases the wiring resistance of the bit line, reducing the operating speed of the semiconductor memory device. Furthermore, because the bit line and the power supply wiring are provided in the same wiring layer, the wiring width of the power supply wiring cannot be increased. This increases the wiring resistance of the power supply wiring and increases the power supply voltage drop, reducing the operating speed and stability of the semiconductor memory device. Furthermore, the distance between the bit line and the power supply wiring is short, so parasitic capacitance increases, reducing the operating speed of the semiconductor memory device.

[0007] In addition, in Patent Document 3, the read bit line, write bit line, and power supply wiring are provided separately in the buried wiring layer and the upper wiring layer, thereby increasing the wiring width of the wiring provided in the upper wiring layer. However, since the wiring in the buried wiring layer cannot be provided overlapping with the transistor (nanosheet), the wiring width of the wiring formed in the buried wiring layer cannot be increased. This increases the wiring resistance and reduces the operating speed of the semiconductor memory device.

[0008] The present disclosure aims to improve the operating speed of a semiconductor memory device in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor.

[0009] In a first aspect of the present disclosure, there is provided a semiconductor memory device including an SRAM cell, wherein the SRAM cell includes a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first write bit line, a drain connected to the first node, and a gate connected to a write word line; a sixth transistor having a source connected to a second write bit line that forms a complementary bit line pair with the first write bit line, a drain connected to the second node, and a gate connected to the write word line; and an eighth transistor having a source connected to a read bit line, a drain connected to the drain of the seventh transistor, and a gate connected to a read word line, the read bit line being formed in a metal wiring layer above the first to eighth transistors, extending in a first direction, and including a first wiring connected to the source of the eighth transistor. The SRAM cell comprises: a first active region constituting the channel, source, and drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping with the first active region in a plan view, and connected to the second power supply; and a first via formed in a region in the first active region where a region serving as the source of the seventh transistor overlaps with the first power supply wiring, and connecting the source of the seventh transistor in the first active region to the first power supply wiring.

[0010] According to the present disclosure, a first power supply wiring connected to a second power supply is formed in a back wiring layer. A first wiring corresponding to a lead bit line is formed in the metal wiring layer. This allows the wiring width of the first wiring formed in the metal wiring layer to be increased. Therefore, the wiring resistance of the bit line can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the first power supply wiring formed in the buried wiring layer can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, thereby suppressing a power supply voltage drop, thereby improving the operating speed and operational stability of the semiconductor memory device. Furthermore, since the bit line and the power supply wiring are formed in different wiring layers, the distance between the bit line and the power supply wiring can be increased. Therefore, parasitic capacitance between the bit line and the power supply wiring can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, by forming a first power supply wiring connected to a second power supply in the back wiring layer, each transistor constituting an SRAM cell can be arranged to overlap with the first power supply wiring. This allows the wiring width of the first power supply wiring formed in the back wiring layer to be increased. Therefore, the wiring resistance of the wiring formed in the back wiring layer can be reduced, thereby improving the operating speed and operational stability of the semiconductor memory device.

[0011] In a second aspect of the present disclosure, there is provided a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first write bit line, a drain connected to the first node, and a gate connected to a write word line; a sixth transistor having a source connected to a second write bit line that forms a complementary bit line pair with the first write bit line, a drain connected to the second node, and a gate connected to the write word line; The SRAM cell comprises a seventh transistor having a gate connected to the second node, and an eighth transistor having a source connected to a read bit line, a drain connected to the drain of the seventh transistor, and a gate connected to a read word line, wherein a first power supply wiring extending in a first direction and connected to the second power supply and the source of the seventh transistor is formed in a metal wiring layer above the first to eighth transistors, the first power supply wiring being formed in a back wiring layer which is a wiring layer on the back side of the first to eighth transistors and including a first wiring extending in the first direction, and the SRAM cell comprises a first active region which constitutes the channel, source, and drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction, and a first via which is formed in a region in the first active region where a region which becomes the source of the eighth transistor overlaps with the first power supply wiring and which connects the source of the eighth transistor in the first active region to the first power supply wiring.

[0012] According to the present disclosure, first wiring corresponding to the read bit lines is formed in the back wiring layer. First power supply wiring connected to a second power supply is formed in the metal wiring layer. This allows the wiring width of the first wiring formed in the back wiring layer to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the first power supply wiring formed in the metal wiring layer can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, thereby suppressing a power supply voltage drop, thereby improving the operating speed and operating stability of the semiconductor memory device. Furthermore, since the bit lines and the power supply wiring are formed in different wiring layers, the distance between the bit lines and the power supply wiring can be increased. Therefore, parasitic capacitance between the bit lines and the power supply wiring can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, by forming first wiring corresponding to the read bit lines in the back wiring layer, the first wiring can be arranged to overlap each transistor constituting the SRAM cell. This allows the wiring width of the first wiring formed in the back wiring layer to be increased. Therefore, the wiring resistance of the wiring formed in the back wiring layer can be reduced, thereby improving the operating speed and operating stability of the semiconductor memory device.

[0013] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, the operating speed and stability of a semiconductor memory device are improved.

[0014] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment; 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 3 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 4 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment; 5 is another configuration example of a semiconductor integrated circuit device according to the first embodiment; 6 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 7 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 8 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment;

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells, and at least some of the plurality of SRAM cells include nanosheet FETs. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In the present disclosure, the transistor included in the SRAM cell is not limited to a nanosheet FET.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0017] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and Figure 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. Figure 2(a) is a cross-section along line X1-X1', Figure 2(b) is a cross-section along line X2-X2', Figure 2(c) is a cross-section along line X3-X3', Figure 3(a) is a cross-section along line X4-X4', and Figure 3(b) is a cross-section along line X5-X5'.

[0018] In the following description, in plan views such as FIG. 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction.

[0019] 4 is a circuit diagram showing the configuration of a two-port SRAM cell according to the first embodiment. As shown in FIG. 4, the two-port SRAM cell has a two-port memory cell circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD, and read access transistor RPG. The load transistors PU1 and PU2 are P-type FETs, while the drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD, and read access transistor RPG are N-type FETs.

[0020] The load transistor PU1 is provided between the power supply voltage VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply voltage VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0021] The access transistor PG1 is provided between the write bit line WBL and the first node NA, and its gate is connected to the write word line WWL. The access transistor PG2 is provided between the write bit line WBLB and the second node NB, and its gate is connected to the write word line WWL. The write bit lines WBL and WBLB form a complementary write bit line pair.

[0022] The read drive transistor RPD has a source connected to the power supply VSS, a gate connected to the second node NB, and a drain connected to the source of the read access transistor RPG, whose gate is connected to the read word line RWL and whose drain is connected to the read bit line RBL.

[0023] 4, when the write bit lines WBL, WBLB constituting a complementary write bit line pair are driven to high and low levels, respectively, and the write word line WWL is driven to high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the write bit lines WBL, WBLB are driven to low and high levels, respectively, and the write word line WWL is driven to high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the write word line WWL is driven to low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0024] Furthermore, when the read bit line RBL is precharged to a high level and the read word line RWL is driven to a high level, the state of the read bit line RBL is determined according to the data written to the second node NB, making it possible to read data from the memory cell. Specifically, when the second node NB is at a high level, the read bit line RBL is discharged to a low level. On the other hand, when the second node NB is at a low level, the read bit line RBL is maintained at a high level.

[0025] As described above, the 2-port SRAM cell has the functions of writing data to the 2-port SRAM cell, holding data, and reading data from the 2-port SRAM cell by controlling the write bit lines WBL, WBLB, read bit line RBL, write word line WWL, and read word line RWL.

[0026] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 1 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0027] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0028] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell inverted in the Y direction.

[0029] As shown in FIG. 1B, the backside of the semiconductor chip on which the transistors are formed has a BM0 (Backside Metal 0) wiring layer and a BM1 (Backside Metal 1) wiring layer. The BM1 wiring layer is located below the BM0 wiring layer, i.e., farther from the transistors. The BM0 wiring layer and the BM1 wiring layer correspond to backside wiring layers.

[0030] The BM0 wiring layer is formed with power supply wirings 11 to 13 that extend in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 11 supplies the power supply voltage VDD. The power supply wiring 12 is formed at the left end of the drawing in the X direction and supplies the power supply voltage VSS. The power supply wiring 13 is formed at the right end of the drawing in the X direction and supplies the power supply voltage VSS. The power supply wiring 12 is shared with other cells arranged on the left side of the drawing. The power supply wiring 13 is shared with other cells arranged on the right side of the drawing.

[0031] The BM1 wiring layer is formed with a power supply wiring 121 extending in the X direction from both the left and right ends of the cell. The power supply wiring 121 supplies a power supply voltage VSS. The power supply wiring 121 is connected to the power supply wiring 12 through a via 131 and to the power supply wiring 13 through a via 132.

[0032] A plurality of active regions that form the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, active regions N1 to N3 are formed in the N-type transistor region. Active region N1 overlaps with power supply wiring 12 in a plan view. Active region N3 overlaps with power supply wiring 13 in a plan view.

[0033] In the N-type transistor region, drive transistors PD1 and PD2, access transistors PG1 and PG2, read drive transistor RPD, and read access transistor RPG are formed. The access transistor PG2, drive transistors PD2 and PD1, access transistor PG1, read drive transistor RPD, and read access transistor RPG each have a channel structure of three overlapping sheets in a plan view, and each have nanosheets 21 to 26 extending in the Y direction.

[0034] In the active region N1, the portion that becomes the source of the drive transistor PD2 is connected to the power supply wiring 12 through a via 91 that is provided at a position that overlaps the power supply wiring 12 in a plan view. In the active region N3, the portion that becomes the source of the read drive transistor RPD is connected to the power supply wiring 13 through a via 92 that is provided at a position that overlaps the power supply wiring 13 in a plan view.

[0035] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in a plan view.

[0036] In the P-type transistor region, load transistors PU1 and PU2 are formed. The load transistors PU1 and PU2 have channels formed of three overlapping sheets in a plan view, and have nanosheets 27 and 28 extending in the Y direction, respectively. In other words, the load transistors PU1 and PU2 are nanosheet FETs.

[0037] The width of the nanosheets 21 to 26 in the X direction is twice the width of the nanosheets 27 and 28 in the X direction.

[0038] In the active region P1, the portion that becomes the source of the load transistor PU1 is connected to the power supply wiring 11 through a via 93 that is provided at a position that overlaps the power supply wiring 11 in a planar view. In the active region P2, the portion that becomes the source of the load transistor PU2 is connected to the power supply wiring 11 through a via 94 that is provided at a position that overlaps the power supply wiring 11 in a planar view.

[0039] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0040] As shown in FIG. 1B, gate wirings (Gate) 31 to 35 are formed extending in the X direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21 in the X and Z directions. The gate wiring 32 surrounds the outer periphery of the nanosheets 27, 23, and 25 in the X and Z directions. The gate wiring 33 surrounds the outer periphery of the nanosheets 22 and 28 in the X and Z directions. The gate wiring 34 surrounds the outer periphery of the nanosheet 24 in the X and Z directions. The gate wiring 35 surrounds the outer periphery of the nanosheet 26 in the X and Z directions. The gate wiring 31 corresponds to the gate of the access transistor PG2. The gate wiring 32 corresponds to the gates of the load transistor PU1, the drive transistor PD1, and the read drive transistor RPD. The gate wiring 33 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 34 corresponds to the gate of the access transistor PG1. The gate wiring 35 corresponds to the gate of the read access transistor RPG.

[0041] The local interconnect layer is formed with local interconnects (LI) 41-50 extending in the X direction. Local interconnect 41 is connected to a portion that will become the source of access transistor PG2 in active region N1. Local interconnect 42 is connected to a portion that will become the source of load transistor PU1 in active region P1. Local interconnect 43 is connected to a portion that will become the source of drive transistor PD1 in active region N2 and a portion that will become the source of read drive transistor RPD in active region N3. Local interconnect 44 is connected to a portion that will become the drain of access transistor PG2 in active region N1, a portion that will become the drain of drive transistor PD2 in active region N1, and a portion that will become the drain of load transistor PU2 in active region P2. Local interconnect 45 is connected to a portion that will become the drain of load transistor PU1 in active region P1, a portion that will become the drain of drive transistor PD1 in active region N2, and a portion that will become the drain of access transistor PG1 in active region N2. Local wiring 46 is connected to the drain of read drive transistor RPD in active region N3 and the drain of read access transistor RPG in active region N3. Local wiring 47 is connected to the source of drive transistor PD2 in active region N1. Local wiring 48 is connected to the source of load transistor PU2 in active region P2. Local wiring 49 is connected to the source of access transistor PG1 in active region N2. Local wiring 50 is connected to the source of read access transistor RPG in active region N3.

[0042] The local wiring 44 is connected to the gate wiring 32 via a shared contact 51. The local wiring 45 is connected to the gate wiring 33 via a shared contact 52. The gate wiring 33, the local wiring 45, and the shared contact 52 correspond to a first node NA. The gate wiring 32, the local wiring 44, and the shared contact 51 correspond to a second node NB.

[0043] As shown in FIG. 1A, wires 61 to 63 extending in the Y direction from the top to the bottom of the cell are formed in the M1 wiring layer, which is a metal wiring layer above the local wiring layer. Wires 64 to 66 are also formed. Wires 61 to 63 correspond to write bit lines WBLB and WBL and read bit line RBL, respectively. Wire 61 overlaps with active region N1 and power supply wiring 12 in a planar view. Wire 62 overlaps with active regions P1 and N2 and power supply wiring 11 in a planar view. Wire 63 overlaps with active region N3 and power supply wiring 13 in a planar view.

[0044] The wiring 61 is connected to the local wiring 41 through a via 53. The wiring 62 is connected to the local wiring 49 through a via 54. The wiring 63 is connected to the local wiring 50 through a via 55.

[0045] Wirings 71 and 72 extending in the X direction from the left to the right of the cell in the drawing are formed in the M2 wiring layer, which is a layer above the M1 wiring layer. The wirings 71 and 72 correspond to the write word line WWL and the read word line RWL, respectively. The wiring 71 is connected to the gate wiring 31 via a via 81, a wiring 64, and a via 56. The wiring 71 is connected to the gate wiring 34 via a via 82, a wiring 65, and a via 57. The wiring 72 is connected to the gate wiring 35 via a via 83, a wiring 66, and a via 58.

[0046] With the above configuration, a power supply wiring 11 that supplies a power supply voltage VDD and power supply wirings 12 and 13 that supply a power supply voltage VSS are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. Wirings 61 to 63 corresponding to the write bit lines WBLB and WBL and the read bit line RBL, respectively, are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, the wiring formed in the M1 wiring layer is only the bit lines, so the wiring width of the wirings 61 to 63 can be increased. Therefore, the wiring resistance of the bit lines can be reduced, and the operating speed of the semiconductor memory device can be improved. Furthermore, since the wiring formed in the BM0 wiring layer is only the power supply wiring that supplies the power supply voltages VDD and VSS, the wiring width of the power supply wirings 11 to 13 can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and a power supply voltage drop can be suppressed, thereby improving the operating speed and operating stability of the semiconductor memory device. Furthermore, since the bit lines and the power supply wiring are formed in different wiring layers, the distance between the bit lines and the power supply wiring can be increased. Therefore, parasitic capacitance between the bit lines and the power supply wiring can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, by forming the power supply wiring 11 that supplies the power supply voltage VDD and the power supply wirings 12 and 13 that supply the power supply voltage VSS in the BM0 wiring layer, which is the backside wiring layer, the transistors that constitute the SRAM cell can be arranged to overlap with the power supply wirings 11 to 13. This allows the wiring width of the power supply wirings 11 to 13 formed in the BM0 wiring layer to be increased. Therefore, the wiring resistance of the wiring formed in the BM0 wiring layer can be reduced. Furthermore, since the power supply wirings 11 to 13 and the transistors that constitute the SRAM cell can be connected through vias formed in the overlapping region, the resistance from the power supply wiring to the transistors can be reduced. Therefore, the operating speed of the semiconductor memory device can be improved. Furthermore, by increasing the wiring width of the power supply wirings 11 to 13, the wiring resistance of the wiring that supplies the power supply voltages VDD and VSS can be reduced, thereby improving the stability of operation, particularly the retention characteristics (static noise margin) of the SRAM cell.

[0047] (Another Configuration Example) Fig. 5(a) shows another configuration example of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power supply wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0048] 5B shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 that supplies VDD and power supply wirings 12 and 13 that supply VSS are formed in a wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active region P1 of chip A via via 93. Power supply wiring 13 is connected to active region N3 of chip A via via 92. Although not shown in the figure, power supply wiring 12 is connected to active region N1 of chip A via via 91. Power supply wiring 11 is connected to active region P2 of chip A via via 94.

[0049] 6A and 6B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 6A shows the upper part of the cell, and Fig. 6B shows the lower part of the cell.

[0050] 6, the width of the power supply wiring 13 in the X direction is larger than that in FIG. 1. Specifically, the power supply wiring 13 overlaps with the wirings 62 and 63 and the active regions N2 and N3 in a plan view. The power supply wiring 13 is also connected to the source of the drive transistor PD1 in the active region N2 through a via 95 provided at the overlapping position in a plan view.

[0051] 6, the width of the power supply wiring 13 in the X direction is increased, so that the power supply voltage VSS supplied to the SRAM cell can be strengthened, thereby improving the operating speed of the semiconductor memory device.

[0052] In addition, the same effects as those in FIG. 1 can be obtained.

[0053] In this modification, the via 95 may be omitted.

[0054] 7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 7A shows the upper part of the cell, and Fig. 7B shows the lower part of the cell.

[0055] 7, compared to FIG. 1, the power supply wiring 14 for the cell is formed in the BM0 wiring layer, extending in the Y direction across both the top and bottom of the cell in the drawing.

[0056] Specifically, power supply wiring 14 is disposed between power supply wirings 11 and 13. Power supply wiring 14 supplies a power supply voltage VSS. In a plan view, power supply wiring 14 overlaps with active region N2 and wiring 62. Power supply wiring 14 is connected to a portion of active region N2 that serves as the source of drive transistor PD1 through a via 96 provided at a position where power supply wiring 14 overlaps with active region N2 in a plan view.

[0057] The power supply wirings 11 to 14 have the same width in the X direction (width L) and are arranged at equal intervals (intervals P) in the X direction.

[0058] In the configuration of FIG. 7, the widths of the power supply wirings 11 to 14 in the X direction are the same, and the spacing between the wirings is equal, which improves the ease of manufacturing the semiconductor memory device and the yield.

[0059] In addition, the same effects as those in FIG. 1 can be obtained.

[0060] The power supply wirings 11 to 14 may have at least one of the same width in the X direction and the same spacing between the wirings.

[0061] 8A and 8B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 8A shows the upper part of the cell, and Fig. 8B shows the lower part of the cell.

[0062] In FIG. 8, compared to FIG. 1, power supply wiring 68 is formed in the M1 wiring layer, extending in the Y direction from both the top and bottom of the cell in the drawing.

[0063] Specifically, the power supply wiring 68 is formed between the wirings 61 and 62. The power supply wiring 68 overlaps with the power supply wiring 11 in a plan view. The power supply wiring 68 is connected to a portion of the active region P1 that will become the source of the load transistor PU1 through a via 59 and a local wiring 42. The power supply wiring 68 is connected to a portion of the active region P2 that will become the source of the load transistor PU2 through a via 60 and a local wiring 48.

[0064] 8, the power supply line 68 that supplies the power supply voltage VDD suppresses crosstalk noise between the lines 61 and 62 that correspond to the write bit lines WBLB and WBL, respectively, thereby stabilizing the operation of the semiconductor memory device.

[0065] In addition, the same effects as those in FIG. 1 can be obtained.

[0066] In this modification, the power supply wiring 11 formed in the BM0 wiring layer and supplying the power supply voltage VDD may be omitted.

[0067] 9A and 9B are plan views showing another example of the layout structure of an SRAM cell according to a second embodiment. Specifically, Fig. 9A shows the upper part of the cell, and Fig. 9B shows the lower part of the cell.

[0068] 9, compared to FIG. 1, in the BM0 wiring layer, wirings 111 to 113 are formed instead of the power supply wirings 11 to 13. In addition, in the M1 wiring layer, power supply wirings 161 to 164 are formed instead of the wirings 61 to 63. In addition, the power supply wiring 121 in the BM1 wiring layer and the vias 131 and 132 connecting the power supply wiring in the BM0 wiring layer and the power supply wiring in the BM1 wiring layer are omitted.

[0069] As shown in FIG. 9B, the BM0 wiring layer is formed with wirings 111 to 113 extending in the Y direction from the top to the bottom of the cell in the drawing. The wirings 111 to 113 correspond to the write bit lines WBLB and WBL and the read bit line RBL, respectively. The wiring 111 overlaps the active region N1 in plan view. The wiring 112 overlaps the active region N2 in plan view. The wiring 113 overlaps the active region N3 in plan view.

[0070] The wiring 111 is connected to the source of the access transistor PG2 in the active region N1 through a via 191 provided at an overlapping position in a plan view. The wiring 112 is connected to the source of the access transistor PG1 in the active region N2 through a via 192 provided at an overlapping position in a plan view. The wiring 113 is connected to the source of the read access transistor RPG in the active region N3 through a via 193 provided at an overlapping position in a plan view.

[0071] As shown in FIG. 9A, power supply wiring 161-164 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer. The power supply wiring 161 supplies a power supply voltage VDD. The power supply wiring 162-164 supply a power supply voltage VSS. The power supply wiring 161 overlaps with the active regions P1 and P2 in a planar view. The power supply wiring 162 overlaps with the active region N1 and wiring 111 in a planar view. The power supply wiring 163 overlaps with the active region N2 and wiring 112 in a planar view. The power supply wiring 164 overlaps with the active region N3 and wiring 113 in a planar view.

[0072] Power supply wiring 161 is connected to the source of load transistor PU1 in active region P1 via via 151 and local wiring 42. Power supply wiring 161 is connected to the source of load transistor PU2 in active region P2 via via 152 and local wiring 48. Power supply wiring 162 is connected to the source of drive transistor PD2 in active region N1 via via 153 and local wiring 47. Power supply wirings 163 and 164 are connected to the source of drive transistor PD1 in active region N2 and the source of read drive transistor RPD in active region N3 via vias 154 and 155 and local wiring 43.

[0073] In FIG. 9 , wirings 111 to 113 corresponding to the write bit lines WBLB and WBL and the read bit line RBL, respectively, are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. A power supply wiring 161 that supplies a power supply voltage VDD and power supply wirings 161 to 164 that supply a power supply voltage VSS are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, only bit lines are formed in the BM0 wiring layer, so the wiring widths of the wirings 111 to 113 can be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, since bit lines are not required as wirings formed in the M1 wiring layer, the wiring widths of the power supply wirings 161 to 164 can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and a power supply voltage drop can be suppressed, thereby improving the operating speed and operational stability of the semiconductor memory device. Furthermore, since the bit lines and the power supply wiring are formed in different wiring layers, the distance between the bit lines and the power supply wiring can be increased. Therefore, parasitic capacitance between the bit lines and the power supply wiring can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, by forming wirings 111-113 corresponding to the write bit lines WBLB and WBL and the read bit line RBL, respectively, in the BM0 wiring layer, which is the backside wiring layer, the wirings 111-113 can be arranged to overlap each transistor constituting the SRAM cell. This allows the wiring width of the wirings 111-113 formed in the BM0 wiring layer to be increased. Therefore, the wiring resistance of the wirings formed in the BM0 wiring layer can be reduced. Furthermore, since the wirings 111-113 and the transistors constituting the SRAM cell can be connected through vias provided in the overlapping regions, the resistance from the bit lines to the transistors can be reduced. Therefore, the operating speed of the semiconductor memory device can be improved. Furthermore, increasing the wiring width of the power supply wirings 161-164 can reduce the wiring resistance of the wirings supplying the power supply voltages VDD and VSS, thereby improving the stability of operation, particularly the retention characteristics (static noise margin) of the SRAM cell.

[0074] In this embodiment, either one of the power supply wirings 163 and 164 that supply the power supply voltage VSS may be omitted.

[0075] 8, the power supply wiring for supplying the power supply voltage VDD may be formed in the BM0 wiring layer. In this case, the power supply wiring 161 formed in the M1 wiring layer for supplying the power supply voltage VDD may be omitted.

[0076] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0077] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0078] In addition, in the above-described embodiments and modifications, the width in the X direction of the nanosheets 21 to 26 is twice the width in the X direction of the nanosheets 27 and 28, but this is not limited to this. The width in the X direction of each of the nanosheets 21 to 28 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0079] In the first embodiment and the modified example described above, a power supply wiring for supplying the power supply voltage VDD may be formed in the BM1 wiring layer instead of the power supply wiring 121 for supplying the power supply voltage VSS. In this case, a via is formed in the region where the power supply wiring overlaps with the power supply wiring 11 for supplying the power supply voltage VDD in the BM0 wiring layer, and the power supply wirings are connected to each other.

[0080] In addition, in each of the above-described embodiments and modifications, the shared contacts 51 and 52 may be manufactured in the same process as the contacts (gate contacts) and local wiring, or may be manufactured in a separate process.

[0081] Furthermore, in each of the above-described embodiments and variations, the power supply that supplies the power supply voltage VDD to the sources of the load transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0082] According to the present disclosure, the operating speed of a semiconductor memory device can be improved in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor.

[0083] 11-14, 68, 161-164 Power supply wiring 91-96, 191-193 Vias 21-28 Nanosheets 31-35 Gate wiring 61-63, 111-113 Wiring PU1, PU2 Load transistor PD1, PD2 Drive transistor PG1, PG2 Access transistor RPD Read drive transistor RPG Read access transistor WBL, WBLB Write bit line RBL Read bit line WWL Write word line RWL Read word line

Claims

1. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first write bit line, a drain connected to the first node, and a gate connected to a write word line; a sixth transistor having a source connected to a second write bit line that forms a complementary bit line pair with the first write bit line, a drain connected to the second node, and a gate connected to the write word line; and a seventh transistor having a source connected to the second power supply and a gate connected to the second node. and an eighth transistor having a source connected to a read bit line, a drain connected to the drain of the seventh transistor, and a gate connected to a read word line, wherein the read bit line is formed in a metal wiring layer above the first to eighth transistors, extends in a first direction, and includes a first wiring connected to the source of the eighth transistor; and the SRAM cell comprises: a first active region constituting the channel, source, and drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping with the first active region in a planar view, and connected to the second power supply; and a first via formed in a region in the first active region where a region that becomes the source of the seventh transistor overlaps with the first power supply wiring, and connecting the source of the seventh transistor in the first active region to the first power supply wiring.

2. A semiconductor memory device according to claim 1, wherein the first active region constitutes the channel, source, and drain of the eighth transistor, and includes an eighth nanosheet extending in the first direction as the channel, and the seventh and eighth nanosheets are arranged side by side in the first direction.

3. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises: a second active region including a sixth nanosheet that forms the channel, source, and drain of the sixth transistor, the channel being extended in the first direction; and a fourth nanosheet that forms the channel, source, and drain of the fourth transistor, the channel being extended in the first direction; a second power supply wiring that is formed in the back wiring layer, extends in the first direction, overlaps with the second active region in a planar view, and is connected to the second power supply; and a second via that is formed in a region where a region in the second active region that becomes the source of the fourth transistor overlaps with the second power supply wiring, and connects the source of the fourth transistor in the second active region to the second power supply wiring, and the fourth and sixth nanosheets are aligned in the first direction.

4. A semiconductor memory device according to claim 1, wherein the first write bit line is formed in the metal wiring layer, extends in the first direction, and includes a second wiring connected to the source of the fifth transistor, and the second write bit line is formed in the metal wiring layer, extends in the first direction, and includes a third wiring connected to the source of the sixth transistor.

5. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises: a third active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; a third power supply wiring formed in the backside wiring layer, extending in the first direction, overlapping the third and fourth active regions in a planar view, and connected to the first power supply; a third via formed in a region in the third active region where a region serving as the source of the first transistor overlaps with the third power supply wiring, connecting the source of the first transistor in the third active region to the third power supply wiring; and a fourth via formed in a region in the fourth active region where a region serving as the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the fourth active region to the third power supply wiring.

6. A semiconductor memory device according to claim 1, wherein the metal wiring layer is formed with a fourth power supply wiring extending in the first direction and connected to the first power supply, and the fourth power supply wiring is connected to the source of the first transistor and the source of the second transistor.

7. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises a fifth active region including a third nanosheet that forms the channel, source, and drain of the third transistor and extends in the first direction as the channel, and a fifth nanosheet that forms the channel, source, and drain of the fifth transistor and extends in the first direction as the channel, and the third and fifth nanosheets are arranged side by side in the first direction.

8. A semiconductor memory device according to claim 7, wherein the first power supply wiring overlaps with the fifth active region in a planar view, the SRAM cell is formed in a region where a region serving as the source of the third transistor in the fifth active region overlaps with the first power supply wiring, and the semiconductor memory device is provided with a fifth via that connects the source of the third transistor in the fifth active region with the first power supply wiring.

9. A semiconductor memory device according to claim 7, wherein the SRAM cell comprises: a fifth power supply wiring formed in the back wiring layer, extending in the first direction, overlapping the fifth active region in a plan view, and connected to the second power supply; and a sixth via formed in a region in the fifth active region where a region serving as the source of the third transistor overlaps with the fifth power supply wiring, connecting the source of the third transistor in the fifth active region to the fifth power supply wiring.

10. A semiconductor memory device according to claim 9, wherein the SRAM cell comprises: a second active region constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction, and a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; a second power supply wiring formed in the back wiring layer, extending in the first direction, overlapping the second active region in a plan view, and connected to the second power supply; and a third power supply wiring formed in the back wiring layer, extending in the first direction, overlapping the third and fourth active regions in a plan view, and connected to the first power supply. a second via formed in a region in the second active region where a region that will become the source of the fourth transistor overlaps with the second power supply wiring, connecting the source of the fourth transistor in the second active region with the second power supply wiring; a third via formed in a region in the third active region where a region that will become the source of the first transistor overlaps with the third power supply wiring, connecting the source of the first transistor in the third active region with the third power supply wiring; and a fourth via formed in a region in the fourth active region where a region that will become the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the fourth active region with the third power supply wiring, wherein the first, second, third, and fifth power supply wirings have the same width in a second direction perpendicular to the first direction.

11. A semiconductor memory device according to claim 9, wherein the SRAM cell comprises: a second active region constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction, and a fourth nanosheet constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; a second power supply wiring formed in the back wiring layer, extending in the first direction, overlapping the second active region in a planar view, and connected to the second power supply; and a third power supply wiring formed in the back wiring layer, extending in the first direction, overlapping the third and fourth active regions in a planar view, and connected to the first power supply. a second via formed in a region in the second active region where a region that will become the source of the fourth transistor overlaps with the second power supply wiring, connecting the source of the fourth transistor in the second active region with the second power supply wiring; a third via formed in a region in the third active region where a region that will become the source of the first transistor overlaps with the third power supply wiring, connecting the source of the first transistor in the third active region with the third power supply wiring; and a fourth via formed in a region in the fourth active region where a region that will become the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the fourth active region with the third power supply wiring, wherein the first, second, third, and fifth power supply wirings are arranged at equal intervals in a second direction perpendicular to the first direction.

12. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first write bit line, a drain connected to the first node, and a gate connected to a write word line; a sixth transistor having a source connected to a second write bit line that forms a complementary bit line pair with the first write bit line, a drain connected to the second node, and a gate connected to the write word line; and a seventh transistor having a source connected to the second power supply and a gate connected to the second node. and an eighth transistor having a source connected to a read bit line, a drain connected to the drain of the seventh transistor, and a gate connected to a read word line, wherein a first power supply wiring extending in a first direction and connected to the second power supply and the source of the seventh transistor is formed in a metal wiring layer above the first to eighth transistors, the read bit line is formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, and includes a first wiring extending in the first direction, wherein the SRAM cell comprises: a first active region that constitutes the channel, source, and drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction, and a first via that is formed in a region in the first active region where a region that becomes the source of the eighth transistor overlaps with the first wiring, and that connects the source of the eighth transistor in the first active region to the first wiring.

13. A semiconductor memory device according to claim 12, wherein the first write bit line is formed in the backside wiring layer and includes a second wiring extending in the first direction, and the SRAM cell comprises: a fifth active region that constitutes the channel, source, and drain of the third transistor, the channel including a third nanosheet extending in the first direction; and a second via that is formed in a region in the fifth active region where the region that becomes the source of the fifth transistor overlaps with the second wiring, and that connects the source of the fifth transistor in the fifth active region to the second wiring.

14. A semiconductor memory device according to claim 12, wherein the second write bit line is formed in the back wiring layer and includes a third wiring extending in the first direction, and the SRAM cell comprises: a second active region that constitutes the channel, source, and drain of the sixth transistor, the channel including a sixth nanosheet extending in the first direction; and a third via that is formed in a region in the second active region where the region that becomes the source of the sixth transistor overlaps with the third wiring, and that connects the source of the sixth transistor in the second active region to the third wiring.

15. A semiconductor memory device according to claim 12, wherein the SRAM cell comprises: a third active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; a second power supply wiring formed in the backside wiring layer, extending in the first direction, overlapping the third and fourth active regions in a planar view, and connected to the first power supply; a fourth via formed in a region in the third active region where the region serving as the source of the first transistor overlaps with the second power supply wiring, connecting the source of the first transistor in the third active region to the second power supply wiring; and a fifth via formed in a region in the fourth active region where the region serving as the source of the second transistor overlaps with the second power supply wiring, connecting the source of the second transistor in the fourth active region to the second power supply wiring.

16. A semiconductor memory device according to claim 12, wherein a third power supply wiring extending in the first direction and connected to the first power supply is formed in the metal wiring layer, and the third power supply wiring is connected to the source of the first transistor and the source of the second transistor.

17. A semiconductor memory device according to claim 12, wherein the metal wiring layer is formed with a fourth power supply wiring that extends in the first direction and is connected to the second power supply, the metal wiring layer is formed with a fifth power supply wiring that extends in the first direction and is connected to the second power supply, the fourth power supply wiring is connected to the source of the fourth transistor, and the fifth power supply wiring is connected to the source of the third transistor.

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