Semiconductor storage device

Abstract

To suppress bending of a plurality of insulating layers.SOLUTION: A semiconductor storage device according to an embodiment comprises: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; a pillar including a channel layer extending in the stacked body along a stacking direction of the stacked body; a contact provided in a region of the stacked body different from an arrangement region of the pillar and connected to one of the plurality of conductive layers; and a plurality of columnar portions provided at a predetermined distance from the contact so as to surround the contact and extending in the stacked body along the stacking direction. Among the plurality of insulating layers, each insulating layer positioned in a region including the contact and surrounded by the plurality of columnar portions has, at least in a part thereof, at least one of a higher Young's modulus, lower compressive stress, and higher tensile stress than each insulating layer in the arrangement region of the pillar.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as three-dimensional nonvolatile memories, multiple sacrificial layers are sometimes stacked and replaced with multiple conductive layers, which can cause the multiple insulating layers interposed between the multiple sacrificial layers to bend. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-102663 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device that can suppress bending of a plurality of insulating layers. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment comprises a stack of alternating conductive layers and insulating layers, a pillar including a channel layer extending through the stack in the stacking direction of the stack, a contact provided in a region of the stack different from the pillar arrangement region and connected to one of the conductive layers, and a plurality of columnar portions provided a predetermined distance from the contact so as to surround the contact and extending through the stack in the stacking direction, and among the plurality of insulating layers, an insulating layer located in a region surrounded by the plurality of columnar portions and including the contact has, at least in part, at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer in the pillar arrangement region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Figure 3] FIG. 1 is a diagram showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Figure 4] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 16] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 17] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 18] FIG. 10 is a cross-sectional view taken along the X direction, showing an example of the configuration of a semiconductor memory device according to a first modification of the first embodiment. [Figure 19] 5A to 5C are cross-sectional views illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a first modification of the first embodiment. [Figure 20] 5A to 5C are cross-sectional views illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a first modification of the first embodiment. [Figure 21] 10 is a cross-sectional view taken along the X direction, showing an example of the configuration of a semiconductor memory device according to a second modification of the first embodiment. FIG. [Figure 22] 10A to 10C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to a second modification of the first embodiment. [Figure 23] FIG. 10 is a cross-sectional view taken along the X direction, showing an example of the configuration of a semiconductor memory device according to a second embodiment. [Figure 24] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 25] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 26] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 27] FIG. 10 is a cross-sectional view taken along the X direction, showing an example of the configuration of a semiconductor memory device a according to Modification 1 of Embodiment 2. [Figure 28] 10A and 10B are diagrams illustrating a part of the procedure of a method for manufacturing a semiconductor memory device according to a first modification of the second embodiment. [Figure 29] FIG. 10 is a cross-sectional view taken along the X direction, showing an example of the configuration of a semiconductor memory device according to a first modification of the second embodiment. [Figure 30] 10A and 10B are diagrams illustrating a part of the procedure of a method for manufacturing a semiconductor memory device according to a second modification of the second embodiment. [Figure 31] FIG. 10 is a cross-sectional view taken along the X direction, showing an example of the configuration of a semiconductor memory device according to a third modification of the second embodiment. [Figure 32]FIG. 10 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] [Embodiment 1] Hereinafter, the first embodiment will be described in detail with reference to the drawings.

[0009] (Configuration example of semiconductor memory device) 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device 1 according to embodiment 1. However, hatching is omitted in FIG. 1 to make the drawing easier to read.

[0010] 1, the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, and a plurality of word lines WL. The semiconductor memory device 1 also includes a peripheral circuit CBA provided on a semiconductor substrate SB above the plurality of word lines WL.

[0011] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and the source line SL and the electrode film EL are kept electrically conductive via the plugs PG. This allows a source potential to be applied to the source line SL from outside the semiconductor memory device 1 via the electrode film EL and the plugs PG.

[0012] A plurality of word lines WL are stacked on the source line SL. A memory region MR is arranged in the center of the plurality of word lines WL, and contact regions ER are arranged at both ends of the plurality of word lines WL.

[0013] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL in the stacking direction. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0014] In the contact region ER, a plurality of contacts CC are arranged, each connected to a corresponding one of the plurality of word lines WL. In this specification, the connection end of the contact CC with the word line WL in the extension direction of the contacts CC is defined as the lower side of the semiconductor memory device 1.

[0015] From the contacts CC, write voltages, read voltages, etc. are applied to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL at the same height as the memory cells. In this way, the word lines WL stacked in multiple layers are individually drawn out by these contacts CC.

[0016] The word lines WL, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around the word lines WL.

[0017] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0018] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 covering the laminate LM, a semiconductor memory device 1 is formed that includes a configuration of multiple word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0019] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Figures 2 and 3. Figures 2 and 3 are diagrams showing an example of the configuration of the semiconductor memory device 1 according to the first embodiment.

[0020] More specifically, Fig. 2(a) is a cross-sectional view along the Y direction showing an example of the configuration of the memory region MR. Fig. 2(b) is an enlarged cross-sectional view of a pillar PL arranged in the memory region MR at the height of the word lines WL. Fig. 2(c) is an enlarged cross-sectional view of a pillar PL arranged in the memory region MR at the height of the select gate lines SGD, SGS.

[0021] FIG. 3 is a cross-sectional view taken along the X direction, showing an example of the configuration of the contact region ER.

[0022] However, in FIGS. 2(a) and 3, the structure below the insulating layer 60 and above the insulating layer 40 are omitted.

[0023] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0024] As shown in FIG. 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, a middle source line BSL, and an upper source line DSLb are stacked on an insulating layer 60 in this order.

[0025] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0026] A laminate LM is disposed on the source line SL. The laminate LM includes laminates LMa and LMb, each of which is formed by alternately stacking a plurality of word lines WL and a plurality of insulating layers OL. The laminate LMa, serving as a first laminate, is disposed above the source line SL, and the laminate LMb, serving as a second laminate, is disposed on the laminate LMa.

[0027] One or more select gate lines SGS are arranged below the word line WL in the bottom layer of the stacked body LMa, with an insulating layer OL interposed between them. In the example of FIG. 2(a), the stacked body LMa includes two select gate lines SGS0 and SGS1 in order from the top layer side. One or more select gate lines SGD are arranged above the word line WL in the top layer of the stacked body LMb, with an insulating layer OL interposed between them. In the example of FIG. 2(a), the stacked body LMb includes two select gate lines SGD0 and SGD1 in order from the top layer side.

[0028] However, the number of stacked layers of these word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary.

[0029] The word lines WL and select gate lines SGD, SGS as the plurality of conductive layers are, for example, tungsten layers or molybdenum layers, etc. The plurality of insulating layers OL are, for example, silicon oxide layers, etc.

[0030] The uppermost insulating layer OL of each of the laminates LMa and LMb is thicker than the other insulating layers OL in the laminates LMa and LMb. The uppermost insulating layer OL of the laminate LMa contacts the lowermost word line WL of the laminate LMb, and insulating layers 52 and 53 are disposed in this order on the uppermost insulating layer OL of the laminate LMb. The insulating layers 52 and 53 form part of the insulating layer 50, and the upper surface of the insulating layer 53 contacts, for example, the lower surface of the insulating layer 40 on the peripheral circuit CBA side.

[0031] The laminated body LM is divided in the Y direction by a plurality of plate-like contacts LI.

[0032] That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the laminate LM. In this way, the plate-shaped contacts LI extend continuously within the laminate LM from one end to the other end in the X direction of the laminate LM. Furthermore, the plate-shaped contacts LI penetrate the laminate LM and the upper source line DSLb to reach the intermediate source line BSL.

[0033] Each of the plate-shaped contacts LI includes an insulating layer 55 and a conductive layer 25. The insulating layer 55 is, for example, a silicon oxide layer, etc. The conductive layer 25 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0034] The insulating layer 55 covers the side walls of the plate contact LI facing each other in the Y direction. The conductive layer 25 is filled inside the insulating layer 55 and is electrically connected to the source lines SL including the intermediate source line BSL. The conductive layer 25 is also connected to the upper layer wiring at a cross section different from that shown in FIG. 2(a). With this configuration, the plate contact LI functions as a source line contact.

[0035] However, instead of the plate-shaped contacts LI, plate-shaped members filled with an insulating layer may penetrate the laminate LM and extend in the X direction, thereby dividing the laminate LM in the Y direction. In this case, such plate-shaped members do not function as source line contacts.

[0036] A plurality of isolation layers SHE are disposed between the plate contacts LI adjacent in the Y direction. These isolation layers SHE penetrate the select gate lines SGD0 and SGD1 of the stacked body LMb, reach the insulating layer OL immediately below the select gate line SGD1, and are insulating layers 57 such as silicon oxide layers that extend in the X direction within the memory region MR of the stacked body LM. With this configuration, the isolation layers SHE selectively isolate the select gate lines SGD0 and SGD1 between the plate contacts LI in the Y direction.

[0037] In the memory region MR of the laminate LM, a plurality of pillars PL are dispersedly arranged, passing through the laminate LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0038] The pillars PL are periodically arranged, for example, in a staggered pattern, when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval shape, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0039] The pillars PL include pillars PLa that extend from the top insulating layer OL of the laminate LMa through the laminate LMa to reach the source line SL, and pillars PLb that extend from the top insulating layer OL of the laminate LMb through the laminate LMb to reach the top insulating layer OL of the laminate LMa and are connected to the upper ends of the corresponding pillars PLa.

[0040] Each of the pillars PL has a memory layer ME extending in the stacking direction within the stacked body LM, a channel layer CN penetrating the stacked body LM and connecting to the intermediate source line BSL, and a core layer CR that serves as the core material of the pillar PL.

[0041] The memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL that reaches the depth of the lower source line DSLa.

[0042] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the middle source line BSL inside the memory layer ME, and reaches the depth of the lower source line DSLa. That is, the channel layer CN is disposed on the side and bottom surfaces of the pillar PL via the memory layer ME. A core layer CR is filled further inside the channel layer CN.

[0043] However, a part of the channel layer CN is in contact with the intermediate source line BSL at its side, and is thereby electrically connected to the source lines SL including the intermediate source line BSL. In addition, the upper end of the channel layer CN is connected to the bit line BL extending in the Y direction in the insulating layer 53 via a plug CH arranged in the insulating layer 52.

[0044] As shown in FIGS. 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery side of the pillar PL.

[0045] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN is, for example, a semiconductor layer such as a polysilicon layer or an amorphous silicon layer.

[0046] As shown in Figure 2(b), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL in portions facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0047] Data from the memory cells MC is read out to bit lines BL connected to the pillars PL. The bit lines BL are connected to electrode pads PDb arranged on the surface of the insulating layer 53. The electrode pads PDb are connected to electrode pads PDc arranged on the surface of the insulating layer 40 and electrically connected to the peripheral circuit CBA. As a result, the data of the memory cells MC read out to the bit lines BL is processed by the peripheral circuit CBA.

[0048] 2(c), with the above configuration, select gates STD are formed on the side of the pillar PL in portions facing the select gate lines SGD. Also, select gates STS are formed on the side of the pillar PL in portions facing the select gate lines SGS. When a predetermined voltage is applied from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC formed in the pillar PL to which these select gates STD and STS belong are selected or unselected.

[0049] As shown in FIG. 3, in the contact region ER, the source line SL has an intermediate insulating layer SCO between the lower source line DSLa and the upper source line DSLb instead of an intermediate source line BSL. This is because the pillar PL to which the source line SL is connected is not arranged in the contact region ER. The intermediate insulating layer SCO is, for example, a silicon oxide layer. However, the source line SL may also have an intermediate source line BSL in the contact region ER.

[0050] Furthermore, in the contact region ER, the laminate LM is provided with a plurality of insulating layers OLc having at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the plurality of insulating layers OL in the memory region MR. As will be described later, these insulating layers OLc are formed by ion-implanting at least one of carbon and nitrogen into the insulating layers OL in the contact region ER after the plurality of insulating layers OL are formed across the memory region MR and the contact region ER.

[0051] That is, the insulating layers OL and OLc in the memory region MR and the contact region ER are both, for example, silicon oxide layers, and the insulating layer OLc in the contact region ER contains, for example, at least one of carbon and nitrogen as a dopant. Note that, when carbon is contained in the insulating layer OLc, the carbon concentration is preferably, for example, 0.5 atomic % or more, more preferably 1.5 atomic % or more.

[0052] In addition, a plurality of contacts CC and a plurality of columnar portions HR are arranged in the contact region ER.

[0053] The contacts CC as first contacts extend within the stacked body LMb in the stacking direction of the stacked body LM, and are respectively connected to one or more select gate lines SGD or a plurality of word lines WL included in the stacked body LMb.

[0054] The contacts CC as second contacts extend through the stacks LMa and LMb in the stacking direction of the stack LM and are connected to one of the word lines WL belonging to the stack LMa. Although not shown, the contacts CC as second contacts are also connected to one or more select gate lines SGS of the stack LMa.

[0055] The upper ends of these contacts CC are disposed in, for example, the uppermost insulating layer OLc of the laminated body LMb, and the lower ends of these contacts CC reach the word lines WL or select gate lines SGD, SGS to be connected, respectively.

[0056] The contact CC also has an insulating layer 56 that covers the outer periphery of the contact CC, and a conductive layer 26 such as a tungsten layer or a copper layer that fills the inside of the insulating layer 56 .

[0057] The conductive layer 26 of the contact CC is connected to an upper-layer wiring MX disposed in the insulating layer 53 via a plug V0 disposed in the insulating layer 52. This upper-layer wiring MX is electrically connected to the peripheral circuit CBA (see FIG. 1) described above via an electrode pad PDb on the surface of the insulating layer 53 and an electrode pad PDc on the surface of the insulating layer 40, etc.

[0058] In addition, within the region sandwiched between the plate-shaped contacts LI, the above-mentioned multiple isolation layers SHE extend in the X-direction within the memory region MR between the plate-shaped contacts LI, and also extend in the X-direction in the portion of the contact region ER where multiple contacts CC connected to the select gate line SGD are arranged.

[0059] As a result, the select gate line SGD is sandwiched on both sides in the Y direction by the plate-like contact LI and the isolation layer SHE, or between two isolation layers SHE, and the end in the X direction is selectively separated into multiple regions separated by the isolation layer SHE. Contacts CC are connected to each of the multiple regions of the select gate line SGD separated by the plate-like contact LI and the isolation layer SHE.

[0060] With this configuration, the word lines WL and select gate lines SGD, SGS of each layer can be electrically led out.

[0061] That is, with the above configuration, a predetermined voltage can be applied to the memory cells MC from the peripheral circuit CBA via the upper layer wiring MX, contacts CC, and word lines WL, causing the memory cells MC to operate as storage elements.

[0062] In addition, a predetermined voltage can be applied from the peripheral circuit CBA to the select gates STD and STS via the upper layer wiring MX, contacts CC, and select gate lines SGD and SGS to select or deselect the memory cells MC. At this time, the memory cells MC are selected or deselected for each region separated by the plate-like contacts LI and the isolation layer SHE.

[0063] In the contact region ER where the plurality of contacts CC are arranged, a plurality of pillar-shaped portions HR are dispersedly arranged, which penetrate the stacked body LM, the upper source line DSLb, and the intermediate insulating layer SCO and reach the lower source line DSLa.

[0064] The plurality of columnar portions HR are arranged in a generally periodic manner, for example, in a grid or staggered pattern, when viewed from the stacking direction of the laminate LM. The reason why the plurality of columnar portions HR are arranged generally periodic is that the periodicity of the arrangement of the columnar portions HR is slightly disrupted around the plurality of contacts CC and the plate-shaped contact LI, since the columnar portions HR are arranged while avoiding interference with the plurality of contacts CC and the plate-shaped contact LI.

[0065] Each of the pillars HR has a cross-sectional shape along the XY plane that is, for example, circular, elliptical, or oval.

[0066] Each columnar portion HR has a columnar portion HRa that passes through the uppermost insulating layer OLc of the laminate LMa to reach the source line SL, and a columnar portion HRb that passes through the uppermost insulating layer OLc of the laminate LMb to pass through the uppermost insulating layer OLc of the laminate LMa and is connected to the upper end of the corresponding columnar portion HRa.

[0067] As will be described later, these pillars HR are dummy pillars that serve to support the components when forming the stack LM from a stack of sacrificial layers and insulating layers, and do not contribute to the function of the semiconductor memory device 1. For this reason, each of the pillars HRa and HRb is made up of a single insulating layer 54 such as a silicon oxide layer, and is configured so that the pillars HR do not electrically affect other components.

[0068] Furthermore, at the same height position of the laminate LM, the cross-sectional area of ​​the columnar portions HR in the direction along the XY plane may be larger than the cross-sectional area of ​​the pillars PL in the direction along the XY plane, for example. Furthermore, the pitch between the columnar portions HR may be larger than the pitch between the pillars PL, for example. In the XY plane, the arrangement density of the columnar portions HR per unit area of ​​the word line WL in the laminate LM may be lower than the arrangement density of the pillars PL per unit area of ​​the word line WL.

[0069] In this way, by configuring the pillars PL to have a smaller cross-sectional area and a narrower pitch than, for example, the columnar portions HR, it is possible to form a large number of memory cells MC at a high density within the stacked body LM of a given size, thereby increasing the storage capacity of the semiconductor memory device 1. On the other hand, since the columnar portions HR are used solely to support the stacked body LM, the manufacturing load of the semiconductor memory device 1 can be reduced by not configuring them with a small cross-sectional area and a precise narrow pitch like, for example, the pillars PL.

[0070] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 of the first embodiment will be described with reference to Figures 4 to 17. Figures 4 to 17 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0071] First, the formation of the structures that will later become part of the pillars PL and columnar portions HR is shown in Fig. 4. Fig. 4 shows a cross section along the X direction of the semiconductor memory device 1 in the middle of manufacturing, including the region that will later become the memory region MR and the region that will later become the contact region ER.

[0072] As shown in FIG. 4(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order above a support substrate SS.

[0073] The support substrate SS may be, for example, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate or a quartz substrate, or a conductive substrate.

[0074] The lower source line DSLa and the upper source line DSLb are, for example, polysilicon layers, etc. The intermediate sacrificial layer SCN is a layer that will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL, and is arranged in a region that will later become the memory region MR. The intermediate insulating layer SCO is, for example, a silicon oxide layer, etc., and is arranged in a region that will later become the contact region ER.

[0075] A stack LMsa is formed on the upper source line DSLb, where multiple insulating layers NL and multiple insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers to be replaced with conductive materials that will later become the word lines WL and select gate lines SGS. The stack LMsa is the part that will later become the stack LMa through this replacement process.

[0076] At this stage, the insulating layers OL, including the uppermost insulating layer OL, may have approximately the same thickness.

[0077] 4(b), in the region that will later become the memory region MR, a plurality of memory holes MHa are formed that penetrate the stacked body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. Also, in the region that will later become the contact region ER, a plurality of holes HLa are formed that penetrate the stacked body LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0078] These memory holes MHa and holes HLa can be formed, for example, collectively. However, the memory holes MHa and holes HLa may also be formed separately. In this case, when forming the memory holes MHa, the region that will later become the contact region ER can be protected with a resist layer or the like. Furthermore, when forming the holes HLa, the region that will later become the memory region MR can be protected with a resist layer or the like.

[0079] 4(c), the memory holes MHa are filled with a sacrificial layer such as an amorphous silicon layer to form a plurality of pillars PLs, and the holes HLa are filled with an insulating layer 54 such as a silicon oxide layer to form a plurality of columnar portions HRa.

[0080] These pillars PLs and columnar portions HRa are formed separately. In this case, when forming the pillars PLs, the region that will later become the contact region ER can be protected with a resist layer or the like. Also, when forming the columnar portion HRa, the region that will later become the memory region MR can be protected with a resist layer or the like.

[0081] Next, the formation of the pillars PL and the columnar portions HR is shown in Figures 5 to 7. Similar to Figure 4 described above, Figures 5 to 7 show cross sections of the semiconductor memory device 1 in the process of being manufactured along the X direction.

[0082] As shown in Figure 5(a), a silicon oxide layer or the like is stacked on the top surface of the laminate LMsa. This makes the top insulating layer OL of the laminate LMsa thicker than the other insulating layers OL. In addition, the top ends of the pillars PLs and the columnar portions HRa are buried in the top insulating layer OL.

[0083] Furthermore, a stack LMsb is formed on the stack LMsa, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The stack LMsb is the portion where the insulating layers NL will later be replaced with word lines WL and select gate lines SGD to become the stack LMb.

[0084] At this stage, the insulating layers OL of the laminated body LMsb, including the uppermost insulating layer OL, may have approximately the same thickness.

[0085] 5(b), in the region that will later become the memory region MR, a plurality of memory holes MHb are formed that penetrate the laminate LMsb and reach the upper ends of the plurality of pillars PLa arranged in the laminate LMsa, and in the region that will later become the contact region ER, a plurality of holes HLb are formed that penetrate the laminate LMsb and reach the upper ends of the plurality of columnar portions HRa arranged in the laminate LMsa.

[0086] These memory holes MHb and holes HLb can be formed, for example, collectively. However, the memory holes MHb and holes HLb may also be formed separately while appropriately protecting the regions that will later become the memory regions MR and the contact regions ER.

[0087] 6(a), in the region that will later become the contact region ER, the holes HLb are filled with an insulating layer 54 such as a silicon oxide layer to form a plurality of columnar portions HRb. In this way, a columnar portion HR including columnar portions HRa and HRb is formed.

[0088] When forming the columnar portion HRb, the region that will later become the memory region MR can be protected with a resist layer or the like.

[0089] 6(b), in the region that will later become the memory region MR, the sacrificial layer is removed from the pillars PLa connected to the bottom ends of the memory holes MHb, thereby forming the memory holes MH that penetrate the stacks LMsa and LMsb and reach the source lines SL.

[0090] As shown in Figure 7(a), a memory layer ME having a stacked structure of a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN (see Figures 2(b) and 2(c)) is formed in each of the multiple memory holes MH, in that order from the outer periphery of the memory hole MH. In addition, a channel layer CN is formed on the sidewalls and bottom surfaces of the multiple memory holes MH via the memory layer ME. In addition, a core layer CR is formed by filling the void in the memory hole MH inside the channel layer CN with a silicon oxide layer or the like.

[0091] At this time, the memory layer ME, the channel layer CN, and the core layer CR are also formed on the top surface of the laminate LMsb, and these memory layer ME, the channel layer CN, and the core layer CR are removed from the top surface of the laminate LMsb by etching back or the like.

[0092] In this way, a plurality of pillars PL are formed in the region that will later become the memory region MR. However, at this point, the memory layer ME covers the entire sidewalls of the plurality of pillars PL, and the channel layer CN is not exposed.

[0093] In the region that will later become the contact region ER, a plurality of columnar portions HR have already been formed by the process shown in Fig. 6(a) above. Therefore, the region that will later become the contact region ER is not affected by the processes shown in Fig. 6(b) and Fig. 7(a).

[0094] As shown in Figure 7(b), a silicon oxide layer or the like is stacked on the top surface of the stacked body LMsb. This makes the top insulating layer OL of the stacked body LMsb thicker than the other insulating layers OL. In addition, the top ends of the pillars PL and the columnar portions HR are buried in the top insulating layer OL.

[0095] Next, FIGS. 8 and 9 show how a plurality of insulating layers OLc are formed in the region that will later become the contact region ER.

[0096] 8 is a top view of a region that will later become the contact region ER, but for convenience of explanation, a plurality of columnar portions HR are shown in FIG.

[0097] 8(a), a plurality of columnar portions HR have already been formed in the region that will later become the contact region ER. The region where the contact CC will later be formed is indicated by a dashed line. In this way, the contact CC will be formed in the region surrounded by a plurality of columnar portions HE when viewed from the stacking direction of the stacked bodies LMsa and LMsb.

[0098] 8(b), a resist pattern 90 is formed to cover the upper surface of the laminated body LMsb. The resist pattern 90 has openings 90op in regions where contacts CC will be formed later.

[0099] Similar to the above-described Figures 4 to 7, Figure 9 is a cross-sectional view along the X direction of the semiconductor memory device 1 during manufacturing, including the region that will later become the memory region MR and the region that will later become the contact region ER, and shows the state after the resist pattern 90 has been formed.

[0100] As shown in FIG. 9(a) and as described above with reference to FIG. 8, a resist pattern 90 having an opening 90op in a region that will later become the contact region ER and where the contact CC will be formed is formed.

[0101] 9(b), ions of at least one of carbon and nitrogen are implanted as a dopant into the openings 90op of the resist pattern 90. As a result, the dopant is implanted into the openings 90op and the multiple insulating layers OL in the regions overlapping the openings 90op and the stacked bodies LMsa and LMsb in the stacking direction, thereby forming multiple insulating layers OLc.

[0102] Next, the state in which a structure that will later become a plurality of contacts CC is formed is shown in FIGS.

[0103] 10 to 12 show a cross section of the contact region ER in the X direction during manufacturing. However, as an example, Fig. 10 to Fig. 12 show an example in which contact holes CLa to CLh are formed so as to reach the respective depth positions of the eight insulating layers NL of the laminated body LMs. Also, Fig. 10 to Fig. 12 omit illustration of the multiple columnar portions HR.

[0104] 10(a), a hard mask pattern 81 having a plurality of openings is formed on the upper surface of the laminate LMs. The hard mask pattern 81 is an inorganic layer that cannot be removed by ashing using, for example, oxygen plasma. Each of the plurality of openings in the hard mask pattern 81 has, for example, a hole shape.

[0105] 10(b), the upper surface of the laminated body LMs exposed from the openings in the hard mask pattern 81 is etched to remove the uppermost insulating layer OLc, thereby forming a plurality of contact holes CLh that penetrate the uppermost insulating layer OLc and reach the insulating layer NL immediately below the insulating layer OLc.

[0106] 10(c), a resist pattern 91 having a plurality of openings is formed by covering a portion of the upper surface of the laminate LMs via a hard mask pattern 81. The resist pattern 91 is an organic layer such as a resist layer that can be removed by ashing using oxygen plasma or the like. From the openings of the resist pattern 91, for example, every other contact hole CLh is exposed.

[0107] As shown in FIG. 11(a), the contact hole CLh exposed from the opening of the resist pattern 91 is further etched to remove, for example, the pair of insulating layers NL and OLc from the bottom surface of the contact hole CLh.

[0108] As a result, a plurality of contact holes CLg are formed, which penetrate the laminate LMs from the top insulating layer OLc to the second insulating layer OLc and reach from the top insulating layer NL to the second insulating layer NL. These contact holes CLg are arranged every other one of the plurality of contact holes CLh covered with the resist pattern 91.

[0109] That is, at this stage, a plurality of contact holes CLh and a plurality of contact holes CLg are formed alternately one by one in the laminated body LMs.

[0110] As shown in FIG. 11(b), the resist pattern 91 is removed by ashing using oxygen plasma or the like.

[0111] 11(c), a resist pattern 92 having a plurality of openings is formed to cover part of the upper surface of the laminated body LMs via a hard mask pattern 81. From the openings of the resist pattern 92, of pairs of adjacent contact holes CLh and CLg, for example, every other pair of contact holes CLh and CLg are exposed.

[0112] As shown in FIG. 12(a), the contact holes CLh and CLg exposed from the openings in the resist pattern 92 are further etched to remove, for example, two pairs of insulating layers NL and OLc from the bottom surfaces of the contact holes CLh and CLg.

[0113] As a result, multiple contact holes CLf are formed from the contact hole CLh that was etched, penetrating the laminate LMs from the top insulating layer OLc to the third insulating layer OLc, and reaching from the top insulating layer NL to the third insulating layer NL.

[0114] In addition, from the contact hole CLg that was etched, multiple contact holes CLe are formed that penetrate the laminate LMs from the top insulating layer OLc to the fourth insulating layer OLc and reach the top insulating layer NL to the fourth insulating layer NL.

[0115] In this way, by the processes up to this point, two sets of contact holes CLh to CLe are formed, in which the contact holes CLh to CLe having successively increasing depths in the laminated body LMs are arranged in this order.

[0116] Thereafter, the resist pattern 92 is removed by ashing using oxygen plasma or the like.

[0117] 12(b), a resist pattern 93 having a plurality of openings is formed to cover part of the upper surface of the laminated body LMs via the hard mask pattern 81. From the openings of the resist pattern 93, one set of contact holes CLh-CLe out of two sets of contact holes CLh-CLe is exposed.

[0118] As shown in FIG. 12(c), the contact holes CLh-CLe exposed from the openings in the resist pattern 92 are further etched to remove, for example, four pairs of insulating layers NL, OLc from the bottom surfaces of the contact holes CLh-CLe.

[0119] As a result, a contact hole CLd is formed that penetrates the laminate LMs from the top insulating layer OLc to the fifth insulating layer OLc from the contact hole CLh that was etched, and reaches the fifth insulating layer NL from the top insulating layer NL.

[0120] In addition, a contact hole CLc is formed from the contact hole CLg that was etched, penetrating the laminate LMs from the top insulating layer OLc to the sixth insulating layer OLc, and reaching the top insulating layer NL to the sixth insulating layer NL.

[0121] In addition, a contact hole CLb is formed from the contact hole CLf that was etched, penetrating the laminate LMs from the top insulating layer OLc to the seventh insulating layer OLc, and from the top insulating layer NL to the seventh insulating layer NL.

[0122] In addition, a contact hole CLa is formed from the contact hole CLe that is the target of etching, penetrating the laminate LMs from the top insulating layer OLc to the eighth insulating layer OLc, and reaching the top insulating layer NL to the eighth insulating layer NL.

[0123] As a result of the above, a plurality of contact holes CLh-CLa are formed, each of which reaches the eight insulating layers NL in the laminate LMs, with the depth gradually increasing. Thereafter, the resist pattern 93 is removed by ashing using oxygen plasma or the like. The hard mask pattern 81 is also removed by etching or the like.

[0124] However, various methods can be considered for forming the contact holes CL that become the contacts CC in the first embodiment, and the methods shown in FIGS. 10 to 12 are merely examples thereof.

[0125] 13 shows a cross section of the semiconductor memory device 1 in the process of being manufactured along the X direction, similar to the above-mentioned FIG. 9 etc. By the processes shown in FIGS. 10 to 12, a plurality of contact holes have already been formed in the region that will later become the contact region ER.

[0126] Figure 13(a) shows contact holes CL that reach the bottom layer of the laminate LMsb, and the fifth and fourth insulating layers NL from the bottom layer of the laminate LMsa, among multiple contact holes that reach different insulating layers NL in the laminates LMsa and LMsb, respectively.

[0127] 13(a), an insulating layer 56 is formed to cover the sidewalls and bottom surfaces of each of the contact holes CL. The insulating layer 56 is, for example, a silicon oxide layer.

[0128] 13(b), a sacrificial layer such as an amorphous silicon layer is filled into each of the contact holes CL via an insulating layer 56. This forms a plurality of pillars CS. These pillars CS are contact-like temporary structures that include the sacrificial layer.

[0129] Next, how the source lines SL and word lines WL are formed will be shown with reference to Figures 14 to 17. Figures 14 to 17 are cross-sectional views along the Y direction of a region that will later become a memory region MR.

[0130] As shown in FIG. 14(a), a slit ST is formed so as to pass through the stacked bodies LMsa, LMsb and the upper source line DSLb and reach the intermediate sacrificial layer SCN.

[0131] The slits ST extend in the X direction within the laminates LMsa and LMsb, i.e., perpendicular to the paper surface. Therefore, in the region that will later become the contact region ER, the lower ends of the slits ST reach the intermediate insulating layer SCO. The slits ST are used in the replacement process described below and will later become the plate-like contacts LI.

[0132] 14(b), an insulating layer 55s is formed on the side walls of the slit ST facing each other in the Y direction. The insulating layer 55s is, for example, a silicon oxide layer, and differs from the above-mentioned insulating layer 55 (see FIG. 2(a)) that the plate contact LI will later have on its side wall, and is a temporary protective layer formed to protect the stacked bodies LMsa and LMsb in subsequent processing.

[0133] As shown in FIG. 15(a), a removal liquid for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 55s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0134] As a result, a gap layer GPn is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPn.

[0135] At this time, since the side walls of the slits ST are protected by the insulating layer 55s, the insulating layer NL in the stacked bodies LMsa and LMsb is prevented from being removed as well.

[0136] 15(b), a chemical solution is appropriately poured into the gap layer GPn through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 2(b) and 2(c)) of the memory layer ME exposed in the gap layer GPn. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPn.

[0137] 16(a), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 55s, and the gap layer GPn is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPn, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0138] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0139] As shown in FIG. 16(b), the insulating layer 55s is removed from the sidewall of the slit ST.

[0140] In the region that will later become the contact region ER, an intermediate insulating layer SCO is formed between the lower source line DSLa and the upper source line DSLb instead of the intermediate sacrificial layer SCN, so that the region that will later become the contact region ER is not affected by the processes shown in FIGS.

[0141] 17(a), a remover for the insulating layer NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL or OLc have been removed.

[0142] The stacked bodies LMga and LMgb, each including a plurality of gap layers GP, have a fragile structure. In the region that will later become the memory region MR, a plurality of pillars PL support the fragile stacked bodies LMga and LMgb. On the other hand, in the region that will later become the contact region ER, a plurality of columnar portions HR support the stacked bodies LMga and LMgb.

[0143] Such a support structure of the pillars PL and the columnar portions HR prevents the remaining insulating layers OL, OLc from bending and the laminated bodies LMga, LMgb themselves from being distorted or collapsing.

[0144] As shown in FIG. 17(b), a source gas of a conductive material such as tungsten or molybdenum is injected into the stacks LMga and LMgb through the slits ST, and the gap layers GP of the stacks LMga and LMgb are filled with the conductive material to form a plurality of word lines WL, etc.

[0145] This forms a stack LM including stacks LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL and OLc are alternately stacked one by one. However, at this point, the separation layer SHE has not yet been formed, and one or more conductive layers 27 including the topmost conductive layer 27 of the stack LMb have not yet become select gate lines SGD separated into a plurality of sections.

[0146] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0147] Thereafter, an insulating layer 55 is formed on the sidewall of the slit ST, and a conductive layer 25 is filled in the insulating layer 55 to form a plate-like contact LI that serves as a source line contact. However, the slit ST may be filled with the insulating layer 55 or the like without forming the conductive layer 25, thereby forming a plate-like member that does not function as a source line contact.

[0148] Furthermore, a plurality of separation layers SHE are formed, which penetrate one or more conductive layers 27, including the topmost conductive layer 27 of the laminated body LMb, and reach the insulating layers OL and OLc directly below, thereby dividing the one or more conductive layers 27, including the topmost conductive layer 27 of the laminated body LMb, into the pattern of the select gate line SGD.

[0149] The sacrificial layer is then removed from the columns CS to form contact holes CL, and the insulating layer 56 covering the bottom surfaces of the contact holes CL is removed. A conductive layer 26 such as a tungsten layer is then filled into each of the contact holes CL whose sidewalls are covered with the insulating layer 56. This forms contacts CC.

[0150] Furthermore, an insulating layer 52 is formed on the upper surface of the laminated body LMb, and plugs CH, V0 are formed penetrating the insulating layer 52. These plugs CH, V0 are connected to the upper ends of the pillar PL and the contact CC, respectively. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and a bit line BL and an upper layer wiring MX are formed in the insulating layer 53. The bit line BL is connected to the pillar PL via the plug CH, and the upper layer wiring MX is connected to the contact CC via the plug V0.

[0151] It should be noted that the plug CH and the bit line BL, and the plug V0 and the upper layer wiring MX, etc. may be formed collectively by using, for example, a dual damascene method.

[0152] Also, electrode pads PDb connected to these bit lines BL and upper layer wiring MX are formed.

[0153] Meanwhile, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads PDc, etc. formed on the surface of the insulating layer 40.

[0154] Furthermore, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads PDb, PDc in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is ground and removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0155] In this manner, the semiconductor memory device 1 of the first embodiment is manufactured.

[0156] (Overview) Semiconductor memory devices, such as three-dimensional nonvolatile memories, are manufactured by, for example, replacing multiple sacrificial layers with multiple word lines. During this replacement process, the insulating layer remaining in the stack after the sacrificial layers have been removed may bend. The bending of the insulating layer may result in the blocking of the gap layer GP where the word lines will be formed.

[0157] In this case, in the region that will later become the memory region, multiple pillars are periodically arranged at a narrow pitch to support the stack during replacement. On the other hand, in the region that will later become the contact region, multiple columnar portions are arranged at a relatively wide pitch, with the periodicity partially disrupted to avoid interference with the contacts. Therefore, the pitch of the multiple columnar portions is even wider at the contact placement position, making the above-mentioned blockage of the insulating layer more likely to occur than in the region that will later become the memory region.

[0158] According to the semiconductor memory device 1 of the first embodiment, among the multiple insulating layers OL, the insulating layer OLc located in the region surrounded by the multiple columnar portions HR and including the contacts CC has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress in at least a portion thereof than the insulating layer OL in the region where the pillar PL is disposed, thereby making it possible to suppress deflection of the insulating layer OLc during replacement processing.

[0159] According to the semiconductor memory device 1 of the first embodiment, the insulating layer OLc in the region where the contacts CC are arranged has a higher Young's modulus than the insulating layer OL in the region where the pillars PL are arranged, over the entire region surrounded by the columnar portions HR, which makes it possible to further suppress bending of the insulating layer OLc during replacement processing.

[0160] (Variation 1) 18 to 20, a semiconductor memory device 1a according to Modification 1 of Embodiment 1 will be described. The semiconductor memory device 1a according to Modification 1 differs from the above-described Embodiment 1 in that an insulating layer OLc is provided for each of the stacked bodies LMa and LMc.

[0161] In the following drawings, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0162] 18 is a cross-sectional view taken along the X direction showing an example of the configuration of a semiconductor memory device 1a according to Modification 1 of Embodiment 1. As shown in Fig. 18, the semiconductor memory device 1a of Modification 1 includes a stacked body LM2 including stacked bodies LMa and LMc.

[0163] The laminated body LMa includes a plurality of insulating layers OLc in the contact region ERa, as in the above-described embodiment 1. Furthermore, although not shown, in the memory region, the laminated body LMa includes a plurality of insulating layers OL.

[0164] In contrast, the laminate LMc further includes a plurality of insulating layers OLc only in a partial region of the contact region ERa. In other regions of the contact region ERa and in the memory region, the laminate LMb includes a plurality of insulating layers OL. More specifically, the insulating layers OLc of the laminate LMc are arranged in a region in the contact region ERa where, of the plurality of contacts CC, contacts CC connected to word lines WL or select gate lines SGD included in the laminate LMb are provided. That is, in the contact region ERa, similar to the memory region, a plurality of insulating layers OL are arranged in a region where, of the plurality of contacts CC, contacts CC connected to word lines WL or select gate lines SGS included in the laminate LMa are provided.

[0165] 19 and 20 are cross-sectional views illustrating, in order, some steps of a method for manufacturing a semiconductor memory device 1a according to Modification 1 of Embodiment 1. More specifically, Fig. 19 and Fig. 20 show a cross section along the X direction of the semiconductor memory device 1a during manufacturing, including a region that will later become a memory region and a region that will later become a contact region ERa.

[0166] As shown in Figure 19(a), in the manufacturing method of the semiconductor memory device 1a of variant example 1, for example, after forming the stack LMsa, pillar PLs, and columnar portion HRa, ion implantation is performed on a portion of the insulating layer OL before forming the stack LMsb.

[0167] That is, a resist pattern 94 having openings 94op is formed in a region that will later become the contact region ERa, where a contact CC that will be connected to the word line WL or the like in the laminate LMa will be formed. Further, ions are implanted into the openings 94op of the resist pattern 94 to form an insulating layer OLc in a partial region of the laminate LMsa.

[0168] 19(b), a plurality of pillars CSa are formed, penetrating the insulating layer NL and the insulating layer OLc formed in a partial region of the laminated body LMsa. The pillars CSa are configured to become the lower structure of contacts CC that will later be connected to word lines WL or the like in the laminated body LMa. That is, the pillars CSa are configured to include a sacrificial layer such as an amorphous silicon layer, similar to the pillars CS in the first embodiment.

[0169] A resist pattern 95 having openings 95op is formed in a region that will later become the contact region ERa, where a contact CC to be connected to the word line WL or the like in the laminate LMb will be formed. Ion implantation is performed into the openings 95op of the resist pattern 95 to form an insulating layer OLc in a partial region of the laminates LMsa and LMsb.

[0170] As shown in FIG. 20(a), a plurality of contact holes CL are formed in a region that will later become the contact region ERa, reaching the plurality of insulating layers NL in the laminated bodies LMsa and LMsb.

[0171] That is, in the region that will later become the contact region ERa, where a contact CC that will be connected to a word line WL or the like in the laminate LMb will be formed, contact holes CL are formed that penetrate the insulating layers NL and OLc of the laminate LMsb and reach the insulating layers NL to be connected.

[0172] On the other hand, in the region where the contacts CC connected to the word lines WL etc. in the laminate LMa will be formed, a plurality of contact holes are formed that penetrate the insulating layers NL and OL of the laminate LMsb and connect to the already formed columns CSa, and the sacrificial layer is temporarily removed from the columns CSa through these contact holes, thereby forming contact holes CL that penetrate the insulating layers NL and OL of the laminates LMsb and LMsa and reach the insulating layers NL to be connected.

[0173] Thereafter, an insulating layer 56 is formed again to cover the sidewalls and bottom surfaces of these contact holes CL.

[0174] 20(b), a sacrificial layer such as an amorphous silicon layer is again filled into the contact hole CL in which the insulating layer 56 has been formed, thereby forming a plurality of pillars CS in the region that will later become the contact region ERa.

[0175] The subsequent steps are carried out in the same manner as in the first embodiment.

[0176] As described above, the multiple columnar portions HR are arranged while avoiding interference with the contacts CC. This results in wider spacing between the columnar portions HR around the contacts CC, making it easier for the insulating layer OL to bend during replacement. Here, the risk of the insulating layer OL being bent is higher in the region below the columnar portions CS than in the portions of the stacks LMsa and LMsb through which the columnar portions CS, which will later become the contacts CC, penetrate. This is because neither the columnar portions CS nor the columnar portions HR are arranged in the region below the columnar portions CS.

[0177] According to the semiconductor memory device 1a of variant example 1, the insulating layer OLc in the laminate LMa in the region where the contacts CC connected to the word lines WL, etc. in the laminate LMa are arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress throughout the entire region surrounded by multiple columnar portions HR than the insulating layer OL in the laminate LMb in the region where the contacts CC connected to the word lines WL, etc. in the laminate LMb are arranged and the insulating layer OL in the region where the pillars PL are arranged.

[0178] In this way, by providing the insulating layer OLc by performing ion implantation only in the region below the contact CC where the risk of the insulating layer OL bending is even higher, the effect of suppressing the bending of the insulating layer OLc can be sufficiently obtained. On the other hand, by not forming a hard insulating layer OLc in the portion where the columnar body CS penetrates the laminate LMb where the risk of the insulating layer OL bending is relatively low, the insulating layer OLc is connected to, for example, the word line WL of the laminate LMa, and it becomes easy to form a contact CC with a high aspect ratio.

[0179] In addition, the semiconductor memory device 1a of the first modification has the same effects as the semiconductor memory device 1 of the first embodiment described above.

[0180] In the above-described first embodiment, after the laminates LMsa and LMsb are formed, the contact holes CL serving as contacts CC connected to the word lines WL or the like in the laminate LMa or the laminate LMb are formed all at once. However, even in the configuration of the above-described first embodiment in which the insulating layer OLc is formed in both the laminates LMa and LMb in the contact region ER, a contact hole may be formed for each of the laminates LMa and LMb.

[0181] This makes it easy to form contact holes that penetrate the laminated bodies LMsa and LMsb on which the hard insulating layer OLc is formed.

[0182] (Variation 2) 21 and 22, a semiconductor memory device 1b according to Modification 2 of Embodiment 1 will be described. The semiconductor memory device 1b according to Modification 2 differs from the above-described Embodiment 1 in that it has an insulating layer OLc in a portion overlapping with the contact CC in the stacking direction.

[0183] In the following drawings, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0184] 21 is a cross-sectional view taken along the X direction showing an example of the configuration of a semiconductor memory device 1b according to Modification 2 of Embodiment 1. As shown in Fig. 21, the semiconductor memory device 1b of Modification 2 includes a stacked body LM3 including stacked bodies LMd and LMe.

[0185] In the laminated bodies LMd and LMe, an insulating layer OLc is provided below each contact CC in the contact region ERb and in a portion overlapping these contacts CC in the lamination direction.

[0186] That is, for example, in a portion of a contact CC connected to a select gate line SGD0 in the top layer of the laminate LMb, the portion of the laminate LMa, LMb below the select gate line SGD0 that overlaps with the contact CC in the stacking direction is entirely made of an insulating layer OLc. Also, for example, in a portion of a contact CC connected to a word line WL in the top layer of the laminate LMa, the insulating layer OLc is not provided on the laminate LMb above the contact CC, and the portion of the laminate LMa below the word line WL in the top layer of the laminate LMa that overlaps with the contact CC in the stacking direction is entirely made of an insulating layer OLc.

[0187] 22 is a cross-sectional view illustrating a part of the steps of a method for manufacturing a semiconductor memory device 1b according to Modification 2 of Embodiment 1. More specifically, FIG. 22 shows a cross section along the X direction of the semiconductor memory device 1b during manufacturing, including a region that will later become a memory region and a region that will later become a contact region ERb.

[0188] 22(a), in the manufacturing method of the semiconductor memory device 1b of the second modification, for example, before forming the insulating layer OLc, a plurality of contact holes CL are formed using a resist pattern 96 having a plurality of openings 96op as a mask. Then, ion implantation is performed from the bottom surfaces of the contact holes CL exposed from the openings 96op of the resist pattern 96, to form the insulating layer OLc below the contact holes CL in the portions overlapping with the contact holes CL in the stacking direction.

[0189] As shown in FIG. 22(b), an insulating layer 56 and a sacrificial layer are formed in the contact holes CL, and a plurality of columns CS are formed.

[0190] The subsequent steps are carried out in the same manner as in the first embodiment.

[0191] According to the semiconductor memory device 1b of variant example 2, the insulating layer OLc in the region where the contact CC is arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress in the portion overlapping with the contact CC in the stacking direction than the insulating layer OL in the region where the pillar PL is arranged.

[0192] In this way, by disposing the insulating layer OLc only at a position overlapping the contact CC in the stacking direction, the effect of suppressing the deflection of the insulating layer OLc can be sufficiently obtained.

[0193] Furthermore, by configuring the insulating layer OLc to have such an arrangement, the formation of the contact holes CL and the ion implantation can be performed using, for example, the same resist pattern 96, thereby reducing the number of steps and lowering manufacturing costs. Furthermore, since the hard insulating layer OLc is formed after the contact holes CL are formed, the formation of the contact holes CL becomes even easier.

[0194] In addition, the semiconductor memory device 1b of the second modification provides the same effects as the semiconductor memory device 1 of the first embodiment described above.

[0195] [Embodiment 2] Hereinafter, the second embodiment will be described in detail with reference to the drawings. The semiconductor memory device of the second embodiment differs from the first embodiment in that, for example, an insulating layer with a high Young's modulus is disposed around the columnar portion supporting the stacked body.

[0196] In the following drawings, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0197] (Configuration example of semiconductor memory device) 23A and 23B are cross-sectional views taken along the X direction, illustrating an example of the configuration of a semiconductor memory device 2 according to embodiment 2. More specifically, FIG. 23A is a cross-sectional view taken along the X direction, illustrating an example of the configuration of a contact region ERf according to embodiment 2. FIG. 23B is an enlarged cross-sectional view of a columnar portion HRf according to embodiment 2.

[0198] 23, the semiconductor memory device 2 of the second embodiment includes a stacked body LM3 including stacked bodies LMf and LMg. Each of the stacked bodies LMf and LMg has a configuration in which a plurality of word lines and insulating layers OL are alternately stacked one by one.

[0199] Furthermore, the columnar portion HRf of the second embodiment has a plurality of flange portions FL on its sidewall at the same height as the plurality of insulating layers OL of the laminate LM4. The flange portions FL are provided so as to surround the outer edge of each columnar portion HRf and protrude from the sidewall of the columnar portion HRf toward the plurality of insulating layers OL. The flange portions FL are, for example, silicon oxide layers containing at least one of carbon and nitrogen, and have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layers OL of the laminate LM4.

[0200] The outer edges of the flanges FL are located at substantially equal distances from the center points of the columnar portions HRf when viewed from the stacking direction, i.e., the outer edges of the flanges FL are arranged substantially concentrically with the sidewalls of the columnar portions HR at the height of the word lines WL, etc.

[0201] In other words, in the semiconductor memory device 2 of embodiment 2, it can be considered that the insulating layer OLc is provided around the columnar portion HR of embodiment 1 so as to be in contact with the sidewall of the columnar portion HR. In this case, it can also be considered that the columnar portion HR corresponds to the core material of the columnar portion HRf having the flange portion FL.

[0202] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 2 according to the second embodiment will be described with reference to Figures 24 to 26. Figures 24 to 26 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 2 according to the second embodiment.

[0203] More specifically, FIGS. 24 to 26 show a cross section along the X direction of the semiconductor memory device 2 in the process of being manufactured, including a region that will later become the memory region MR and a region that will later become the contact region ERf.

[0204] As shown in Figure 24(a), in the manufacturing method of the semiconductor memory device 2 of embodiment 2, instead of forming columnar portions HRa, HRb, etc. for each of the stacked bodies LMsa, LMsb as in the above-mentioned embodiment 1, the columnar portion HRf is formed all at once after the stacked body LMsb is formed.

[0205] More specifically, in the method for manufacturing the semiconductor memory device 2 of the second embodiment, after forming the hole HLa, the hole HLa is filled with a sacrificial layer such as an amorphous silicon layer instead of the insulating layer 54. Furthermore, after forming the hole HLb, the hole HLb is filled with a sacrificial layer such as an amorphous silicon layer instead of the insulating layer 54.

[0206] As a result, a columnar portion HRs filled with the sacrificial layer is formed in the hole HL penetrating the stacked bodies LMsa and LMsb. By filling the hole HL with the sacrificial layer or the like in this way, it is possible to prevent the hole HL from being processed when, for example, a pillar PL or the like is formed later.

[0207] As shown in FIG. 24(b), after the pillars PL and the like are formed, the sacrificial layer in the holes HL is removed.

[0208] As shown in Figure 25(a), a chemical solution that dissolves the insulating layer OL is poured into the hole HL. As a result, the insulating layer OL exposed on the side wall of the hole HL retreats from the side wall toward the periphery of the hole HL. At this time, the amount of retreat of the insulating layer OL at the outer periphery of the hole HL is substantially the same in all directions. In other words, this results in the formation of multiple brim-shaped gap layers GPf that protrude substantially concentrically into the insulating layer OL on the side wall portion of the hole HL remaining at the height of the insulating layer NL.

[0209] The plurality of brim-shaped gap layers GPf may be formed by a method other than the above-mentioned wet etching, such as chemical dry etching.

[0210] 25(b), an insulating layer such as a silicon oxide layer is formed on the sidewall and bottom surface of the hole HL by, for example, atomic layer deposition (ALD), etc. At this time, at least one of carbon and nitrogen is added to the film formation gas so that a predetermined concentration of carbon or the like is contained in the insulating layer.

[0211] As a result, an insulating layer 54w is formed on the sidewalls and bottom surface of the hole HL including the plurality of brim-shaped gap layers GPf. However, the insulating layer 54w may be formed by a method other than ALD, such as low pressure chemical vapor deposition (LP-CVD).

[0212] 26(a), the insulating layer 54w formed on the sidewalls and bottom surface of the hole HL except for the inside of the brim-shaped gap layer GPf is removed, thereby forming a plurality of flange portions FL filled with the insulating layer 54w inside the brim-shaped gap layer GPf.

[0213] 26(b), the holes HL are filled with an insulating layer 54. In this way, the columnar portions HRf of the second embodiment are formed.

[0214] The subsequent steps are performed in the same manner as in the first embodiment, except that ions are not implanted into the insulating layers OL of the stacked bodies LMsa and LMsb.

[0215] (Overview) According to the semiconductor memory device 2 of embodiment 2, the multiple columnar portions HRf are provided with multiple flange portions FL that protrude into the multiple insulating layers OL at height positions of the multiple insulating layers OL and have at least one of a higher Young's modulus, lower compressive stress, and higher tensile stress than the multiple insulating layers OL.

[0216] Alternatively, according to the semiconductor memory device 2 of embodiment 2, the insulating layers OLc have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress within a predetermined distance from the portion in contact with the columnar portions HR toward the outside of the columnar portions HR, compared to other portions.

[0217] This makes it possible to suppress bending of the insulating layer OL during the replacement process.

[0218] In addition, the semiconductor memory device 2 of the second embodiment has the same effects as the semiconductor memory device 1 of the first embodiment described above.

[0219] In the second embodiment described above, the insulating layer 54w is formed to cover the entire sidewall of the hole HL, and then the insulating layer 54w on the sidewall is removed to form the flange portion FL. However, the insulating layer 54w may be selectively formed within the flange-shaped gap layer GPf. In this case, for example, a gas that preferentially adsorbs to the insulating layer OL can be used as the deposition gas. Alternatively, an inhibitor layer that inhibits the formation of the insulating layer 54w is formed on the insulating layer NL, and then the insulating layer 54w is formed.

[0220] As a result, the insulating layer 54w is selectively formed in the brim-shaped gap layer GPf, and the insulating layer 54 is not formed to cover the entire sidewall of the hole HL as shown in Fig. 25(b) above, but the insulating layer 54w is formed in the brim-shaped gap layer GPf as shown in Fig. 26(a) above.

[0221] (Variation 1) 27 and 28, a semiconductor memory device 2a according to Modification 1 of Embodiment 2 will be described. The semiconductor memory device 2a according to Modification 1 differs from the above-described Embodiment 1 in that it includes a columnar portion HRw having an insulating layer 54w on its sidewall in addition to a flange portion FL.

[0222] In the following drawings, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0223] 27A and 27B are cross-sectional views taken along the X direction, showing an example of the configuration of a semiconductor memory device 2a according to Modification 1 of Embodiment 2. More specifically, FIG. 27A is a cross-sectional view taken along the X direction, showing an example of the configuration of a contact region ERw according to Modification 1. FIG. 27B is an enlarged cross-sectional view of a columnar portion HRw according to Modification 1.

[0224] 27, the semiconductor memory device 2a of Modification 1 includes a plurality of columnar portions HRw. Similar to the second embodiment, these columnar portions HRw include a plurality of flange portions FL. The columnar portions HRw also include an insulating layer 54w covering their sidewalls and bottom surfaces. Similar to the insulating layer 54w described above, the insulating layer 54w is, for example, a silicon oxide layer containing at least one of carbon and nitrogen, and has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer OL of the laminate LM4.

[0225] In other words, the semiconductor memory device 2a of Modification 1 can be considered as having an insulating layer OLc that covers the columnar portion HR and has a plurality of flange portions FL provided around the columnar portion HR of the above-described Embodiment 1. In this case, the columnar portion HR can also be considered to correspond to the core material of the columnar portion HRw that has the insulating layer 54w.

[0226] 28 is a diagram illustrating a part of the steps of a method for manufacturing a semiconductor memory device 2a according to Modification 1 of Embodiment 2. More specifically, Fig. 28 shows a cross section along the X direction of the semiconductor memory device 2a during manufacturing, including a region that will later become the memory region MR and a region that will later become the contact region ERw.

[0227] 28(a) is the same as the state shown in FIG. 25(b) of the above-described embodiment 2. That is, a plurality of brim-shaped gap layers GPf are formed on the side walls of each of the plurality of holes HL, and an insulating layer 54w is formed on the side walls and bottom surfaces of these holes HL.

[0228] 28(b), in the method for manufacturing the semiconductor memory device 2a of the first modification, the insulating layer 54 is filled into the hole HL without removing the insulating layer 54w on the sidewall and bottom surface of the hole HL, thereby forming the columnar portion HRw of the first modification.

[0229] The subsequent steps are carried out in the same manner as in the second embodiment.

[0230] According to the semiconductor memory device 2 of the first modification, the plurality of columnar portions HRw extend in the stacking direction and have sidewalls that have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the plurality of insulating layers OL. This configuration also makes it possible to suppress deflection of the insulating layers OL during the replacement process.

[0231] In addition, the semiconductor memory device 2a of the first modification has the same effects as the semiconductor memory device 2 of the second embodiment described above.

[0232] (Variation 2) 29 and 30, a semiconductor memory device 2b according to Modification 2 of Embodiment 2 will be described. The semiconductor memory device 2b according to Modification 2 differs from the above-described Embodiment 2 in that the entire semiconductor memory device 2b includes a columnar portion HRc having a high Young's modulus or the like.

[0233] In the following drawings, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0234] 29A and 29B are cross-sectional views taken along the X direction, illustrating an example of the configuration of a semiconductor memory device 2b according to Modification 1 of Embodiment 2. More specifically, FIG. 29A is a cross-sectional view taken along the X direction, illustrating an example of the configuration of a contact region ERc according to Modification 2. FIG. 29B is an enlarged cross-sectional view of a columnar portion HRc according to Modification 2.

[0235] 29, the semiconductor memory device 2b of Modification 2 includes a plurality of columnar portions HRc. Similar to the second embodiment, these columnar portions HRc include a plurality of flange portions FL. Furthermore, the main body portions of the columnar portions HRc also include an insulating layer 54c, similar to the plurality of flange portions FL, that has a higher Young's modulus, a lower compressive stress, and / or a higher tensile stress than the insulating layer OL of the multilayer body LM4. That is, the insulating layer 54c is, for example, a silicon oxide layer containing at least one of carbon and nitrogen.

[0236] 30 is a diagram illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 2b according to Modification 2 of Embodiment 2. More specifically, Fig. 30 shows a cross section along the X direction of the semiconductor memory device 2b during manufacturing, including a region that will later become the memory region MR and a region that will later become the contact region ERc.

[0237] 30(a) is the same as the state shown in FIG. 24(b) of the second embodiment. That is, it shows a state in which a chemical solution or the like is injected through the holes HL, or a CDE or the like is used to recede the insulating layers OL exposed on the side walls of each of the holes HL. Therefore, a plurality of brim-shaped gap layers GPf are provided on the side walls of each of the holes HL.

[0238] 30(b), the holes HL are filled with an insulating layer 54c, thereby forming a plurality of columnar portions HRc.

[0239] The subsequent steps are carried out in the same manner as in the second embodiment.

[0240] According to the semiconductor memory device 2b of the second modification, the plurality of columnar portions HRc contain the same material as the plurality of flange portions FL. This configuration also makes it possible to suppress bending of the insulating layer OL during replacement processing.

[0241] In addition, the semiconductor memory device 2b of the second modification provides the same effects as the semiconductor memory device 2 of the second embodiment described above.

[0242] (Variation 3) Next, a semiconductor memory device 2c according to Modification 3 of Embodiment 2 will be described with reference to Fig. 31. The semiconductor memory device 2c according to Modification 3 differs from the above-described Embodiment 2 in that an insulating layer with a high Young's modulus, for example, is disposed around the plate contact LI.

[0243] In the following drawings, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0244] 31 is a cross-sectional view along the X direction showing an example of the configuration of a semiconductor memory device 2c according to Modification 3 of Embodiment 2. More specifically, FIG. 31 is a cross-sectional view along the X direction showing an example of the configuration of a memory region MRp of Modification 3.

[0245] 31 , the semiconductor memory device 2c of the third modification includes a plurality of plate-shaped contacts LIp. The plate-shaped contacts LIp include a plurality of protrusions PR extending from the sidewalls of the plate-shaped contacts LIp toward the insulating layers OL at height positions corresponding to the insulating layers OL of the laminate LM4. The protrusions PR are, for example, silicon oxide layers containing at least one of carbon and nitrogen, and have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layers OL of the laminate LM4.

[0246] The protrusion PR provided on the plate contact LIp can also be formed in the same manner as the flange portion FL of the columnar portion HRf in the second embodiment. That is, after the above-described slit ST is formed, the insulating layer OL exposed on the side wall of the slit ST is recessed at a predetermined timing. Furthermore, an insulating layer, such as a silicon oxide layer containing at least one of carbon and nitrogen, is formed on the side wall of the slit ST using ALD, LP-CVD, or the like. At this time, an insulating layer may be selectively formed in the gap layer on the side wall of the slit ST, which is formed by the recession of the insulating layer OL, by combining ALD, LP-CVD, or the like with a selective growth method. When the insulating layer is formed on the entire side wall of the slit ST, the insulating layer is removed from the side wall of the slit ST. This results in the above-described protrusion PR.

[0247] As described above, the columnar portions HR and the like in the first embodiment are arranged within the contact region ER while avoiding interference with the plate-shaped contacts LI as well as the contacts CC. Therefore, the arrangement density of the columnar portions HR is reduced even around the plate-shaped contacts LI, making it easier for the insulating layer OL to bend.

[0248] According to the semiconductor memory device 2c of the third modification, the plate contact LIp has a plurality of protrusions PR that protrude from both sidewalls in the Y direction toward the insulating layers OL at height positions of the insulating layers OL. In other words, the insulating layers OL have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than other portions within a predetermined distance from the portion of the insulating layers OL that contacts the plate contact LI, excluding the protrusions PR, toward the columnar portions HR. This makes it possible to suppress deflection of the insulating layers OL even in the region between the plate contact Lip and the columnar portions HR.

[0249] [Other embodiments] In the above-described first and second embodiments and their respective modifications, the insulating layer OLc or the like having at least one of a high Young's modulus, low compressive stress, and high tensile stress contains, for example, at least one of carbon and nitrogen. However, such an insulating layer OLc may also contain a metal or the like. That is, the insulating layer OLc may be a metal oxide layer or the like. The metal oxide layer may contain, for example, at least one of aluminum, zirconium, molybdenum, hafnium, and titanium as the contained metal.

[0250] In the above-described first and second embodiments and their modifications, the contact regions ER and the like are arranged at both ends of the laminate LM in the X direction. However, the arrangement positions of the contact regions in the laminate LM are not limited to this. The contact regions may be arranged, for example, in the center of the laminate LM. In this case, the memory regions MR may be arranged, for example, at both ends of the laminate LM.

[0251] Furthermore, in the above-described first and second embodiments and their respective modifications, for example, in the contact region ER, a plurality of contacts CC penetrate the laminate LM and are connected to the word lines WL or the like to be connected. However, as in the semiconductor memory device 3 shown in Fig. 32, for example, a laminate may be formed having a staircase portion SR in which the word lines WL or the like are processed into a staircase shape, and the contacts CC may be connected to the word lines WL that form each terrace surface of the staircase portion. In this case, too, the staircase portion SR may be located at the end or center of the laminate in the X direction.

[0252] In the above-described first and second embodiments and their modifications, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0253] In the above-described first and second embodiments and their modifications, the columnar portion HR is made of a single insulating layer 54. However, the columnar portion HR may have the same layer structure as the pillar PL, for example.

[0254] In the above-described first and second embodiments and their modifications, the insulating layers NL and OL are laminated in two separate steps to form a two-tier laminate LM including laminates LMa and LMb. However, the laminate may have a one-tier structure, or a three-tier or more structure. By increasing the number of tiers, the number of stacked word lines WL can be further increased.

[0255] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0256] 1, 1a, 1b, 2, 2a, 2b, 2c, 3...semiconductor memory device, CBA...peripheral circuit, CC...contact, CL, CLa to CLh...contact hole, ER, ERa, ERb, ERc, ERf, ERw...contact region, HR, HRa, HRb, HRc, HRf, HRw...columnar portion, LI, LIp...plate-shaped contact, LM, LMa, LMb, LMc, LMd, LMe, LMf, LMg, LMga, LMgb, LMsa, LMsb...laminated body, MC...memory cell, MR, MRp...memory region, NL, OL, OLc...insulating layer, PL, PLa, PLb...pillar, SB...semiconductor substrate, SGD, SGS...select gate line, STD, STS...select gate, SS...support substrate, ST...slit, WL...word line.

Claims

1. a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; a pillar including a channel layer extending in a stacking direction of the stack; a contact provided in a region of the stack different from a region where the pillar is disposed, the contact being connected to one of the plurality of conductive layers; a plurality of columnar portions that are provided at a predetermined distance from the contact so as to surround the contact and extend in the stacking direction of the laminate; Among the plurality of insulating layers, an insulating layer located in a region including the contact and surrounded by the plurality of columnar portions has, at least in a portion thereof, at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than an insulating layer in an arrangement region of the pillar. Semiconductor memory device.

2. Among the plurality of insulating layers, the insulating layer in the region where the contact is arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer in the region where the pillar is arranged, throughout the entire region surrounded by the plurality of columnar portions.

2. The semiconductor memory device according to claim 1.

3. Among the plurality of insulating layers, the insulating layer in the region where the contact is arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer in the region where the pillar is arranged, at least in a portion overlapping with the contact in the stacking direction.

2. The semiconductor memory device according to claim 1.

4. the insulating layers have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress within a predetermined distance from a portion in contact with the columnar portions toward an outside of the columnar portions, compared to other portions; 2. The semiconductor memory device according to claim 1.

5. a plate-like portion extending through the stack in a first direction intersecting the stacking direction and in the stacking direction, and dividing the stack in a second direction intersecting the first direction and the stacking direction; The plurality of insulating layers are a portion of the plate-like portion contacting the plate-like portion within a predetermined distance toward the plurality of columnar portions has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than other portions; 2. The semiconductor memory device according to claim 1.

6. the insulating layer having at least one of a high Young's modulus, a low compressive stress, and a high tensile stress contains at least one of carbon, nitrogen, and a metal; 2. The semiconductor memory device according to claim 1.

7. the insulating layer having at least one of a high Young's modulus, a low compressive stress, and a high tensile stress contains 0.5 atomic % or more of carbon; 7. The semiconductor memory device according to claim 6.

8. the plurality of insulating layers include silicon oxide layers; 7. The semiconductor memory device according to claim 6.

9. the insulating layer having at least one of a high Young's modulus, a low compressive stress, and a high tensile stress contains at least one of carbon and nitrogen as a dopant; 4. The semiconductor memory device according to claim 3.

10. The insulating layer having at least one of a high Young's modulus, a low compressive stress, and a high tensile stress is containing at least one of carbon, nitrogen, aluminum, zirconium, molybdenum, hafnium, and titanium; 5. The semiconductor memory device according to claim 4.

11. a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; a pillar including a channel layer extending in a stacking direction of the stack; a contact provided in a region of the stack different from a region where the pillar is disposed, the contact being connected to one of the plurality of conductive layers; a plurality of columnar portions that are provided at a predetermined distance from the contact so as to surround the contact and extend in the stacking direction of the laminate; Among the plurality of insulating layers, the insulating layer in the region where the contact is arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer in the region where the pillar is arranged, at least in a portion overlapping with the contact in the stacking direction. Semiconductor memory device.

12. Among the plurality of insulating layers, the insulating layer in the region where the contact is arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer in the region where the pillar is arranged, throughout the entire region surrounded by the plurality of columnar portions.

12. The semiconductor memory device according to claim 11.

13. Among the plurality of insulating layers, at least an insulating layer located below the one conductive layer to which the contact is connected has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress throughout an entire region surrounded by the plurality of columnar portions, compared to an insulating layer in an arrangement region of the pillar.

12. The semiconductor memory device according to claim 11.

14. The laminate is a first laminate; a second stack provided above the first stack, The contact a first contact connected to a first conductive layer in the first stack of the plurality of conductive layers; a second contact connected to a second conductive layer in the second stack of the plurality of conductive layers; The plurality of columnar portions are a plurality of first pillars provided to surround the first contact; a plurality of second pillars provided to surround the second contact; Among the plurality of insulating layers, the insulating layer in the first stack in the region where the first contact is arranged has at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layer in the second stack in the region where the first contact is arranged and the insulating layer in the pillar arrangement region, throughout the entire region surrounded by the plurality of first columnar portions; Among the plurality of insulating layers, the insulating layers in the first and second stacks in the region where the second contacts are arranged have at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the insulating layers in the second stacks in the region where the first contacts are arranged and the insulating layers in the pillar arrangement region, throughout the entire region surrounded by the plurality of second columnar portions.

12. The semiconductor memory device according to claim 11.

15. a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; a pillar including a channel layer extending in a stacking direction of the stack; a contact provided in a region of the stack different from a region where the pillar is disposed, the contact being connected to one of the plurality of conductive layers; a plurality of columnar portions that are provided at a predetermined distance from the contact so as to surround the contact and extend in the stacking direction of the laminate; The plurality of columnar portions are a plurality of flange portions are provided at height positions of the plurality of insulating layers, protruding into the plurality of insulating layers, and having at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the plurality of insulating layers; Semiconductor memory device.

16. The outer edge of each of the plurality of flanges is the conductive layers are provided substantially concentrically with the sidewall portions of the plurality of columnar portions at the height positions of the plurality of conductive layers; 16. The semiconductor memory device according to claim 15.

17. The outer edge of each of the plurality of flanges is at positions spaced substantially equidistant from the center points of the plurality of columnar portions as viewed in the stacking direction, 16. The semiconductor memory device according to claim 15.

18. The plurality of columnar portions are Each of the laminates has an insulating core material extending in the stacking direction, The outer edge of each of the plurality of flanges is Located substantially equidistant from the sidewalls of the core; 18. The semiconductor memory device according to claim 17.

19. The plurality of columnar portions are a sidewall extending in the stacking direction and having at least one of a higher Young's modulus, a lower compressive stress, and a higher tensile stress than the plurality of insulating layers; 16. The semiconductor memory device according to claim 15.

20. The plurality of columnar portions are The plurality of flanges include the same material.

16. The semiconductor memory device according to claim 15.

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