Semiconductor storage device

Abstract

To provide a semiconductor storage device including an oxide semiconductor transistor.SOLUTION: A semiconductor storage device of an embodiment comprises: a first capacitor including a first electrode, a second electrode, and a first capacitor insulation film provided between the first and second electrodes; and a first transistor including a first oxide semiconductor layer electrically connected to the second electrode and extending in a first direction, a first gate electrode surrounding the first oxide semiconductor layer, and a third electrode electrically connected to the first oxide semiconductor layer and provided on the opposite side of the second electrode. The second electrode includes a first portion, a second portion provided between the first portion and the first oxide semiconductor layer, and a third portion provided between the second portion and the first oxide semiconductor layer. A first width in a second direction perpendicular to the first direction of the first portion is smaller than a second width in the second direction of the second portion, and a third width in the second direction of the third portion is smaller than the second width.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] An oxide semiconductor transistor having a channel formed in an oxide semiconductor layer has an excellent characteristic of extremely small channel leakage current during off-state operation. Therefore, for example, the oxide semiconductor transistor can be applied to a switching transistor of a memory cell of a dynamic random access memory (DRAM). When the oxide semiconductor transistor is applied to a switching transistor of a memory cell, the oxide semiconductor layer of the oxide semiconductor transistor is electrically connected to a storage node electrode of a capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0285350 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor memory device including an oxide semiconductor transistor. [Means for solving the problem]

[0005] a first transistor including: a first capacitor including a first electrode, a second electrode, and a first capacitor insulating film provided between the first electrode and the second electrode; a first oxide semiconductor layer electrically connected to the second electrode and extending in a first direction; a first gate electrode surrounding the first oxide semiconductor layer; a first gate insulating film provided between the first gate electrode and the first oxide semiconductor layer; and a third electrode electrically connected to the first oxide semiconductor layer and having the first oxide semiconductor layer provided between the second electrode and the first gate electrode; [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an equivalent circuit diagram of a semiconductor memory device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment. [Figure 5] FIG. 2 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the first embodiment. [Figure 6] FIG. 2 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the first embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 8] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 9] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10]5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a comparative example. [Figure 16] FIG. 2 is a schematic cross-sectional view of a semiconductor memory device according to a first modified example of the first embodiment. [Figure 17] FIG. 2 is an enlarged schematic cross-sectional view of a semiconductor memory device according to a first modified example of the first embodiment. [Figure 18] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. [Figure 20] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a second embodiment. [Figure 21] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a second embodiment. [Figure 22] FIG. 10 is an enlarged schematic cross-sectional view of a semiconductor memory device according to a second embodiment. [Figure 23] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 24] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 25] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 26] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 27] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 28]5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 29] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described may be omitted as appropriate.

[0008] Furthermore, in this specification, the terms "upper", "lower", "upper", "lower", "upper" or "lower" may be used for convenience. "Up", "lower", "upper", "lower", "upper" or "lower" are terms that indicate a relative positional relationship within the drawing, and are not terms that define a positional relationship with respect to gravity.

[0009] Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor memory device in this specification can be performed using, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford backscattering spectroscopy (RBS). Furthermore, for measuring the thickness of the components constituting the semiconductor memory device, the distance between the components, the crystal grain size, and the crystal orientation, for example, a transmission electron microscope (TEM) can be used. Furthermore, for measuring the crystal orientation, for example, nanobeam electron diffraction (NBED) can be used.

[0010] (First embodiment) A semiconductor memory device according to a first embodiment includes a first capacitor including a first electrode, a second electrode, and a first capacitor insulating film provided between the first and second electrodes; a first oxide semiconductor layer electrically connected to the second electrode and extending in a first direction; a first gate electrode surrounding the first oxide semiconductor layer; a first gate insulating film provided between the first gate electrode and the first oxide semiconductor layer; and a third electrode electrically connected to the first oxide semiconductor layer and having the first oxide semiconductor layer provided between the first electrode and the second electrode. The second electrode includes a first portion, a second portion provided between the first portion and the first oxide semiconductor layer, and a third portion provided between the second portion and the first oxide semiconductor layer. A first width of the first portion in a second direction perpendicular to the first direction is smaller than a second width of the second portion in the second direction, and a third width of the third portion in the second direction is smaller than the second width.

[0011] 1 is an equivalent circuit diagram of a semiconductor memory device according to a first embodiment. The semiconductor memory device according to the first embodiment is a semiconductor memory 100. The semiconductor memory 100 according to the first embodiment is a DRAM. The semiconductor memory 100 uses oxide semiconductor transistors as switching transistors of memory cells of the DRAM.

[0012] 1 is a diagram showing a portion of a memory cell array included in a semiconductor memory 100. A plurality of memory cells are arranged in the memory cell array. While FIG. 1 illustrates an example in which there are four memory cells, the number of memory cells included in the memory cell array is not limited to four.

[0013] The memory cell array of the semiconductor memory 100 includes a plurality of memory cells MC1, MC2, MC3, and MC4, a plurality of word lines WL1 and WL2, a plurality of bit lines BL1 and BL2, and a plate line PL. The first memory cell MC1 includes a first transistor TR1 and a first capacitor CA1. The second memory cell MC2 includes a second transistor TR2 and a second capacitor CA2. The third memory cell MC3 includes a third transistor TR3 and a third capacitor CA3. The fourth memory cell MC4 includes a fourth transistor TR4 and a fourth capacitor CA4.

[0014] Hereinafter, one of the memory cells MC1, MC2, MC3, and MC4, or the memory cells MC1, MC2, MC3, and MC4 collectively, may be simply referred to as a memory cell MC. Also, one of the word lines WL1 and WL2, or the word lines WL1 and WL2 collectively, may be simply referred to as a word line WL. Also, one of the bit lines BL1 and BL2, or the bit lines BL1 and BL2 collectively, may be simply referred to as a bit line BL.

[0015] Hereinafter, one of the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4, or the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 collectively, may be simply referred to as a transistor TR. Also, one of the first capacitor CA1, the second capacitor CA2, the third capacitor CA3, and the fourth capacitor CA4, or the first capacitor CA1, the second capacitor CA2, the third capacitor CA3, and the fourth capacitor CA4 collectively, may be simply referred to as a capacitor CA.

[0016] The word line WL is electrically connected to the gate electrode of the transistor TR. The bit line BL is electrically connected to one of the source and drain electrodes of the transistor TR. The other of the source and drain electrodes of the transistor TR is electrically connected to one of the electrodes of the capacitor CA. The other of the electrodes of the capacitor CA is connected to the plate line PL.

[0017] The memory cell MC stores data by storing charge in a capacitor CA. Data is written and read by turning on a transistor TR.

[0018] One memory cell MC can be selected by selecting one bit line BL and one word line WL. For example, by applying a desired voltage to the bit line BL and a voltage to the word line WL, the transistor TR is turned on and data is written to the memory cell MC. Also, for example, by turning on the transistor TR, a voltage change on the bit line BL corresponding to the amount of charge stored in the capacitor CA is detected and data from the memory cell MC is read.

[0019] 2, 3, and 4 are schematic cross-sectional views of the semiconductor memory device of the first embodiment. Fig. 2 is a cross-section including the first memory cell MC1 and the second memory cell MC2 of Fig. 1.

[0020] Fig. 3 is a cross-sectional view taken along line AA' in Fig. 2. Fig. 4 is a cross-sectional view taken along line BB' in Fig. 2. In Fig. 2, the up-down direction is referred to as a first direction. In Fig. 2, the left-right direction is referred to as a second direction. The second direction is perpendicular to the first direction.

[0021] The semiconductor memory 100 of the first embodiment includes a substrate 10, a substrate insulating layer 12, a plate electrode 14, a first storage node electrode 16a, a second storage node electrode 16b, a first capacitor insulating film 18a, a second capacitor insulating film 18b, a first source-drain electrode 20a, a second source-drain electrode 20b, a first oxide semiconductor layer 22a, a second oxide semiconductor layer 22b, a first gate electrode 24a, a second gate electrode 24b, a first gate insulating film 26a, a second gate insulating film 26b, a bit line 28, and an interlayer insulating layer 30.

[0022] The first storage node electrode 16a includes a first metal region 16a1 and a first oxide conductor region 16a2, and the second storage node electrode 16b includes a second metal region 16b1 and a second oxide conductor region 16b2.

[0023] The plate electrode 14 is an example of a first electrode. The first storage node electrode 16a is an example of a second electrode. The second storage node electrode 16b is an example of a fourth electrode. The first source-drain electrode 20a is an example of a third electrode. The second source-drain electrode 20b is an example of a fifth electrode.

[0024] The first metal region 16a1 is an example of a first region, and the first oxide conductor region 16a2 is an example of a second region.

[0025] Hereinafter, the first storage node electrode 16a and the second storage node electrode 16b may be collectively referred to as storage node electrodes 16. The first capacitor insulating film 18a and the second capacitor insulating film 18b may be collectively referred to as capacitor insulating film 18. The first source-drain electrode 20a and the second source-drain electrode 20b may be collectively referred to as source-drain electrodes 20. The first oxide semiconductor layer 22a and the second oxide semiconductor layer 22b may be collectively referred to as oxide semiconductor layers 22. The first gate electrode 24a and the second gate electrode 24b may be collectively referred to as gate electrodes 24. The first gate insulating film 26a and the second gate insulating film 26b may be collectively referred to as gate insulating film 26.

[0026] The substrate 10 is, for example, a semiconductor substrate. The substrate 10 is, for example, a silicon substrate. For example, an insulating substrate can also be used as the substrate 10. Furthermore, the substrate 10 can also be omitted.

[0027] A memory cell array is provided on a substrate 10. A transistor TR and a capacitor CA are provided on the substrate 10. The capacitor CA is provided between the substrate 10 and the transistor TR.

[0028] The substrate insulating layer 12 is provided on the substrate 10. The substrate insulating layer 12 is provided between the substrate 10 and the plate electrode 14. The substrate insulating layer 12 is an insulator. The substrate insulating layer 12 is, for example, silicon oxide.

[0029] The capacitor CA includes a plate electrode 14, a storage node electrode 16, and a capacitor insulating film 18.

[0030] The plate electrode 14 is provided on the substrate insulating layer 12. The plate electrode 14 is a conductor. The plate electrode 14 includes, for example, a metal or a metal compound. The plate electrode 14 is, for example, titanium nitride.

[0031] The plate electrode 14 corresponds to the plate line PL in the equivalent circuit diagram of FIG.

[0032] The storage node electrode 16 is provided on the plate electrode 14. The storage node electrode 16 extends in a first direction. The storage node electrode 16 is a conductor.

[0033] The first storage node electrode 16a includes, for example, a first metal region 16a1 and a first oxide conductor region 16a2, and the second storage node electrode 16b includes, for example, a second metal region 16b1 and a second oxide conductor region 16b2.

[0034] The first oxide conductor region 16a2 is provided between the first metal region 16a1 and the first oxide semiconductor layer 22a and is in contact with the first metal region 16a1 and the first oxide semiconductor layer 22a.

[0035] The second oxide conductor region 16b2 is provided between the second metal region 16b1 and the second oxide semiconductor layer 22b and is in contact with the second metal region 16b1 and the second oxide semiconductor layer 22b.

[0036] The first metal region 16a1 and the second metal region 16b1 include a metal or a metal compound. The first metal region 16a1 and the second metal region 16b1 are, for example, metal nitrides. The first metal region 16a1 and the second metal region 16b1 include, for example, at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), and nitrogen (N). The first metal region 16a1 and the second metal region 16b1 are, for example, titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

[0037] The first oxide conductor region 16a2 and the second oxide conductor region 16b2 include an oxide conductor, and the chemical compositions of the first oxide conductor region 16a2 and the second oxide conductor region 16b2 are different from the chemical compositions of the first metal region 16a1 and the second metal region 16b1.

[0038] The first oxide conductor region 16a2 and the second oxide conductor region 16b2 contain, for example, at least one metal element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O). The first oxide conductor region 16a2 and the second oxide conductor region 16b2 contain, for example, indium tin oxide. The first oxide conductor region 16a2 and the second oxide conductor region 16b2 are, for example, indium tin oxide.

[0039] The first oxide conductor region 16a2 is, for example, polycrystalline. The

[0111] directions of the crystals contained in the first oxide conductor region 16a2 are oriented in a first direction. Whether the

[0111] directions of the crystals contained in the first oxide conductor region 16a2 are oriented in the first direction can be determined, for example, from an image acquired by a TEM. For example, the angle between the

[0111] axes of the crystals and the first direction is calculated from an image of a cross section parallel to the first direction. If the average value of the calculated angles is within 20 degrees, the

[0111] directions of the crystals are considered to be oriented in the first direction. Whether the

[0111] directions of the crystals contained in the first oxide conductor region 16a2 are oriented in the first direction can be determined, for example, from an electron diffraction pattern acquired by nanobeam electron diffraction. For example, if the diffraction spot intensity in the

[0111] direction is greater than the diffraction spot intensity in other directions, the

[0111] directions of the multiple crystals are considered to be oriented in the first direction.

[0040] The second oxide conductor region 16b2 is, for example, polycrystalline, and the

[0111] directions of the crystals contained in the second oxide conductor region 16b2 are oriented in the first direction.

[0041] The capacitor insulating film 18 is provided between the plate electrode 14 and the storage node electrode 16. The capacitor insulating film 18 contacts the plate electrode 14 and the storage node electrode 16.

[0042] The capacitor insulating film 18 is an insulator. The capacitor insulating film 18 includes, for example, an insulator having a higher dielectric constant than silicon dioxide. The capacitor insulating film 18 includes, for example, a so-called high-k insulator.

[0043] The capacitor insulating film 18 contains, for example, zirconium oxide and has a multilayer structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide.

[0044] The plate electrode 14 is provided outside the storage node electrode 16. As shown in FIG. 3, in the AA' cross section perpendicular to the first direction, the plate electrode 14 surrounds the storage node electrode 16. In the AA' cross section, the plate electrode 14 surrounds the capacitor insulating film 18. In the AA' cross section, the capacitor insulating film 18 surrounds the storage node electrode 16.

[0045] The transistor TR includes an oxide semiconductor layer 22, a gate electrode 24, a gate insulating film 26, a storage node electrode 16, and source / drain electrodes 20. The storage node electrode 16 functions as the source / drain electrodes of the transistor TR.

[0046] The oxide semiconductor layer 22 is provided on the storage node electrode 16. The oxide semiconductor layer 22 is provided between the storage node electrode 16 and the source / drain electrodes 20.

[0047] The oxide semiconductor layer 22 is electrically connected to the storage node electrode 16 and the source / drain electrodes 20. The oxide semiconductor layer 22 is in contact with, for example, the storage node electrode 16 and the source / drain electrodes 20. The oxide semiconductor layer 22 extends in a first direction.

[0048] In the oxide semiconductor layer 22, a channel that serves as a current path is formed when the transistor TR is in an on-state.

[0049] The oxide semiconductor layer 22 is an oxide semiconductor, and is, for example, amorphous.

[0050] The oxide semiconductor layer 22 contains at least one metal element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), calcium (Ca), and cadmium (Cd), and oxygen (O).

[0051] The oxide semiconductor layer 22 contains, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), zinc (Zn), and oxygen (O). The oxide semiconductor layer 22 contains, for example, indium gallium zinc oxide. The oxide semiconductor layer 22 is, for example, indium gallium zinc oxide.

[0052] The oxide semiconductor layer 22 has a chemical composition different from the chemical compositions of the storage node electrode 16 and the source / drain electrodes 20, for example.

[0053] The oxide semiconductor layer 22 contains, for example, oxygen vacancies, which function as donors.

[0054] The gate electrode 24 faces the oxide semiconductor layer 22. As shown in Fig. 4, the gate electrode 24 surrounds the oxide semiconductor layer 22 in the cross section BB' perpendicular to the first direction. The gate electrode 24 is provided around the oxide semiconductor layer 22. The transistor TR is a so-called surrounding gate transistor (SGT).

[0055] The gate electrode 24 is a conductor. The gate electrode 24 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 24 includes, for example, tungsten (W). The gate electrode 24 is, for example, tungsten.

[0056] The gate electrodes 24 correspond to the word lines WL in the equivalent circuit diagram of Fig. 1. For example, the first gate electrode 24a corresponds to the first word line WL1. Also, for example, the second gate electrode 24b corresponds to the second word line WL2.

[0057] The gate insulating film 26 is provided between the oxide semiconductor layer 22 and the gate electrode 24. As shown in FIG. 4 , the gate insulating film 26 surrounds the oxide semiconductor layer 22 in the cross section taken along line BB′ perpendicular to the first direction. The gate insulating film 26 is provided between the storage node electrode 16 and the source-drain electrodes 20. The gate insulating film 26 is in contact with, for example, the storage node electrode 16 and the source-drain electrodes 20.

[0058] The gate insulating film 26 is an insulator. The gate insulating film 26 contains, for example, silicon (Si) and nitrogen (N). The gate insulating film 26 contains, for example, silicon nitride.

[0059] The source / drain electrode 20 is provided on the oxide semiconductor layer 22. The source / drain electrode 20 is in contact with the oxide semiconductor layer 22. The source / drain electrode 20 is provided on the side of the oxide semiconductor layer 22 opposite to the storage node electrode 16. The oxide semiconductor layer 22 is provided between the storage node electrode 16 and the source / drain electrode 20.

[0060] The source / drain electrodes 20 include, for example, an oxide conductor. The source / drain electrodes 20 include, for example, the same oxide conductor as the storage node electrode 16.

[0061] The source / drain electrodes 20 contain, for example, at least one metal element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O). The source / drain electrodes 20 contain, for example, indium tin oxide. The source / drain electrodes 20 are, for example, indium tin oxide.

[0062] The bit line 28 is provided on the transistor TR. The bit line 28 extends in the second direction. The bit line 28 is provided on the source-drain electrode 20. The bit line 28 is in contact with the source-drain electrode 20.

[0063] The bit line 28 is a conductor. The bit line 28 includes, for example, a metal or a metal compound. The bit line 28 includes, for example, at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). The bit line 28 has, for example, a stacked structure of titanium nitride and tungsten.

[0064] The bit line 28 corresponds to the bit line BL in the equivalent circuit diagram of Fig. 1. For example, the bit line 28 corresponds to the first bit line BL1.

[0065] The interlayer insulating layer 30 is provided around the memory cells MC. The interlayer insulating layer 30 is provided, for example, around the first memory cell MC1 and the second memory cell MC2.

[0066] The interlayer insulating layer 30 is an insulator and includes, for example, silicon oxide.

[0067] Fig. 5 is an enlarged schematic cross-sectional view of the semiconductor memory device of the first embodiment. Fig. 5 is an enlarged schematic cross-sectional view of a portion of Fig. 1. Fig. 5 shows a portion of the storage node electrode 16, a portion of the oxide semiconductor layer 22, and a portion of the gate insulating film 26 of the first memory cell MC1 and the second memory cell MC2.

[0068] The first storage node electrode 16a includes a first portion 16ax, a second portion 16ay, and a third portion 16az. The second portion 16ay is provided between the first oxide semiconductor layer 22a and the first portion 16ax. The third portion 16az is provided between the first oxide semiconductor layer 22a and the second portion 16ay.

[0069] The third portion 16az is the uppermost portion of the first storage node electrode 16a. The third portion 16az is in contact with, for example, the first oxide semiconductor layer 22a.

[0070] The first width (W1 in FIG. 5) of the first portion 16ax in the second direction is smaller than the second width (W2 in FIG. 5) of the second portion 16ay in the second direction. Also, the third width (W3 in FIG. 5) of the third portion 16az in the second direction is smaller than the second width W2.

[0071] The upper portion of the first storage node electrode 16a has a barrel shape in a cross section parallel to the first direction.

[0072] The first portion 16ax is located, for example, in the first metal region 16a1. The second portion 16ay is located, for example, in the first oxide conductor region 16a2. The third portion 16az is located, for example, in the first oxide conductor region 16a2.

[0073] For example, the first width W1 is 0.5 to 0.9 times the second width W2. Also, for example, the third width W3 is 0.7 to 0.95 times the second width W2. Also, for example, the third width W3 is larger than the first width W1.

[0074] The second storage node electrode 16b includes a fourth portion 16bx, a fifth portion 16by, and a sixth portion 16bz. The fifth portion 16by is provided between the second oxide semiconductor layer 22b and the fourth portion 16bx. The sixth portion 16bz is provided between the second oxide semiconductor layer 22b and the fifth portion 16by.

[0075] The sixth portion 16bz is the uppermost portion of the second storage node electrode 16b. The sixth portion 16bz is in contact with, for example, the second oxide semiconductor layer 22b.

[0076] The first width (W4 in FIG. 5) of the fourth portion 16bx in the second direction is smaller than the second width (W5 in FIG. 5) of the fifth portion 16by in the second direction. Also, the sixth width (W6 in FIG. 5) of the sixth portion 16bz in the second direction is smaller than the fifth width W5.

[0077] The upper portion of the second storage node electrode 16b has a barrel shape in a cross section parallel to the first direction.

[0078] The fourth portion 16bx is located, for example, in the second metal region 16b1. The fifth portion 16by is located, for example, in the second oxide conductor region 16b2. The sixth portion 16bz is located, for example, in the second oxide conductor region 16b2.

[0079] For example, the fourth width W4 is 0.5 to 0.9 times the fifth width W5. Also, for example, the sixth width W6 is 0.7 to 0.95 times the fifth width W5. For example, the sixth width W6 is larger than the fourth width W4.

[0080] 5, the shortest distance between the first storage node electrode 16a and the second storage node electrode 16b in the second direction (d in FIG. 5) is smaller than, for example, the first width W1. Also, as shown in FIG. 5, the shortest distance between the first storage node electrode 16a and the second storage node electrode 16b in the second direction (d in FIG. 5) is smaller than, for example, the fourth width W4.

[0081] The first oxide conductor region 16a2 covers, for example, the side surface of the first metal region 16a1, and the second oxide conductor region 16b2 covers, for example, the side surface of the second metal region 16b1.

[0082] Fig. 6 is an enlarged schematic cross-sectional view of the semiconductor memory device of the first embodiment, taken along the line CC' in Fig. 5. The CC' cross section is perpendicular to the first direction.

[0083] 6, for example, in the CC' cross section, the first oxide conductor region 16a2 surrounds at least a part of the first metal region 16a1. Also, as shown in FIG. 6, for example, in the CC' cross section, the second oxide conductor region 16b2 surrounds at least a part of the second metal region 16b1.

[0084] Next, an example of a method for manufacturing the semiconductor memory device of the first embodiment will be described.

[0085] A method for manufacturing a semiconductor memory device according to a first embodiment includes forming a first pillar having a layered structure made of a first conductor, an insulator, and a second conductor, the first pillar having at least an upper surface made of the second conductor, the first pillar protruding from the periphery and extending in a first direction; forming a second pillar having a layered structure made of the first conductor, the insulator, and the second conductor, the second pillar having at least an upper surface made of the second conductor, the second pillar protruding from the periphery and extending in the first direction, the second pillar being positioned in a second direction perpendicular to the first direction with respect to the first pillar; forming oxide conductors on the upper surfaces of the first pillar and the second pillar such that the oxide conductors formed on the upper surfaces of the first pillar and the second pillar do not contact each other; removing corners of the upper surface of the oxide conductor formed on at least the upper surface of the first pillar; removing corners of the upper surface of the oxide conductor formed on at least the upper surface of the second pillar; and filling a space between the first pillar and the second pillar with an insulating film.

[0086] 7, 8, 9, 10, 11, 12, 13, and 14 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device of the first embodiment. Each of Figures 7 to 14 shows a cross section corresponding to Figure 2. Figures 7 to 14 are views showing an example of a method for manufacturing the semiconductor memory 100.

[0087] The following description will be given taking as an example a case where the substrate insulating layer 12 is silicon oxide, the plate electrode 14 is titanium nitride, the metal region of the storage node electrode 16 is titanium nitride, the oxide conductor region of the storage node electrode 16 is indium tin oxide, the capacitor insulating film 18 is zirconium oxide, the source / drain electrodes 20 are indium tin oxide, the oxide semiconductor layer 22 is indium gallium zinc oxide, the gate electrode 24 is tungsten, the gate insulating film 26 is silicon nitride, and the interlayer insulating layer 30 is silicon oxide.

[0088] First, a first silicon oxide film 51, a first titanium nitride film 52, a second silicon oxide film 53, and a first silicon nitride film 54 are formed on the substrate 10. The first silicon oxide film 51, the first titanium nitride film 52, the second silicon oxide film 53, and the first silicon nitride film 54 are formed by, for example, a chemical vapor deposition method (CVD method).

[0089] The first silicon oxide film 51 will eventually become the substrate insulating layer 12. The first titanium nitride film 52 will eventually become part of the plate electrode 14. The second silicon oxide film 53 will eventually become part of the interlayer insulating layer 30.

[0090] Next, a first opening 55 is formed that penetrates the first silicon nitride film 54 and the second silicon oxide film 53 and reaches the first titanium nitride film 52 (FIG. 7). The first opening 55 is formed by using, for example, lithography and reactive ion etching (RIE).

[0091] Next, the first opening 55 is filled with a second titanium nitride film 56, a zirconium oxide film 57, and a third titanium nitride film 58. The second titanium nitride film 56, the zirconium oxide film 57, and the third titanium nitride film 58 are formed by, for example, an atomic layer deposition method (ALD method). Note that before the zirconium oxide film 57 is formed, the second titanium nitride film 56 is patterned in the first opening 55.

[0092] Next, the zirconium oxide film 57 and the third titanium nitride film 58 on the surface of the first silicon nitride film 54 are removed (FIG. 8). The zirconium oxide film 57 and the third titanium nitride film 58 are removed by, for example, chemical mechanical polishing (CMP).

[0093] The second titanium nitride film 56 will eventually become a part of the plate electrode 14. The zirconium oxide film 57 will eventually become a capacitor insulating film 18. The third titanium nitride film 58 will eventually become a part of the storage node electrode 16.

[0094] Next, the first silicon nitride film 54 and a portion of the zirconium oxide film 57 are removed (FIG. 9). The first silicon nitride film 54 and a portion of the zirconium oxide film 57 are removed by, for example, wet etching.

[0095] By removing the first silicon nitride film 54, a part of the third titanium nitride film 58 protrudes from the upper surface of the second silicon oxide film 53. A pillar 58x of titanium nitride protruding from the surrounding insulator is formed.

[0096] The pillar 58x has a layered structure of a second titanium nitride film 56, a zirconium oxide film 57, and a third titanium nitride film 58. The top and side surfaces of the pillar 58x are made of titanium nitride.

[0097] Next, an indium tin oxide film 60 is formed on the upper surfaces of the pillars 58x of the third titanium nitride film 58 (FIG. 10). The indium tin oxide film 60 is formed under conditions in which the upward growth rate is faster than the lateral growth rate. The indium tin oxide film 60 is also formed under conditions in which step coverage is poor.

[0098] The width in the second direction of the indium tin oxide film 60 formed on the top surface of the pillar 58x is larger than the width in the second direction of the pillar 58x. Furthermore, the indium tin oxide films 60 formed on the top surfaces of two pillars 58x adjacent to each other in the second direction are formed so as not to be in contact with each other.

[0099] The indium tin oxide film 60 is formed under conditions such that, for example, the

[0111] directions of the multiple crystals contained in the indium tin oxide film 60 are oriented in a direction perpendicular to the top surfaces of the pillars 58x of the third titanium nitride film 58. The indium tin oxide film 60 is formed such that, for example, the

[0111] directions of the multiple crystals contained in the indium tin oxide film 60 are oriented in a first direction. By forming the indium tin oxide film 60 such that the

[0111] directions of the multiple crystals contained in the indium tin oxide film 60 are oriented in the first direction, the upward growth rate of the indium tin oxide film 60 becomes faster than the lateral growth rate.

[0100] The indium tin oxide film 60 is formed, for example, so as to cover a portion of the side surface of the pillar 58x. Because the indium tin oxide film 60 is formed under conditions that result in a fast upward growth rate, the indium tin oxide films 60 on two adjacent pillars 58x are prevented from coming into contact with each other. Furthermore, because the indium tin oxide film 60 is formed under conditions that result in poor step coverage, the indium tin oxide film 60 is hardly formed on the top surface of the second silicon oxide film 53 between two adjacent pillars 58x.

[0101] The indium tin oxide film 60 is formed by, for example, a physical vapor deposition (PVD) method which has poor step coverage, or by, for example, a sputtering method which has poor step coverage.

[0102] Next, the corners of the upper surface of the indium tin oxide film 60 are removed (FIG. 11). The corners of the upper surface of the indium tin oxide film 60 are formed into a forward tapered shape.

[0103] For example, the corners of the upper surface of the indium tin oxide film 60 are removed by RIE, or for example, the corners of the upper surface of the indium tin oxide film 60 are removed by wet etching.

[0104] For example, even if the indium tin oxide film 60 is formed on the upper surface of the second silicon oxide film 53 between the two pillars 58x, it is possible to remove the indium tin oxide film 60 by etching to remove the corners of the upper surface of the indium tin oxide film 60.

[0105] Next, a third silicon oxide film 61 is formed on the indium tin oxide film 60 and the second silicon oxide film 53. The third silicon oxide film 61 is formed by, for example, a CVD method. The corners of the upper surface of the indium tin oxide film 60 have a forward tapered shape, which improves the embedding property of the third silicon oxide film 61 between two adjacent pillars 58x. The third silicon oxide film 61 will eventually become part of the interlayer insulating layer 30.

[0106] Next, the third silicon oxide film 61 on the indium tin oxide film 60 is removed (FIG. 12). The third silicon oxide film 61 is removed by, for example, CMP.

[0107] Next, a fourth silicon oxide film 62 is formed on the indium tin oxide film 60 and the third silicon oxide film 61. The fourth silicon oxide film 62 is formed by, for example, a CVD method. The fourth silicon oxide film 62 will eventually become a part of the interlayer insulating layer 30.

[0108] Next, a tungsten film 63 is formed on the fourth silicon oxide film 62. The tungsten film 63 is formed by, for example, a CVD method.

[0109] Next, the tungsten film 63 is patterned. The tungsten film 63 is patterned by, for example, lithography and RIE. The tungsten film 63 will eventually become the gate electrode 24.

[0110] Next, a fifth silicon oxide film 64 is formed on the tungsten film 63 (FIG. 13). The fifth silicon oxide film 64 is formed by, for example, a CVD method. The fifth silicon oxide film 64 will eventually become a part of the interlayer insulating layer 30.

[0111] Next, a second opening 65 is formed through the fifth silicon oxide film 64, the tungsten film 63, and the fourth silicon oxide film 62 to reach the indium tin oxide film 60 (FIG. 14). The second opening 65 is formed by using, for example, lithography and RIE.

[0112] Next, a silicon nitride gate insulating film 26 and an indium gallium zinc oxide oxide semiconductor layer 22 are formed in the second opening 65. Next, an indium tin oxide source / drain electrode 20 is formed on the oxide semiconductor layer 22. Thereafter, a tungsten bit line 28 is formed on the source / drain electrode 20.

[0113] By the above manufacturing method, the semiconductor memory 100 shown in FIGS. 2, 3, 4, 5, and 6 is manufactured.

[0114] Next, the operation and effects of the semiconductor memory device of the first embodiment will be described.

[0115] When an oxide semiconductor transistor is used as a switching transistor of a DRAM memory cell, the oxide semiconductor layer of the oxide semiconductor transistor is electrically connected to a storage node electrode of a capacitor. From the viewpoint of improving the characteristics of the DRAM memory cell, it is desirable to reduce the connection resistance between the oxide semiconductor layer and the storage node electrode. Reducing the connection resistance between the oxide semiconductor layer and the storage node electrode improves, for example, the operating speed of the memory cell.

[0116] Fig. 15 is a schematic cross-sectional view of a semiconductor memory device of a comparative example. The semiconductor memory 900 of the comparative example is a DRAM. The semiconductor memory 900 uses oxide semiconductor transistors as switching transistors of memory cells of the DRAM. Fig. 15 corresponds to Fig. 2 of the first embodiment.

[0117] The semiconductor memory 900 of the comparative example differs from the semiconductor memory 100 of the first embodiment in that the width of the upper part of the storage node electrode 16 in the second direction is constant. The semiconductor memory 900 also differs from the semiconductor memory 100 of the first embodiment in that the upper part of the storage node electrode 16 is rectangular rather than barrel-shaped in a cross section parallel to the first direction. The semiconductor memory 900 also differs from the semiconductor memory 100 of the first embodiment in that the first oxide conductor region 16a2 does not cover the side surfaces of the first metal region 16a1. The semiconductor memory 900 also differs from the semiconductor memory 100 of the first embodiment in that the second oxide conductor region 16b2 does not cover the side surfaces of the second metal region 16b1.

[0118] In the comparative semiconductor memory 900, the width in the second direction of the upper part of the storage node electrode 16 is constant. Therefore, the electrical resistance of the upper part of the storage node electrode 16 increases, which may increase the connection resistance between the oxide semiconductor layer 22 and the storage node electrode 16.

[0119] In the semiconductor memory 100 of the first embodiment, the width in the second direction of the upper part of the storage node electrode 16 is partially increased, which reduces the electrical resistance of the upper part of the storage node electrode 16 and the connection resistance between the oxide semiconductor layer 22 and the storage node electrode 16.

[0120] In the comparative semiconductor memory 900, the first oxide conductor region 16a2 and the first metal region 16a1 of the first memory cell MC1 are in contact only at the top surface of the first metal region 16a1. Therefore, the interface resistance between the first oxide conductor region 16a2 and the first metal region 16a1 may be increased. This may increase the connection resistance between the first oxide semiconductor layer 22a and the first storage node electrode 16a. For the same reason, the connection resistance between the second oxide semiconductor layer 22b and the second storage node electrode 16b of the second memory cell MC2 may be increased.

[0121] In the semiconductor memory 100 of the first embodiment, the first oxide conductor region 16a2 and the first metal region 16a1 of the first memory cell MC1 are in contact with each other at the top and side surfaces of the first metal region 16a1. This reduces the interface resistance between the first oxide conductor region 16a2 and the first metal region 16a1, thereby reducing the connection resistance between the first oxide semiconductor layer 22a and the first storage node electrode 16a. For the same reason, the connection resistance between the second oxide semiconductor layer 22b and the second storage node electrode 16b of the second memory cell MC2 is also reduced.

[0122] To further reduce the interface resistance between the first oxide conductor region 16a2 and the first metal region 16a1, the first oxide conductor region 16a2 preferably surrounds at least a portion of the first metal region 16a1 in a cross section perpendicular to the first direction, as shown in Fig. 6. For the same reason, the second oxide conductor region 16b2 preferably surrounds at least a portion of the second metal region 16b1 in a cross section perpendicular to the first direction.

[0123] In the comparative semiconductor memory 900, the width of the upper portion of the storage node electrode 16 in the second direction is constant. Therefore, when an opening for forming the oxide semiconductor layer 22 is provided above the storage node electrode 16, the alignment margin between the opening and the upper surface of the storage node electrode 16 becomes small. This may make it difficult to manufacture the semiconductor memory 900.

[0124] In the semiconductor memory 100 of the first embodiment, the width of the upper part of the storage node electrode 16 in the second direction is partially increased. Therefore, when an opening for forming the oxide semiconductor layer 22 is provided above the storage node electrode 16, there is a large alignment margin between the opening and the upper part of the storage node electrode 16. This makes it easier to manufacture the semiconductor memory 100.

[0125] In the semiconductor memory 100 of the first embodiment, the corners of the upper surface of the upper portion of the storage node electrode 16 are forward tapered. This improves the embedding property when forming an insulating film on the storage node electrode 16. For example, this improves the embedding property of the insulating film in the portion between the first oxide conductor region 16a2 and the second oxide conductor region 16b2. This improves, for example, the manufacturing yield of the semiconductor memory 100.

[0126] The first width W1 of the first portion 16ax of the first storage node electrode 16a is preferably 0.5 to 0.9 times, and more preferably 0.6 to 0.8 times, the second width W2.

[0127] When the thickness exceeds the lower limit, the width of the upper part of the first storage node electrode 16a in the second direction increases, thereby reducing the electrical resistance of the storage node electrode 16. When the thickness exceeds the lower limit, the width of the upper part of the first storage node electrode 16a in the second direction increases, thereby increasing the alignment margin between the opening for forming the oxide semiconductor layer 22 and the upper part of the storage node electrode 16 when the opening is provided above the storage node electrode 16.

[0128] Furthermore, by keeping the value below the upper limit, the distance between the first storage node electrode 16a and the second storage node electrode 16b can be secured, and an electrical short circuit between the first storage node electrode 16a and the second storage node electrode 16b can be suppressed.

[0129] For the same reasons as above, the fourth width W4 of the fourth portion 16bx of the second storage node electrode 16b is preferably 0.5 to 0.9 times the fifth width W5, and more preferably 0.6 to 0.8 times the fifth width W5.

[0130] The third width W3 of the first storage node electrode 16a is preferably 0.7 to 0.95 times the second width W2, and more preferably 0.8 to 0.9 times.

[0131] Exceeding the lower limit increases the width of the upper surface of the first storage node electrode 16a in the second direction, thereby reducing the electrical resistance of the storage node electrode 16. Exceeding the lower limit also increases the width of the upper surface of the first storage node electrode 16a in the second direction, thereby increasing the alignment margin between the opening for forming the oxide semiconductor layer 22 and the upper surface of the storage node electrode 16 when the opening is provided above the storage node electrode 16.

[0132] Furthermore, by making the thickness smaller than the upper limit, the angle of the forward taper of the corner of the upper surface of the upper part of the storage node electrode 16 becomes larger, and the embedding property is further improved when forming an insulating film on the first storage node electrode 16a.

[0133] For the same reasons as above, the sixth width W6 of the second storage node electrode 16b is preferably 0.7 to 0.95 times, and more preferably 0.8 to 0.9 times, the fifth width W5.

[0134] From the viewpoint of reducing the electrical resistance of the first storage node electrode 16a, the third width W3 of the first storage node electrode 16a is preferably larger than the first width W1. From the viewpoint of reducing the electrical resistance of the second storage node electrode 16b, the sixth width W6 of the second storage node electrode 16b is preferably larger than the fourth width W4.

[0135] From the viewpoint of reducing the electrical resistance of the storage node electrode 16, it is preferable that the shortest distance (d in FIG. 5) between the first storage node electrode 16a and the second storage node electrode 16b in the second direction is smaller than the first width W1 of the first storage node electrode 16a and the fourth width W4 of the second storage node electrode 16b.

[0136] According to the semiconductor memory 100 of the first embodiment, the connection resistance between the oxide semiconductor layer 22 and the storage node electrode 16 can be reduced.

[0137] (First Modification) The semiconductor memory device of the first modification of the first embodiment differs from the semiconductor memory device of the first embodiment in that the second electrode further includes a third region of semiconductor surrounded by the first region. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0138] Fig. 16 is a schematic cross-sectional view of a semiconductor memory device according to a first modification of the first embodiment. The semiconductor memory device according to the first modification is a semiconductor memory 101. Fig. 16 corresponds to Fig. 2 of the first embodiment.

[0139] The first storage node electrode 16a further includes a first semiconductor region 16a3, which is an example of a third region.

[0140] The first semiconductor region 16a3 is surrounded by the first metal region 16a1. The first semiconductor region 16a3 includes a semiconductor. For example, the first semiconductor region 16a3 is polycrystalline silicon germanium containing conductive impurities. The first semiconductor region 16a3 is, for example, polycrystalline silicon containing conductive impurities.

[0141] The second storage node electrode 16b further includes a second semiconductor region 16b3.

[0142] The second semiconductor region 16b3 is surrounded by the second metal region 16b1. The second semiconductor region 16b3 includes a semiconductor. The second semiconductor region 16b3 is, for example, polycrystalline silicon germanium containing conductive impurities. The second semiconductor region 16b3 is, for example, polycrystalline silicon containing conductive impurities.

[0143] When manufacturing semiconductor memory 101, for example, first metal region 16a1 in contact with the bottom and side surfaces of first semiconductor region 16a3 and first metal region 16a1 in contact with the top surface of first semiconductor region 16a3 are formed as separate films. Similarly, second metal region 16b1 in contact with the bottom and side surfaces of second semiconductor region 16b3 and second metal region 16b1 in contact with the top surface of second semiconductor region 16b3 are formed as separate films.

[0144] Fig. 17 is an enlarged schematic cross-sectional view of a semiconductor memory device according to a first modified example of the first embodiment. Fig. 17 is an enlarged schematic cross-sectional view of a portion of Fig. 16. Fig. 17 shows a portion of the storage node electrode 16, a portion of the oxide semiconductor layer 22, and a portion of the gate insulating film 26 of the first memory cell MC1 and the second memory cell MC2. Fig. 17 corresponds to Fig. 5 of the first embodiment.

[0145] The first storage node electrode 16a includes a first portion 16ax, a second portion 16ay, and a third portion 16az. The second portion 16ay is provided between the first oxide semiconductor layer 22a and the first portion 16ax. The third portion 16az is provided between the first oxide semiconductor layer 22a and the second portion 16ay.

[0146] The third portion 16az, which is the topmost portion of the first storage node electrode 16a, is in contact with, for example, the first oxide semiconductor layer 22a.

[0147] The first width (W1 in FIG. 17) of the first portion 16ax in the second direction is smaller than the second width (W2 in FIG. 17) of the second portion 16ay in the second direction. Also, the third width (W3 in FIG. 17) of the third portion 16az in the second direction is smaller than the second width W2.

[0148] The first portion 16ax is located, for example, across the first metal region 16a1 and the first semiconductor region 16a3. The second portion 16ay is located, for example, in the first oxide conductor region 16a2. The third portion 16az is located, for example, in the first oxide conductor region 16a2.

[0149] The second storage node electrode 16b includes a fourth portion 16bx, a fifth portion 16by, and a sixth portion 16bz. The fifth portion 16by is provided between the second oxide semiconductor layer 22b and the fourth portion 16bx. The sixth portion 16bz is provided between the second oxide semiconductor layer 22b and the fifth portion 16by.

[0150] The sixth portion 16bz, which is the topmost portion of the second storage node electrode 16b, is in contact with, for example, the second oxide semiconductor layer 22b.

[0151] The first width (W4 in FIG. 17) of the fourth portion 16bx in the second direction is smaller than the fifth width (W5 in FIG. 17) of the fifth portion 16by in the second direction. Also, the sixth width (W6 in FIG. 17) of the sixth portion 16bz in the second direction is smaller than the fifth width W5.

[0152] The fourth portion 16bx is located, for example, across the second metal region 16b1 and the second semiconductor region 16b3. The fifth portion 16by is located, for example, in the second oxide conductor region 16b2. The sixth portion 16bz is located, for example, in the second oxide conductor region 16b2.

[0153] According to the semiconductor memory 101 of the first modification of the first embodiment, the connection resistance between the oxide semiconductor layer 22 and the storage node electrode 16 can be reduced, similarly to the semiconductor memory 100 of the first embodiment.

[0154] (Second Modification) The semiconductor memory device of the second modification of the first embodiment further includes a first insulating layer provided between the second electrode and the first gate electrode and in contact with the second electrode, and differs from the semiconductor memory device of the first embodiment in that the first insulating layer surrounds the first oxide semiconductor layer in a cross section perpendicular to the first direction. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0155] Fig. 18 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. The semiconductor memory device according to the second modification is a semiconductor memory 102. Fig. 18 corresponds to Fig. 2 of the first embodiment.

[0156] The semiconductor memory 102 includes a first upper surface insulating layer 27a and a second upper surface insulating layer 27b. The first upper surface insulating layer 27a is an example of a first insulating layer.

[0157] The first upper surface insulating layer 27a is provided between the first storage node electrode 16a and the first gate electrode 24a. The first upper surface insulating layer 27a is provided on the first storage node electrode 16a. The first upper surface insulating layer 27a is in contact with the first storage node electrode 16a.

[0158] The second upper surface insulating layer 27b is provided between the second storage node electrode 16b and the second gate electrode 24b. The second upper surface insulating layer 27b is provided on the second storage node electrode 16b. The second upper surface insulating layer 27b is in contact with the second storage node electrode 16b.

[0159] 19 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment, taken along the line DD' in FIG.

[0160] 19, the first top surface insulating layer 27a surrounds the first oxide semiconductor layer 22a in the DD' cross section perpendicular to the first direction, and the second top surface insulating layer 27b surrounds the second oxide semiconductor layer 22b in the DD' cross section perpendicular to the first direction.

[0161] The first upper surface insulating layer 27a and the second upper surface insulating layer 27b are insulators. The chemical compositions of the first upper surface insulating layer 27a and the second upper surface insulating layer 27b are different from the chemical composition of the interlayer insulating layer 30. The first upper surface insulating layer 27a and the second upper surface insulating layer 27b include, for example, silicon nitride or aluminum oxide.

[0162] The first and second upper surface insulating layers 27a and 27b function as a hard mask on the storage node electrode 16 when, for example, manufacturing the semiconductor memory 102. Furthermore, the first and second upper surface insulating layers 27a and 27b function as an etching stopper film when, for example, an opening into which the oxide semiconductor layer 22 is to be embedded is formed above the storage node electrode 16.

[0163] According to the semiconductor memory 102 of the second modification of the first embodiment, the connection resistance between the oxide semiconductor layer 22 and the storage node electrode 16 can be reduced, similar to the semiconductor memory 100 of the first embodiment.

[0164] As described above, according to the first embodiment and the modification, a semiconductor memory device including an oxide semiconductor transistor and having low connection resistance between the oxide semiconductor layer of the oxide semiconductor transistor and the storage node electrode can be realized.

[0165] (Second embodiment) The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that the second electrode surrounds the first electrode in a cross section perpendicular to the first direction. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0166] 20 and 21 are schematic cross-sectional views of the semiconductor memory device of the second embodiment.

[0167] FIG. 21 is a cross-sectional view taken along the line EE' of FIG.

[0168] The semiconductor memory 200 of the second embodiment includes a substrate 10, a substrate insulating layer 12, a plate electrode 14, a first storage node electrode 16a, a second storage node electrode 16b, a first capacitor insulating film 18a, a second capacitor insulating film 18b, a first source-drain electrode 20a, a second source-drain electrode 20b, a first oxide semiconductor layer 22a, a second oxide semiconductor layer 22b, a first gate electrode 24a, a second gate electrode 24b, a first gate insulating film 26a, a second gate insulating film 26b, a bit line 28, and an interlayer insulating layer 30.

[0169] The first storage node electrode 16a includes a first metal region 16a1 and a first oxide conductor region 16a2, and the second storage node electrode 16b includes a second metal region 16b1 and a second oxide conductor region 16b2.

[0170] The plate electrode 14 is an example of a first electrode. The first storage node electrode 16a is an example of a second electrode. The second storage node electrode 16b is an example of a fourth electrode. The first source-drain electrode 20a is an example of a third electrode. The second source-drain electrode 20 is an example of a fifth electrode.

[0171] The first metal region 16a1 is an example of a first region, and the first oxide conductor region 16a2 is an example of a second region.

[0172] Hereinafter, the first storage node electrode 16a and the second storage node electrode 16b may be collectively referred to as storage node electrodes 16. The first capacitor insulating film 18a and the second capacitor insulating film 18b may be collectively referred to as capacitor insulating film 18. The first source-drain electrode 20a and the second source-drain electrode 20b may be collectively referred to as source-drain electrodes 20. The first oxide semiconductor layer 22a and the second oxide semiconductor layer 22b may be collectively referred to as oxide semiconductor layers 22. The first gate electrode 24a and the second gate electrode 24b may be collectively referred to as gate electrodes 24. The first gate insulating film 26a and the second gate insulating film 26b may be collectively referred to as gate electrodes 24.

[0173] The plate electrode 14 is provided inside the storage node electrode 16. As shown in FIG. 21 , in the E-E' cross section perpendicular to the first direction, the storage node electrode 16 surrounds the plate electrode 14. In the E-E' cross section, the storage node electrode 16 surrounds the capacitor insulating film 18. In the E-E' cross section, the capacitor insulating film 18 surrounds the plate electrode 14.

[0174] 21 , in the E-E' cross section perpendicular to the first direction, the first storage node electrode 16a surrounds the plate electrode 14. In the E-E' cross section, the first metal region 16a1 surrounds the plate electrode 14. In the E-E' cross section, the first storage node electrode 16a surrounds the first capacitor insulating film 18a. In the E-E' cross section, the first capacitor insulating film 18a surrounds the plate electrode 14.

[0175] 21 , in the E-E' cross section perpendicular to the first direction, the second storage node electrode 16b surrounds the plate electrode 14. In the E-E' cross section, the second metal region 16b1 surrounds the plate electrode 14. In the E-E' cross section, the second storage node electrode 16b surrounds the second capacitor insulating film 18b. In the E-E' cross section, the second capacitor insulating film 18b surrounds the plate electrode 14.

[0176] Fig. 22 is an enlarged schematic cross-sectional view of a semiconductor memory device of the second embodiment. Fig. 22 is an enlarged schematic cross-sectional view of a portion of Fig. 20. Fig. 22 shows a portion of the storage node electrode 16, a portion of the oxide semiconductor layer 22, and a portion of the gate insulating film 26 of the first memory cell MC1 and the second memory cell MC2. Fig. 22 corresponds to Fig. 5 of the first embodiment.

[0177] The first storage node electrode 16a includes a first portion 16ax, a second portion 16ay, and a third portion 16az. The second portion 16ay is provided between the first oxide semiconductor layer 22a and the first portion 16ax. The third portion 16az is provided between the first oxide semiconductor layer 22a and the second portion 16ay.

[0178] The third portion 16az, which is the topmost portion of the first storage node electrode 16a, is in contact with, for example, the first oxide semiconductor layer 22a.

[0179] The first width (W1 in FIG. 22) of the first portion 16ax in the second direction is smaller than the second width (W2 in FIG. 22) of the second portion 16ay in the second direction. Also, the third width (W3 in FIG. 22) of the third portion 16az in the second direction is smaller than the second width W2.

[0180] The first portion 16ax is located, for example, across the first metal regions 16a1 on either side of the plate electrode 14. The second portion 16ay is located, for example, in the first oxide conductor region 16a2. The third portion 16az is located, for example, in the first oxide conductor region 16a2.

[0181] The second storage node electrode 16b includes a fourth portion 16bx, a fifth portion 16by, and a sixth portion 16bz. The fifth portion 16by is provided between the second oxide semiconductor layer 22b and the fourth portion 16bx. The sixth portion 16bz is provided between the second oxide semiconductor layer 22b and the fifth portion 16by.

[0182] The sixth portion 16bz, which is the topmost portion of the second storage node electrode 16b, is in contact with, for example, the second oxide semiconductor layer 22b.

[0183] The first width (W4 in FIG. 22) of the fourth portion 16bx in the second direction is smaller than the fifth width (W5 in FIG. 22) of the fifth portion 16by in the second direction. Also, the sixth width (W6 in FIG. 22) of the sixth portion 16bz in the second direction is smaller than the fifth width W5.

[0184] The fourth portion 16bx is located, for example, across the second metal regions 16b1 on both sides of the plate electrode 14. The fifth portion 16by is located, for example, in the second oxide conductor region 16b2. The sixth portion 16bz is located, for example, in the second oxide conductor region 16b2.

[0185] Next, an example of a method for manufacturing the semiconductor memory device according to the second embodiment will be described.

[0186] 23, 24, 25, 26, 27, 28, and 29 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor memory device of the second embodiment. Each of Figures 23 to 29 shows a cross section corresponding to Figure 20. Figures 23 to 29 are views showing an example of a method for manufacturing the semiconductor memory 200.

[0187] The following description will be given taking as an example a case where the substrate insulating layer 12 is silicon oxide, the plate electrode 14 is titanium nitride, the metal region of the storage node electrode 16 is titanium nitride, the oxide conductor region of the storage node electrode 16 is indium tin oxide, the capacitor insulating film 18 is zirconium oxide, the source / drain electrodes 20 are indium tin oxide, the oxide semiconductor layer 22 is indium gallium zinc oxide, the gate electrode 24 is tungsten, the gate insulating film 26 is silicon nitride, and the interlayer insulating layer 30 is silicon oxide.

[0188] First, a first silicon oxide film 51, a first titanium nitride film 52, and a second silicon oxide film 53 are formed on a substrate 10. The first silicon oxide film 51, the first titanium nitride film 52, and the second silicon oxide film 53 are formed by, for example, a CVD method.

[0189] The first silicon oxide film 51 will eventually become the substrate insulating layer 12. The first titanium nitride film 52 will eventually become part of the plate electrode 14. The second silicon oxide film 53 will eventually become part of the interlayer insulating layer 30.

[0190] Next, a first opening 55 is formed through the second silicon oxide film 53 to reach the first titanium nitride film 52 (FIG. 23). The first opening 55 is formed by using, for example, lithography and RIE.

[0191] Next, the first opening 55 is filled with a second titanium nitride film 56. The second titanium nitride film 56 is formed by using, for example, a CVD method.

[0192] Next, the second titanium nitride film 56 on the surface of the second silicon oxide film 53 is removed (FIG. 24). The second titanium nitride film 56 is removed by, for example, CMP. The second titanium nitride film 56 will eventually become part of the plate electrode 14.

[0193] Next, the second silicon oxide film 53 is removed (FIG. 25). The second silicon oxide film 53 is removed by, for example, wet etching. A pillar made of the second titanium nitride film 56 is formed.

[0194] Next, a zirconium oxide film 57 and a third titanium nitride film 58 are formed on the pillars formed of the second titanium nitride film 56 (FIG. 26). The zirconium oxide film 57 and the third titanium nitride film 58 are formed by, for example, the ALD method.

[0195] The zirconium oxide film 57 will eventually become the capacitor insulating film 18. The third titanium nitride film 58 will eventually become part of the storage node electrode 16.

[0196] By forming a zirconium oxide film 57 and a third titanium nitride film 58 on the pillars formed of the second titanium nitride film 56, pillars 58x of titanium nitride protruding from the surroundings are formed.

[0197] The pillar 58x has a layered structure of a second titanium nitride film 56, a zirconium oxide film 57, and a third titanium nitride film 58. The top and side surfaces of the pillar 58x are made of titanium nitride.

[0198] Next, an indium tin oxide film 60 is formed on the top surface of the pillar 58x (FIG. 27). The indium tin oxide film 60 is formed under conditions in which the upward growth rate is faster than the lateral growth rate. The indium tin oxide film 60 is also formed under conditions in which the step coverage is poor.

[0199] The width in the second direction of the indium tin oxide film 60 formed on the top surface of the pillar 58x is larger than the width in the second direction of the pillar 58x. Furthermore, the indium tin oxide films 60 formed on the top surfaces of two pillars 58x adjacent to each other in the second direction are formed so as not to be in contact with each other.

[0200] The indium tin oxide film 60 is formed under conditions such that, for example, the

[0111] directions of the multiple crystals contained in the indium tin oxide film 60 are oriented in a direction perpendicular to the top surfaces of the pillars 58x of the third titanium nitride film 58. The indium tin oxide film 60 is formed such that, for example, the

[0111] directions of the multiple crystals contained in the indium tin oxide film 60 are oriented in a first direction. By forming the indium tin oxide film 60 such that the

[0111] directions of the multiple crystals contained in the indium tin oxide film 60 are oriented in the first direction, the upward growth rate of the indium tin oxide film 60 becomes faster than the lateral growth rate.

[0201] The indium tin oxide film 60 is formed, for example, so as to cover a portion of the side surface of the pillar 58x. Because the indium tin oxide film 60 is formed under conditions that result in a fast upward growth rate, contact between the indium tin oxide films 60 on two adjacent pillars 58x is suppressed. Furthermore, because the indium tin oxide film 60 is formed under conditions that result in poor step coverage, it is hardly formed on the top surface of the third titanium nitride film 58 between two adjacent pillars 58x.

[0202] The indium tin oxide film 60 is formed by, for example, a PVD method which has poor step coverage.The indium tin oxide film 60 is formed by, for example, a sputtering method which has poor step coverage.

[0203] Next, the third titanium nitride film 58 between two adjacent pillars 58x is removed using the indium tin oxide film 60 as a mask. The third titanium nitride film 58 is removed by, for example, the RIE method. Before etching by the RIE method, for example, a hard mask may be formed on the indium tin oxide film 60.

[0204] Next, the corners of the upper surface of the indium tin oxide film 60 are removed (FIG. 28). The corners of the upper surface of the indium tin oxide film 60 are formed into a forward tapered shape. Note that the removal of the corners of the upper surface of the indium tin oxide film 60 may be performed before removing the third titanium nitride film 58 between two adjacent pillars 58x.

[0205] For example, the corners of the upper surface of the indium tin oxide film 60 are removed by the RIE method used to remove the third titanium nitride film 58. Furthermore, for example, the corners of the upper surface of the indium tin oxide film 60 are removed by wet etching.

[0206] For example, if an indium tin oxide film 60 is formed on the upper surface of the third titanium nitride film 58 between two pillars 58x by etching to remove the corners of the upper surface of the indium tin oxide film 60, the indium tin oxide film 60 can be removed.

[0207] Next, a third silicon oxide film 61 is formed on the indium tin oxide film 60. The third silicon oxide film 61 is formed by, for example, a CVD method. The corners of the upper surface of the indium tin oxide film 60 have a forward tapered shape, which improves the embedding ability of the third silicon oxide film 61 between two adjacent pillars 58x. The third silicon oxide film 61 will eventually become part of the interlayer insulating layer 30.

[0208] Next, the third silicon oxide film 61 on the indium tin oxide film 60 is removed (FIG. 29). The third silicon oxide film 61 is removed by, for example, CMP.

[0209] Thereafter, a transistor is formed on the indium tin oxide film 60 using the same manufacturing method as for the semiconductor memory 100 of the first embodiment. On the indium tin oxide film 60, a tungsten gate electrode 24, a silicon nitride gate insulating film 26, an indium gallium zinc oxide oxide semiconductor layer 22, an indium tin oxide source / drain electrode 20, and a tungsten bit line 28 are formed.

[0210] By the above manufacturing method, the semiconductor memory 200 shown in FIGS. 20, 21, and 22 is manufactured.

[0211] As described above, according to the second embodiment, similarly to the first embodiment, a semiconductor memory device including an oxide semiconductor transistor and having low connection resistance between the oxide semiconductor layer of the oxide semiconductor transistor and the storage node electrode can be realized.

[0212] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0213] 10 Substrate 14 Plate electrode (first electrode) 16a First storage node electrode (second electrode) 16a1 First metal region (first region) 16a2 First oxide conductor region (second region) 16ax Part 1 16ay 2nd part 16az Third Part 16b Second storage node electrode (fourth electrode) 16bx 4th part 16by 5th part 16bz Part 6 18a first capacitor insulating film 18b Second capacitor insulating film 20a First source / drain electrode (third electrode) 20b Second source / drain electrode (fifth electrode) 22a First oxide semiconductor layer 22b Second oxide semiconductor layer 24a first gate electrode 24b Second gate electrode 26a First gate insulating film 26b Second gate insulating film 27a First upper insulating layer (first insulating layer) 100 Semiconductor memory (semiconductor storage device) 101 Semiconductor memory (semiconductor storage device) 102 Semiconductor memory (semiconductor storage device) 200 Semiconductor memory (semiconductor storage device) CA1 First Capacitor CA2 First Capacitor TR1 First transistor TR2 Second transistor W1 First width W2 Second width W3 Third width W4 Fourth width W5 Fifth width W6 6th width d Shortest distance

Claims

1. a first capacitor including a first electrode, a second electrode, and a first capacitor insulating film provided between the first electrode and the second electrode; a first transistor including: a first oxide semiconductor layer electrically connected to the second electrode and extending in a first direction; a first gate electrode surrounding the first oxide semiconductor layer; a first gate insulating film provided between the first gate electrode and the first oxide semiconductor layer; and a third electrode electrically connected to the first oxide semiconductor layer and having the first oxide semiconductor layer provided between the first gate electrode and the second electrode; the second electrode includes a first portion, a second portion provided between the first portion and the first oxide semiconductor layer, and a third portion provided between the second portion and the first oxide semiconductor layer; a first width of the first portion in a second direction perpendicular to the first direction is smaller than a second width of the second portion in the second direction; A third width of the third portion in the second direction is smaller than the second width.

2. The semiconductor memory device according to claim 1 , wherein said third portion is in contact with said first oxide semiconductor layer.

3. Further comprising a substrate; 2. The semiconductor memory device according to claim 1, wherein the first capacitor is provided between the substrate and the first transistor.

4. 2. The semiconductor memory device according to claim 1, wherein said first width is 0.5 to 0.9 times said second width, and said third width is 0.7 to 0.95 times said second width.

5. 2. The semiconductor memory device according to claim 1, wherein said third width is greater than said first width.

6. 2. The semiconductor memory device according to claim 1, wherein the second electrode includes: a first region containing a metal or a metal compound; and a second region provided between the first region and the first oxide semiconductor layer, in contact with the first region and the first oxide semiconductor layer, and containing an oxide conductor.

7. 7. The semiconductor memory device according to claim 6, wherein said second region surrounds at least a part of said first region in a cross section perpendicular to said first direction.

8. 7. The semiconductor memory device according to claim 6, wherein the second region contains at least one metal element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O).

9. 7. The semiconductor memory device according to claim 6, wherein said second region is polycrystalline, and the [111] direction of a plurality of crystals contained in said second region is oriented in said first direction.

10. 7. The semiconductor memory device according to claim 6, wherein the first region contains at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), and nitrogen (N).

11. 2. The semiconductor memory device according to claim 1, wherein said first electrode surrounds said second electrode in a cross section perpendicular to said first direction.

12. 2. The semiconductor memory device according to claim 1, wherein said second electrode surrounds said first electrode in a cross section perpendicular to said first direction.

13. a first insulating layer provided between the second electrode and the first gate electrode and in contact with the second electrode; The semiconductor memory device according to claim 1 , wherein said first insulating layer surrounds said first oxide semiconductor layer in a cross section perpendicular to said first direction.

14. 14. The semiconductor memory device according to claim 13, wherein said first insulating layer includes silicon nitride or aluminum oxide.

15. a fourth electrode; and a second capacitor including a second capacitor insulating film provided between the first electrode and the fourth electrode; a second transistor including: a second oxide semiconductor layer electrically connected to the fourth electrode and extending in the first direction; a second gate electrode surrounding the second oxide semiconductor layer; a second gate insulating film provided between the second gate electrode and the second oxide semiconductor layer; and a fifth electrode electrically connected to the second oxide semiconductor layer and having the second oxide semiconductor layer provided between the fifth electrode and the fourth electrode, the fourth electrode includes a fourth portion, a fifth portion provided between the fourth portion and the second oxide semiconductor layer, and a sixth portion provided between the fifth portion and the second oxide semiconductor layer; a fourth width of the fourth portion in the second direction is smaller than a fifth width of the fifth portion in the second direction; 2. The semiconductor memory device according to claim 1, wherein a sixth width in said second direction of said sixth portion is smaller than said fifth width.

16. 16. The semiconductor memory device according to claim 15, wherein a shortest distance between said second electrode and said fourth electrode in said second direction is smaller than said first width and said fourth width.

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