Systems and methods for systems-on-a-wafer

Abstract

A system-on-a-wafer (SoW) includes a first plurality of integrated circuits (ICs) and a second plurality of ICs. The first plurality of ICs is communicatively coupled to the second plurality of ICs and is configured to perform one or more computing tasks. The SoW further includes a control module configured to determine a status of each of the first and second plurality of ICs and determine that a first IC of the first plurality of ICs has failed or is malfunctioning. The control module is configured to select an IC of the second plurality of ICs to replace a functionality of the first IC. An intra-SoW connector can electrically or optically connect chip connectors on the neighboring pair of pieces. A respective inter-SoW connector can be connected to an intra-SoW connector to provide an optical or electrical connection to an inter- SoW connector in another SoW.

Description

SYSTEMS AND METHODS FOR SYSTEMS-ON-A-WAFERCROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the priority benefit of U.S. Application No. 63 / 561,003, filed March 4, 2024; U.S. Application No. 63 / 561 ,495, filed March 5, 2024; U.S. Application No. 63 / 565,794, filed March 15, 2024; and U.S. Application No. 63 / 663,526, filed June 24, 2024; each of which are incorporated herein by reference in their entirety for all purposes.BACKGROUND|0002| Recent advances in artificial intelligence (Al) and other computational techniques have spurred a need for improvements to computational density, computing power, and heat transfer as a means to improve computational system performance. For a given integrated circuit (IC), increasing a computational frequency produces increased computational throughput, but also increases an amount of heat generated as a byproduct of the increased computational throughput.

[0003] ICs (or semiconductor dies) may be manufactured on silicon wafers, with each silicon wafer containing dozens or hundreds of ICs. These ICs may then be separated, e.g., using a die saw, and further integrated into a server or other computing system. However, advances in manufacturing technology have led to the creation of systems-on-a-wafer (SoWs), in which a fully integrated computational system is manufactured using a wafer as a base. These SoWs are not segmented after manufacturing; rather, each SoW may contain a plurality of ICs, interconnections between ICs such as traces, leads, pads, etc., and other components for networking, power distribution, and other functionalities.|0004| A data center may include multiple networked computing systems to process, store, and distribute large amounts of data. Conventional data centers typically include aggregated computational resources, such as rack servers with central processing units (CPUs) and memory mounted to a single printed circuit board (PCB). For these data centers, the CPUs are configured to perform a wide array of workloads, such as managing databases and providing applications and services to a large user base. However, some workloads, particularly workloads involving high performance computing, artificial intelligence (Al), and data analytics, have grown in size to such an extent that CPUs alone are no longer suitable to facilitate execution of these workloads without incurring significant time and costs for computation. For example, large language models have recently doubled in size every few months.

[0005] Accordingly, data centers configured to execute these workloads have undergone significant changes in recent years to accommodate the rapid growth of these workloads. One recent advancement is the system -on-a- wafer (SoW) in which central processing units (CPUs), graphics processing units (GPUs), and / or other semiconductor chips are mounted on a common semiconductor wafer. The integration of semiconductor chips on a common semiconductor wafer reduces latency compared to conventional servers. SoWs are a recent technological advancement and lack supporting structures and apparatus.SUMMARY

[0006] To address the lack of supporting structures and apparatus for systems-on-a-wafer (SoWs), a mechanical support apparatus is provided. The mechanical support apparatus includes first and second frames that are configured to support and engage a SoW, a power distribution board, and respective thermal exchange modules.

[0007] Computing performance of SoWs and systems-on-a-panel (SoPs) depends on the proper functioning of dozens or hundreds of ICs. As a result, manufacturing yield performance plays a critical role; if one connection or IC fails, an entire SoW / SoP may not function properly. Incorporating reconfigurable and repairable arrangements of ICs within an SoW / SoP can ensure proper system performance and reliability.

[0008] The present technology is directed toward several methods and systems for implementing reconfiguration and repair functionality in an SoW / SoP. A first approach involves integrating more ICs than an original functional requirement, thus providing spare ICs that can replace failed ones. Additionally or alternatively, a separate socket or module dedicated to reconfiguration and repair purposes may be provided.

[0009] In addition to redundancy design for ICs, sockets, and modules, bypass functions may be included in the SoW / SoP design and firmware capabilities to supplement repair and reconfiguration functionality. Beyond addressing IC failure issues, reconfigurable ICs, sockets, and modules can also be utilized for performance or functionality enhancement. For instance, switch ICs can be placed in reconfigurable sockets or modules, enabling functionality changes by activating the switch module.

[0010] To provide improved computational density while addressing reliability issues, one or more SoWs / SoPs are provided. An SoW may include a semiconductor wafer on which an array of chips is mounted. The chips include logic processing chips or ICs such as GPUs and / or CPUs. The chips can also include memory, input / output (I / O) chips, network interface controllers (NICs), and / or switches. The SoW can also include one or more power modules and / or one or more chip connectors.|00111 Further, to address the issues with the high replacement cost and high maintenance complexity of current SoWs, a multi-piece SoW is provided. Each piece of the multi -piece SoW is physically divided and physically separated from the other pieces. Neighboring pieces are mechanically attached and electrically or optically coupled through a respective intra-SoW connector. An inter-SoW connector can be electrically or optically to the intra-SoW connector to provide electrical or optical connection terminals that can be connected to an electrical or optical cable, which can be connected to an inter-SoW connector on another SoW.

[0012] By physically separating the SoW into pieces, the replacement cost and maintenance complexity of the SoW is reduced. An individual piece (or pieces) of the SoW can be removed and replaced when one or more components of the piece catastrophically fail.

[0013] In some aspects, the techniques described herein relate to a system-on-a-wafer (SoW) including: a semiconductor wafer physically divided into a plurality of pieces; a plurality of chips mounted on each piece of the plurality of pieces; a plurality of chip connectors, wherein each chip connector is mounted on a respective piece; a plurality of piece wiring layers, wherein each piece wiring layer electrically couples the plurality of chips on the respective piece to a respective chip connector on the respective piece; and at least one intra-SoW electrical connector; wherein the at least one intra-SoW electrical connector is attached to a neighboring pair of pieces and electrically connects the chip connectors on the neighboring pair of pieces.

[0014] In some aspects, the techniques described herein relate to a system-on-a-wafer (SoW) including: a semiconductor wafer physically divided into a plurality of pieces; a plurality of chips mounted on each piece; a plurality of electrical switch over optics (ESOO) devices, wherein each ESOO device is mounted on a respective piece and includes an electrical switch electrically connected to an optical engine; a plurality of piece wiring layers, wherein each piece wiring layer electrically couples the plurality of chips on the respective piece to a respective electrical switch in a respective ESOO device on the respective piece; and at least one intra-SoW optical connector, wherein each intra-SoW optical connector is attached to a neighboring pair of pieces and optically connects respective optical engines in the ESOO devices on the neighboring pair of pieces.

[0015] In some aspects, the techniques described herein relate to a server including: a first system- on-a-wafer (SoW) including: a first semiconductor wafer physically divided into a plurality of first pieces; a plurality of first chips mounted on each first piece; a plurality of first chip connectors, wherein each first chip connector is mounted on a respective first piece; a plurality of first piece wiring layers, wherein each first piece wiring layer electrically couples the plurality of first chips on the respective first piece to a respective first chip connector on the respective first piece; at least one first intra-SoW electrical connector, wherein each first intra-SoW electrical connector is attached to a neighboring pair of first pieces and electrically connects the first chip connectors on the neighboring pair of first pieces; and at least one first inter-SoW electrical connector, wherein each first inter-SoW electrical connector is disposed on and electrically connected to a respective first intra-SoW electrical connector; a second SoW including: a second semiconductor wafer physically divided into a plurality of second pieces; a plurality of second chips mounted on each second piece; a plurality of second chip connectors, wherein each second chip connector is mounted on a respective second piece; a plurality of second piece wiring layers, wherein each second piece wiring layer electrically couples the plurality of second chips on the respective second piece to a respective second chip connector on the respective second piece; at least one second intra-SoW electrical connector, wherein each second intra-SoW electrical connector is attached to a neighboring pair of second pieces and electrically connects the second chip connectors on the neighboring pair of second pieces; and at least one second inter-SoW electrical connector, wherein each second inter-SoW electrical connector is disposed on and electrically connected to a respective second intra-SoW electrical connector; and at least one electrical cable, wherein the at least one electrical cable electrically connects a respective first inter-SoW electrical connector and a respective second inter-SoW electrical connector.

[0016] In some aspects, the techniques described herein relate to a server including: a first system- on-a-wafer (SoW) including: a first semiconductor wafer physically divided into a plurality of first pieces; a plurality of first chips mounted on each first piece; a plurality of first electrical switch over optics (ESOO) devices, wherein each first ESOO device is mounted on a respective first piece and includes a first electrical switch electrically connected to a first optical engine; a plurality of first piece wiring layers, wherein each first piece wiring layer electrically couples the plurality of first chips on the respective first piece to a respective first electrical switch in a respective first ESOO device on the respective first piece; at least one first intra-SoW optical connector, wherein the at least one first intra-SoW optical connector is attached to a neighboring pair of first pieces and optically connects respective first optical engines in the first ESOO devices on the neighboring pair of first pieces; and at least one first inter-SoW optical connector, wherein each first inter-SoW optical connector is disposed on and optically connected to a respective first intra-SoW optical connector; a second SoW including: a second semiconductor wafer physically divided into a plurality of second pieces; a plurality of second chips mounted on each second piece; a plurality of second ESOO devices, wherein each second ESOO device is mounted on a respective second piece and includes a second electrical switch electrically connected to a second optical engine; a plurality of second piece wiring layers, wherein each second piece wiring layer electrically couples the plurality of second chips on the respective second piece to a respective second electrical switch in a respective second ESOO device on the respective second piece; at least one second intra-SoW optical connector, wherein the at least one second intra-SoW optical connector is attached to a neighboring pair of second pieces and optically connects respective second optical engines in the second ESOO devices on the neighboring pair of second pieces; and at least one second inter-SoW optical connector, where the at least one second inter-SoW optical connector disposed on and optically connected to a respective second intra-SoW optical connector; and at least one optical cable, wherein the at least one optical cable optically connects a respective first inter-SoW optical connector and a respective second inter-SoW optical connector of the second SoW.

[0017] In some aspects, the techniques described herein relate to a method for dynamically configuring a computing system, the method including: operating a first plurality of integrated circuits (ICs) to perform at least a first computing task; determining that a first IC of the first plurality is not functioning properly; selecting a second IC from a second plurality of ICs; and operating the second IC to perform at least a second computing task that would have been assigned to the first IC if the first IC had been functioning properly; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; and the first plurality is distinct from the second plurality.

[0018] In some aspects, the techniques described herein relate to a method for dynamically configuring a computing system, the method including: configuring a first plurality of integrated circuits (ICs) to perform one or more computing tasks; determining that a first IC of the first plurality is not functioning properly; selecting a second IC from a second plurality of ICs; and performing the one or more computing tasks with the second IC and a subgroup of the first plurality; wherein: the first plurality and the second plurality are mounted on a semiconductorwafer; the first plurality is distinct from the second plurality; and the subgroup includes all ICs of the first plurality except for the first IC.

[0019] In some aspects, the techniques described herein relate to a method for dynamically configuring a computing system, the method including: configuring a first plurality of integrated circuits (ICs) to perform one or more computing tasks, the first plurality including a first IC; selecting a second IC from a second plurality of ICs; and performing the one or more computing tasks with the second IC and a subgroup of the first plurality; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; the first plurality is distinct from the second plurality; and the subgroup includes each IC of the first plurality except for the first IC.

[0020] In some aspects, the techniques described herein relate to a system for dynamically configurable computation, the system including: a semiconductor wafer; a first plurality of integrated circuits (ICs) mounted on the semiconductor wafer; a second plurality of ICs mounted on the semiconductor wafer; and a control module mounted on the semiconductor wafer; wherein: the control module is communicatively coupled with the first plurality and the second plurality; the control module is configured to assign one or more computing tasks to the first plurality and the second plurality; and the control module is configured to select a second IC of the second plurality to replace an operation of a first IC of the first plurality.

[0021] In some aspects, the techniques described herein relate to a mechanical support including: a first frame having a first body that defines a first open center, wherein: the first open center is configured to receive a system-on-a-wafer (SoW) and at least one first thermal exchange module in direct physical contact with the SoW; and the first body defines a plurality of first holes extending through first opposing sides of the first frame; a second frame having a second body that defines a second open center, wherein: the second open center is aligned with respect to the first open center; the second open center is configured to receive a power distribution board and at least one second thermal exchange module in direct physical contact with the power distribution board; the second body defines a plurality of second holes extending through second opposing sides of the second frame; and each second hole is aligned with a respective first hole; and a plurality of bolts, wherein: each bolt extends through the respective first hole and a respective second hole; and the plurality of bolts align the first frame with respect to the second frame.

[0022] In some aspects, the techniques described herein relate to an assembly including: a mechanical support including: a first frame having a first body that defines a first open center, wherein the first body defines a plurality of first holes extending through first opposing sides of the first frame; a second frame having a second body that defines a second open center, wherein: the second open center is aligned with respect to the first open center; the second body defines a plurality of second holes extending through second opposing sides of the second frame; and each second hole is aligned with a respective first hole; a plurality of bolts, wherein: each bolt extends through a respective first hole and a respective second hole; and the plurality of bolts align the first frame with respect to the second frame; a system-on-a-chip (SoW) disposed in the first open center; at least one first thermal exchange module disposed in the first open center, wherein the at least one first thermal exchange module is in direct physical contact with the SoW; a power distributionboard disposed in the second open center; and at least one second thermal exchange module disposed in the second open center, wherein the at least one second thermal exchange module is disposed in direct physical contact with the power distribution board.

[0023] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein. The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0025] FIG. 1 shows a block diagram of a system-on-a-wafer (SoW) according to an embodiment.

[0026] FIG. 2 shows a cross section of the SoW illustrated in FIG. 1 according to an embodiment.|0027| FIG. 3 shows a cross section of the SoW illustrated in FIG. 1 according to another embodiment.

[0028] FIG. 4 shows an example SoW in which the semiconductor wafer is physically divided and physically separated into four pieces.

[0029] FIG. 5 shows an alternative embodiment of the SoW illustrated in FIG. 4

[0030] FIG. 6 shows an isometric and partially exploded view of an assembly according to an embodiment.|00311 FIG. 7 shows an example physically divided SoW according to another embodiment.

[0032] FIG. 8 shows an example physically divided SoW according to another embodiment.

[0033] FIG. 9 shows an example physically divided SoW according to another embodiment.|0034| FIG. 10 shows a server that includes two SoWs that are electrically connected according to an embodiment.

[0035] FIG. 11 shows a server that includes two SoWs that are optically connected according to an embodiment.

[0036] FIG. 12 illustrates a comparison between a circular wafer and a square panel wafer.

[0037] FIG. 13 illustrates a comparison of IC density between a circular SoW and a square panel SoW.

[0038] FIG. 14 illustrates a graph of IC density vs. IC separation.

[0039] FIG. 15A illustrates an SoW in accordance with the present technology.

[0040] FIG. 15B illustrates an SoW in accordance with the present technology.

[0041] FIG. 15C illustrates an SoW in accordance with the present technology.

[0042] FIG. 15D illustrates an SoW in accordance with the present technology.

[0043] FIGS. 16A and 16B show an example cross section of a mechanical support for a system- on-a- wafer (SoW) according to an embodiment.

[0044] FIG. 17 shows an isometric view of the upper frame of the mechanical support illustrated in FIG. I to further illustrate the boiler plate and the boiling enhancement coating (BEC), according to an embodiment.

[0045] FIG. 18 shows an isometric view of an SoW according to an embodiment.

[0046] FIG. 19 shows an isometric exploded view of the power distribution board, the boiler plate, and the BEC that are included in the lower frame of the mechanical support illustrated in FIG. 1, according to an embodiment.

[0047] FIG. 20 shows an isometric transparent view of the lower frame of the mechanical support illustrated in FIG. 16A, according to an embodiment.

[0048] FIG. 21 A illustrates an exploded view of a mechanical support assembly for a SoW in accordance with the present technology.

[0049] FIG. 2 IB illustrates an isometric view of an assembly in accordance with the present technology.

[0050] FIG. 21C shows a top and two side profile views of an assembly in accordance with the present technology.

[0051] FIG. 2 ID illustrates a bottom view of an assembly in accordance with the present technology, which primarily shows the bottom of bracket.|0052| FIG. 22 shows top and side views of a BEC top frame.

[0053] FIG. 23 illustrates top and side views of a BEC block.

[0054] FIG. 24 illustrates top and side views of a TIM.

[0055] FIG. 25 illustrates top and side views of an SoW.

[0056] FIG. 26 illustrates top and side views of an IO PCB and a VRM PCB mechanically and communicatively coupled to an SoW.

[0057] FIG. 27 illustrates top and side views of an IO frame.

[0058] FIG. 28 illustrates a PDB PCB in accordance with the present technology.

[0059] FIG. 29 illustrates front and side views of a bracket.

[0060] FIG. 30 illustrates a manufacturing order for joining the constituent components of assembly to form assembly.

[0061] FIG. 31A and FIG. 3 IB illustrate top and side views, respectively, of a jig for assembling an assembly in accordance with the present technology.

[0062] FIG. 32A and FIG. 32B illustrate top and side views, respectively, of a jig for assembling an assembly in accordance with the present technology.

[0063] FIG. 33 A illustrates three cables interfacing with three receptacles 3312a-c.

[0064] FIG. 33B illustrates a closeup of a receptacle, wires, a cable, and a self-aligning snap-in connector.

[0065] FIG. 34 illustrates an example wiring diagram utilizing a cable and receptacle analogous to that depicted in FIGS. 33A and 33B.

[0066] FIG. 35 illustrates modules having both SDRAM and VRMs.|0067| FIG. 36 illustrates a top view of an SDRAM module.

[0068] FIG. 37 illustrates two additional combined SDRAM and VRM modules.

[0069] FIG. 38 illustrates a top view of an SDRAM / VRM module.

[0070] FIG. 39 illustrates an assembly that includes a plurality of elastomer sockets providing a mechanical and communicative coupling for VRM modules and PCIe connectors to substrate.

[0071] FIG. 40A and FIG. 40B illustrate top and side views of an example block diagram of a VRM module attached to an elastomer, which in turn is disposed on a substrate.

[0072] FIG. 41A and FIG. 41B illustrate side and front views of a clamp assembly for securing a cable and connector to a substrate using a clamp.

[0073] FIG. 42A illustrates a block diagram of a system having a VRM electrically coupled to a plurality of logic ICs.

[0074] FIG. 42B illustrates the use of a pogo connector to communicatively couple a VRM with a PDB.

[0075] FIG. 43 A and FIG. 43B illustrate side and top views, respectively, of a pogo connector.

[0076] FIG. 44A and FIG. 44B illustrate side and top views, respectively, of a block diagram of a VRM assembly with boiling plate and TIM for improved heat extraction.

[0077] FIG. 45 depicts aspects of an immersion cooling system for dissipating heat from one or more heat-generating components such as semiconductor die packages via immersion cooling.DETAILED DESCRIPTION

[0078] Following below are more detailed descriptions of various concepts related to, and implementations of, a system-on-a- wafer (SoW), servers including SoWs, and mechanical structures for SoW s. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enablethose skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.

[0079] The figures and example implementations described below are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of such known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.An Example SoW|0080| FIG. 1 shows a block diagram of an SoW 100 according to an embodiment. The SoW 100 includes a semiconductor wafer 101, a plurality of chips 110, one or more voltage regulation modules (VRMs) 120, and one or more chip connectors 130.

[0081] The semiconductor wafer 101 comprises a semiconducting material such as silicon, gallium arsenide, sapphire, silicon carbine, indium phosphide, gallium nitride, germanium, and / or another semiconducting material.

[0082] The chips 110 are mounted on or above the semiconductor wafer 101. The chips 110 (equivalently, logic ICs) can be multi-functional and can include logic chips, switches, memory modules (e g., high-bandwidth memory (HBM)), network interface controllers (NICs), input / output (I / O) controllers, and / or other chips. Examples of logic chips include such as graphics processing units (GPUs), central processing units (CPUs), data processing units (DPUs), tensor processing units (TPUs), systems on a chip (SoCs), and the like. Examples of a switch chip are disclosed in Provisional Application No. 63 / 123,476, filed on October 31, 2023, Provisional Application No. 63 / 614,508, filed on December 22, 2023, and U.S. Provisional Patent Application 63 / 556,768, filed February 22, 2024, the entirety of which are hereby incorporated by reference.

[0083] A memory module may be an IC configured to store data and may include a dynamic random access memory (DRAM) module, a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a non-volatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable ROM (OTPROM), or the like), or any suitable type of memory module.|0084| The chips 110 can be selected in any combination to provide an overall function or architecture for the SoW 100. For example, the chips 110 can be selected such that the SoW 100 can function as server or a portion of a server. Examples of servers that the SoW 100 can function as can include an artificial intelligence (Al) training server, an Al inference server, a web server, a database server, an email server, a web proxy server, a domain name server (DNS), an application server, and / or another server.

[0085] The chips 110 are electrically coupled to one or more modules or structures that are mounted on or above the semiconductor wafer 101 and that are electrically coupled to the chips I 10. The modules / structures can include a VRM 120 and / or a chip connector 130. The VRM 120 can include a voltage converter that can modulate an external supply voltage to a chip supply voltage that is at an appropriate level to power some or all of the chips 110. There can be multiple VRM 120. In an example, there can be one VRM 120 for (e.g., electrically connected to) each semiconductor chip 110. In another example, two or more semiconductor chips can be electrically connected to (e.g., can share) a VRM 120.

[0086] The chip connector 130 provides an electrical connection point to an external electrical component and / or to another SoW. One or more of the modules can be located directly above one or more of the chips 110 but are not illustrated in FIG. 1 for illustration purposes only so as to not obscure the chips 1 10. In some embodiments, the chip connector 130 can be or can include an electrical switch over optics (ESOO) device, for example as disclosed in Provisional Application No. 63 / 614,508, titled “Integrated Switch Optical Engine Platform Including Electrical Switch Over Optics Device,” filed on December 22, 2023 and U.S. Provisional Patent Application 63 / 556,768, filed February 22, 2024 and entitled “INTEGRATED SWITCH OPTICAL ENGINE PLATFORM INCLUDING ELECTRICAL SWITCH OVER OPTICS DEVICE INTEGRATED WITH SY STEM-ON- A- WAFER,” the entirety of which are hereby incorporated by reference.

[0087] FIG. 2 shows a cross section of SoW 100 through plane 20 in FIG 1 according to an embodiment. In this embodiment, a redistribution layer 200 may be located between the chips 110 and the modules mounted on or above the semiconductor wafer 101 , such as the VRM 120 and the chip connector 130. The redistribution layer 200 includes electrical wiring 210 that electrically connects each chip 110 to the VRM 120, to the chip connector 130, and / or to another module mounted on or above the semiconductor wafer 101. The electrical wiring 210 can include one or more levels including a multilevel wiring structure. The electrical wiring 210 can include or define an Integrated Fan-Out (InFO) packaging connection. The redistribution layer 200 includes an electrical insulator 220, such as silicon dioxide, that electrically isolates the wires and levels of the electrical wiring 210. The redistribution layer 200 can alternately be referred to as a wiring layer.

[0088] The structure illustrated in FIG. 2 can be manufactured by mounting the chips 110 on (e.g., directly or indirectly) the semiconductor wafer 101. Next, an epoxy and / or reflow material 230 may be formed on and / or between the chips 110. The epoxy / reflow material 230 can be planarized. The redistribution layer 200 may be formed on the epoxy / reflow material 230 and / or on the chips 110. The electrical wiring 210 can be formed by photolithography and etching of the electrical insulator 220 to form patterns and metal deposition into the patterns. The VRM 120, the chip connector 130, and / or other modules are mounted on redistribution layer 200 and electrically coupled to the appropriate leads or terminals of the electrical wiring 210. This manufacturing process can be referred to as chip-first manufacturing process.

[0089] FIG. 3 shows a cross section of SoW 100 through plane 20 in FIG 1 according to another embodiment. In this embodiment, first and second redistribution layers 301 , 302 are located between the chips 110 and the modules mounted on or above the semiconductor wafer 101, suchas the VRM 120 and the chip connector 130. A plurality of local silicon interconnects (LSIs) 310 are located between the first and second redistribution layers 301, 302. The LSIs 310 are electrically coupled to the chips 1 10 through first electrical wiring 31 I in the first redistribution layer 301. The LSIs 310 are electrically coupled to the VRM 120, to the chip connector 130, and / or to another module mounted on or above the semiconductor wafer 101 through second electrical wiring 312 in the second redistribution layer 302. Thus, the chips 110 are electrically coupled to the to the VRM 120, to the chip connector 130, and / or to another module mounted on or above the semiconductor wafer 101 through the first electrical wiring 311, the second electrical wiring 312, and the LSIs 310. The first and second redistribution layers 301, 302 also include a respective electrical insulator 321, 322 that can be the same as electrical insulator 220. The first and second redistribution layers 301, 302 can be formed in the same or similar manner as the redistribution layer 200. As in the embodiment of FIG. 2, an epoxy / reflow material 230 is formed on and / or between the chips 110.

[0090] The embodiment illustrated in FIG. 3 can be formed in a chip-last manufacturing process. The chip-last manufacturing process can also be referred as a chip-on-wafer (CoW) manufacturing process.Example Multi-Piece SoWs

[0091] FIG. 4 shows an example SoW 400 in which the semiconductor wafer 101 is physically divided and physically separated into four pieces 401a-d (in general, piece 401). Each piece 401 is equal in size (e.g., in surface area) and represents a quarter or quadrant of the semiconductor wafer 101 and of the SoW 400. The semiconductor wafer 101 is typically circular. In one example, each piece 401 can be a sector of the semiconductor wafer 101. Alternatively, each piece 401 can be a chord or another piece. In some embodiments, the pieces 401 can represent a combination of sector(s), chord(s), and / or other pieces of the semiconductor wafer 101. There can be fewer pieces 401 (e.g., two or three) or additional pieces 401 (5 or more) in other embodiments. The pieces 401 can be formed by laser cutting or another technique.

[0092] The semiconductor chips 110 on each piece 401 can be the same or different than the semiconductor chips 110 on one or more other pieces 401. In one example, the configuration, arrangement, and / or functionality of the semiconductor chips 1 10 on each piece 401 is the same. In another example, the configuration, arrangement, and / or functionality of the semiconductor chips 110 on each piece 401 is different. In one embodiment, a first piece 401a includes GPUs and memory modules as the semiconductor chips 110, for example to provide Al training / processing functionality; a second piece 401b includes CPUs and memory modules as the semiconductor chips 1 10, for example to provide CPU functionality; a third piece 401c includes switches as the semiconductor chips 110, for example to provide switching functionality; and a fourth piece 40 Id includes memory modules as the semiconductor chips 110, for example to provide memory functionality.

[0093] In each piece 401, the semiconductor chips 1 10 are electrically connected to an intra-SoW electrical connector 410a-d (in general, intra-SoW electrical connector 410) through one or more layers of electrical wiring 210 (e.g., one or more piece electrical wiring layers). Each piece 401 iselectrically coupled to neighboring pieces 401 using a respective chip connector 130 and a respective intra-SoW electrical connector 410. The intra-SoW electrical connector 410 includes a substrate 412, such as an organic substrate, and a plurality of electrical wires 414. The intra-SoW electrical connector 410 can comprise a segment of a printed circuit board (PCB) in which the wires 414 are disposed on the PCB substrate. The electrical wires 414 are electrically connected to a respective chip connector 130 on each neighboring piece 401. Each piece 401 can include two chip connectors 130 including a first chip connector 130 electrically connected to a first intra-SoW electrical connector 410 to provide an electrical connection to a first neighboring piece 401 and a second chip connector 130 electrically connected to a second intra-SoW electrical connector 410 to provide an electrical connection to a second neighboring piece 401. Each intra-SoW electrical connector 410 may communicatively and / or mechanically couple a respective first piece to a respective second piece, the first piece and the second piece neighboring one another. Each piece in Fig. 4 is depicted as having two chip connectors. Each intra-SoW electrical connector connects at least one chip connector on one piece to at least one chip connector on a neighboring piece.

[0094] For example, neighboring pieces 401a, 401b are electrically connected using an intra-SoW electrical connector 410a and respective chip connectors 130. Neighboring pieces 401b, 401d are electrically connected using an intra-SoW electrical connector 410b and respective chip connectors 130. Neighboring pieces 401c, 401d are electrically connected using an intra-SoW electrical connector 410c and respective chip connectors 130. Neighboring pieces 401a, 401c are electrically connected using an intra-SoW electrical connector 410d and respective chip connectors 130. A first piece may be neighboring a second piece if a portion of the second piece is the closest piece to a portion of the first piece.

[0095] The intra-SoW connectors 410 can be physically attached to one another, for example in the shape of a cross or in another shape. In other embodiments, at least two of the intra-SoW connectors 410 are physically attached to one another. In other embodiments, none of the intra- SoW connectors 410 are physically attached to one another.|0096| In some embodiments, an inter-SoW electrical connector 420a-d (in general, inter-SoW electrical connector 420) can be disposed a respective intra-SoW electrical connector 410, as shown in FIG. 5. The inter-SoW electrical connector 420 is electrically connected to the electrical wires 414 on an intra-SoW electrical connector 410 to provide an electrical connection to neighboring pieces 401. The inter-SoW electrical connector 420 can comprise a connection interface that is configured to receive and form a connection with terminals of an electrical cable. The connection interface can be compatible with one or more standards such as the Peripheral Component Interconnect Express (PCIE) standard, the Compute Express Link (CXL) standard, and / or another standard. The inter-SoW electrical connector 420 can be electrically connected to an inter-SoW connector on another SoW or on a piece of another SoW. Additionally or alternatively, the inter-SoW electrical connector 420 can be electrically connected to a device, a server, a chip, a switch, or another component.

[0097] For example, an intra-SoW electrical connector 420a is electrically connected to the electrical wires 414 on the intra-SoW electrical connector 410a to provide an electrical connectionto respective chip connectors 130 and chips 110 on neighboring pieces 401a, 401b. An intra-SoW electrical connector 420b is electrically connected to the electrical wires 414 on the intra-SoW electrical connector 410b to provide an electrical connection to respective chip connectors 130 and chips 110 on neighboring pieces 401b, 40 Id. An intra-SoW electrical connector 420c is electrically connected to the electrical wires 414 on the intra-SoW electrical connector 410c to provide an electrical connection to respective chip connectors 130 and chips 110 on neighboring pieces 401c, 401d. An intra-SoW electrical connector 420d is electrically connected to the electrical wires 414 on the intra-SoW electrical connector 410d to provide an electrical connection to respective chip connectors 130 and chips 110 on neighboring pieces 401a, 401c. In some embodiments, an inter- SoW electrical connector 420 only disposed on one or more some of the intra-SoW connector(s) 410.

[0098] At least some of the intra-SoW connectors 410 can include a respective alignment structure 500 that can be used to align the position of the intra-SoW connectors 410 with respect to other structures, such as other layers, a frame, and / or another structure. The alignment structure 500 can comprise an alignment pin or a hole.

[0099] The intra-SoW connectors 410 can also include one or more passive electrical components 510, such as one or more capacitors, one or more inductors, and / or one or more resistors.

[0100] An advantage of the SoW 400 is that each piece 401 can be individually removed and replaced, if needed, in case of a failure of one or more components of the piece 401 that cannot be repaired with any built-in redundancy. Thus, a portion (e.g., one or more pieces 401) of the SoW400 can be replaced without having to replace the entire SoW 400 due to a failure of only a portion or components of the SoW 400.

[0101] FIG. 6 shows an isometric and partially exploded view of an assembly 600 according to an embodiment. The assembly 600 includes an SoW 400 where each piece 401 is mounted on a frame 601 that mechanically supports the pieces 401. In this embodiment, the alignment structure 500 comprises alignment pins 612 that fit into respective holes 602 in the frame. When the alignment pins 612 are in the holes 602, the intra-SoW connectors 410 are located at predetermined positions on the frame 601, which can include a respective recess to receive each intra-SoW electrical connector 410. In addition, when the alignment pins 612 are in the holes 602, the pieces401 are located at predetermined positions on the frame 601, which include holes 604 to expose the pieces 401.

[0102] Each piece 401 is mounted on the frame 601 such that a first side of piece 401 with the semiconductor chips 1 10 is in or faces the hole 604. The VRMs 120 are mounted on the first side of each piece 401 and can extend, at least partially, into the respective hole 604.

[0103] A respective cooling plate 610 can be placed on a second side 402 of each piece 401. The cooling plates 610 can comprise components of an immersion cooling system, such as the immersion cooling system 4500 illustrated in FIG. 45. For example, the cooling plates 610 can be the same as a heat spreader 4552 (FIG. 45).|00104| The inter-SoW connectors 420 can extend vertically from the plane intra-SoW connectors 410 and the pieces 401. In some embodiments, the inter-SoW connectors 420 include connectionterminals 620 that can be configured to receive and / or engage a standard cable connection such as a PCIE cable.

[0105] FIG. 7 shows an example SoW 700 according to another embodiment. The SoW 700 is the same as the SoW 400 except that in the SoW 700, the semiconductor wafer 101 is physically divided and physically separated into two pieces 701a, 701b. The two pieces 701a, 701b can represent two halves. An intra-SoW electrical connector 410 physically connects the pieces 701a, 701b. The intra-SoW electrical connector 410 provides electrical connection between at least one respective chip connector 130 on each piece 701a, 701b. In some embodiments, the intra-SoW electrical connector 410 can provide electrical connection between two (e.g., a plurality of ) chip connectors 130 on each piece 701a, 701b. Alternatively, there can be two or more intra-SoW connectors 410 between the pieces 701a, 701b.

[0106] FIG. 8 shows an example SoW 800 according to another embodiment. The SoW 800 is the same as the SoW 400 except that in the SoW 800, the semiconductor wafer 101 is physically divided and physically separated into three pieces 801a-c. The three pieces 801a-c can represent the physical division and separation of the semiconductor wafer 101 by two chords 802, 803. In other embodiments, the semiconductor wafer 101 can be physically divided and separated by three or more chords. Each piece 801a-c can have the same size (e g., surface area) or different sizes (e.g., surface areas). In addition, each piece 801a-c can have the same number of semiconductor chips 110 or different number of semiconductor chips 110. The semiconductor chips 110 can have the same function or a different function on each piece 801a-c.

[0107] FIG. 9 shows an example SoW 900 according to another embodiment. The SoW 900 is the same as the SoW 400 except that in the SoW 900, the chip connectors 130 are replaced with ESOO devices 930. Each ESOO device 930 includes an electrical switch and an optical engine to convert between electrical and optical signals. The electrical switch in the ESOO device 930 is electrically connected to each chip 1 10 on a piece 401 . The optical engine in the ESOO device 930 is optically connected to the optical engine in an ESOO device 930 of a neighboring piece 401, for example through optical fibers 914 in an intra-SoW optical connector 910. The optical fibers 914 can also be optically connected to an inter-SoW optical connector 920 that can be optically connected to an inter-SoW optical connector 920 of another piece or of another SoW. The optical fibers 914 can be mounted or disposed in an optical cable, a substrate, or another structure 912.|00108| For example, neighboring pieces 401a, 401b are optically connected using an intra-SoW optical connector 910a and respective ESOO devices 930. Neighboring pieces 401b, 401d are electrically connected using an intra-SoW optical connector 910b and respective ESOO devices 930. Neighboring pieces 401 c, 40 I d are electrically connected using an intra-SoW optical connector 910c and respective ESOO devices 930. Neighboring pieces 401a, 401c are electrically connected using an intra-SoW optical connector 910d and respective ESOO devices 930.Example Servers Including Multi-Piece SoWs

[0109] FIG. 10 shows a server 1000 that includes two SoWs 1001 , 1002 that are electrically connected according to an embodiment. Each SoW 1001, 1002 is the same as SoW 400. In otherembodiments, one or both SoWs 1001, 1002 can be the same as SoW 700, SoW 800, or another SoW.

[0110] The inter-SoW electrical connector 420a on SoW 1001 is electrically connected to the inter-SoW electrical connector 420a on SoW 1002 through an electrical cable 1010a. The inter- SoW electrical connector 420c on SoW 1001 is electrically connected to the inter-SoW electrical connector 420c on SoW 1002 through an electrical cable 1010c.

[0111] Through the inter-SoW connectors 420a, the electrical cable 1010a, the respective intra- SoW connectors 410, and the respective chip connectors 130, the chips 110 on pieces 401a and 401b of SoW 1001 are electrically connected to (e.g., in electrical communication with) the chips 110 on pieces 401a and 401b of SoW 1002. Through the inter-SoW connectors 420c, the electrical cable 1010c, the respective intra- SoW connectors 410, and the respective chip connectors 130, the chips 110 on pieces 401c and 401d of SoW 1001 are electrically connected to (e.g., in electrical communication with) the chips 110 on pieces 401c and 401d of SoW 1002.

[0112] The inter-SoW connector(s) 420b and / or 420d on SoW 1001 can be electrically connected to (e.g., through a respective electrical cable) the inter-SoW connector(s) 420b and / or 420d on SoW 1002. Alternatively, the inter-SoW connector(s) 420b and / or 420d on SoW 1001 and / or the inter-SoW connector(s) 420b and / or 420d on SoW 1002 can be electrically connected to (e.g., through a respective electrical cable) respective inter-SoW connector) s) on other SoW(s).

[0113] FIG. 11 shows a server 1100 that includes two SoWs 1101, 1102 that are optically connected according to an embodiment. Each SoW 1 101 , 1 102 is the same as SoW 900. In other embodiments, one or both SoWs 1101, 1102 can have another configuration.

[0114] The inter-SoW optical connector 920a on SoW 1101 is optically connected to the inter- SoW optical connector 920a on SoW 1102 through an optical cable 1110a. The inter-SoW optical connector 920c on SoW 1101 is optically connected to the inter-SoW optical connector 920c on SoW 1102 through an optical cable 1110c.

[0115] Through the inter-SoW optical connectors 920a, the optical cable 1110a, the respective intra-SoW optical connectors 910, and the respective ESOO devices 930, the chips 110 on pieces 401a and 401b of SoW 1101 are optically and electrically connected to the chips 110 on pieces 401a and 401b of SoW 1102. Through the inter-SoW optical connectors 920c, the optical cable 1110c, the respective intra-SoW optical connectors 910, and the respective ESOO devices 930, the chips 110 on pieces 401c and 401d of SoW 1101 are optically and electrically connected to the chips 110 on pieces 401c and 401d of SoW 1102.

[0116] The inter-SoW optical connector(s) 920b and / or 920d on SoW 1101 can be optically connected to (e.g., through a respective optical cable) the inter-SoW connector(s) 920b and / or 920d on SoW 1102. Alternatively, the inter-SoW optical connector(s) 920b and / or 920d on SoW 1101 and / or the inter-SoW optical connector(s) 920b and / or 920d on SoW 1002 can be optically connected to (e.g., through a respective optical cable) respective inter-SoW optical connector(s) on other SoW(s).Reconfigurable and Repairable Circular and Panel Wafers

[0117] The present technology is additionally directed toward reconfigurable and / or repairable integrated circuit (IC) arrays on systems-on-a-wafer (SoWs) / systems-on-a-panel (SoPs). These IC arrays may include a plurality of ICs (which may be on the order of tens, hundreds, or thousands of ICs) configured to perform computations such as artificial intelligence (Al) training and inference, video processing, computer model processing, mathematical and / or physics simulations, cryptocurrency mining, or any suitable computations. A traditional SoW / SoP may include an array of multiple ICs, for example 60 ICs. Prior to use in a production setting, each SoW / SoP will undergo testing to determine which, if any, of the ICs in an IC array are malfunctioning or inoperable.

[0118] In a conventional SoW / SoP, a number of ICs included in an IC array is traditionally equal to a design specification. If one or more ICs of the IC array are malfunctioning or inoperable, the SoW / SoP may operate with a computing speed / power / frequency below the design specification, which may result in suboptimal performance and render the SoW / SoP unable to perform tasks for which it was designed. Accordingly, the inventors of the present technology have appreciated the need for SoWs / SoPs that include dynamic configurations of IC arrays, and which make use of hardware or software mechanisms for rerouting, remapping, or reassigning certain ICs to fill shortcomings of ICs that are malfunctioning or inoperable.

[0119] FIG. 12 illustrates a comparison between a circular wafer 1210 that may be used as an SoW vs. a panel wafer 1220 that may be used as an SoW (or SoP) in accordance with the present technology. An SoW in accordance with the present technology may be any suitable shape, including circular, ovular, square, rectangular, irregularly shaped, triangular, curved, rounded, or the like. In particular, a panel wafer 1220 may have the benefit of a larger functional area 1222 (e.g., surface area on which computing hardware including integrated circuits, ICs, memory modules, IC connectors, power modules, or other components may be disposed for a given maximum dimension) compared to a functional area 1212 of circular wafer 1210.

[0120] For example, each of circular wafer 1210 and panel wafer 1220 may have maximum principal dimensions (e.g., horizontal and vertical extents) of 300 mm. However, circular wafer 1210 may have a functional area 1212 of 210 mm by 210 mm (i.e., 44,100 mm2) while panel wafer 1220 may have a functional area 1222 of 270 mm by 270 mm (i.e., 72,900 mm2) - an increase of 65% over the functional area 1212 of circular wafer 1210. This larger functional area 1222 may allow for a higher IC density, computing performance, bandwidth, and functionality on a given wafer as well as increasing IC (and associated computational) density in a computing system using panel wafer SoWs instead of circular wafer SoWs.

[0121] Equivalently, for a fixed functional area (e.g., a functional area of about 210 mm by about 210 mm, or about 44,100 mm2), a panel wafer 1220 may have a smaller overall footprint than circular wafer 1210 (e.g., a maximum principal dimension of panel wafer 1220 may be smaller than a maximum principal dimension of circular wafer 1210). For example, as illustrated in FIG. 12, circular wafer 1210 may have a functional area 1212 of about 210 mm by about 210 mm, or about 44, 100 mm2and a maximum dimension of 300 mm. Assuming the same margins between an edge of panel wafer 1220 and the functional area 1222 of 15 mm per side, a panel wafer 1220having the same functional area may require a maximum dimension of only 240 mm. This additional space may be utilized for additional computing components in a server, to reduce an overall footprint of a server, reduce a latency between SoWs in a computing system, or the like.

[0122] Further, semiconductor dies, ICs, and processors are typically square in profile, which means that a greater percentage of the total area of a square panel wafer may be utilized to include ICs than a corresponding circular wafer SoW of the same maximum principal dimensions. For example, FIG. 12 circular wafer 1210 has a diameter of 300 mm and panel wafer 1220 has length and width of 300 mm each. The total area of circular wafer 1210 is 7tx1502 = 70,686 mm2and the total area of panel wafer 1220 is 3002= 90,000 mm2. The functional area 1212 of circular wafer 1210 is 44, 100 mm2and the usable percentage of circular wafer 1210 is 44,100 ' 70,686 = 62.4%, whereas the functional area 1222 of panel wafer 1220 is 72,900 mm2+ 90,000 mm2= 81%. This increase in functional area for an exemplary panel wafer 1220 means better overall system performance, improved computational density, higher computational throughput, greater potential revenues from selling computing power, and various additional improvements.

[0123] FIG. 13 illustrates a comparison of IC density between a circular wafer SoW 1300a vs. a panel wafer SoW 1300b. Each SoW may have the same maximum dimension (e.g., about 300 mm) and same spacing between analogous components (e.g., a same distance between adjacent ICs). Additionally, each SoW may include analogous or substantially identical components (e.g., ICs, memory modules, IC connectors, and IC interconnects). However, in an example, panel wafer SoW 1300b may include 96 ICs 1310b, whereas circular wafer SoW 1300a may only include 60 ICs 1310a, an increase of 60% for panel wafer SoW 1300b. Each additional IC 1310b may increase a computational performance (e.g., computational speed), reliability (by enabling a portion of ICs 1310b to be kept in reserve if one or more other ICs 1310b fail or malfunction), computational flexibility (e.g., allowing additional tasks to be run at a given time by panel wafer SoW 1300b as compared to circular wafer SoW 1300a), or the like.

[0124] Circular wafer SoW 1300a may include a plurality of ICs 1310a (labelled C0-C59) disposed on a semiconductor wafer 1302a. Each IC 1310a may be communicatively coupled to one or more memory modules 1312a. Each IC of ICs 1310a may additionally be communicatively coupled to one or more other ICs of ICs 1310a via one or more IC interconnects 1322a. A plurality of ICs 13 10a may be arranged into one or more groups (e g., pairs of rows such as group C0-C 19). Each group of ICs 1310a may be communicatively coupled to one or more other groups via group interconnects 1320a, which may be particularly configured to transfer data generated by a plurality of ICs with high bandwidth and low latency. For example, group interconnects 1320a may provide the same data transfer speeds and latencies as one or more IC interconnects 1322a, but with a high enough bandwidth to support data transfers from a plurality of ICs at the same time. For instance, group interconnects 1320a may provide enough bandwidth to support data transfers at or about the maximum for two or more, four or more, eight or more, ten or more, 15 or more, 20 or more, 25 or more, 50 or more, 100 or more, or any suitable number of ICs at a time.

[0125] Circular wafer SoW 1300a may additionally include one or more memory modules 13 12a, each of which is communicatively coupled to a respective IC of ICs 1310a. Each of one or morememory modules 1312a may be analogous to other memory modules described herein.

[0126] Circular wafer SoW 1300a may additionally include one or more SoW connectors 1330a, which may provide an electrical connection point to an external electrical component and / or to another SoW. SoW connectors 1330a may provide a low-latency connection having a bandwidth that exceeds that of group interconnects 1320a and / or one or more IC interconnects 1322a by a suitable margin, such as by a factor of about two, a factor of about four, a factor of about eight, a factor of about ten, a factor of about 15, a factor of about 20, a factor of about 25, a factor of about 40, a factor of about 50, a factor of about 75, a factor of about 100, a factor of about 500, or any suitable factor.

[0127] Panel wafer SoW 1300b may include a plurality of components analogous to those described with respect to circular wafer SoW 1300a and disposed on semiconductor wafer 1302b. For example, panel wafer SoW 1300b may include a plurality of ICs 1310b, a plurality of memory modules 1312b, a plurality of group interconnects 1320b, a one or more IC interconnects 1322b, and one or more SoW one or more SoW connectors 1330b. Panel wafer SoW 1300b may include an equal or greater number of analogous components to circular wafer SoW 1300a. For example, each group of ICs of panel wafer SoW 1300b may include 24 ICs as compared to 20 ICs per group of circular wafer SoW 1300a, and panel wafer SoW 1300b may include four groups of 24 ICs as compared to three groups of 20 ICs on circular wafer SoW 1300a. The extra group in panel wafer SoW 1300b may necessitate one or more additional group interconnects 1320a as well as additional memory modules 1312b. One or more SoW connectors 1330b may further have a higher bandwidth than one or more SoW connectors 1330a to account for the larger amount of data being processed by additional ICs C60-C95 of panel wafer SoW 1300b.

[0128] FIG. 14 illustrates a graph 1400 comparing the number of ICs per wafer vs. individual IC area in mm2 for a panel wafer SoW and a circular wafer SoW of the same maximum dimension. Graph 1400 shows for every IC area between 100 mm2 and 800 mm2 (and assuming equal spacing and analogous arrangement of ICs on the respective wafers), a panel wafer SoW can include more ICs than a circular wafer SoW of the same maximum dimension. For example, graph 1400 shows that for a IC area of 200 mm2, an exemplary circular wafer SoW may include 220 ICs, while an exemplary panel wafer SoW may include 364 ICs, a 65% increase for the panel wafer SoW over the circular wafer SoW.|00129| Further implementations of SoWs in accordance with the present technology, including additional examples of wiring layers providing connections between arrays of ICs on an SoW, examples of types of ICs that may be used in accordance with the present technology, local silicon interconnects, integrated fan-out packaging, and other similar details of SoWs may be found in U.S. Provisional Patent Application No. 63 / 611,410, filed December 18, 2023, and U.S. Provisional Patent Application No. 63 / 643,728, filed May 7, 2024, both of which are incorporated herein by reference in their entirety.

[0130] FIG. 15A illustrates an SoW 1500a utilizing all available system ICs 1510 in accordance with the present technology. SoW 1500a may include semiconductor wafer 1502, which may be a square panel wafer. SoW 1500a may further include a plurality of system ICs 1510, which may beidentified as C0-C95 for a total of 96 ICs. Each IC of system ICs 1510 may perform computing tasks assigned to it by a controller such as control module 1540. Control module 1540 may be disposed on semiconductor wafer 1502, or may be disposed remotely to semiconductor wafer 1502 (e.g., be embodied as a central processing unit (CPU) head node of a server on which SoW 1500a is disposed, an immersion cooling system baseboard management controller (BMC), a server BMC, a distributed controller such as a facility control plane, or any suitable controller).

[0131] SoW 1500a may further include one or more wafer connectors 1530, which may be network interface cards (NICs) or other suitable communications interfaces providing a communicative coupling between SoW 1500a and other devices such as another SoW, an immersion cooling system, a distributed control system, a server baseboard management controller (BMC), a facility controller, a remote device (e.g., a remote client device or customer device such as a customer desktop computer, smartphone, etc ), or any suitable device. One or more wafer connectors 1530 may utilize a peripheral component interconnect express (PCIe) communication protocol or any suitable communication protocol. SoW 1500a may be at least partially disposed and operated within an immersion cooling liquid to improve a heat transfer from heat-generating components of SoW 1500a including system ICs 1510. For example, one or more ICs of system ICs 1510 and / or redundant ICs 1514 may be operated at a first power in an immersion cooling liquid. The first power may be a power that would damage the one or more ICs if they were operated in air at the same first power, but would not damage the one or more ICs at least in part due to the higher heat removal capacity of the immersion cooling liquid.

[0132] system ICs 1510 may include any suitable computing hardware configured to perform calculations and / or logic such as central processing units (CPU), graphics processing units (GPU), tensor processing units (TPU), data processing units (DPU), digital signal processors (DSP), artificial intelligence (Al) accelerators, three-dimensional integrated circuit (3DIC) stacks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGA), and / or other densely patterned semiconductor die. Each IC of system ICs 1510 may be configured to perform distributed computing tasks such as Al model training, Al inference, video and / or graphics processing, and the like.

[0133] system ICs 1510 may be physically arranged as groups, e.g., rows or clusters of ICs such as C0-C23, C24-C47, C48-C7 I , and C72-C95. Each group may be communicatively coupled to one or more other groups through group interconnects 1520, which may be configured for higher bandwidth than IC interconnects 1522. For example, group interconnects 1520 may be fiber optic conduits and / or bundles of a plurality of wires, traces, etc., and may be configured to transfer data between a plurality of ICs at the same time.

[0134] Each IC of system ICs 1510 may be disposed at about a first distance from at least one other IC of system ICs 1510. For example, system ICs 1510 may be disposed in a rectilinear array with each IC of system ICs 1510 spaced a predetermined distance apart from adjacent ICs. A predetermined distance may be about 1 mm, about 10 mm, about 15 mm, about 20 mm, about 50 mm, about 100 mm, about 200 mm, about 500 mm, between about 1 mm and about 20 mm, between about 10 mm and about 50 mm, between about 20 mm and about 100 mm, between about50 mm and about 200 mm, between about 100 mm and about 500 mm, or any suitable distance. Any of the above distances may vary by + / - 10% with respect to a stated value.

[0135] Each IC of system ICs 1510 may be connected to one or more additional ICs through one or more IC interconnects 1522. The IC interconnects may be traces, leads, wires, or other suitable communications path from one IC of system ICs 1510 to one or more additional ICs of system ICs 1510. IC interconnects 1522 may provide one or more communications paths for system ICs 1510 to wafer connector 1530, control module 1540, or any other suitable component. IC interconnects 1522 may additionally or alternatively provide power for system ICs 1510. Control module 1540 or another suitable controller may utilize IC interconnects 1522 to configure system ICs 1510, upload firmware, assign computing tasks, control an operation of one, some, or all of system ICs 1510, or otherwise communicate with system ICs 1510.

[0136] In an embodiment, control module 1540 may create one or more subgroups of ICs from system ICs 1510. The one or more subgroups may be assigned similar computing tasks, may be separated based on a type of computing task, may be assigned computing tasks based on an entity to which a task is associated (e.g., assigned a first customer’s computing tasks), or the like. For example, ICs C0-C23 may be assigned computing tasks for a first customer, ICs C24-C47 may be assigned computing tasks for a second customer, etc. Control module 1540 may create subgroups of ICs from system ICs 1510 based on a type of computing task; for example, control module 1540 may create a first subgroup of system ICs 1510 that includes ICs C0-C47 and assign this first subgroup Al training tasks. Control module 1540 may create a second subgroup of system ICs 1510 that includes ICs C48-C95 and assign this second subgroup cryptocurrency hash computation tasks.

[0137] Control module 1540 may create subgroups of any appropriate size and / or composition. For example, control module 1540 may create a first subgroup of six ICs (e.g., C0-C5) and then may add or subtract ICs from the first subgroup based on computational resource utilization, task type, task urgency, task duration, available power, thermal factors (e.g., how much heat is being generated by the ICs of the first subgroup, a temperature of any one or more of the ICs of the first subgroup, a temperature or contamination state of an immersion cooling liquid in which SoW 1500a is disposed, etc.), remuneration received from a customer (e.g., if a customer pays more, control module 1540 may assign additional ICs to complete the customer’s task more quickly), or the like.

[0138] In an embodiment, control module 1540 may create subgroups of ICs that include physically contiguous ICs (e.g., each IC of a subgroup is adjacent (including diagonally or otherwise adjacent) to at least one other IC of the subgroup, for example C0-C1-C2; C95-C94- C82-C81, etc.) or may create subgroups of ICs that include ICs that are physically separated by at least one or more of system ICs 1510 (e.g., a subgroup consisting of ICs CO, Cl 1, C84, and C95). Control module 1540 may include ICs in a subgroup based on a physical location of one or more of the ICs, a communication pathway between one or more of the ICs, a length or location of IC interconnects 1522 connecting the ICs of the subgroup, a signal transfer time between any two or more ICs of the subgroup, a signal loss between any two or more ICs of the subgroup, anoperational parameter of the ICs (e.g., control module 1540 may create a subgroup of ICs that are below a threshold temperature at a given point in time), an operational status of each IC (e.g., functioning properly, failed, malfunctioning, an operational frequency, voltage, current, etc. of each IC, or any suitable parameter corresponding to an operational status), or the like.

[0139] SoW 1500a may include one or more memory modules 1512. A memory module may be an IC configured to store data and may include a dynamic random access memory (DRAM) module, a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a non-volatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable ROM (OTPROM), or the like), or any suitable type of memory module.

[0140] Each memory module may be directly communicatively coupled to a single respective IC, or may be communicatively coupled to a plurality of ICs. For example, a memory module 1512 may be accessible (e.g., communicatively coupled to in such a way as to allow creation, deletion, alteration, substitution, modification, addition, subtraction, copying, reading, and / or writing of data stored thereon) by only one IC of system ICs 1510 (e g., each memory module is uniquely coupled to a respective IC), or may be accessible by a plurality of system ICs 1510. Each IC of system ICs 1510 and redundant ICs 1514 may be communicatively coupled to one or more memory modules 1512. Each memory module of one or more memory modules 1512 may be communicatively coupled to a single IC of system ICs 1510 or redundant ICs 1514.

[0141] Control module 1540 may control one or more operations of SoW 1500a. One or more operations of SoW 1500a that may be managed by a control module 1540 include throttling, rate limiting, or depowering system ICs 1510, controlling a voltage, a current, a resistance, a capacitance, a temperature, a flow rate, a frequency, a power, a storage of energy, an operation of a battery, or any suitable operation. Control module 1540 may further control an operation of any power components, communication components (e g., network interface cards (NICs)), sensors, or other components or hardware disposed on SoW 1500a.

[0142] FIG. 15B illustrates a SoW 1500b analogous to SoW 1500a and which further includes a plurality of reconfigurable and / or repairable ICs embodied as redundant ICs 1514. SoW 1500b may include analogous components to that of SoW 1500a including semiconductor wafer 1502, system ICs 1510, one or more memory modules 1512, group interconnects 1520, IC interconnects 1522, one or more wafer connectors 1530, and control module 1540.

[0143] Control module 1540 may configure or operate a first plurality of system ICs 1510 to perform at least a first computing task, such as an Al training or inference task, a video processing task, a model computation task, a mathematical calculation, a video processing task, or any suitable computing task. For example, control module 1540 may assign an Al training task to ICs C0-C1- C2-C12-C13-C14. Control module 1540 may then determine that a first IC of the first plurality of system ICs 1510 is no longer functioning properly, for example that C2 is no longer functioning properly (e.g., the IC has failed, is above a threshold safe operating temperature, is no longer communicating properly with control module 1540 or one or more system ICs 1510, is damaged,has a bug in firmware or has been tampered with, or is otherwise non-functional. Control module 1540 may subsequently select a second IC from a second plurality of ICs, e.g., from the plurality of ICs consisting of redundant ICs 1514. For example, control module 1540 may select redundant IC C3. Control module 1540 may then operate redundant IC C3 to perform second computing tasks that would have been assigned to C2 if C2 was functioning properly.

[0144] FIG. 15B shows redundant ICs 1514, which are labeled as C3, C8, C27, C32, C51, C56, C75, and C79. Redundant ICs 1514 may be used to replace a functionality of system ICs 1510 that fail or malfunction during or prior to operation and may be distinct from system ICs 1510 (e.g., classified distinctly in software [having different firmware or operating instructions compared to system ICs 1510, having a different classification compared to system ICs 1510, having a different grouping compared to system ICs 1510, etc.], a different type, physical design, or model of IC than system ICs 1510, or other suitable distinction). A redundant IC of redundant ICs 1514 may be selected, e g., by control module 1540, to replace a failed or malfunctioning IC based on a location of the malfunctioning IC. For example, upon determining that IC C54 has failed or is malfunctioning, control module 1540 may select redundant IC C56 to perform one or more functions or computing tasks that would have been assigned to C54 had C54 been functioning properly. Control module 1540 may select redundant IC C56 based on a physical proximity to C54 (e.g., because C56 is the closest redundant IC to C54), based on an amount of time to transfer data to C56 as compared to C54, based on a type or functionality of C56, or any suitable selection criterion.

[0145] Each IC of redundant ICs 1514 may be disposed adjacent to another IC of redundant ICs 1514. Alternatively, each IC of redundant ICs 1514 may be disposed with at least one IC of system ICs 1510 between it and any other IC of redundant ICs 1514. In an embodiment, redundant ICs 1514 may have a regular (i.e., repeated) spacing on SoW 1500b, for example as illustrated in FIG. 15B.

[0146] Each IC of system ICs 1510 and redundant ICs 1514 may be disposed at about a first distance from at least one other IC of system ICs 1510 and / or redundant ICs 1514. For example, system ICs 1510 and redundant ICs 1514 may be disposed in a rectilinear array with each IC of system ICs 1510 and redundant ICs 1514 spaced a predetermined distance apart from adjacent ICs. A predetermined distance may be about 1 mm, about 10 mm, about 15 mm, about 20 mm, about 50 mm, about 100 mm, about 200 mm, about 500 mm, between about 1 mm and about 20 mm, between about 10 mm and about 50 mm, between about 20 mm and about 100 mm, between about 50 mm and about 200 mm, between about 100 mm and about 500 mm, or any suitable distance.

[0147] Control module 1540 may select a redundant IC to replace a failed or malfunctioning IC based on a grouping of system ICs 1510, i.e., selecting a redundant IC to perform computing tasks that may otherwise have been assigned to the failed or malfunctioning IC. For example control module 1540 may create a subgroup of system ICs 1510 to perform one or more computing tasks, such as subgroup C52-C53-C54-C55-C64-C65-C66-C67. Control module 1540 may determine that an IC of the subgroup has failed or is malfunctioning, e g., that C53 has failed. Control module 1540 may select redundant IC C51 due to its proximity to failed IC C53, or may select C56 due toits proximity to a greater number of remaining ICs of the subgroup as compared to C51. A proximity may be assessed based on a length or delay of a computing pathway such as IC interconnects 1522 that couples each IC of the subgroup to a respective redundant TC (e g., control module 1540 may compare an average length of IC interconnects 1522 from redundant IC C51 and redundant IC C56 to each respective IC of the subgroup and select a redundant IC based on the shortest average length, shortest communication time, highest bandwidth, lowest latency, etc.).

[0148] Control module 1540 may select a redundant IC to replace a failed or malfunctioning IC based on whether the redundant IC is in use or not in use. For example, if redundant IC C51 is in use to replace a first malfunctioning IC, control module 1540 may select redundant IC C56 to replace a second malfunctioning IC even if control module 1540 would select redundant IC C51 were it not in use.

[0149] Additionally or alternatively, control module 1540 may utilize one or more ICs of redundant ICs 1514 to supplement an overall performance of SoW 1500b even if no system ICs 1510 are determined to have failed or malfunctioned. For example, a baseline performance of SoW 1500b may be relative to a total number of system ICs 1510, such as 88 ICs. In an embodiment, each IC of both system ICs 1510 and redundant ICs 1514 may be substantially identical or analogous. Control module 1540 may increase a total performance of SoW 1500b by assigning tasks to redundant ICs 1514 as well as system ICs 1510 rather than keeping redundant ICs 1514 in reserve in case of a failure or malfunction of system ICs 1510. This may allow SoW 1500b to operate at a computing speed or power above a design power or speed for SoW 1500b, for example by providing about 5% more computing speed or power above a design computing speed or power. In increase in computing speed or power above a design computing speed or power may be about 1%, about 2%, about 8 %, about 10%, about 15%, about 20%, about 25%, about 50%, about 100%, about 200%, about 500%, or any suitable increase.

[0150] SoW 1500b may include a number of redundant ICs 1514 based on a number of functional system ICs 1510. For example, SoW 1500b may include one redundant IC for every 12 system ICs. Additionally or alternatively, SoW 1500b may include one redundant IC for every five system ICs, eight system ICs, ten system ICs, 15 system ICs, 20 system ICs, 24 system ICs, 30 system ICs, 36 system ICs, 50 system ICs, 100 system ICs, or any suitable number of system ICs.

[0151] FIG. 15C illustrates a SoW 1500c including a plurality of redundant ICs 1514 disposed in a backup group 1504. SoW 1500c may include analogous components to that of SoW 1500a and SoW 1500b including semiconductor wafer 1502, system ICs 1510, one or more memory modules 1512, group interconnects 1520, IC interconnects 1522, one or more wafer connectors 1530, and control module 1540 and further including a backup group 1504 having a plurality of redundant ICs 1514. Backup group 1504 may include any suitable number of redundant ICs 1514 including two redundant ICs, four redundant ICs, six redundant ICs, eight redundant ICs, ten redundant ICs, 12 redundant ICs, 16 redundant ICs, 20 redundant ICs, 50 redundant ICs, 100 redundant ICs, or any suitable number of redundant ICs.

[0152] Control module 1540 may dynamically assign one or more redundant ICs 1514 of backup group 1504 to replace a functionality of one or more system ICs 1510 that have failed,malfunctioned, are operating sub-optimally, to enhance a functionality and / or computational performance of SoW 1500c, or for any suitable purpose. For example, control module 1540 may determine that IC C 15 has ceased functioning properly and should be replaced with one or more redundant ICs 1514 of backup group 1504. Control module 1540 may select an appropriate redundant IC 1514 such as C79 and assign one or more computing tasks to C79 that would have been assigned to Cl 5 had C 15 been functioning properly. In an embodiment, control module 1540 may replace one or more system ICs 1510 with one or more redundant ICs 1514 even if the one or more system ICs 1510 are operating within normal limits or otherwise functioning properly.

[0153] In an aspect, control module 1540 may determine that a functional IC of system ICs 1510 has failed or is malfunctioning and replace a number of system ICs equivalent to a number of redundant ICs 1514 in backup group 1504. For example, control module 1540 may determine that functional IC C5 has failed. Control module 1540 may then replace a functionality of all of ICs C3-C7 and C 15-C19 with redundant ICs 1514 of backup group 1504. Alternatively, control module 1540 may assign a same number of redundant ICs 1514 to replace a functionality of a number of functional system ICs 1510 that have failed or malfunctioned. For example, if control module 1540 determines that three functional system ICs 1510 have failed, control module 1540 may assign three redundant ICs 1514 to replace the functionality of the failed ICs.

[0154] Control module 1540 may assign ICs to one or more subgroups including subgroups of system ICs that are part of functional system ICs 1510 or subgroups of redundant ICs that are part of backup group 1504. For example, control module 1540 may create a first subgroup including ICs C0-C1 -C2-C12-C13-C14 and a second subgroup C3-C4-C15-C16. Control module 1540 may further create a third backup subgroup of redundant ICs including C79-C80-C81-C91-C92-C93 and a fourth backup subgroup of redundant ICs including C82-C83-C94-C95. Control module 1540 may detect that C4 of the second subgroup has failed or malfunctioned. Control module 1540 may then replace a functionality of the second subgroup with the fourth subgroup of redundant ICs 1514 from backup group 1504. Additionally or alternatively, control module 1540 may replace the second subgroup with the fourth subgroup and subsequently create a fifth subgroup of three ICs including C3-C15-C16.

[0155] FIG. 15D illustrates a SoW 1500d including a plurality of redundant ICs 1514 disposed in a backup group 1504 and additionally including a repair module 1550. SoW 1500d may include analogous components to that of SoW 1500a and SoW 1500b including semiconductor wafer 1502, system ICs 1510, one or more memory modules 1512, group interconnects 1520, IC interconnects 1522, one or more wafer connectors 1530, and control module 1540 and backup group 1504 having a plurality of redundant ICs 1514. Backup group 1504 may include any suitable number of redundant ICs 1514 including two redundant ICs, four redundant ICs, six redundant ICs, eight redundant ICs, ten redundant ICs, 12 redundant ICs, 16 redundant ICs, 20 redundant ICs, 50 redundant ICs, 100 redundant ICs, or any suitable number of redundant ICs.

[0156] SoW 1500d may further include a repair module 1550 configured to identify, troubleshoot, and repair a failed or malfunctioning IC. Repair module 1550 may additionally or alternatively determine one or more redundant ICs 1514 of backup group 1504 to replace an IC ofsystem ICs 1510 that is malfunctioning. Repair module 1550 may perform one or more functions that control module 1540 is configured to perform, such as assigning redundant ICs 1514, controlling an operation of system ICs 1510, assigning computing tasks to system ICs 1510 and / or redundant ICs 1514, or the like. Repair module 1550 may be configured to update a firmware of ICs of 1500d including system ICs 1510 and / or redundant ICs 1514.

[0157] Repair module 1550 may be configured to diagnose or otherwise determine a cause of a malfunction of an IC of 1500d. For example, repair module 1550 may be configured to determine if a voltage provided to an IC is too high or too low, if a temperature of an IC is too high or too low, if a power provided to an IC is too high or too low, if one or more connections (e.g., communicative, electrical, power, etc.) have been interrupted, if one or more signals transmitted to or from an IC is unacceptably attenuated or disrupted, etc. Repair module 1550 may then assign an IC of redundant ICs 1514 to replace a malfunctioning IC or may transmit a notification to control module 1540 indicating that an IC is malfunctioning and / or a source of the malfunction.Mechanical Support for System on Wafer

[0158] Following below are more detailed descriptions of various concepts related to, and implementations of, a mechanical support for a system-on-a-wafer (SoW) and an assembly that includes a mechanical support and an SoW. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.

[0159] The figures and example implementations described below are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of such known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.An Example Mechanical Support

[0160] FIGS. 16A and 16B show an example cross section of a mechanical support 1600 for an SoW according to an embodiment. The mechanical support 1600 includes an upper frame 1610 and a lower frame 1620. The upper frame 1610 and the lower frame 1620 can be in the form of a cylinder or a rectangular prism with a hollow or open (in general, open) center 1615, 1625, respectively. The open centers 1615, 1625 can be the same size as each other and can be in the shape of a circle or cylinder. The mechanical support 1600 is in an open state in FIGS. 16A and 16BA.

[0161] The upper frame 1610 has a body 1611 that extends from a first end 1612 to a second end 1613 of the upper frame 1610. The first end 1612 includes an inner flange 1614 that extendsradially inwardly toward the open center 1615, such that the open center 1615 is smaller at the inner flange 1614 compared to at the body 1611.

[0162] The lower frame 1620 has a body 1621 that extends from a first end 1622 to a second end 1623. The first end 1622 includes an inner flange 1624 that extends radially inwardly toward the open center 1625, such that the open center 1625 is smaller at the inner flange 1624 compared to at the body 1621.

[0163] The upper frame 1610 and the lower frame 1620 can be symmetric with respect to one another, though the dimensions of the upper frame 1610 may be different than the dimensions of lower frame 1620. For example, the height of the upper frame 1610 may be different than the height of the lower frame 1620, where the height is measured with respect to a central axis 1616. Additionally or alternatively, the upper frame 1610 and / or the lower frame 1620 can be symmetric with respect to the central axis 1616.

[0164] The body 1611 of the upper frame 1610 and the body 1621 of the lower frame 1620 include a plurality of holes 1630 that are aligned with each other to receive a plurality of bolts 1632. The bolts 1632 can align the upper frame 1610 and the lower frame 1620 with respect to each other and with respect to the bolts 1632. The mechanical support 1600 can transition to a closed state by moving (e g. sliding) the upper frame 1610 towards the lower frame 1620 along the bolts 1632 and / or the lower frame 1620 towards the upper frame 1610 along the bolts 1632. When the mechanical support 1600 is in the closed state, a small gap can remain between the upper frame 1610 and the lower frame 1620 to allow for cables 1634, such as Peripheral Component Interconnect Express (PCIE) ribbon cables, to pass through. Alternatively, the cables 1634 can pass through slots 2000 (FIG. 20) in the lower frame 1620, in which case the upper frame 1610 and the lower frame 1620 can be in direct physical contact when the mechanical support 1600 is in the closed state. When the mechanical support 1600 is in the closed state, the relative distance, as measured with respect to the central axis 1616, between the upper frame 1610 and the lower frame 1620 is smaller compared to when the mechanical support 1600 is in the open state. The cables 1634 can be electrical cables and / or optical cables.

[0165] The upper frame 1610 is configured to receive and mechanically support a plurality of components including a subframe 1640, an SoW 1641 , at least one thermal interface material (TIM) 1642, a boiler plate 1643, and a boiling enhancement coating (BEC) 1644. The SoW 1641 is between the subframe 1640 and each TIM 1642. Each TIM 1642 may be disposed between each semiconductor chip 1652 and the boiler plate 1643 and may serve to enhance a heat transfer between boiler plate 1643 and each semiconductor chip 1652. The boiler plate 1643 is disposed between each TIM 1642 and the BEC 1644. The BEC 1644 is located adjacent to and in physical contact with the inner flange 1614.

[0166] The SoW 1641 includes a semiconductor wafer 1651, semiconductor chips 1652, and a redistribution layer (RDL) 1653. Voltage regulator modules (VRMs) 1658 are electrically mounted on the RDL 1653. The semiconductor wafer 1651 is between the semiconductor chips1652 and the RDL 1653. The semiconductor chips 1652 can be electrically coupled to the RDL1653 using deep trench caps (DTCs) 1654 and / or local silicon interconnects (LSIs) 1655. Thesemiconductor chips 1652 are electrically connected to the VRMs 1658 through the DTCs 1654 and / or the LSIs 1655 and the RDL 1653. The semiconductor chips 1652 are also electrically connected to chip connectors 1656 through the DTCs 1654 and / or the LSTs 1655 and the RDL 1653. The chip connectors 1656 can be PC1E connectors, or other connectors or switches.

[0167] A plurality of screws 1617 can extend through the subframe 1640, the SoW 1641, the TIM 1642, the boiler plate 1643, and the BEC 1644. The screws 1617 can align the subframe 1640, the SoW 1641, the TIM 1642, the boiler plate 1643, and the BEC 1644 with respect to each other and can apply a force to ensure direct physical contact between neighboring components / layers. Direct physical contact can be useful, for example, to maximize heat transfer between the SoW 1641, the TIM 1642, the boiler plate 1643, and the BEC 1644. The TIM 1642, the boiler plate 1643, and the BEC 1644 can represent at least one thermal exchange module 1671 and can comprise components of an immersion cooling system, such as immersion cooling system 4500 (FIG. 45).

[0168] The lower frame 1620 is configured to receive and mechanically support a plurality of components including a power distribution board 1661 (e.g., a DC power distribution board), a TIM 1662, a boiler plate 1663, and a BEC 1664. The TIM 1662 is between the power distribution board 1661 and the boiler plate 1663. The boiler plate 1663 is between the TIM 1662 and the BEC 1664. The BEC 1664 is located adj cent to and in physical contact with the inner flange 1624.

[0169] The VRMs 1658 are electrically coupled to the power distribution board 1661 to receive DC power from the power distribution board 1661.|00170| A plurality of screws 1627 can extend through the DC power distribution board 1661, the TIM 1662, the boiler plate 1663, and the BEC 1664. The screws 1627 can align the power distribution board 1661, the TIM 1662, the boiler plate 1663, and the BEC 1664 with respect to each other and can apply a force to ensure direct physical contact between neighboring components / layers. Direct physical contact can be useful, for example, to maximize heat transfer between the power distribution board 1661, the TIM 1662, the boiler plate 1663, and the BEC 1664. The TIM 1662, the boiler plate 1663, and the BEC 1664 can represent at least one thermal exchange module 1672 and can comprise components of an immersion cooling system, such as immersion cooling system 4500 (FIG. 45).

[0171] The mechanical support 1600, the SoW 1641, the at least one thermal module 1671, the power distribution board 1661, the at least one thermal module 1672 can comprise an assembly 12.

[0172] FIG. 17 shows an isometric view of the upper frame 1610 to further illustrate the boiler plate 1643 and the BEC 1644.

[0173] FIG. 18 shows an isometric view of the SoW 1641 to further illustrate the cables 1634, chip connectors 1656, semiconductor wafer 1651, and semiconductor chips 1652 according to an embodiment.|00174| FIG. 19 shows an isometric exploded view of the power distribution board 1661, the boiler plate 1663, and the BEC 1664 that are included in the lower frame 1620, according to anembodiment. The TIM 1662 is located on the back side of the power distribution board 1661 between the boiler plate 1663 and the power distribution board 1661, and thus is obscured in this view. Additional circuitry 1900 of the power distribution board 1661 are illustrated including a disconnect switch, a VRM input, a pulse-width modulator input, and output capacitors. The power distribution board 1661 also includes a 12V input connector 1910.

[0175] FIG. 20 shows an isometric transparent view of the lower frame 1620 according to an embodiment. The lower frame 1620 can include a plurality of holes or slots (in general, slots) 2000 that the cables 1634 can pass through. The slots 2000 extend from the open center 1625 radially outwardly through the body 1621 (e.g., from an inner side 2011 to an outer side 2012 of the body 1621). The slots 2000 can reduce or eliminate the need for any gap between the upper frame 1610 and the lower frame 1620 in the closed state, thus allowing the components to be more closely placed together to reduce space.

[0176] FIG. 21 A illustrates an exploded view of a mechanical support assembly 2100 for a SoW in accordance with the present technology. Assembly 2100 may include a BEC top frame 2104, BEC block 2108, TIM 2112, SoW 2116, input / output (IO) PCB 2120, VRM PCB 2124, IO frame 2128, power distribution board (PDB) 2132, and bracket 2136, each of which will be described in greater detail below. Assembly 2100 may be immersed in immersion cooling liquid, for example as part of a server. Assembly 2100 may be part of a suitable immersion cooling system, e.g., immersion cooling system 4500 depicted in FIG. 45.

[0177] Assembly 2100 may have any suitable dimensions including length and width, labeled L and W in FIG. 21B. For example, assembly 2100 may have a length of between about 375 mm and about 400 mm, and a width of between about 300 mm and about 350 mm. However, any suitable dimensions are envisioned. Further, it may be advantageous for a height (e.g., a dimension orthogonal to both the length and width) of assembly 2100 to have a height that is less than a threshold height. For example, a height of assembly 2100 may preferably be less than 100 mm, less than about 80 mm, less than about 70 mm, less than about 60 mm, less than about 50 mm, less than about 40 mm, less than about 30 mm, less than about 20 mm, less than about 10 mm, or any suitable thickness.

[0178] FIG. 21 C shows a top and two side profile views of assembly 2100. BEC top frame 2104 is visible in all three views, with the top view in particular illustrating openings within BEC top frame 2104 which expose BEC block 2108 to immersion cooling liquid when assembly 2100 is disposed in immersion cooling liquid. FIG. 21D illustrates a bottom view of assembly 2100, which primarily shows the bottom of bracket 2136.

[0179] FIG. 22 shows top and side views of BEC top frame 2104. BEC top frame 2104 is shown as having 20 apertures 2140 for thermally coupling logic ICs or other heat generating components (e.g., which are part of SoW 2116) to immersion cooling liquid in which assembly 2100 is disposed. BEC top frame 2104 may have any suitable number of apertures 2140. BEC top frame 2104 may function to conduct heat generated by SoW 21 16 through TIM 21 12 and to increase a surface area for heat to transfer into an immersion cooling liquid. BEC top frame 2104 may include slots 2141 (equivalently, channels 2141) for both increasing an exposed surface area of BEC topframe 2104 as well as providing a path for immersion cooling liquid to replace immersion cooling vapor when SoW 2116 is operating and generating heat and giving immersion cooling vapor a path by which to move away from apertures 2140.

[0180] BEC top frame 2104 may be made of a suitable material such as copper, steel (including stainless steel), iron, titanium, aluminum, or any suitable material. BEC top frame 2104 may include one or more coatings, treatments, or surface modifications to create a hydrophobic effect. For example, BEC top frame 2104 may include a hydrophobic coating such as silane, polytetrafluoroethylene (PTFE), cerium oxide, or any suitable hydrophobic coating. Additionally or alternatively, BEC top frame 2104 may include surface modification such as laser surface topology modification or other etching processes that create surface features having a pitch, scale, and / or major dimension configured to reduce a surface energy of the BEC top frame 2104. For example, a laser may be used to selectively remove material in a predetermined pattern (e.g., cross hatching, a grid defined by repeated volumes of removed material, lines, etc.) from BEC top frame 2104 such that the surface of BEC top frame 2104 becomes more hydrophobic.

[0181] Such a hydrophobic coating may help prevent an accumulation of contamination and / or deposition of impurities dissolved in immersion cooling liquid in which assembly 2100 is disposed. For example, when water is introduced to an immersion cooling system (for example, from the atmosphere when an immersion cooling tank lid is open or from an accidental spillage of water into an immersion cooling tank from cooling pipes), the water may mix with immersion cooling liquid and form acidic or corrosive compounds. These compounds may significantly disrupt the operation of components within an immersion cooling system or destroy components entirely. A coating in accordance with the present technology may help mitigate or impede a deposition or corrosion associated with a contaminant in immersion cooling liquid.

[0182] FIG. 23 illustrates top and side views of BEC block 2108. BEC block 2108 may be made of any suitably heat conducting material such as copper, although any material contemplated herein may be used. BEC block 2108 may have suitable dimensions, for example a length of between about 200 mm and about 225 mm, a width of between about 175 mm and about 200 mm, and a height of between about 1 mm and about 10 mm. BEC block 2108 may function to thermally couple heat generating components (e.g., logic ICs on SoW 2116) to an immersion cooling liquid in which assembly 2100 is disposed. Some or all portions of BEC block 2108 may include a surface coating or treatment, such as that described above with respect to BEC top frame 2104.

[0183] FIG. 24 illustrates top and side views of TIM 2112. TIM 2112 may be made of any suitable material such as silicone. TIM 2112 may additionally or alternatively include filler materials such as metal oxides, carbon (e.g., carbon black), metals, and the like. TIM 21 12 may preferably have a thickness of less than about 1 mm; for example less than about 0.75 mm, less than about 0.5 mm, less than about 0.3 mm, less than about 0.25 mm, less than about 0.2 mm, less than about 0.1 mm, or any suitable thickness.

[0184] FIG. 25 illustrates top and side views of SoW 21 16. SoW 21 16 may include a plurality of IO chiplets 2160 for managing data transfer to and from logic ICs 2162. IO chiplets 2160 may be communicatively coupled to logic ICs 2162 as well as logic ICs or other components disposed ondifferent SoWs or in different computing systems through suitable networking and connection hardware. SoW 2116 may further include a plurality of wafer connectors 2164, which may be analogous to one or more wafer connectors 1530. Logic ICs 2162 may be multi-functional and can include logic chips, switches, memory modules, NICs, input / output (I / O) controllers, and / or other chips. Examples of logic chips include GPUs, DPUs, CPUs, TPUs, SoCs, DRAM, SRAM, NVRAM, EEPROM, EPROM, OTPROM, SSDs, or the like.

[0185] FIG. 26 illustrates top and side views of IO PCB 2120 and VRMPCB 2124 mechanically and communicatively coupled to SoW 2116. IO PCB 2120 may include one or more connectors and one or more communications paths (e.g., wires or traces) that communicatively couple components of SoW 2116 (e.g., logic ICs 2162) with components external to SoW 2116. VRM PCB 2124 may electrically couple SoW 2116 and PDB PCB 2132. VRM PCB 2124 may function to regulate one or more voltages provided by PDB PCB 2132 to SoW 2116. IO PCB 2120 may enable communication between a plurality of SoWs, e g., between SoW 2116 and an analogous SoW, between SoW 2116 and one or more external components such as a remote computer, or any suitable component. IO PCB may include one or more fanouts of communications paths (such as PCIe lanes), e g., from IO chiplets 2160 to connectors 2126 disposed on one or more of the fanouts.

[0186] FIG. 27 illustrates top and side views of IO frame 2128. IO frame 2128 may be analogous to lower frame 1620 in FIG. 20. IO frame may be made of any suitable material including copper, steel, iron, aluminum, titanium, or the like. IO frame 2128 may have exemplary dimensions of about 275 mm to about 300 mm in length and width, and a height of between about 10 mm and about 20 mm. IO frame 2128 may serve to provide structural support for assembly 2100, SoW 2116, and cabling attached to SoW 2116 such that forces applied to connectors or other portions of assembly 2100 (e.g., during handling, plugging or unplugging cables, or the like) do not transfer to SoW 2116 and damage or break it.

[0187] FIG. 28 illustrates a PDB PCB 2132 in accordance with the present technology. PDB PCB 2132 may include bus bar connectors 2170, which may receive power from a bus bar as, e g., a 48 V input. PDB PCB 2132 may further include an intermediate bus converter module (IBC 2172) configured to convert the input voltage from the bus bar and bus bar connectors 2170 to a lower voltage appropriate for logic ICs, e g., approximately 1.2 V. PDB PCB 2132 further includes a plurality of placement areas 2174 for VRMs of VRM PCB 2124. Placement areas 2174 may include electrical coupling to IBC 2172 and / or bus bar connectors 2170.

[0188] FIG. 29 illustrates front and side views of bracket 2136. Bracket 2136 may be mechanically coupled to PDB PCB 2132 and / or IO frame 2128 and provide a structure for attaching assembly 2100 to a server, immersion cooling container, or other suitable object. Bracket 2136 may be made out of a suitable material, for example steel, aluminum, titanium, or any other suitable material.

[0189] FIG. 30 illustrates a partial manufacturing order 3000 for joining the constituent components of assembly 2100 to form assembly 2100. Grouping 3005a including VRM PCB 2124 and IO PCB 2120 are attached to SoW 2116. Assembled grouping 3005b is then attached to BECblock 2108, TIM 2112, and BEC top frame 2104. PDB PCB 2132 and bracket 2136 are then added, forming assembly 2100.

[0190] FIG. 31 A and FIG. 3 IB illustrate top and side views, respectively, of a jig 3100 for assembling assembly 2100. Jig 3100 may be used to hold or support various components of assembly 2100 while they are being joined. Jig 3100 may include a base 3104, a bottom portion 3106, a top portion 3108, top opening 3112, handle 3116, hinge 3120, side opening 3122, guiding structures 3124, and opening mechanism 3128. Top portion 3108 may rotate about hinge 3120 in order to open and allow the insertion of components of assembly 2100. Once each piece of assembly 2100 has been inserted into jig 3100, top portion 3108 may be closed and pressure applied to compress components of the assembly 2100, ensuring good thermal contact between each of the components of assembly 2100 and reducing a height of the assembly.

[0191] FIG. 32A and FIG. 32B illustrate top and side views, respectively, of a jig 3200 for assembling assembly 2100. Jig 3200 may be substantially analogous to jig 3100, except instead of being mounted on base 3104, jig 3200 may be mounted on a post 3102. Thus, bottom portion 3106 and top portion 3108 may rotate about post 3102, giving a user additional flexibility when working with jig 3200 as compared to jig 3100.100192] FIG. 33 A and FIG. 33B illustrate a cable arrangement 3300 in accordance with the present technology. Arrangement 3300 may include a receptacle 3312 configured to interface with a cable 3316 via self-aligning snap-in connector 3320. Self-aligning snap-in connector 3320 may include a v-groove passive alignment feature as well as wires 3318. Wires 3318 may be embodied as copper wires, gold-coated copper wires, or any suitable type of wire, trace, or communications path. Each wire of wires 3318 may interface with a corresponding wire of wires 3314. Wires 3314 may be included in receptacle 3312 and continue into module 3308 to communicatively couple a component within, on, proximal to, or associated with module 3308 with another component communicatively coupled via cable 3316. FIG. 33 A illustrates three cables interfacing with three receptacles 3312a-c. Module 3308 may be mounted on substrate 3304, e g., an SoW RDL.

[0193] FIG. 33B illustrates a closeup of receptacle 3312, wires 3314, cable 3316, and selfaligning snap-in connector 3320. Both wires 3314 and wires 3318 may be gold-coated copper wires, uncoated copper wires, or any material suitable for carrying signals.

[0194] FIG. 34 illustrates an example wiring diagram utilizing a cable and receptacle analogous to that depicted in FIGS. 33 A and 33B. An SoW top frame 3404 may be disposed on an SoW RDL 3408, which is disposed on an SoW mid frame 3420. SoW mid frame 3420 may in turn be disposed on an SoW PDB 3402. SoW PDB 3402 may be configured to provide power to SoW RDL 3408 through one or more traces (not shown). The SoW mid frame 3420 may house receptacle 3412, which may interface with cable 3416 to communicatively couple an first component to which cable 3416 is connected with a second component to which communication path 3414 is connected (e.g., a logic IC disposed on or in SoW RDL 3408). Receptacle 3412 may include one or more communications paths 3414 (e g., wires made from copper or gold-plated copper), which may be communicatively coupled to the redistribution layer of SoW RDL 3408 through a solder connection 3418. Any suitable join is contemplated between communication path 3414 and SoWRDL 3408, including a bump bond, a C4 bond, physical pressure (i.e., where communication path 3414 and SoW RDL 3408 are in physical contact, but not affixed to one another), or the like.

[0195] FIG. 34 further illustrates a closeup of cable 3416 interfaced with receptacle 3412 and thereby communicatively coupling communication path 3414 with wires of cable 3416. In particular, FIG. 34 shows the communications path 3414 within receptacle 3412 and terminating at solder connection 3418.

[0196] FIG. 35 illustrates module 3500 and module 3501, both of which include both SDRAM and VRM modules. Module 3500 includes SDRAM modules 3554 mounted to a interposer PCB 3505 and communicatively coupled to one or more logic ICs 3552. Module 3500 may be mechanically coupled to SoW RDL 3504 and communicatively coupled to one or more logic ICs 3552 via connections 3510. Connections 3510 may be embodied as a ball grid array (BGA), elastomer, interposer, solder connections, bump bonds, microbump bonds, C4 bonds, or any suitable connections. Interposer PCB 3505 may include one or more traces or wiring layers that provide a communications path between SDRAM modules 3554 and SoW RDL 3504. VRM 3558 may be mounted (e.g., disposed on, attached to, etc.) to a interposer PCB 3506 and configured to provide power to one or more logic ICs 3552 and / or SDRAM modules 3554. Interposer PCB 3505 and interposer PCB 3506 may be separated by one or more standoffs 3508.

[0197] Module 3501 may have a similar arrangement to module 3500, except SDRAM modules 3554 may be mounted directly to SoW RDL 3504 (e.g., soldered directly to SoW RDL 3504), in which case connections 3510 and interposer PCB 3505 may be omitted. In the case of module 3501, SDRAM modules 3554 and VRM 3558 may be communicatively and / or electrically coupled with one or more logic ICs 3552 and / or other components of an SoW directly through SoW RDL 3504. Compared to module 3500, module 3501 may utilize additional connectors (not shown) for electrically coupling VRM 3558 with one ormore logic ICs 3552, SDRAM modules 3554, or other components.|00198| FIG. 36 illustrates a top view of an SDRAM module 3600. SDRAM module 3600 may include SDRAM modules 3654, for example eight SDRAM modules 3654. SDRAM modules 3654 may be mounted on interposer PCB 3604, e.g., by soldering the SDRAM modules 3654. SDRAM module 3600 may further include standoffs 3602 for securing SDRAM module 3600 to an SoW or other component. SDRAM module 3600 may further include one or more VRM power connectors 3620, which may be configured to provide an electrical connection between one or more VRMs and SDRAM modules 3654. In an aspect, SDRAM module 3600 may have dimensions (e g., length and width) between about 40 mm and about 50 mm.

[0199] SDRAM module 3600 is illustrated as having eight SDRAM modules 3654, but any number of SDRAM modules 3654 are contemplated with the present invention, including two SDRAM modules 3654, four SDRAM modules 3654, six SDRAM modules 3654, or any suitable number. SDRAM module 3600 may correspond to module 3500 and / or module 3501.

[0200] FIG. 37 illustrates two additional combined SDRAM and VRM modules, module 3700 and module 3701. Module 3700 and / or module 3701 may be disposed on SoW RDL 3704. SoW RDL 3704 may further include logic ICs 3752, which may be analogous to or the same as otherlogic ICs described herein. Module 3700 and module 3701 may each include a plurality of SDRAM modules 3754. Module 3700 and module 3701 may each include any suitable number of plurality of SDRAM modules 3754, for example two SDRAM modules 3754, four SDRAM modules 3754, six SDRAM modules 3754, eight SDRAM modules 3754, or other numbers of plurality of SDRAM modules 3754 as appropriate. Module 3700 and module 3701 utilize a stacking arrangement of SDRAM modules to reduce a horizontal footprint (e.g., a footprint in a plane parallel to SoW RDL 3704).

[0201] Module 3700 and module 3701 may include a plurality of connections 3710 configured to communicatively couple SDRAM modules 3754 to one another as well as logic ICs 3752, SoW RDL 3704, or other components disposed on or communicatively coupled with SoW RDL 3704. Connections 3710 may include wires, traces, leads, pads, or other suitable components for providing a path for signals and / or power. Module 3700 may include interposer 3705 on which each SDRAM module of the plurality of SDRAM modules 3754 of module 3700 are disposed. Plurality of connections 3710 may be disposed within interposer 3705, e.g., may be integrated with interposer 3705 as an RDL.

[0202] One or more VRMs 3758 may be disposed on interposer 3706 and may be electrically coupled to plurality of SDRAM modules 3754, logic ICs 3752, and / or SoW RDL 3704 through one or more connectors analogous to one or more VRM power connectors 3620 shown in FIG. 36 and 3820 shown in FIG. 38. Module 3701 may be analogous to module 3700, except a plurality of plurality of SDRAM modules 3754 may be disposed directly on SoW RDL 3704 instead of interposer 3705. As in module 3700, module 3701 may include plurality of connections 3710 for providing a path for signals and / or power between plurality of SDRAM modules 3754 as well as One or more VRMs 3758, logic ICs 3752, and SoW RDL 3704.

[0203] Module 3700 and module 3701 may further include one or more standoffs 3708, which may be analogous to one or more standoffs 3508.|00204| FIG. 38 illustrates a top view of a module 3800, which may correspond to module 3700 and / or module 3701. Module 3800 may include interposer 3804 on which a plurality of SDRAM modules 3854 are mounted. Module 3800 may include one or more VRM power connectors 3820, which may be configured to provide an electrical connection between one or more VRMs and SDRAM modules 3854. In an aspect, SDRAM module 3800 may have dimensions (e.g., length and width) between about 30 mm and about 40 mm, such as about 35 mm. The reduced horizontal footprint of module 3800 as compared to modules 3500, 3501, and 3600 may enable a larger number of SDRAM modules to be mechanically and communicatively coupled to an SoW, with a potential tradeoff of larger overall SoW height (and a larger overall height of an assembly of which modules 3700, 3701, and 3800 are apart). Module 3800 may further include standoffs 3802, which may be analogous to standoffs 3602.

[0205] FIG. 39 illustrates an assembly 3900 that includes a plurality of elastomer sockets 3940 providing a mechanical and communicative coupling for VRM modules 3958 and PCIe connectors 3956 to substrate 3953. Each elastomer socket 3940 may include connectors 3942, which may be disposed on or in the plurality of elastomer sockets 3940. An advantage of plurality of elastomersockets 3940 is that the components such as VRM modules 3958 and / or PCIe connectors 3956 may be removed from substrate 3953 without damaging the substrate. An elastomer socket 3940 may be decoupled from substrate 3953 without requiring the breaking of a solder or other permanent connection, as well as relatively reducing a force required to decouple the elastomer socket 3940, thus decreasing a likelihood of damaging substrate 3953. Plurality of elastomer sockets 3940 may be made of silicone or other suitable material, and may include metal wires, traces, pads, leads, or other connectors 3942 for transmitting signals and power.

[0206] FIG. 40A and FIG. 40B illustrate top and side views of an example block diagram of a VRM module 4058 attached to an elastomer 4040, which in turn is disposed on substrate 4053. The VRM module 4058 and elastomer 4040 are disposed within a mounting hole of IO frame 2128. Elastomer 4040 provides a mechanical and communicative coupling between VRM module 4058 and substrate 4053. FIGS. 40A and 40B additionally illustrate an outline of IO frame 2128 to show how the VRM module 4058 and elastomer 4040 may sit inside an aperture of IO frame 2128 and be supported by IO frame 2128. Substrate 4053 may be disposed on and be secured to / supported by a surface of IO frame 2128.

[0207] FIG. 41 A and FIG. 41B illustrate side and front views of an clamp assembly 4100 for securing a cable and connector to a substrate using a clamp. Cable 4116 may interface with connector 4112, which is communicatively coupled to substrate 4153 through elastomer socket 4140. Elastomer socket 4140 may include one or more connectors 4142 that provide a communicative coupling between connector 4112, cable 4116, substrate 4153, and / or one or more components disposed on or communicatively coupled with substrate 4153. Connector may be at least partially mechanically secured to substrate 4153 by clamp 4150. Clamp 4150 may be made of any material that is suitably compatible with immersion cooling liquid, such as steel, aluminum, silicone, titanium, polycarbonate, copper, or the like. Clamp 4150 may be mechanically attached to substrate 4153 by screws 4160.

[0208] FIG. 42A illustrates a block diagram of a system 4200 having a VRM 4258 electrically coupled to a plurality of logic ICs 4252, for example four logic ICs 4252.

[0209] FIG. 42B illustrates the use of a pogo connector 4240 to communicatively couple a VRM 4258 with a PDB 4232. VRM 4258 may be mounted on a wafer 4216. A pogo connector 4240 may include one or more spring-loaded pins which enable communicative and electrical coupling between a plurality of components while more evenly distributing forces experienced by system 4200 during compression.

[0210] FIG. 43A and FIG. 43B illustrate side and top views, respectively, of a pogo connector 4300. Pogo connector 4300 may include a housing 4310, communications pins 4320, power pins 4330, and ground pins 4340. Each of communications pins 4320, power pins 4330, and ground pins 4340 may be spring-loaded and compressible.

[0211] FIG. 44A and FIG. 44B illustrate side and top views, respectively, of a block diagram of a VRM assembly with boiling plate and TIM for improved heat extraction. VRM assembly 4400 may include VRM 4458, which is mechanically and / or communicatively coupled with logic ICs. 4452 through connections 4410. Connections 4410 may be solder connections or any other suitableconnection type as contemplated herein. Logic ICs 4452 may be disposed within substrate 4404, which may be an SoW RDL as contemplated herein. A TIM 4470 may be disposed on VRM 4458, and a boiler plate 4460 may be disposed on TIM 4470. Boiler plate 4460 may be made of any suitable material, such as copper, steel, aluminum, titanium, or the like, and may include one or more surface treatments as described herein.

[0212] FIG. 45 depicts aspects of an immersion cooling system 4500 for dissipating heat from one or more heat-generating components such as semiconductor die packages 4505 via immersion cooling. Each package 4505 can include one or more semiconductor dies that produce heat when the system is in operation. The immersion cooling system 4500 in the illustrated example of FIG. 45 is a two-phase immersion cooling system, though the invention may also be implemented in a single-phase immersion cooling system.

[0213] One or more semiconductor die packages 4505 may be 3DIC stacks in accordance with the present technology. For example, one or more semiconductor die packages 4505 may include a logic IC and at least one memory module bonded to the logic IC using a hybrid bond or microbump bond. Additionally or alternatively, the one or more semiconductor die packages 4505 may be part of one or more SoWs, such as SoWs described herein.|00214| Immersion cooling systems may provide particular advantage to 3DIC stacks and SoWs due to the lower surface area to volume ratio of a 3DIC stack or SoW compared to the individual components of the 3DIC stack or SoW (e g., a bonded logic IC and memory module will have a lower surface area to volume ratio than the combined surface area to volume ratio of the physically separated logic IC and memory module) as well as the additional heat generated by state of the art logic ICs. This lower surface area to volume ratio means waste heat generated by the 3DIC stack may not be as efficiently dissipated and may require better cooling performance than air cooling can provide. Two-phase immersion cooling in particular can provide this additional heat removal required by 3DIC stacks.|00215| Immersion cooling system 4500 includes a container such as tank 4520 filled, at least in part, with immersion cooling liquid 4564. The immersion cooling system 4500 can further include at least one chiller 4580 that flows a heat-transfer fluid through at least one condenser tube 4570 that is disposed in the tank 4520 and headspace 4508. Condenser tubes 4570 and chiller 4580 may be part of a heat exchanger. The packages 4505 can be mounted on one or more printed circuit boards (PCBs) 4557 that are immersed, at least in part, in the immersion cooling liquid 4564. Immersion-cooling system 4500 may further include a filter 4575 disposed adjacent to the tank 4520.

[0216] Filter 4575 may include a filtration media, a housing, and a pump configured to force immersion cooling liquid 4564 through filter 4575 to remove contaminants, particulates, or other impurities that may be added to immersion cooling liquid 4564 during use. Filter 4575 may be housed outside of tank 4520 while being in fluidic communication with immersion cooling liquid 4564 in tank 4520. Alternatively, filter 4575 may be submerged within immersion cooling liquid 4564 inside of tank 4520.

[0217] Immersion cooling liquid 4564 may be a hydrocarbon, a fluoroketone, an oil, or a similardielectric liquid that will act as an insulator while simultaneously transferring heat from package 4505 more efficiently than air. Examples of immersion cooling liquid 4564 are Novec™ 649, Novec™ 7000, and Novec™ 7100 produced by 3M™. An exemplary immersion cooling liquid 4564 used in accordance with embodiments of the present invention may have a dielectric constant baseline value of about 1.8-2 at a frequency of about 1 kHz.

[0218] In an embodiment of the invention, immersion cooling liquid 4564 may be considered unacceptably contaminated if the dielectric constant and / or dielectric loss tangent of immersion cooling fluid being used in an immersion cooling system 4500 differs by a threshold amount as compared to unused or pure immersion cooling liquid 4564. For example, immersion cooling liquid 4564 may be considered unacceptably contaminated or degraded if the dielectric constant and / or dielectric loss tangent differs by a threshold of 10% or more as compared to unused or pure immersion cooling liquid 4564. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be 20%, 15%, 5%, 3%, 1%, or any suitable threshold.

[0219] Contamination of the immersion cooling liquid 4564 and resulting changes to dielectric constant and / or dielectric loss tangent may alter or negatively impact operation of components within immersion cooling liquid 4564 including semiconductor die(s) 4550. An altered dielectric constant and / or dielectric loss tangent may result in undesirable cross-talk between components on a PCB, additional noise or reduction in signal strength transmitted along exposed wires of a PCB or semiconductor die(s) 4550 submerged in immersion fluid, and / or signal dissipation through the immersion cooling liquid 4564. Signal loss may be severe enough that two elements may be effectively represented as being separated by an open circuit despite being physically connected. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be selected based on an observed or inferred effect on one or more submerged semiconductor die(s) 4550. For example, an increase in PCIe bit error rate above an error rate baseline may be correlated with an increase in dielectric constant and / or dielectric loss tangent above a dielectric constant and / or dielectric loss tangent baseline. Accordingly, operation of semiconductor die(s) 4550 may be throttled or suspended when a dielectric constant and / or dielectric loss tangent of immersion cooling liquid 4564 exceeds a predetermined threshold.

[0220] Changes to dielectric constant and / or dielectric loss tangent may be caused by contaminants within immersion cooling liquid 4564. In some cases, changes to dielectric constant and / or dielectric loss tangent may be reversed by filtering the contaminants from immersion cooling liquid 4564. In some embodiments, upon detecting an increase in dielectric constant and / or dielectric loss tangent of immersion cooling liquid 4564, controller 4502 may instruct filter 4575 to increase filtration throughput or notify a user that an immersion cooling liquid 4564 filtration media may need to be replaced. If a dielectric constant and / or dielectric loss tangent exceeds a predetermined threshold, controller 4502 may throttle or shut down one or more semiconductor die(s) 4550, generate a notification that immersion cooling liquid 4564 should be replaced, trigger an alarm, etc.

[0221] Further examples of sensors and methods for immersion cooling contamination monitoring may include probes for monitoring immersion cooling liquid parameters such asdielectric constant and dielectric loss tangent, and processors configured to identify trends in sensor data, model immersion cooling system behavior as a function of contamination, and alter operations of immersion cooling systems based on detected levels and / or states of contamination may be found in U.S. Provisional Patent Application 63 / 516,748, filed July 31, 2023 and entitled “Di-Electric Monitoring of Immersion Fluid During Cooling Operation,” the entirety of which is incorporated herein by reference.

[0222] The illustrated example of FIG. 45 is not intended to be to scale. The immersion cooling system 4500 may house and provide immersion cooling liquid 4564 to tens, hundreds, or even thousands of packages 4505. In some cases, the immersion cooling system 4500 can be small (e.g., the size of a floor unit air conditioner, approximately 1 meter high, 0.5 meter width, 0.5 meter depth or length). In some implementations, the immersion cooling system can be large (e.g., the size of a van or larger, approximately 2.5 meters high, 2.5 meters width, 4 meters depth or length).

[0223] The immersion cooling system 4500 can also include a controller 4502 (e.g., a microcontroller, programmable logic controller (PLC), microprocessor, field-programmable gate array, logic circuitry, memory, or some combination thereof) to manage system operation. Controller 4502 can perform various system functions such as monitoring temperatures of system components, cooling fluid level, tank access, chiller operation etc. The controller 4502 can further issue commands to control system operation such as executing a start-up sequence, executing a shut-down sequence, assigning workloads among the packages, changing cooling fluid level, changing the temperature of the heat-transfer fluid circulated by the chiller 4580, etc. In some implementations, controller 4502 can include (or itself be) a baseboard management controller (BMC) 4504. That is, the BMC 4504 may monitor and control all aspects of system operation for the immersion cooling system 4500 in addition to monitoring and controlling workloads of the semiconductor dies 4550 in the packages 4505 cooled by the system. The immersion cooling system 4500 can also include a network interface controller (NIC 4503) to allow the system to communicate over a network, such as a local area network or wide area network. The immersion cooling system 4500 can further include a fluid sensor array 4590 having a plurality of fluid sensors 4510. Fluid sensors 4510 may include one or more leak detection sensors at least partially submerged in immersion cooling liquid 4564.

[0224] The semiconductor die(s) 4550 and can be mounted on and attached to a printed circuit board (PCB) 4555 (sometimes referred to as a substrate) in device package 4505. The package 4505 can be made commercially available as an off-the-shelf (OTS) product. The package 4505 can be used for single-phase or two-phase immersion cooling of at least one semiconductor die 4550, such as a microprocessor (e.g., a central processing unit (CPU) and / or graphics processing unit (GPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0225] In the two-phase immersion cooling system 4500 of FIG. 45, heat flows from the semiconductor die 4550 where it is generated into the heat spreader 4552. The heat spreader 4552is in thermal contact with an immersion cooling liquid 4564 that can flow over and extract heat from the heat spreader 4552. The amount of heat delivered by the heat spreader 4552 to the immersion cooling liquid 4564 is enough to boil the immersion cooling liquid 4564 that contacts the heat spreader 4552 (creating bubbles 4565 and potentially creating froth 4567 when bubbles 4565 reach the surface of immersion cooling liquid 4564). The vapor 4566 from the boiled immersion cooling liquid 4564 can be cooled and condensed back to liquid droplets 4568, for example, by the condenser tube 4570. The heat-transfer fluid, such as chilled water, from the chiller 4580 can be circulated through the condenser tube 4570 to lower the temperature of the condenser tube 4570 below the condensation point in the headspace 4508 of the tank 4520. As a result, vapor 4566 condenses on exterior surfaces of the condenser tube 4570 and liquid droplets 4568 from the condensed vapor can drip and / or flow back to the immersion cooling liquid 4564. There may be a plurality of condenser tubes 4570 in tank 4520 to condense the vapor 4566 into droplets. Some or all of the condenser tubes 4570 may or may not be located directly over the PCBs 4557. Instead, the condenser tube(s) 4570 can be located near one or more walls of the tank 4520, such that the condenser tube(s) 4570 are not directly over the PCBs 4557 on which the packages 4505 are mounted.

[0226] To improve thermal performance in two-phase immersion cooling system 4500, the heat spreader 4552 can include a boiling enhancement coating (BEC) on at least one surface. The BEC can be formed from copper or a copper alloy and can be porous, for example, though BECs can take various forms. In some cases, the BEC is a micro porous copper coating having a thickness from approximately or exactly 50 microns to 500 microns thick (which may be produced by electroplating and / or etching). In some implementations, the BEC comprises a mesh copper layer bonded (e.g., via resistance heating) to at least an outer surface of the heat spreader 4552. In some cases, the BEC is applied as particulates to at least one smooth surface of the heat spreader 4552 and then subsequently sintered to adhere to one another and to the heat spreader 4552. The BEC provides an improved surface area to contact the immersion cooling liquid 4564 and can increase the heat transfer coefficient from the heat spreader 4552 to the immersion cooling liquid 4564 by up to a factor of 15 versus a smooth surface on the heat spreader 4552. Accordingly, BECs can increase thermal conductivity to, and accelerate the boiling of, the immersion cooling liquid 4564.

[0227] Further implementations of boiling enhancement coatings and enclosures are possible. Additional arrangements, applications, and methods of use of boiling enhancement coatings and enclosures, including with semiconductor dies and 3DIC stacks, are described in the below U.S. Patent Applications.

[0228] U.S. Patent Application No. 18 / 327,615, filed June 1, 2023 and entitled "Boiler Enhancement Coatings with Active Boiling Management,” discloses heat spreader and boiling enhancement enclosure architectures thermally and / or mechanically coupled to one or more semiconductor dies or logic ICs that may be used for passive and / or active management of immersion cooling fluid boiling, including through the use of valves to control pressure of boiling immersion cooling fluid within a boiling enhancement chamber, particularly in paragraphs

[0018] -

[0039] and FIGS. 3-5B. The entirety of U.S. Patent Application No. 18 / 327,615 is incorporated herein by reference.

[0229] U.S. Provisional Patent Application No. 63 / 500,167, filed May 4, 2023 and entitled “Direct to Chip Heat Spreader and Boiler Enhancement Coatings for Microelectronics,” discloses heat spreader and BECs thermally and / or mechanically coupled to one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0015] -

[0033] and FIGS. 2A-4. BEC form factors may include graphite heat spreader architectures, vapor chambers, heat pipes, copper plates, fins, and the like. BEC form factors may be thermally and / or mechanically coupled to the one or more semiconductor dies, logic ICs, and / or 3DIC stacks through a thermally conductive epoxy, and may have varying dimensions relative to a surface to which the semiconductor dies and / or logic ICs are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 500,167 is incorporated herein by reference.

[0230] U.S. Patent Application No. 18 / 460,091, filed September 1, 2023 and entitled “Direct to Chip Application of Boiling Enhancement Coating,” discloses BECs and methods for applying BECs to semiconductor dies, logic ICs, and / or 3DIC stacks in accordance with the present technology. In particular, paragraphs

[0024] -

[0046] and FIGS. 2A-5 disclose embodiments of BEC layers, adhesives, solders, sintering, laser ablation, meshes, and other BECs and BEC application methods. The entirety of U.S. Patent Application No. 18 / 460,091 is incorporated herein by reference.

[0231] U.S. Provisional Patent Application No. 63 / 506,945, filed June 8, 2023 and entitled “Vapor-Shedding Structures for Boiler Plates in Two-Phase Immersion Cooling Systems,” discloses structures that may be thermally and / or mechanically coupled to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks to enable the shedding of immersion cooling vapors generated from the boiling of immersion cooling fluid during operation of the computing hardware. In particular, paragraphs

[0021] -

[0039] and FIGS. 3A-5 disclose vapor-shedding structures including varying porosities, constituent materials, and geometries relative to the computing hardware on which they are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 506,945 is incorporated herein by reference.|00232| U.S. Provisional Application No. 63 / 513,828, filed July 14, 2023 and entitled “Grinding Apparatuses and Methods for Mechanically Modifying Surfaces of Processors to Promote Boiling of a Coolant Liquid,” discloses methods for creating boiling enhancement modifications to surfaces such as the surfaces of computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0036] -

[0095] and FIGS. 2A-8. For example, grooves, patterns, gouges, trenches, or other structures may be added to a surface or lid of a processor, semiconductor die, logic IC, 3DIC stack component, and / or BEC to encourage nucleation sites for bubbles of immersion cooling vapor to form during a cooling process, thus decreasing the thermal resistance between the processor, semiconductor die, logic IC, and / or 3DIC stack component and the surrounding immersion cooling fluid. The entirety of U.S. Provisional Application No. 63 / 513,828 is incorporated herein by reference.

[0233] U.S. Provisional Patent Application No. 63 / 513,829, filed July 14, 2023 and entitled “Electrical Connector Having a Heater to Facilitate Boiling of a Coolant Liquid to Improve Signal Integrity in Immersion Cooling Environment,” discloses heaters for promoting boiling ofimmersion cooling fluid near electrical connectors such as connections between components of a 3DIC stack and enable improved impedances at those connectors, particularly in paragraphs

[0019] -

[0052] and FTGS. 1 A-3B. The entirety of U.S. Provisional Patent Application No. 63 / 513,829 is incorporated herein by reference.

[0234] U.S. Provisional Patent Application No. 63 / 603,242, filed November 28, 2023 and entitled “Woven Boiler Enhancement Coatings,” provides additional examples of BECs including woven BECs with variable weave patterns, densities, attachment mechanisms, and materials (including copper and tungsten) that may be attached to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks in order to promote more efficient heat transfer and immersion cooling vapor nucleation, particularly in paragraphs

[0031] -

[0055] and FIGS. 3-7. The entirety of U.S. Provisional Patent Application No. 63 / 603,242 is incorporated herein by reference.Exemplary Claim Clauses

[0235] Clause 1. A system-on-a-wafer (SoW) comprising: a semiconductor wafer physically divided into a plurality of pieces; a plurality of chips mounted on each piece of the plurality of pieces; a plurality of chip connectors, wherein each chip connector is mounted on a respective piece; a plurality of piece wiring layers, wherein each piece wiring layer electrically couples the plurality of chips on the respective piece to a respective chip connector on the respective piece; and at least one intra-SoW electrical connector; wherein the at least one intra-SoW electrical connector is attached to a neighboring pair of pieces and electrically connects the chip connectors on the neighboring pair of pieces.

[0236] Clause 2. The SoW of clause 1, wherein: the at least one intra-SoW electrical connector comprises a substrate and a plurality of electrical wires disposed on the substrate; and the plurality of electrical wires electrically connects the chip connectors on the neighboring pair of pieces.

[0237] Clause 3. The SoW of clause 1 or 2, wherein: a respective inter-SoW electrical connector is disposed on and electrically connected to each intra-SoW electrical connector; and the respective inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a cable.

[0238] Clause 4. The SoW of clause 2, wherein: the semiconductor wafer is physically divided into first and second pieces; a first intra-SoW electrical connector is attached to the first and second pieces; and the plurality of electrical wires are electrically connected to a first chip connector on the first piece and a first chip connector on a second piece.

[0239] Clause 5. The SoW of clause 4, wherein the first and second pieces are first and second sectors of the semiconductor wafer.

[0240] Clause 6. The SoW of clause 5, wherein the first and second sectors are first and second halves of the semiconductor wafer.

[0241] Clause 7. The SoW of clause 4, wherein: the semiconductor wafer is physically divided into first, second, third, and fourth pieces; a second intra-SoW electrical connector is attached to the second and third pieces, wherein the plurality of electrical wires in the second intra-SoWelectrical connector is electrically connected to a second chip connector on the second piece and a first chip connector on the third piece; a third intra-SoW electrical connector is attached to the third and fourth pieces, wherein the plurality of electrical wires in the third intra-SoW electrical connector is electrically connected to a second chip connector on the third piece and a first chip connector on the fourth piece; and a fourth intra-SoW electrical connector is attached to the first and fourth pieces, wherein the plurality of electrical wires in the fourth intra-SoW electrical connector is electrically connected to a second chip connector on the first piece and a second chip connector on the fourth piece.

[0242] Clause 8. The SoW of clause 7, wherein the first, second, third, and fourth pieces are first, second, third, and fourth sectors of the semiconductor wafer.

[0243] Clause 9. The SoW of clause 8, wherein the first, second, third, and fourth sectors are first, second, third, and fourth quarters of the semiconductor wafer.

[0244] Clause 10. The SoW of any of clauses 7-9, further comprising: a first inter-SoW electrical connector disposed on and electrically connected to the first intra-SoW electrical connector, wherein the first inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a first electrical cable; a second inter-SoW electrical connector disposed on and electrically connected to the second intra-SoW electrical connector, wherein the second inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a second electrical cable; a third inter-SoW electrical connector disposed on and electrically connected to the third intra-SoW electrical connector, wherein the third inter- SoW electrical connector comprises connection terminals configured to engage respective terminals of a third electrical cable; and a fourth inter-SoW electrical connector disposed on and electrically connected to the fourth intra-SoW electrical connector, wherein the fourth inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a fourth electrical cable.|00245| Clause 11. The SoW of any of clauses 7-10, wherein the first intra-SoW electrical connector, the second intra-SoW electrical connector, the third intra-SoW electrical connector, and the fourth intra-SoW electrical connector are attached to one another.

[0246] Clause 12. A system-on-a-wafer (SoW) comprising: a semiconductor wafer physically divided into a plurality of pieces; a plurality of chips mounted on each piece; a plurality of electrical switch over optics (ESOO) devices, wherein each ESOO device is mounted on a respective piece and comprises an electrical switch electrically connected to an optical engine; a plurality of piece wiring layers, wherein each piece wiring layer electrically couples the plurality of chips on the respective piece to a respective electrical switch in a respective ESOO device on the respective piece; and at least one intra-SoW optical connector, wherein each intra-SoW optical connector is attached to a neighboring pair of pieces and optically connects respective optical engines in the ESOO devices on the neighboring pair of pieces.

[0247] Clause 13. The SoW of clause 12, wherein each intra-SoW electrical connector comprises a plurality of optical fibers that optically connect the respective optical engines in the ESOO devices on the neighboring pair of pieces.

[0248] Clause 14. The SoW of clause 12 or 13, wherein: a respective inter-SoW optical connector is disposed on and optically connected to each intra-SoW optical connector; and the respective inter-SoW optical connector comprises connection terminals configured to engage respective terminals of an optical cable.

[0249] Clause 15. The SoW of clause 13, wherein: the semiconductor wafer is physically divided into first and second pieces; a first intra-SoW optical connector is attached to the first and second pieces; and the plurality of optical fibers is optically connected to a first optical engine in a first ESOO device on the first piece and to a first optical engine in a first ESOO device on the second piece.

[0250] Clause 16. The SoW of clause 15, wherein the first and second pieces are first and second sectors of the semiconductor wafer.|002511 Clause 17. The SoW of clause 16, wherein the first and second sectors are first and second halves of the semiconductor wafer.

[0252] Clause 18. The SoW of clause 15, wherein: the semiconductor wafer is physically divided into first, second, third, and fourth pieces; a second intra-SoW optical connector is attached to the second and third pieces; the plurality of optical fibers in the second intra-SoW optical connector is optically connected to a second optical engine in a second ESOO device on the second piece and to a first optical engine in a first ESOO device on the third piece; a third intra-SoW optical connector is attached to the third and fourth pieces; the plurality of optical fibers in the third intra- SoW optical connector is optically connected to a second optical engine in a second ESOO device on the third piece and to a first optical engine in a first ESOO device on the fourth piece; a fourth intra-SoW optical connector is attached to the first and fourth pieces; and the plurality of optical fibers in the fourth intra-SoW optical connector is optically connected to a second optical engine in a second ESOO device on the first piece and to a second optical engine in a second ESOO device on the fourth piece.

[0253] Clause 19. The SoW of clause 18, wherein the first, second, third, and fourth pieces are first, second, third, and fourth sectors of the semiconductor wafer.

[0254] Clause 20. The SoW of clause 19, wherein the first, second, third, and fourth sectors are first, second, third, and fourth quarters of the semiconductor wafer.

[0255] Clause 21. The SoW of any of clauses 18-20, further comprising: a first inter-SoW optical connector disposed on and optically connected to the first intra-SoW optical connector, wherein the first inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a first optical cable; a second inter-SoW optical connector disposed on and optically connected to the second intra-SoW optical connector, wherein the second inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a second optical cable; a third inter-SoW optical connector disposed on and optically connected to the third intra-SoW optical connector, wherein the third inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a third optical cable; and a fourth third inter-SoW optical connector disposed on and optically connected to the fourth intra-SoW optical connector, wherein the fourth inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a fourth optical cable.

[0256] Clause 22. The SoW of any of clauses 18-21 , wherein the first intra-SoW optical connector, the second intra-SoW optical connector, the third intra-SoW optical connector, and the fourth intra-SoW optical connector are attached to one another.

[0257] Clause 23. A server comprising: a first system -on-a- wafer (SoW) comprising: a first semiconductor wafer physically divided into a plurality of first pieces; a plurality of first chips mounted on each first piece; a plurality of first chip connectors, wherein each first chip connector is mounted on a respective first piece; a plurality of first piece wiring layers, wherein each first piece wiring layer electrically couples the plurality of first chips on the respective first piece to a respective first chip connector on the respective first piece; at least one first intra-SoW electrical connector, wherein each first intra-SoW electrical connector is attached to a neighboring pair of first pieces and electrically connects the first chip connectors on the neighboring pair of first pieces; and at least one first inter-SoW electrical connector, wherein each first inter-SoW electrical connector is disposed on and electrically connected to a respective first intra-SoW electrical connector; a second SoW comprising: a second semiconductor wafer physically divided into a plurality of second pieces; a plurality of second chips mounted on each second piece; a plurality of second chip connectors, wherein each second chip connector is mounted on a respective second piece; a plurality of second piece wiring layers, wherein each second piece wiring layer electrically couples the plurality of second chips on the respective second piece to a respective second chip connector on the respective second piece; at least one second intra-SoW electrical connector, wherein each second intra-SoW electrical connector is attached to a neighboring pair of second pieces and electrically connects the second chip connectors on the neighboring pair of second pieces; and at least one second inter-SoW electrical connector, wherein each second inter-SoW electrical connector is disposed on and electrically connected to a respective second intra-SoW electrical connector; and at least one electrical cable, wherein the at least one electrical cable electrically connects a respective first inter-SoW electrical connector and a respective second inter- SoW electrical connector.

[0258] Clause 24. A server comprising: a first system-on-a-wafer (SoW) comprising: a first semiconductor wafer physically divided into a plurality of first pieces; a plurality of first chips mounted on each first piece; a plurality of first electrical switch over optics (ESOO) devices, wherein each first ESOO device is mounted on a respective first piece and comprises a first electrical switch electrically connected to a first optical engine; a plurality of first piece wiring layers, wherein each first piece wiring layer electrically couples the plurality of first chips on the respective first piece to a respective first electrical switch in a respective first ESOO device on the respective first piece; at least one first intra-SoW optical connector, wherein the at least one first intra-SoW optical connector is attached to a neighboring pair of first pieces and optically connects respective first optical engines in the first ESOO devices on the neighboring pair of first pieces; and at least one first inter-SoW optical connector, wherein each first inter-SoW optical connector is disposed on and optically connected to a respective first intra-SoW optical connector; a second SoW comprising: a second semiconductor wafer physically divided into a plurality of secondpieces; a plurality of second chips mounted on each second piece; a plurality of second ESOO devices, wherein each second ESOO device is mounted on a respective second piece and comprises a second electrical switch electrically connected to a second optical engine; a plurality of second piece wiring layers, wherein each second piece wiring layer electrically couples the plurality of second chips on the respective second piece to a respective second electrical switch in a respective second ESOO device on the respective second piece; at least one second intra-SoW optical connector, wherein the at least one second intra-SoW optical connector is attached to a neighboring pair of second pieces and optically connects respective second optical engines in the second ESOO devices on the neighboring pair of second pieces; and at least one second inter-SoW optical connector, where the at least one second inter-SoW optical connector disposed on and optically connected to a respective second intra-SoW optical connector; and at least one optical cable, wherein the at least one optical cable optically connects a respective first inter-SoW optical connector and a respective second inter-SoW optical connector of the second SoW.

[0259] Clause 25. A method for dynamically configuring a computing system, the method comprising: operating a first plurality of integrated circuits (ICs) to perform at least a first computing task; determining that a first IC of the first plurality is not functioning properly; selecting a second IC from a second plurality of ICs; and operating the second IC to perform at least a second computing task that would have been assigned to the first IC if the first IC had been functioning properly; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; and the first plurality is distinct from the second plurality.

[0260] Clause 26. The method of clause 25, further comprising operating, in an immersion cooling liquid, at least one IC of the first plurality of ICs or of the second plurality of ICs.

[0261] Clause 27. The method of clause 25, wherein: each IC of the first plurality and of the second plurality is disposed at about a first distance from at least one other IC of the first plurality or of the second plurality; and at least one IC of the first plurality is disposed between any two ICs of the second plurality.

[0262] Clause 28. The method of clause 25, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

[0263] Clause 29. The method of clause 25, wherein each IC of the first plurality and of the second plurality is communicatively coupled with at least one respective memory module.

[0264] Clause 30. The method of clause 29, wherein each memory module of the at least one memory module is communicatively coupled with a respective IC of the first plurality and of the second plurality.

[0265] Clause 31. The method of clause 25, wherein the second plurality of ICs is communicatively coupled with a repair module.|00266| Clause 32. The method of clause 25, wherein the second computing tasks are assigned by a control module.

[0267] Clause 33. The method of clause 25, wherein the first plurality and the second plurality are operated at least in part by a control module.

[0268] Clause 34. The method of clause 25, wherein the first plurality is distinct from the second plurality based on a software classification of the first plurality compared to a software classification of the second plurality.

[0269] Clause 35. The method of clause 25, wherein the first plurality is distinct from the second plurality based on a type of IC of the first plurality compared to a type of IC of the second plurality.

[0270] Clause 36. The method of clause 25, wherein the first plurality is distinct from the second plurality based on a physical design of the first plurality compared to a physical design of the second plurality.

[0271] Clause 37. A method for dynamically configuring a computing system, the method comprising: configuring a first plurality of integrated circuits (ICs) to perform one or more computing tasks; determining that a first IC of the first plurality is not functioning properly; selecting a second IC from a second plurality of ICs; and performing the one or more computing tasks with the second IC and a subgroup of the first plurality; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; the first plurality is distinct from the second plurality; and the subgroup comprises all ICs of the first plurality except for the first IC.

[0272] Clause 38. The method of clause 37, further comprising operating, in an immersion cooling liquid, at least one IC of the first plurality or of the second plurality.

[0273] Clause 39. The method of clause 38, further comprising operating at least one IC of the first plurality in an immersion cooling liquid at a power that would damage the at least one IC if the at least one IC were operated in air at the power.

[0274] Clause 40. The method of clause 37, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality.

[0275] Clause 41. The method of clause 40, wherein at least one IC of the first plurality is disposed between any two ICs of the second plurality.

[0276] Clause 42. The method of clause 37, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

[0277] Clause 43. The method of clause 37, wherein each IC of the first plurality and of the second plurality is communicatively coupled with at least one respective memory module.

[0278] Clause 44. The method of clause 43, wherein each memory module of the at least one memory module is communicatively coupled to a respective IC of the first or second plurality.

[0279] Clause 45. The method of clause 37, wherein the first plurality and the second plurality are communicatively coupled with a repair module.

[0280] Clause 46. The method of clause 37, wherein the one or more computing tasks are assigned by a control module.

[0281] Clause 47. The method of clause 37, wherein the first plurality and the second plurality are operated at least in part by a control module.

[0282] Clause 48. The method of clause 37, wherein the first plurality is distinct from the second plurality based on a software classification of the first plurality compared to a software classification of the second plurality.

[0283] Clause 49. The method of clause 37, wherein the first plurality is distinct from the second plurality based on a type of IC of the first plurality compared to a type of IC of the second plurality.

[0284] Clause 50. The method of clause 37, wherein the first plurality is distinct from the second plurality based on a physical design of the first plurality compared to a physical design of the second plurality.

[0285] Clause 51. A method for dynamically configuring a computing system, the method comprising: configuring a first plurality of integrated circuits (ICs) to perform one or more computing tasks, the first plurality comprising a first IC; selecting a second IC from a second plurality of ICs; and performing the one or more computing tasks with the second IC and a subgroup of the first plurality; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; the first plurality is distinct from the second plurality; and the subgroup comprises each IC of the first plurality except for the first IC.

[0286] Clause 52. The method of clause 51, further comprising operating, in an immersion cooling liquid, at least one IC of the first plurality or of second plurality.

[0287] Clause 53. The method of clause 52, further comprising operating at least one IC of the first plurality in an immersion cooling liquid at a power that would damage the at least one IC of the first plurality if the at least one IC were operated in air at the power.

[0288] Clause 54. The method of clause 51, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality.

[0289] Clause 55. The method of clause 54, wherein at least one IC of the first plurality is disposed between any two ICs of the second plurality.

[0290] Clause 56. The method of clause 51, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

[0291] Clause 57. The method of clause 51, wherein each IC of the first plurality and of the second plurality is communicatively coupled with at least one respective memory module.

[0292] Clause 58. The method of clause 51, wherein the first plurality and the second plurality are communicatively coupled with a repair module.

[0293] Clause 59. The method of clause 51, wherein the one or more computing tasks are assigned by a control module.

[0294] Clause 60. The method of clause 51 , wherein the first plurality and the second plurality are operated at least in part by a control module.

[0295] Clause 61. The method of clause 51 , wherein the first plurality is distinct from the second plurality based on a software classification of the first plurality compared to a software classification of the second plurality.

[0296] Clause 62. The method of clause 51, wherein the first plurality is distinct from the second plurality based on a type of IC of the first plurality compared to a type of IC of the second plurality.

[0297] Clause 63. The method of clause 51 , wherein the first plurality is distinct from the second plurality based on a physical design of the first plurality compared to a physical design of the second plurality.

[0298] Clause 64. A system for dynamically configurable computation, the system comprising: a semiconductor wafer; a first plurality of integrated circuits (ICs) mounted on the semiconductor wafer; a second plurality of ICs mounted on the semiconductor wafer; and a control module mounted on the semiconductor wafer; wherein: the control module is communicatively coupled with the first plurality and the second plurality; the control module is configured to assign one or more computing tasks to the first plurality and the second plurality; and the control module is configured to select a second IC of the second plurality to replace an operation of a first IC of the first plurality.

[0299] Clause 65. The system of clause 64, wherein the control module is further configured to select the second IC of the second plurality to replace the operation of the first IC of the first plurality in response to determining that the first IC is malfunctioning.

[0300] Clause 66. The system of clause 64, further comprising a plurality of memory modules, wherein: each memory module of the plurality of memory modules is communicatively coupled to an IC of the first plurality or of the second plurality.

[0301] Clause 67. The system of clause 64, further comprising a plurality of memory modules, wherein: each IC of the first plurality and of the second plurality is communicatively coupled with at least one memory module.

[0302] Clause 68. The system of clause 64, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and at least one IC of the first plurality is disposed between any two ICs of the second plurality.

[0303] Clause 69. The system of clause 64, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

[0304] Clause 70. The system of clause 64, further comprising a repair module, wherein: the repair module is configured to: determine a cause of a malfunction of the first IC; assign the one or more computing tasks to the first plurality and to the second plurality; and configure a firmware of the first plurality and of the second plurality.

[0305] Clause 71. A mechanical support comprising: a first frame having a first body that defines a first open center, wherein: the first open center is configured to receive a system-on-a-wafer (SoW) and at least one first thermal exchange module in direct physical contact with the SoW; and the first body defines a plurality of first holes extending through first opposing sides of the first frame; a second frame having a second body that defines a second open center, wherein: the second open center is aligned with respect to the first open center; the second open center is configured to receive a power distribution board and at least one second thermal exchange module in direct physical contact with the power distribution board; the second body defines a plurality of second holes extending through second opposing sides of the second frame; and each second hole is aligned with a respective first hole; and a plurality of bolts, wherein: each bolt extends through the respective first hole and a respective second hole; and the plurality of bolts align the first frame with respect to the second frame.

[0306] Clause 72. The mechanical support of clause 71, wherein the first frame and / or the second frame is / are configured to slidingly engage the plurality of bolts to adjust a relative distance between the first frame with respect to the second frame.

[0307] Clause 73. The mechanical support of clause 72, wherein: the mechanical support is configured to transition between a closed state and an open state; and the relative distance is smaller in the closed state than in the open state.

[0308] Clause 74. The mechanical support of clause 73, wherein, when the mechanical support is in the closed state, the first frame is in direct physical contact with the second frame.

[0309] Clause 75. The mechanical support of any of clauses 71-74, wherein: the plurality of first opposing sides are a first top side and a first bottom side; the plurality of second opposing sides are a second top side and a second bottom side; the first bottom side faces the second top side; the first body includes a first inner flange at the first top side; the first inner flange extends inwardly toward the first open center; the second body includes a second inner flange at the second bottom side; and the second inner flange extends inwardly toward the second open center.

[0310] Clause 76. The mechanical support of clause 75, wherein: the first inner flange is configured to mechanically engage a first boiling enhancement coating (BEC); and the second inner flange is configured to mechanically engage the first BEC.|003111 Clause 77. The mechanical support of any of clauses 71-75, wherein: the at least one first thermal exchange module includes a first boiler plate; and the at least one second thermal exchange module includes a second boiler plate.

[0312] Clause 78. The mechanical support of any of clauses 71-77, wherein: the second body has a plurality of slots that are configured to receive respective cables that extend from the SoW; and each slot extends from an inner side to an outer side of the second body.

[0313] Clause 79. An assembly comprising: a mechanical support comprising: a first frame having a first body that defines a first open center, wherein the first body defines a plurality of first holes extending through first opposing sides of the first frame; a second frame having a second body that defines a second open center, wherein: the second open center is aligned with respect to the first open center; the second body defines a plurality of second holes extending through second opposing sides of the second frame; and each second hole is aligned with a respective first hole; a plurality of bolts, wherein: each bolt extends through a respective first hole and a respective second hole; and the plurality of bolts align the first frame with respect to the second frame; a system-on- a-chip (SoW) disposed in the first open center; at least one first thermal exchange module disposed in the first open center, wherein the at least one first thermal exchange module is in direct physical contact with the SoW; a power distribution board disposed in the second open center; and at least one second thermal exchange module disposed in the second open center, wherein the at least one second thermal exchange module is disposed in direct physical contact with the power distribution board.

[0314] Clause 80. The assembly of clause 79, wherein the at least one first thermal exchange module includes a first thermal interface material, a first boiler plate, and a first boiling enhancement coating.

[0315] Clause 81. The assembly of clause 80, wherein: the first thermal interface material is disposed on the SoW, and the first boiler plate is between the first thermal interface material and the first boiling enhancement coating.

[0316] Clause 82. The assembly of any of clauses 79-81, wherein the at least one second thermal exchange module includes a second thermal interface material, a second boiler plate, and a second boiling enhancement coating.

[0317] Clause 83. The assembly of clause 82, wherein: the second thermal interface material is disposed on the power distribution board; and the second boiler plate is between the second thermal interface material and the second boiling enhancement coating.

[0318] Clause 84. The assembly of any of clauses 79-83, further comprising: a first plurality of screws extend through the SoW and the at least one first thermal exchange module; and a second plurality of screws extend through the power distribution board and the at least one second thermal exchange module.

[0319] Clause 85. The assembly of any of clauses 79-84, wherein the SoW is mounted on a subframe.

[0320] Clause 86. The assembly of any of clauses 79-85, wherein: the SoW includes a plurality of chip connectors; the assembly further comprises a plurality of cables, wherein each cable is connected to a respective chip connector; and the second body includes a plurality of slots, wherein: each slot extends from an inner side to an outer side of the second body; and each cable passes through a respective slot.|00321| Clause 87. The assembly of clause 79, wherein: the at least one first thermal exchange module includes a first thermal interface material, a first boiler plate, and a first boilingenhancement coating; the at least one second thermal exchange module includes a second thermal interface material, a second boiler plate, and a second boiling enhancement coating; the first opposing sides are a first top side and a first bottom side; the second opposing sides are a second top side and a second bottom side; the first bottom side faces the second top side; the first body includes a first inner flange at the first top side; the first inner flange extends inwardly toward the first open center to mechanically engage the first boiling enhancement coating; the second body includes a second inner flange at the second bottom side; and the second inner flange extends inwardly toward the second open center to mechanically engage the second boiling enhancement coating.

[0322] Clause 88. An immersion cooling system comprising the at least one first thermal exchange module and the at least one second thermal exchange module of any of clauses 79-87.Conclusion

[0323] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.|00324| Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0325] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0326] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0327] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0328] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0329] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0330] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A system-on-a-wafer (SoW) comprising: a semiconductor wafer physically divided into a plurality of pieces; a plurality of chips mounted on each piece of the plurality of pieces; a plurality of chip connectors, wherein each chip connector is mounted on a respective piece; a plurality of piece wiring layers, wherein each piece wiring layer electrically couples the plurality of chips on the respective piece to a respective chip connector on the respective piece; and at least one intra-SoW electrical connector; wherein the at least one intra-SoW electrical connector is attached to a neighboring pair of pieces and electrically connects the chip connectors on the neighboring pair of pieces.

2. The SoW of claim 1, wherein: the at least one intra-SoW electrical connector comprises a substrate and a plurality of electrical wires disposed on the substrate; and the plurality of electrical wires electrically connects the chip connectors on the neighboring pair of pieces.

3. The SoW of claim 1 or 2, wherein: a respective inter-SoW electrical connector is disposed on and electrically connected to each intra-SoW electrical connector; and the respective inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a cable.

4. The SoW of claim 2, wherein: the semiconductor wafer is physically divided into first and second pieces; a first intra-SoW electrical connector is attached to the first and second pieces; and the plurality of electrical wires are electrically connected to a first chip connector on the first piece and a first chip connector on a second piece.

5. The SoW of claim 4, wherein the first and second pieces are first and second sectors of the semiconductor wafer.

6. The SoW of claim 5, wherein the first and second sectors are first and second halves of the semiconductor wafer.

7. The SoW of claim 4, wherein: the semiconductor wafer is physically divided into first, second, third, and fourth pieces; a second intra-SoW electrical connector is attached to the second and third pieces, wherein the plurality of electrical wires in the second intra-SoW electrical connector iselectrically connected to a second chip connector on the second piece and a first chip connector on the third piece; a third intra-SoW electrical connector is attached to the third and fourth pieces, wherein the plurality of electrical wires in the third intra-SoW electrical connector is electrically connected to a second chip connector on the third piece and a first chip connector on the fourth piece; and a fourth intra-SoW electrical connector is attached to the first and fourth pieces, wherein the plurality of electrical wires in the fourth intra-SoW electrical connector is electrically connected to a second chip connector on the first piece and a second chip connector on the fourth piece.

8. The SoW of claim 7, wherein the first, second, third, and fourth pieces are first, second, third, and fourth sectors of the semiconductor wafer.

9. The SoW of claim 8, wherein the first, second, third, and fourth sectors are first, second, third, and fourth quarters of the semiconductor wafer.

10. The SoW of any of claims 7-9, further comprising: a first inter-SoW electrical connector disposed on and electrically connected to the first intra-SoW electrical connector, wherein the first inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a first electrical cable; a second inter-SoW electrical connector disposed on and electrically connected to the second intra-SoW electrical connector, wherein the second inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a second electrical cable; a third inter-SoW electrical connector disposed on and electrically connected to the third intra-SoW electrical connector, wherein the third inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a third electrical cable; and a fourth inter-SoW electrical connector disposed on and electrically connected to the fourth intra-SoW electrical connector, wherein the fourth inter-SoW electrical connector comprises connection terminals configured to engage respective terminals of a fourth electrical cable.

11. The SoW of any of claims 7-10, wherein the first intra-SoW electrical connector, the second intra-SoW electrical connector, the third intra-SoW electrical connector, and the fourth intra-SoW electrical connector are attached to one another.

12. A system-on-a-wafer (SoW) comprising: a semiconductor wafer physically divided into a plurality of pieces; a plurality of chips mounted on each piece; a plurality of electrical switch over optics (ESOO) devices, wherein each ESOO device is mounted on a respective piece and comprises an electrical switch electrically connected to an optical engine;a plurality of piece wiring layers, wherein each piece wiring layer electrically couples the plurality of chips on the respective piece to a respective electrical switch in a respective ESOO device on the respective piece; and at least one intra-SoW optical connector, wherein each intra-SoW optical connector is attached to a neighboring pair of pieces and optically connects respective optical engines in the ESOO devices on the neighboring pair of pieces.

13. The SoW of claim 12, wherein each intra-SoW electrical connector comprises a plurality of optical fibers that optically connect the respective optical engines in the ESOO devices on the neighboring pair of pieces.

14. The SoW of claim 12 or 13, wherein: a respective inter-SoW optical connector is disposed on and optically connected to each intra-SoW optical connector; and the respective inter-SoW optical connector comprises connection terminals configured to engage respective terminals of an optical cable.

15. The SoW of claim 13, wherein: the semiconductor wafer is physically divided into first and second pieces; a first intra-SoW optical connector is attached to the first and second pieces; and the plurality of optical fibers is optically connected to a first optical engine in a first ESOO device on the first piece and to a first optical engine in a first ESOO device on the second piece.

16. The SoW of claim 15, wherein the first and second pieces are first and second sectors of the semiconductor wafer.

17. The SoW of claim 16, wherein the first and second sectors are first and second halves of the semiconductor wafer.

18. The SoW of claim 15, wherein: the semiconductor wafer is physically divided into first, second, third, and fourth pieces; a second intra-SoW optical connector is attached to the second and third pieces; the plurality of optical fibers in the second intra-SoW optical connector is optically connected to a second optical engine in a second ESOO device on the second piece and to a first optical engine in a first ESOO device on the third piece; a third intra-SoW optical connector is attached to the third and fourth pieces; the plurality of optical fibers in the third intra-SoW optical connector is optically connected to a second optical engine in a second ESOO device on the third piece and to a first optical engine in a first ESOO device on the fourth piece; a fourth intra-SoW optical connector is attached to the first and fourth pieces; and the plurality of optical fibers in the fourth intra-SoW optical connector is optically connected to a second optical engine in a second ESOO device on the first piece and to a secondoptical engine in a second ESOO device on the fourth piece.

19. The SoW of claim 18, wherein the first, second, third, and fourth pieces are first, second, third, and fourth sectors of the semiconductor wafer.

20. The SoW of claim 19, wherein the first, second, third, and fourth sectors are first, second, third, and fourth quarters of the semiconductor wafer.

21. The SoW of any of claims 18-20, further comprising: a first inter-SoW optical connector disposed on and optically connected to the first intra- SoW optical connector, wherein the first inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a first optical cable; a second inter-SoW optical connector disposed on and optically connected to the second intra-SoW optical connector, wherein the second inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a second optical cable; a third inter-SoW optical connector disposed on and optically connected to the third intra- SoW optical connector, wherein the third inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a third optical cable; and a fourth third inter-SoW optical connector disposed on and optically connected to the fourth intra-SoW optical connector, wherein the fourth inter-SoW optical connector comprises connection terminals configured to engage respective terminals of a fourth optical cable.

22. The SoW of any of claims 18-21, wherein the first intra-SoW optical connector, the second intra-SoW optical connector, the third intra-SoW optical connector, and the fourth intra-SoW optical connector are attached to one another.

23. A server comprising: a first system-on-a-wafer (SoW) comprising: a first semiconductor wafer physically divided into a plurality of first pieces; a plurality of first chips mounted on each first piece; a plurality of first chip connectors, wherein each first chip connector is mounted on a respective first piece; a plurality of first piece wiring layers, wherein each first piece wiring layer electrically couples the plurality of first chips on the respective first piece to a respective first chip connector on the respective first piece; at least one first intra-SoW electrical connector, wherein each first intra-SoW electrical connector is attached to a neighboring pair of first pieces and electrically connects the first chip connectors on the neighboring pair of first pieces; and at least one first inter-SoW electrical connector, wherein each first inter-SoW electrical connector is disposed on and electrically connected to a respective first intra- SoW electrical connector; a second SoW comprising:a second semiconductor wafer physically divided into a plurality of second pieces; a plurality of second chips mounted on each second piece; a plurality of second chip connectors, wherein each second chip connector is mounted on a respective second piece; a plurality of second piece wiring layers, wherein each second piece wiring layer electrically couples the plurality of second chips on the respective second piece to a respective second chip connector on the respective second piece; at least one second intra-SoW electrical connector, wherein each second intra-SoW electrical connector is attached to a neighboring pair of second pieces and electrically connects the second chip connectors on the neighboring pair of second pieces; and at least one second inter-SoW electrical connector, wherein each second inter-SoW electrical connector is disposed on and electrically connected to a respective second intra-SoW electrical connector; and at least one electrical cable, wherein the at least one electrical cable electrically connects a respective first inter-SoW electrical connector and a respective second inter-SoW electrical connector.

24. A server comprising: a first system-on-a-wafer (SoW) comprising: a first semiconductor wafer physically divided into a plurality of first pieces; a plurality of first chips mounted on each first piece; a plurality of first electrical switch over optics (ESOO) devices, wherein each first ESOO device is mounted on a respective first piece and comprises a first electrical switch electrically connected to a first optical engine; a plurality of first piece wiring layers, wherein each first piece wiring layer electrically couples the plurality of first chips on the respective first piece to a respective first electrical switch in a respective first ESOO device on the respective first piece; at least one first intra-SoW optical connector, wherein the at least one first intra- SoW optical connector is attached to a neighboring pair of first pieces and optically connects respective first optical engines in the first ESOO devices on the neighboring pair of first pieces; and at least one first inter-SoW optical connector, wherein each first inter-SoW optical connector is disposed on and optically connected to a respective first intra-SoW optical connector; a second SoW comprising: a second semiconductor wafer physically divided into a plurality of second pieces; a plurality of second chips mounted on each second piece; a plurality of second ESOO devices, wherein each second ESOO device is mounted on a respective second piece and comprises a second electrical switch electrically connected to a second optical engine; a plurality of second piece wiring layers, wherein each second piece wiring layerelectrically couples the plurality of second chips on the respective second piece to a respective second electrical switch in a respective second ESOO device on the respective second piece; at least one second intra-SoW optical connector, wherein the at least one second intra-SoW optical connector is attached to a neighboring pair of second pieces and optically connects respective second optical engines in the second ESOO devices on the neighboring pair of second pieces; and at least one second inter-SoW optical connector, where the at least one second inter- SoW optical connector disposed on and optically connected to a respective second intra-SoW optical connector; and at least one optical cable, wherein the at least one optical cable optically connects a respective first inter-SoW optical connector and a respective second inter-SoW optical connector of the second SoW.

25. A method for dynamically configuring a computing system, the method comprising: operating a first plurality of integrated circuits (ICs) to perform at least a first computing task; determining that a first IC of the first plurality is not functioning properly; selecting a second IC from a second plurality of ICs; and operating the second IC to perform at least a second computing task that would have been assigned to the first IC if the first IC had been functioning properly; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; and the first plurality is distinct from the second plurality.

26. The method of claim 25, further comprising operating, in an immersion cooling liquid, at least one IC of the first plurality of ICs or of the second plurality of ICs.

27. The method of claim 25, wherein: each IC of the first plurality and of the second plurality is disposed at about a first distance from at least one other IC of the first plurality or of the second plurality; and at least one IC of the first plurality is disposed between any two ICs of the second plurality.

28. The method of claim 25, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

29. The method of claim 25, wherein each IC of the first plurality and of the second plurality is communicatively coupled with at least one respective memory module.

30. The method of claim 29, wherein each memory module of the at least one memory module is communicatively coupled with a respective IC of the first plurality and of the second plurality.

31. The method of claim 25, wherein the second plurality of ICs is communicatively coupled with a repair module.

32. The method of claim 25, wherein the second computing tasks are assigned by a control module.

33. The method of claim 25, wherein the first plurality and the second plurality are operated at least in part by a control module.

34. The method of claim 25, wherein the first plurality is distinct from the second plurality based on a software classification of the first plurality compared to a software classification of the second plurality.

35. The method of claim 25, wherein the first plurality is distinct from the second plurality based on a type of IC of the first plurality compared to a type of IC of the second plurality.

36. The method of claim 25, wherein the first plurality is distinct from the second plurality based on a physical design of the first plurality compared to a physical design of the second plurality.

37. A method for dynamically configuring a computing system, the method comprising: configuring a first plurality of integrated circuits (ICs) to perform one or more computing tasks; determining that a first IC of the first plurality is not functioning properly; selecting a second IC from a second plurality of ICs; and performing the one or more computing tasks with the second IC and a subgroup of the first plurality; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; the first plurality is distinct from the second plurality; and the subgroup comprises all ICs of the first plurality except for the first IC.

38. The method of claim 37, further comprising operating, in an immersion cooling liquid, at least one IC of the first plurality or of the second plurality.

39. The method of claim 38, further comprising operating at least one IC of the first plurality in an immersion cooling liquid at a power that would damage the at least one IC if the at least one IC were operated in air at the power.

40. The method of claim 37, wherein:each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality.

41. The method of claim 40, wherein at least one IC of the first plurality is disposed between any two ICs of the second plurality.

42. The method of claim 37, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

43. The method of claim 37, wherein each IC of the first plurality and of the second plurality is communicatively coupled with at least one respective memory module.

44. The method of claim 43, wherein each memory module of the at least one memory module is communicatively coupled to a respective IC of the first or second plurality.

45. The method of claim 37, wherein the first plurality and the second plurality are communicatively coupled with a repair module.

46. The method of claim 37, wherein the one or more computing tasks are assigned by a control module.

47. The method of claim 37, wherein the first plurality and the second plurality are operated at least in part by a control module.

48. The method of claim 37, wherein the first plurality is distinct from the second plurality based on a software classification of the first plurality compared to a software classification of the second plurality.

49. The method of claim 37, wherein the first plurality is distinct from the second plurality based on a type of IC of the first plurality compared to a type of IC of the second plurality.

50. The method of claim 37, wherein the first plurality is distinct from the second plurality based on a physical design of the first plurality compared to a physical design of the second plurality.

51. A method for dynamically configuring a computing system, the method comprising: configuring a first plurality of integrated circuits (ICs) to perform one or more computing tasks, the first plurality comprising a first IC; selecting a second IC from a second plurality of ICs; andperforming the one or more computing tasks with the second IC and a subgroup of the first plurality; wherein: the first plurality and the second plurality are mounted on a semiconductor wafer; the first plurality is distinct from the second plurality; and the subgroup comprises each IC of the first plurality except for the first IC.

52. The method of claim 51, further comprising operating, in an immersion cooling liquid, at least one IC of the first plurality or of second plurality.

53. The method of claim 52, further comprising operating at least one IC of the first plurality in an immersion cooling liquid at a power that would damage the at least one IC of the first plurality if the at least one IC were operated in air at the power.

54. The method of claim 51, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality.

55. The method of claim 54, wherein at least one IC of the first plurality is disposed between any two ICs of the second plurality.

56. The method of claim 51 , wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

57. The method of claim 51, wherein each IC of the first plurality and of the second plurality is communicatively coupled with at least one respective memory module.

58. The method of claim 51, wherein the first plurality and the second plurality are communicatively coupled with a repair module.

59. The method of claim 51, wherein the one or more computing tasks are assigned by a control module.

60. The method of claim 51, wherein the first plurality and the second plurality are operated at least in part by a control module.

61. The method of claim 51 , wherein the first plurality is distinct from the second plurality based on a software classification of the first plurality compared to a software classification of the second plurality.

62. The method of claim 51, wherein the first plurality is distinct from the second plurality based on a type of TC of the first plurality compared to a type of IC of the second plurality.

63. The method of claim 51 , wherein the first plurality is distinct from the second plurality based on a physical design of the first plurality compared to a physical design of the second plurality.

64. A system for dynamically configurable computation, the system comprising: a semiconductor wafer; a first plurality of integrated circuits (ICs) mounted on the semiconductor wafer; a second plurality of ICs mounted on the semiconductor wafer; and a control module mounted on the semiconductor wafer; wherein: the control module is communicatively coupled with the first plurality and the second plurality; the control module is configured to assign one or more computing tasks to the first plurality and the second plurality; and the control module is configured to select a second IC of the second plurality to replace an operation of a first IC of the first plurality.

65. The system of claim 64, wherein the control module is further configured to select the second IC of the second plurality to replace the operation of the first IC of the first plurality in response to determining that the first IC is malfunctioning.

66. The system of claim 64, further comprising a plurality of memory modules, wherein: each memory module of the plurality of memory modules is communicatively coupled to anIC of the first plurality or of the second plurality.

67. The system of claim 64, further comprising a plurality of memory modules, wherein: each IC of the first plurality and of the second plurality is communicatively coupled with at least one memory module.

68. The system of claim 64, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and at least one IC of the first plurality is disposed between any two ICs of the second plurality.

69. The system of claim 64, wherein: each IC of the first plurality and of the second plurality is disposed at a first distance from at least one other IC of the first plurality or of the second plurality; and each IC of the second plurality is disposed adjacent to at least one other IC of the second plurality.

70. The system of claim 64, further comprising a repair module, wherein: the repair module is configured to: determine a cause of a malfunction of the first IC; assign the one or more computing tasks to the first plurality and to the second plurality; and configure a firmware of the first plurality and of the second plurality.

71. A mechanical support comprising: a first frame having a first body that defines a first open center, wherein: the first open center is configured to receive a system-on-a-wafer (SoW) and at least one first thermal exchange module in direct physical contact with the SoW; and the first body defines a plurality of first holes extending through first opposing sides of the first frame; a second frame having a second body that defines a second open center, wherein: the second open center is aligned with respect to the first open center; the second open center is configured to receive a power distribution board and at least one second thermal exchange module in direct physical contact with the power distribution board; the second body defines a plurality of second holes extending through second opposing sides of the second frame; and each second hole is aligned with a respective first hole; and a plurality of bolts, wherein: each bolt extends through the respective first hole and a respective second hole; and the plurality of bolts align the first frame with respect to the second frame.

72. The mechanical support of claim 71, wherein the first frame and / or the second frame is / are configured to slidingly engage the plurality of bolts to adjust a relative distance between the first frame with respect to the second frame.

73. The mechanical support of claim 72, wherein: the mechanical support is configured to transition between a closed state and an open state; and the relative distance is smaller in the closed state than in the open state.

74. The mechanical support of claim 73, wherein, when the mechanical support is in the closed state, the first frame is in direct physical contact with the second frame.

75. The mechanical support of any of claims 71-74, wherein: the plurality of first opposing sides are a first top side and a first bottom side; the plurality of second opposing sides are a second top side and a second bottom side; the first bottom side faces the second top side; the first body includes a first inner flange at the first top side;the first inner flange extends inwardly toward the first open center; the second body includes a second inner flange at the second bottom side; and the second inner flange extends inwardly toward the second open center.

76. The mechanical support of claim 75, wherein: the first inner flange is configured to mechanically engage a first boiling enhancement coating (BEC); and the second inner flange is configured to mechanically engage the first BEC.

77. The mechanical support of any of claims 71-75, wherein: the at least one first thermal exchange module includes a first boiler plate; and the at least one second thermal exchange module includes a second boiler plate.

78. The mechanical support of any of claims 71-77, wherein: the second body has a plurality of slots that are configured to receive respective cables that extend from the SoW; and each slot extends from an inner side to an outer side of the second body.

79. An assembly comprising: a mechanical support comprising: a first frame having a first body that defines a first open center, wherein the first body defines a plurality of first holes extending through first opposing sides of the first frame; a second frame having a second body that defines a second open center, wherein: the second open center is aligned with respect to the first open center; the second body defines a plurality of second holes extending through second opposing sides of the second frame; and each second hole is aligned with a respective first hole; a plurality of bolts, wherein: each bolt extends through a respective first hole and a respective second hole; and the plurality of bolts align the first frame with respect to the second frame; a system-on-a-chip (SoW) disposed in the first open center; at least one first thermal exchange module disposed in the first open center, wherein the at least one first thermal exchange module is in direct physical contact with the SoW; a power distribution board disposed in the second open center; and at least one second thermal exchange module disposed in the second open center, wherein the at least one second thermal exchange module is disposed in direct physical contact with the power distribution board.

80. The assembly of claim 79, wherein the at least one first thermal exchange module includes a first thermal interface material, a first boiler plate, and a first boiling enhancement coating.

81. The assembly of claim 80, wherein:the first thermal interface material is disposed on the SoW, and the first boiler plate is between the first thermal interface material and the first boiling enhancement coating.

82. The assembly of any of claims 79-81, wherein the at least one second thermal exchange module includes a second thermal interface material, a second boiler plate, and a second boiling enhancement coating.

83. The assembly of claim 82, wherein: the second thermal interface material is disposed on the power distribution board; and the second boiler plate is between the second thermal interface material and the second boiling enhancement coating.

84. The assembly of any of claims 79-83, further comprising: a first plurality of screws extend through the SoW and the at least one first thermal exchange module; and a second plurality of screws extend through the power distribution board and the at least one second thermal exchange module.

85. The assembly of any of claims 79-84, wherein the SoW is mounted on a subframe.

86. The assembly of any of claims 79-85, wherein: the SoW includes a plurality of chip connectors; the assembly further comprises a plurality of cables, wherein each cable is connected to a respective chip connector; and the second body includes a plurality of slots, wherein: each slot extends from an inner side to an outer side of the second body; and each cable passes through a respective slot.

87. The assembly of claim 79, wherein: the at least one first thermal exchange module includes a first thermal interface material, a first boiler plate, and a first boiling enhancement coating; the at least one second thermal exchange module includes a second thermal interface material, a second boiler plate, and a second boiling enhancement coating; the first opposing sides are a first top side and a first bottom side; the second opposing sides are a second top side and a second bottom side; the first bottom side faces the second top side; the first body includes a first inner flange at the first top side; the first inner flange extends inwardly toward the first open center to mechanically engage the first boiling enhancement coating; the second body includes a second inner flange at the second bottom side; and the second inner flange extends inwardly toward the second open center to mechanicallyengage the second boiling enhancement coating.

88. An immersion cooling system comprising the at least one first thermal exchange module and the at least one second thermal exchange module of any of claims 79-87.

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