Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel. The array substrate comprises a base substrate and a first transistor arranged on one side of the base substrate; a first opening is formed at the position of a first planarization layer corresponding to the first transistor; a second planarization layer is provided to fill the first opening; the refractive index of the first planarization layer is lower than that of the second planarization layer, so as to form a microlens structure at the position corresponding to the first transistor. Thus, the problems in existing VR displays that the transmittance is low and it is difficult to improve the transmittance are alleviated.

Description

Array substrate and display panel

[0001] This application claims priority to Chinese patent application No. 202410291167.1 filed on March 13, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0003] With the development of display technology, virtual reality (VR) displays, due to their realistic stereoscopic imaging characteristics, are widely used in scientific and technological development, commerce, healthcare, education, virtual campuses, aerospace, and other fields. VR displays are relatively small because both head-mounted displays and glasses-type displays are used close to the user's eyes. Furthermore, VR displays require high resolution (e.g., greater than 1000 PPI) to enhance immersion and realism. Therefore, VR displays have high resolution and small pixel size.

[0004] However, VR displays are limited by their high-resolution structural design, resulting in a lower in-plane aperture ratio than conventional products, and correspondingly lower panel transmittance. Currently, the main approach to meeting high brightness requirements is to increase backlight brightness, but this also increases power consumption. Furthermore, higher backlight brightness can also cause channel leakage current to worsen. Consequently, existing VR displays suffer from low transmittance and are difficult to improve. SUMMARY OF THE INVENTION

[0005] The present application provides an array substrate and a display panel to alleviate the technical problems of low transmittance and difficulty in improving existing VR displays.

[0006] An embodiment of the present application provides an array substrate, comprising:

[0007] substrate;

[0008] a first transistor, disposed on one side of the substrate;

[0009] A first planar layer is provided on a side of the first transistor away from the substrate and has a first opening at a position corresponding to the first transistor;

[0010] an auxiliary electrode, disposed in the first opening and connected to the first transistor;

[0011] a second planar layer, disposed on a side of the auxiliary electrode away from the first planar layer and filling the first opening; and

[0012] a first electrode, disposed on a side of the second planar layer away from the substrate and connected to the auxiliary electrode;

[0013] The refractive index of the first flat layer is smaller than the refractive index of the second flat layer.

[0014] An embodiment of the present application further provides a display panel, which includes an array substrate, wherein the array substrate includes:

[0015] substrate;

[0016] a first transistor, disposed on one side of the substrate;

[0017] A first planar layer is provided on a side of the first transistor away from the substrate and has a first opening at a position corresponding to the first transistor;

[0018] an auxiliary electrode, disposed in the first opening and connected to the first transistor;

[0019] a second planar layer, disposed on a side of the auxiliary electrode away from the first planar layer and filling the first opening; and

[0020] a first electrode, disposed on a side of the second planar layer away from the substrate and connected to the auxiliary electrode;

[0021] The refractive index of the first flat layer is smaller than the refractive index of the second flat layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] FIG1 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present application.

[0024] FIG. 2 is a schematic diagram of the optical path of light passing through the first flat layer and the second flat layer in FIG. 1 .

[0025] FIG3 is a detailed schematic diagram of the first opening in FIG1 .

[0026] FIG4 is a schematic plan view of the first opening in FIG3 .

[0027] FIG5 is a schematic diagram of another cross-sectional structure of an array substrate provided in an embodiment of the present application.

[0028] FIG6 is a schematic diagram of another cross-sectional structure of an array substrate provided in an embodiment of the present application.

[0029] FIG7 is a schematic diagram of another cross-sectional structure of an array substrate provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0030] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0031] In one embodiment, the present application provides an array substrate, comprising:

[0032] substrate;

[0033] a first transistor, disposed on one side of the substrate;

[0034] A first planar layer is provided on a side of the first transistor away from the substrate and has a first opening at a position corresponding to the first transistor;

[0035] an auxiliary electrode, disposed in the first opening and connected to the first transistor;

[0036] a second planar layer, disposed on a side of the auxiliary electrode away from the first planar layer and filling the first opening; and

[0037] a first electrode, disposed on a side of the second planar layer away from the substrate and connected to the auxiliary electrode;

[0038] The refractive index of the first flat layer is smaller than the refractive index of the second flat layer.

[0039] In one embodiment, an upper surface of the second planar layer at a side away from the substrate is flush with an upper surface of the first planar layer at a side away from the substrate.

[0040] In one embodiment, the auxiliary electrode extends from the first opening to the upper surface of the first planar layer on a side away from the substrate, and contacts the first electrode.

[0041] In one embodiment, the refractive index of the first planar layer is in a range of 1.4 to 1.5, and the refractive index of the second planar layer is in a range of 1.6 to 1.8.

[0042] In one embodiment, the first opening includes a first opening and a second opening that are oppositely arranged, the first opening is located on a side of the second opening away from the first transistor, and the opening size of the first opening is larger than the opening size of the second opening.

[0043] In one embodiment, the opening size of the first opening is greater than 2 microns, and the depth of the first opening is greater than 1 micron.

[0044] In one embodiment, the hole wall of the first opening is curved.

[0045] In one embodiment, the first transistor includes an active layer, a source electrode, and a drain electrode. The source electrode and the drain electrode are both connected to the active layer, and one of the source electrode and the drain electrode is further connected to the auxiliary electrode.

[0046] In one embodiment, the drain electrode is connected to the auxiliary electrode, and the drain electrode is a transparent electrode.

[0047] In one embodiment, the material of the active layer includes a metal oxide semiconductor material, the array substrate further includes a second transistor connected to the first transistor, and the material of the active layer of the second transistor includes polysilicon.

[0048] An embodiment of the present application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0049] In the array substrate and display panel provided in the embodiments of the present application, the array substrate includes a substrate and a first transistor arranged on one side of the substrate, a first flat layer arranged on a side of the first transistor away from the substrate, and a first opening arranged at a position corresponding to the first transistor, an auxiliary electrode arranged in the first opening and connected to the first transistor, a second flat layer arranged on a side of the auxiliary electrode away from the first flat layer and filled in the first opening, a first electrode arranged on a side of the second flat layer away from the substrate and connected to the auxiliary electrode, wherein the refractive index of the first flat layer is smaller than the refractive index of the second flat layer; in this way, by providing the first opening in the first flat layer with a low refractive index at the position corresponding to the first transistor and filling the first opening with the second flat layer with a high refractive index, a microlens structure is formed at the position corresponding to the first transistor, and light passing through the microlens structure is converged, which can improve the brightness of the light output and thereby improve the transmittance, thereby alleviating the technical problem of low transmittance and difficulty in improving the transmittance of existing VR displays.

[0050] The array substrate and display panel of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Please refer to Figures 1 to 4. Figure 1 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present application. Figure 2 is a schematic diagram of the optical path of light passing through the first and second planar layers in Figure 1. Figure 3 is a detailed schematic diagram of the first opening in Figure 1. Figure 4 is a planar view of the first opening in Figure 3. Referring to Figure 1, array substrate 100 includes a substrate 10, a first transistor 20, a first planar layer 30, an auxiliary electrode 40, a second planar layer 50, and a first electrode 60 disposed on one side of substrate 10. The first planar layer 30 is disposed on a side of the first transistor 20 away from the substrate 10 and has a first opening 301 disposed at a position corresponding to the first transistor 20. The auxiliary electrode 40 is disposed within the first opening 301 and is connected to the first transistor 20. The second planar layer 50 is disposed on a side of the auxiliary electrode 40 away from the first planar layer 30 and fills the first opening 301. The first electrode 60 is disposed on a side of the second planar layer 50 away from the substrate 10 and is connected to the auxiliary electrode 40. The refractive index of the first planar layer 30 is smaller than the refractive index of the second planar layer 50 .

[0052] In this embodiment, a first opening 301 is provided in the first flat layer 30 with a low refractive index at a position corresponding to the first transistor 20, and a second flat layer 50 with a high refractive index is filled in the first opening 301 to form a microlens structure at a position corresponding to the first transistor 20. Light passing through the microlens structure converges, thereby increasing the brightness of the light output and thereby increasing the transmittance, thereby alleviating the problem of low transmittance and difficulty in improving the transmittance of existing VR displays.

[0053] Specifically, referring to Figure 1, the first transistor 20 is arranged on one side of the substrate 10. Optionally, a buffer layer 11 is further provided between the substrate 10 and the first transistor 20. The buffer layer 11 can prevent unwanted impurities or contaminants (such as moisture, oxygen, etc.) from diffusing from the substrate 10 to the device that may be damaged by these impurities or contaminants, while also providing a flat top surface. The buffer layer 11 can be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide. The substrate 10 can be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it can include a rigid substrate such as a glass substrate, a quartz substrate, or a silicon wafer. When the substrate 10 is a flexible substrate, it can include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film.

[0054] The first transistor 20 includes an active layer 21, a first gate 22, a source 23, and a drain 24. The source 23 and the drain 24 are both connected to the active layer 21, and one of the source 23 and the drain 24 is also connected to the auxiliary electrode 40. This embodiment uses the example of the drain 24 being connected to the auxiliary electrode 40 for illustration.

[0055] The active layer 21 of the first transistor 20 is disposed on a side of the buffer layer 11 away from the substrate 10. The active layer 21 of the first transistor 20 includes a channel region 211 and a source doped region 212 and a drain doped region 213 located on opposite sides of the channel region 211. The first gate 22 is disposed corresponding to the channel region 211, the source 23 is connected to the source doped region 212, and the drain 24 is connected to the drain doped region 213. Optionally, the source doped region 212 and the drain doped region 213 each include a heavily doped region and a lightly doped region, the heavily doped region being located on a side of the lightly doped region away from the channel region 211, and the source 23 and the drain 24 are both connected to the corresponding heavily doped region, so that the source 23 and the drain 24 form good ohmic contacts with the active layer 21. The material of the active layer 21 includes polysilicon (p-Si), such as low temperature polysilicon (LTPS).

[0056] Of course, the array substrate 100 further includes multiple insulating layers located between the various structures of the first transistor 20. The multiple insulating layers include a first gate insulating layer 12 located between the active layer 21 and the first gate electrode 22, and a first interlayer insulating layer 13 located between the first gate electrode 22 and the source electrode 23 and the drain electrode 24. Optionally, multiple insulating layers are provided between the first gate electrode 22 and the source electrode 23 and the drain electrode 24. For example, a second interlayer insulating layer 14 is further provided between the first gate electrode 22 and the source electrode 23 and the drain electrode 24. The second interlayer insulating layer 14 is located on a side of the first interlayer insulating layer 13 away from the substrate 10.

[0057] Specifically, the first gate insulating layer 12 covers the active layer 21 and the buffer layer 11. The first gate insulating layer 12 may be silicon nitride (SiNx), silicon oxide (SiOx), or a stacked layer of silicon nitride and silicon oxide.

[0058] The first gate 22 is located on a side of the active layer 21 away from the substrate 10. Specifically, the first gate 22 is disposed on a side of the first gate insulating layer 12 away from the active layer 21, and the first gate 22 is disposed corresponding to the channel region 211 of the active layer 21. Optionally, the first gate 22 is a single layer or a stack of metals such as Mo, Al, Cu, Ti, or alloys thereof.

[0059] The first interlayer insulating layer 13 covers the first gate electrode 22 and the first gate insulating layer 12. The second interlayer insulating layer 14 covers the first interlayer insulating layer 13. The first interlayer insulating layer 13 and the second interlayer insulating layer 14 are made of different materials. For example, the first interlayer insulating layer 13 is made of silicon nitride, and the second interlayer insulating layer 14 is made of silicon oxide.

[0060] The source electrode 23 and the drain electrode 24 are both located on a side of the active layer 21 away from the substrate 10. Furthermore, the source electrode 23 and the drain electrode 24 are both located on a side of the first gate electrode 22 away from the active layer 21. Specifically, the source electrode 23 and the drain electrode 24 are both disposed on a side of the second interlayer insulating layer 14 away from the first gate electrode 22. A second opening 140 is provided in the second interlayer insulating layer 14, through which the drain electrode 24 is connected to the drain doping region 213 of the active layer 21. The second opening 140 penetrates the second interlayer insulating layer 14, the first interlayer insulating layer 13, and the first gate insulating layer 12 to expose the drain doping region 213 of the active layer 21. Accordingly, the source electrode 23 can be connected to the source doping region 212 of the active layer 21 through other openings in the second interlayer insulating layer 14. Of course, in order to increase the wiring space on the array substrate 100 , one of the source electrode 23 and the drain electrode 24 can be disposed on the second interlayer insulating layer 14 , and the other can be disposed on other film layers.

[0061] Optionally, to increase the aperture ratio of the array substrate 100 and thereby improve transmittance, the drain electrode 24 is formed of a transparent conductive material, such as indium tin oxide (ITO). This means that the drain electrode 24 is a transparent electrode. The source electrode 23 is made of a different material than the drain electrode 24. The source electrode 23 is made of a metallic conductive material with strong reducing properties. For example, the source electrode 23 is formed of a titanium-aluminum-titanium stack. Titanium has a strong reducing property and can remove oxygen atoms from the active layer 21, reducing oxygen vacancies and forming a heavily doped region on the surface of the active layer 21, thereby forming a good ohmic contact with the source electrode 23. Of course, the source electrode 23 can also be formed of other metallic conductive materials, such as copper, molybdenum, etc.

[0062] The first planarization layer 30 covers the source electrode 23, the drain electrode 24, and the second interlayer insulating layer 14. The first planarization layer 30 is provided with a first opening 301 at a position corresponding to the first transistor 20. For example, the first planarization layer 30 is provided with the first opening 301 at a position corresponding to the drain electrode 24, and the first opening 301 exposes the drain electrode 24. Optionally, the central axis of the first opening 301 coincides with the central axis of the second opening 140. For example, the dotted line PP' shown in Figure 1 is the central axis of the first opening 301 and the second opening 140.

[0063] The auxiliary electrode 40 is disposed within the first opening 301 and is connected to the drain electrode 24 exposed by the first opening 301. The auxiliary electrode 40 is formed of a transparent conductive material, such as indium tin oxide (ITO), meaning that the auxiliary electrode 40 is a transparent electrode. Optionally, the material of the auxiliary electrode 40 is the same as that of the drain electrode 24.

[0064] The second flat layer 50 covers the auxiliary electrode 40 and fills the first opening 301. The second flat layer 50 and the first flat layer 30 are both formed of organic materials, wherein the refractive index of the second flat layer 50 is greater than the refractive index of the first flat layer 30. For example, the refractive index of the first flat layer 30 is in the range of 1.4 to 1.5, and the refractive index of the second flat layer 50 is in the range of 1.6 to 1.8. In this way, the first flat layer 30 with a low refractive index and the second flat layer 50 with a high refractive index form a microlens structure. When light passes through the microlens structure, light converges, as shown in Figure 2. The dotted line with an arrow in Figure 2 represents the propagation path of the light. Light convergence can improve light extraction efficiency, thereby increasing light output brightness, and thus improving transmittance.

[0065] In one embodiment, with continued reference to FIG1 and FIG2 , the upper surface 51 of the second planar layer 50 on the side away from the substrate 10 is flush with the upper surface 31 of the first planar layer 30 on the side away from the substrate 10. The second planar layer 50 and the first planar layer 30 are separated by the auxiliary electrode 40. The auxiliary electrode 40 extends along the wall of the first opening 301. The extended end 401 of the auxiliary electrode 40 is flush with the upper surface 31 of the first planar layer 30 on the side away from the substrate 10. The extended end 401 of the auxiliary electrode 40 is also flush with the upper surface 51 of the second planar layer 50 on the side away from the substrate 10. In other words, the second planar layer 50 fills the space enclosed by the auxiliary electrode 40, and the extended end 401 of the auxiliary electrode 40 is exposed in the gap between the second planar layer 50 and the first planar layer 30. The first electrode 60 is disposed on the upper surface 51 of the second planar layer 50, distal from the substrate 10, and is connected to the extended end 401 of the auxiliary electrode 40, thereby electrically connecting the first electrode 60 to the drain electrode 24. Of course, the first electrode 60 also extends from the upper surface 51 of the second planar layer 50 to the upper surface 31 of the first planar layer 30. The first electrode 60 is formed of a transparent conductive material, such as indium tin oxide (ITO), meaning that the first electrode 60 is a transparent electrode. The material of the first electrode 60 can be the same as that of the auxiliary electrode 40.

[0066] Furthermore, the upper surface 31 of the first flat layer 30, the upper surface 51 of the second flat layer 50 and the extended end 401 of the auxiliary electrode 40 are all flush, and a smooth film surface can be formed. In this way, when the first electrode 60 is formed on the upper surface 31 of the first flat layer 30, the upper surface 51 of the second flat layer 50 and the extended end 401 of the auxiliary electrode 40, the risk of short circuit, crosstalk, etc. of the first electrode 60 can be reduced, and a larger area of ​​the first electrode 60 can be formed to increase the effective surface connection of the first electrode 60, thereby further improving the light extraction efficiency.

[0067] Optionally, the array substrate 100 further includes a second electrode 70 located on a side of the first electrode 60 away from the substrate 10. A passivation layer 15 is disposed between the first electrode 60 and the second electrode 70 to isolate the first electrode 60 from the second electrode 70. The passivation layer 15 can be silicon nitride (SiNx), silicon oxide (SiOx), or a stack of silicon nitride and silicon oxide. The second electrode 70 can be made of the same material as the first electrode 60. For example, the second electrode 70 can also be formed of the transparent conductive material indium tin oxide, meaning that the second electrode 70 is a transparent electrode. The first electrode 60 is a pixel electrode, and the second electrode 70 is a common electrode. Both the first electrode 60 and the second electrode 70 are patterned electrodes.

[0068] The detailed structure of the first opening 301 is described in detail below:

[0069] 3 and 4 , the first opening 301 includes a first opening 3011 and a second opening 3012 disposed opposite each other. The first opening 3011 is located on a side of the second opening 3012 away from the first transistor 20, and the first opening 3011 is larger than the second opening 3012. For example, when the depth of the first opening 301 is greater than 1 micron, the first opening 3011 is larger than 2 microns to enable the first planarizing layer 30 and the second planarizing layer 50 to form a microlens structure of appropriate size. If the size of the first opening 3011 is too small, the flatness of the first planarizing layer 30 and the light-gathering effect of the formed microlens will be affected. The size of the second opening 3012 depends on the size of the drain electrode 24, and the depth of the first opening 301 depends on the thickness of the first planarizing layer 30. Among them, the opening size of the first opening 3011 refers to the maximum size of the first opening 3011. For example, when the shape of the first opening 3011 is circular, the opening size of the first opening 3011 refers to the diameter of the circle; the opening size of the second opening 3012 refers to the maximum size of the second opening 3012. For example, when the shape of the second opening 3012 is circular, the opening size of the second opening 3012 refers to the diameter of the circle. The shape of the second opening 3012 depends on the shape of the drain 24.

[0070] Optionally, the hole wall 3013 of the first opening 301 is curved to enhance the light focusing effect of the microlens structure formed by the first flat layer 30 and the second flat layer 50. Specifically, in a longitudinal cross-section, the hole wall 3013 of the first opening 301 is arc-shaped.

[0071] The auxiliary electrode 40 covers the hole wall 3013 of the first opening 301, and the thickness of the auxiliary electrode 40 near the second opening 3012 is greater than the thickness near the first opening 3011, so as to improve the stability of the connection between the auxiliary electrode 40 and the drain 24 and reduce the contact impedance between the auxiliary electrode 40 and the drain 24.

[0072] In one embodiment, referring to Figures 1 to 5 , Figure 5 is a schematic diagram of another cross-sectional structure of an array substrate provided in an embodiment of the present application. Unlike the above embodiment, the auxiliary electrode 40 extends from the first opening 301 to the upper surface 31 of the first planar layer 30 away from the substrate 10 and contacts the first electrode 60.

[0073] Specifically, referring to Figure 5 , the auxiliary electrode 40 includes a first sub-portion 41 located within the first opening 301 and a second sub-portion 42 located on the upper surface of the first planar layer 30. The second sub-portion 42 is formed by the first sub-portion 41 extending from the first opening 301 toward the upper surface 31 of the first planar layer 30. In other words, the first sub-portion 41 and the second sub-portion 42 are integrally formed. The second sub-portion 42 is connected to the first electrode 60 to increase the contact area between the auxiliary electrode 40 and the first electrode 60, thereby improving the connection stability between the auxiliary electrode 40 and the first electrode 60 and reducing the contact impedance between the auxiliary electrode 40 and the first electrode 60.

[0074] The second flat layer 50 is located within the space enclosed by the auxiliary electrode 40. The upper surface 51 of the second flat layer 50 is flush with the upper surface of the second sub-portion 42 on the side away from the substrate 10. In this case, the upper surface 51 of the second flat layer 50 is higher than the upper surface 31 of the first flat layer 30. For other explanations, please refer to the above embodiment and will not be repeated here.

[0075] In one embodiment, referring to Figures 1 to 6 , Figure 6 is a schematic cross-sectional view of another embodiment of the array substrate provided in this application. Unlike the above embodiment, referring to Figure 6 , the auxiliary electrode 40 is integrally formed with the drain electrode 24 , i.e., the auxiliary electrode 40 and the drain electrode 24 are formed in the same process step to simplify the process. For other explanations, please refer to the above embodiment and will not be repeated here.

[0076] In one embodiment, referring to Figures 1 to 7, Figure 7 is a schematic cross-sectional view of another embodiment of the array substrate provided in the present application. Unlike the above embodiment, the active layer 21 is made of a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). The array substrate 100 also includes a second transistor 80 connected to the first transistor 20. The active layer 21 of the second transistor 80 is made of polysilicon, such as low-temperature polysilicon (LTPS).

[0077] Specifically, referring to Figure 7, the first transistor 20 is an oxide transistor, the second transistor 80 is a polysilicon transistor, the second transistor 80 includes an active layer 81, a first gate 82, a source 83 and a drain 84, the first transistor 20 also includes a second gate 25 arranged in the same layer as the first gate 82 of the second transistor 80, and the first gate 22 of the first transistor 20 is arranged in the same layer as the source 83 and drain 84 of the second transistor 80. It should be noted that "arranged in the same layer" in this application means that in the preparation process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are arranged in the same layer. For example, in this embodiment, the first gate 22 of the first transistor 20 and the source 83 and drain 84 of the second transistor 80 are obtained by patterning the same conductive film layer, and the first gate 22 of the first transistor 20 and the source 83 and drain 84 of the second transistor 80 are arranged in the same layer.

[0078] Furthermore, the array substrate 100 further includes a second gate insulating layer 16 and a third gate insulating layer 17. The second gate insulating layer 16 covers the active layer 21 of the second transistor 80. The first gate 82 of the second transistor 80 and the second gate 25 of the first transistor 20 are disposed on a side of the second gate insulating layer 16 away from the substrate 10. The third gate insulating layer 17 covers the first gate 82 of the second transistor 80, the second gate 25 of the first transistor 20, and the second gate insulating layer 16. The active layer 21 of the first transistor 20 is disposed on a side of the third gate insulating layer 17 away from the substrate 10. For other explanations, please refer to the above embodiment and will not be repeated here.

[0079] Based on the same inventive concept, an embodiment of the present application further provides a display panel, comprising the array substrate 100 of one of the aforementioned embodiments. Optionally, the display panel is a liquid crystal display panel, further comprising an opposing substrate disposed opposite the array substrate 100, and a liquid crystal layer located between the array substrate 100 and the opposing substrate. The opposing substrate may be a color filter substrate.

[0080] According to the above embodiments, it can be seen that:

[0081] In the array substrate and display panel provided in the present application, the array substrate includes a substrate and a first transistor arranged on one side of the substrate, a first flat layer arranged on a side of the first transistor away from the substrate, and a first opening arranged at a position corresponding to the first transistor, an auxiliary electrode arranged in the first opening and connected to the first transistor, a second flat layer arranged on a side of the auxiliary electrode away from the first flat layer and filled in the first opening, a first electrode arranged on a side of the second flat layer away from the substrate and connected to the auxiliary electrode, wherein the refractive index of the first flat layer is smaller than the refractive index of the second flat layer; in this way, by providing the first opening in the first flat layer with a low refractive index at the position corresponding to the first transistor and filling the first opening with the second flat layer with a high refractive index, a microlens structure is formed at the position corresponding to the first transistor, and light passing through the microlens structure is converged, which can improve the brightness of the light output and thereby improve the transmittance, thereby alleviating the technical problem of low transmittance and difficulty in improving the transmittance of existing VR displays.

[0082] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, comprising: substrate; a first transistor, disposed on one side of the substrate; A first planar layer is provided on a side of the first transistor away from the substrate and has a first opening at a position corresponding to the first transistor; an auxiliary electrode, disposed in the first opening and connected to the first transistor; a second planar layer, disposed on a side of the auxiliary electrode away from the first planar layer and filling the first opening; as well as a first electrode, disposed on a side of the second planar layer away from the substrate and connected to the auxiliary electrode; The refractive index of the first flat layer is smaller than the refractive index of the second flat layer.

2. The array substrate according to claim 1, wherein: An upper surface of the second flat layer at a side away from the substrate is flush with an upper surface of the first flat layer at a side away from the substrate.

3. The array substrate according to claim 1, wherein: The auxiliary electrode extends from the first opening to the upper surface of the first flat layer on a side away from the substrate and contacts the first electrode.

4. The array substrate according to claim 1, wherein: The refractive index of the first flat layer ranges from 1.4 to 1.5, and the refractive index of the second flat layer ranges from 1.6 to 1.

8.

5. The array substrate according to claim 1, wherein: The first opening includes a first opening and a second opening that are oppositely arranged. The first opening is located on a side of the second opening away from the first transistor. The opening size of the first opening is larger than the opening size of the second opening.

6. The array substrate according to claim 5, wherein: The opening size of the first opening is greater than 2 micrometers, and the depth of the first opening is greater than 1 micrometer.

7. The array substrate according to claim 5, wherein: The hole wall of the first opening is curved.

8. The array substrate according to any one of claims 1 to 7, wherein: The first transistor includes an active layer, a source electrode, and a drain electrode. The source electrode and the drain electrode are both connected to the active layer, and one of the source electrode and the drain electrode is further connected to the auxiliary electrode.

9. The array substrate according to claim 8, wherein: The drain electrode is connected to the auxiliary electrode and is a transparent electrode.

10. The array substrate according to claim 8, wherein: The material of the active layer includes a metal oxide semiconductor material. The array substrate further includes a second transistor connected to the first transistor. The material of the active layer of the second transistor includes polysilicon.

11. A display panel comprising an array substrate, the array substrate comprising: substrate; a first transistor, disposed on one side of the substrate; A first planar layer is provided on a side of the first transistor away from the substrate and has a first opening at a position corresponding to the first transistor; an auxiliary electrode, disposed in the first opening and connected to the first transistor; a second planar layer, disposed on a side of the auxiliary electrode away from the first planar layer and filling the first opening; as well as a first electrode, disposed on a side of the second planar layer away from the substrate and connected to the auxiliary electrode; The refractive index of the first flat layer is smaller than the refractive index of the second flat layer.

12. The display panel according to claim 11, wherein: An upper surface of the second flat layer at a side away from the substrate is flush with an upper surface of the first flat layer at a side away from the substrate.

13. The display panel according to claim 11, wherein: The auxiliary electrode extends from the first opening to the upper surface of the first flat layer on a side away from the substrate and contacts the first electrode.

14. The display panel according to claim 11, wherein: The refractive index of the first flat layer ranges from 1.4 to 1.5, and the refractive index of the second flat layer ranges from 1.6 to 1.

8.

15. The display panel according to claim 11, wherein The first opening includes a first opening and a second opening that are oppositely arranged. The first opening is located on a side of the second opening away from the first transistor. The opening size of the first opening is larger than the opening size of the second opening.

16. The display panel according to claim 15, wherein: The opening size of the first opening is greater than 2 micrometers, and the depth of the first opening is greater than 1 micrometer.

17. The display panel according to claim 15, wherein: The hole wall of the first opening is curved.

18. The display panel according to any one of claims 1 to 17, wherein: The first transistor includes an active layer, a source electrode, and a drain electrode. The source electrode and the drain electrode are both connected to the active layer, and one of the source electrode and the drain electrode is further connected to the auxiliary electrode.

19. The display panel according to claim 18, wherein: The drain electrode is connected to the auxiliary electrode and is a transparent electrode.

20. The display panel according to claim 18, wherein The material of the active layer includes a metal oxide semiconductor material. The array substrate further includes a second transistor connected to the first transistor. The material of the active layer of the second transistor includes polysilicon.

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